Hybrid passivated back-contact cell and method for preparing same by means of one-shot annealing

Abstract

The present application belongs to the technical field of the preparation of hybrid passivated back-contact cells, and specifically relates to a hybrid passivated back-contact cell and a method for preparing same by means of one-shot annealing. The preparation method comprises: S101, providing a silicon wafer with both surfaces polished and cleaned; S102, forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer, wherein annealing is not performed during the forming process of the first semiconductor layer; S103, forming a second semiconductor opening region; S104, performing texturing and cleaning, and forming a textured surface at the same time; S105, then forming a third semiconductor layer on the front surface of the silicon wafer, wherein the forming process of the third semiconductor layer comprises second in-situ doping deposition; after the second in-situ doping deposition, performing one-shot annealing on the first semiconductor layer and the third semiconductor layer at a low pressure; then depositing an anti-reflection layer; and then cleaning same; and S106, depositing a second semiconductor layer. In the present application, annealing is performed only once in the whole process, and therefore the equipment cost is greatly reduced, and both the short-circuit current and conversion efficiency of a cell are improved.

Description

A combined passivation back contact cell and a one-time annealing preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority and benefits of Chinese patent application number 2023113769745, filed with the State Intellectual Property Office of China on October 24, 2023, entitled “A combined passivated back contact battery and its one-time annealing preparation method”, and incorporates the full text of the patent application into this application by reference. Technical Field

[0003] The present application belongs to the technical field of combined passivation back contact cell preparation, and specifically relates to a combined passivation back contact cell and a single annealing preparation method thereof. Background Art

[0004] In back-contact cells, the tunneling polycrystalline process requires a thinner third doped polycrystalline layer on the front side to increase the battery current, while a thicker first doped polysilicon layer is required on the back side to improve conductivity. According to the traditional scheme, two annealing processes are required (one annealing to form the third semiconductor layer on the front side and a lower annealing temperature is required, and one annealing to form the first semiconductor layer on the back side and a higher annealing temperature is required to evenly diffuse phosphorus impurities into the entire polysilicon film in the first semiconductor layer). The equipment cost is significantly increased, and the first doped polysilicon layer on the back side will be damaged by the two annealing processes, which affects the back passivation level.

[0005] Moreover, tunneling polycrystalline passivation contacts are usually formed by in-situ doping deposition annealing using tubular PECVD. In order to ensure electron tunneling and carrier transport on the front side, the second tunneling oxide layer set on the front side in the traditional battery structure is relatively thin, with a thickness of 1-2nm. It is easily affected by the annealing temperature and the front passivation is damaged. Therefore, different annealing temperatures need to be used according to the difference in the thickness of the polysilicon deposited on the surface of the second tunneling oxide layer. This is because if the annealing temperature is too high, the diffusion of impurities such as phosphorus and oxygen will damage the oxide layer.

[0006] In summary, in the traditional preparation method of back-contact batteries, based on the considerations of the corresponding doped polycrystalline layers and the corresponding tunneling oxide layers on the front and back sides of the battery, two annealing processes are used with different annealing temperatures. The equipment cost is high, and the first doped polysilicon layer on the back side will be damaged by two annealings, which will affect the passivation and conductivity of the film layer.

[0007] It should be noted that this part of the content of this application only provides background technology related to this application, and does not necessarily constitute prior art or public knowledge.

[0008] Summary of the Invention

[0009] The purpose of this application is to overcome the defects of the existing technology that the traditional preparation process equipment is high in cost and the first doped polysilicon layer on the back will be damaged, and to provide a combined passivation back contact battery and a one-time annealing preparation method thereof. The one-time annealing preparation method only performs one annealing throughout the entire process, which greatly reduces the equipment cost and takes into account the improvement of the battery's short-circuit current and battery conversion efficiency.

[0010] To achieve the above objectives, in a first aspect, the present application provides a single-annealing method for preparing a combined passivated back contact cell, comprising the following steps:

[0011] S101, provide double-sided polished and cleaned silicon wafers;

[0012] S102, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, wherein the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer, wherein the formation process of the first semiconductor layer includes a first in-situ doping deposition without annealing; the thickness of the first tunneling silicon oxide layer is 1-2 nm;

[0013] S103, performing a first etching opening on the back surface obtained in S102 to form a second semiconductor opening region;

[0014] S104, then performing texturing cleaning to remove the remaining mask layer and the first semiconductor layer in the second semiconductor opening region, while forming a textured surface on the front side of the silicon wafer and the second semiconductor opening region; then performing cleaning to remove the mask layer on the back side outside the second semiconductor opening region;

[0015] S105, then forming a third semiconductor layer on the front side of the silicon wafer, the third semiconductor layer comprising a second tunneling oxide layer and a third doped polycrystalline layer doped with carbon and / or oxygen, the formation process of the third semiconductor layer comprising a second in-situ doping deposition; the second tunneling oxide layer is thickened to a thickness of 4-6 nm;

[0016] After the second in-situ doping deposition, the first semiconductor layer and the third semiconductor layer are subjected to a primary annealing at low pressure, wherein the conditions of the primary annealing include: an annealing pressure of 2000 mtorr to 1 atm, an annealing temperature of 850-950° C., and an annealing time of 10-60 min;

[0017] Then, an anti-reflection layer is deposited on the surface of the third semiconductor layer; and then the back surface coating is removed by cleaning.

[0018] S106 , then depositing a second semiconductor layer on the back surface of the substrate obtained in S105 , wherein the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped crystalline silicon layer.

[0019] In some preferred embodiments of the present application, the ratio of the thickness of the second tunneling oxide layer to the third carbon-doped and / or oxygen-doped polycrystalline layer is 1:0.8-3, preferably 1:1.5-3, and preferably 1:2-3.

[0020] The thickness of the third carbon-doped and / or oxygen-doped polycrystalline layer described in the present application is 4-15 nm.

[0021] In some preferred embodiments of the present application, S105 also includes: as the second tunnel oxide layer thickens, the thickness of the third doped polycrystalline layer is reduced and / or the effective phosphorus doping concentration is reduced, and the adjustment degree of the thickness and the effective phosphorus doping concentration of the third doped polycrystalline layer satisfies: for every 1 nm thickening of the second tunnel oxide layer, the thickness of the third doped polycrystalline layer is reduced by 1-6 nm, and / or the effective phosphorus doping concentration is reduced by 20%-50%.

[0022] Preferably, S105 also includes: as the second tunnel oxide layer thickens, the thickness of the third doped polycrystalline layer is reduced and / or the effective phosphorus doping concentration is reduced, and the adjustment degree of the thickness and the effective phosphorus doping concentration of the third doped polycrystalline layer meets the following requirements: for every 1 nm thickening of the second tunnel oxide layer, the thickness of the third doped polycrystalline layer is reduced by 1-2 nm, and / or the effective phosphorus doping concentration is reduced by 35%-50%.

[0023] Further preferably, the ratio of the surface doping index of the carbon and / or oxygen-doped third doped polycrystalline layer to the first doped polysilicon layer is 5-15:1, wherein the surface doping index is the ratio of the effective phosphorus doping concentration of the corresponding doped layer to the thickness of the doped layer.

[0024] The thickness of the first doped polysilicon layer in the present application is 150-300 nm.

[0025] Preferably, the effective phosphorus doping concentration of the first doped polysilicon layer is 1e19-8e21cm -3 The effective phosphorus doping concentration of the carbon-doped and / or oxygen-doped third doped polycrystalline layer is 5e18-5e20cm -3 .

[0026] In some preferred embodiments of the present application, the third doped polycrystalline layer is doped with carbon and its effective carbon doping concentration is 1e19-4e21cm -3 .

[0027] In some preferred embodiments of the present application, the third doped polycrystalline layer is doped with oxygen and its effective oxygen doping concentration is 1e19-3e20cm -3 .

[0028] In some preferred embodiments of the present application, the band gap width of the third doped polycrystalline layer is 1.9-2.3 eV.

[0029] In some preferred embodiments of the present application, the one-time annealing preparation method further comprises:

[0030] S107, then performing a second etching opening on the back surface obtained in S106 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, followed by cleaning; forming an isolation region between the second semiconductor opening region and the first semiconductor opening region;

[0031] S108, depositing a transparent conductive film on the back surface obtained in S107;

[0032] S109, then performing a third etching opening at the isolation region to form an insulating trench located between the second semiconductor opening region and the first semiconductor opening region;

[0033] S110 , forming a first metal electrode on the surface of the first semiconductor opening region on the back surface obtained in S109 , and forming a second metal electrode on the surface of the second semiconductor opening region.

[0034] In a second aspect, the present application provides a combined passivation back contact cell, which is prepared by the single annealing preparation method described in the first aspect. Beneficial effects:

[0035] The present application adopts the above-mentioned technical solution, especially by increasing the thickness of the second tunnel oxide layer provided on the front side to 4-6nm, and combining it with a third doped polycrystalline layer doped with carbon and / or oxygen, so as to ensure the passivation level of the front side while also improving the short-circuit current. It is also more resistant to high temperatures and can be annealed together with the thicker first doped polysilicon layer on the back side, with only one annealing process. This greatly reduces equipment cost and significantly reduces the damage to the first doped polysilicon layer caused by two anneals, thereby improving the open circuit voltage and fill factor. In addition, the third doped polycrystalline layer provided on the front side is combined with the use of an appropriately high temperature annealing in the first annealing to improve the short-circuit current of the battery. The thicker second tunnel oxide layer is resistant to high temperatures and will not be adversely affected by the passivation loss caused by annealing at such high temperatures, thereby facilitating the improvement of both the short-circuit current and the conversion efficiency of the battery. Under the same conditions, if a thinner second tunnel oxide layer is used in the prior art, then the passivation level will be seriously reduced due to the damage of the second tunnel oxide layer at the higher temperature in the first annealing. Under the same conditions, using the lower annealing temperature used in existing technologies can lead to reduced short-circuit current, open-circuit voltage, and fill factor due to insufficient phosphorus diffusion in the first doped polysilicon layer and insufficient crystallinity in the first and second doped polysilicon layers. Under the same conditions, if the third doped polysilicon layer is not doped with carbon and / or oxygen, the bandgap of the polysilicon is smaller, resulting in lower short-circuit current and lower cell conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0037] FIG1 is a schematic diagram of the structure of the S101 silicon wafer after polishing and cleaning in Example 1 of the present application;

[0038] FIG2 is a schematic structural diagram of forming a first semiconductor layer and a mask layer on the back side of an S102 silicon wafer in Example 1 of the present application;

[0039] FIG3 is a schematic structural diagram of a second semiconductor opening region formed on the back side of the S103 silicon wafer in Example 1 of the present application;

[0040] FIG4 is a schematic diagram of the structure of the S104 silicon wafer after texturing and cleaning in Example 1 of the present application;

[0041] FIG5 is a schematic structural diagram of the third semiconductor layer and the anti-reflection layer formed on the front side of the S105 silicon wafer in Example 1 of the present application;

[0042] FIG6 is a schematic diagram of the structure of forming a second semiconductor layer on the back side of an S106 silicon wafer in Example 1 of the present application;

[0043] FIG7 is a schematic structural diagram of a first semiconductor opening region formed on the back side of an S107 silicon wafer in Example 1 of the present application;

[0044] FIG8 is a schematic diagram of the structure of a transparent conductive film deposited on the back side of an S108 silicon wafer in Example 1 of the present application;

[0045] FIG9 a is a schematic structural diagram of an insulating trench mask pattern formed on the back side of an S109 silicon wafer in Example 1 of the present application;

[0046] FIG9 b is a schematic diagram of the structure of the insulating groove formed on the back side of the S109 silicon wafer in Example 1 of the present application;

[0047] FIG10 is a schematic diagram of the structure of metal electrodes formed on the back side of the S13 silicon wafer in Example 1 of the present application.

[0048] FIG11 is a process flow chart of the single annealing preparation method of the present application.

[0049] Explanation of the reference numerals: 10. Silicon wafer, 11. First tunneling silicon oxide layer, 12. N-type first doped polycrystalline silicon layer, 13. Mask layer, 14. Second tunneling oxide layer, 15. N-type third doped polycrystalline layer, 16. Anti-reflection layer, 17. Intrinsic amorphous silicon layer, 18. P-type doped amorphous silicon layer, 19. Transparent conductive film, 20. Acid-resistant mask material, 21n. First metal electrode, 21p. Second metal electrode. DETAILED DESCRIPTION

[0050] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0051] In a first aspect, the present application provides a single-annealing method for preparing a combined passivated back contact cell, comprising the following steps:

[0052] S101, provide double-sided polished and cleaned silicon wafers;

[0053] S102, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, wherein the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer, wherein the formation process of the first semiconductor layer includes a first in-situ doping deposition without annealing; the thickness of the first tunneling silicon oxide layer is 1-2 nm;

[0054] S103, performing a first etching opening on the back surface obtained in S102 to form a second semiconductor opening region;

[0055] S104, then performing texturing cleaning to remove the remaining mask layer and the first semiconductor layer in the second semiconductor opening region, while forming a textured surface on the front side of the silicon wafer and the second semiconductor opening region; then performing cleaning to remove the mask layer on the back side outside the second semiconductor opening region;

[0056] S105, then forming a third semiconductor layer on the front side of the silicon wafer, the third semiconductor layer comprising a second tunneling oxide layer and a third doped polycrystalline layer doped with carbon and / or oxygen, the formation process of the third semiconductor layer comprising a second in-situ doping deposition; the second tunneling oxide layer is thickened to a thickness of 4-6 nm;

[0057] After the second in-situ doping deposition, the first semiconductor layer and the third semiconductor layer are subjected to a primary annealing at low pressure, wherein the conditions of the primary annealing include: an annealing pressure of 2000 mtorr to 1 atm, an annealing temperature of 850-950° C., and an annealing time of 10-60 min;

[0058] Then, an anti-reflection layer is deposited on the surface of the third semiconductor layer; and then the back surface coating is removed by cleaning.

[0059] S106 , then depositing a second semiconductor layer on the back surface obtained in S105 , the second semiconductor layer including an intrinsic amorphous silicon layer and a second doped crystalline silicon layer.

[0060] The silicon wafer in S101 may be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0061] The mask layer in S102 may be, for example, at least one of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the mask layer may be, for example, 50-200 nm.

[0062] The first etching method in S103 can be laser or mask etching. For example, the laser is ultraviolet or green laser with a pulse width less than 100 ns. The width Wp of the formed second semiconductor opening region can be 0.3-0.6 mm.

[0063] The cleaning in S104 may be performed using hydrofluoric acid, for example.

[0064] The type and deposition method of the anti-reflection layer in S105 can be any of those in the prior art, such as silicon nitride, etc., and the deposition method is tubular PECVD deposition. The thickness of the anti-reflection layer can be, for example, 700-850 nm.

[0065] In some preferred embodiments of the present application, the thickness ratio of the second tunneling oxide layer to the third carbon- and / or oxygen-doped polycrystalline layer is 1:0.8-3, preferably 1:1.5-3, preferably 1:2-3, and further preferably 1:2.5-3. This preferred embodiment has an appropriate thickness ratio and can withstand higher temperature annealing in a single annealing process, which is more conducive to ensuring the passivation level and improving the crystallinity of the film layer.

[0066] The thickness of the third carbon-doped and / or oxygen-doped polycrystalline layer described in the present application is 4-15 nm.

[0067] In some preferred embodiments of the present application, S105 also includes: as the second tunnel oxide layer thickens, the thickness of the third doped polycrystalline layer is reduced and / or the effective phosphorus doping concentration is reduced, and the adjustment degree of the thickness and the effective phosphorus doping concentration of the third doped polycrystalline layer meets the following requirements: for every 1 nm thickening of the second tunnel oxide layer, the thickness of the third doped polycrystalline layer is reduced by 1-6 nm, and / or the effective phosphorus doping concentration is reduced by 20%-50%, for example, it can be reduced by 20%, 30%, 40%, 45%, 50%, etc.

[0068] Preferably, S105 further includes: reducing the thickness of the third doped polycrystalline layer and / or reducing the effective phosphorus doping concentration as the second tunneling oxide layer thickens, and the thickness and effective phosphorus doping concentration of the third doped polycrystalline layer are adjusted to meet the following conditions: for every 1 nm increase in the thickness of the second tunneling oxide layer, the thickness of the third doped polycrystalline layer decreases by 1-2 nm, and / or the effective phosphorus doping concentration decreases by 35%-50%. This preferred solution, by appropriately reducing the thickness and effective phosphorus doping concentration of the carbon- and / or oxygen-doped third doped polycrystalline layer as the second tunneling oxide layer thickens, can reduce light absorption by the first doped polycrystalline silicon layer during a single annealing process, thereby further facilitating improved short-circuit current.

[0069] In the present application, the thickness and effective phosphorus doping concentration of the third doped polycrystalline layer can be appropriately selected, provided that the adjustment conditions for the thickness and effective phosphorus doping concentration of the third doped polycrystalline layer are met. Further preferably, the ratio of the surface doping index of the carbon-doped and / or oxygen-doped third doped polycrystalline layer to the first doped polysilicon layer is 5-15:1, preferably 5-10:1, where the surface doping index is the ratio of the effective phosphorus doping concentration of the corresponding doped layer to the thickness of the doped layer. In this preferred embodiment, the thickness and effective phosphorus doping concentration of the third doped polycrystalline layer are both appropriate, which is more conducive to the field passivation effect of the third doped polysilicon layer and further improves the front passivation level.

[0070] The thickness of the first doped polysilicon layer in the present application is 150-300 nm.

[0071] Preferably, the effective phosphorus doping concentration of the first doped polysilicon layer is 1e19-8e21cm -3 .

[0072] Preferably, the effective phosphorus doping concentration of the carbon-doped and / or oxygen-doped third polycrystalline layer is 5e18-5e20 cm -3 .

[0073] In some preferred embodiments of the present application, the third doped polycrystalline layer is doped with carbon and its effective carbon doping concentration is 1e19-4e21cm -3 .

[0074] In some preferred embodiments of the present application, the third doped polycrystalline layer is doped with oxygen and its effective oxygen doping concentration is 1e19-3e20cm -3 .

[0075] In some preferred embodiments of the present application, the bandgap width of the third doped polycrystalline layer is 1.9-2.3 eV. Carbon and / or oxygen doping of the third doped polycrystalline layer of the present application enables the bandgap width to be 1.9-2.3 eV, which is more conducive to ensuring a higher level of front passivation while simultaneously improving short-circuit current and battery conversion efficiency.

[0076] The formation of the first semiconductor layer in S102 of the present application and the formation of the third semiconductor layer in S105 can be carried out according to the methods in the prior art. For example, a tubular PECVD (plasma enhanced chemical vapor deposition) in-situ doping deposition process can be used, as long as a film layer of the required thickness and corresponding doping can be obtained.

[0077] Exemplarily, the formation process of the first semiconductor layer in S102 includes: using a tubular PECVD in-situ doping deposition process, first performing the first stage, in which silane and nitrous oxide are introduced, glow is turned on, and a first tunneling silicon oxide layer is formed by chemical reaction. The reaction temperature of the first stage is 400-450°C, the reaction pressure is 100-2000mtorr, and the time is 10-60s; then entering the second stage, in which silane, phosphine, hydrogen and optional methane are introduced, glow is turned on, and a phosphorus-doped and optionally carbon-doped polysilicon layer is formed by chemical reaction. The reaction temperature of the second stage is 400-450°C, the reaction time is 500-1500s, and the reaction pressure is 100-2000mtorr. Carbon doping of the polysilicon layer of the first semiconductor layer is beneficial to improving the short-circuit current of the battery. When carbon is doped, its effective carbon doping concentration can be 1e19-4e21cm -3 .

[0078] Exemplarily, the formation process of the third semiconductor layer described in S105 includes: using a tubular PECVD in-situ doping deposition process, first performing the first stage, in which silane and nitrous oxide are introduced, the glow is turned on, and a second tunneling oxide layer is formed by chemical reaction. The reaction temperature of the first stage is 400-450°C, the reaction pressure is 100-2000mtorr, and the time is 10-60s; then entering the second stage, in which silane, phosphine, methane, and hydrogen are introduced, the glow is turned on, and a carbon-doped polycrystalline silicon layer is formed by chemical reaction. The reaction temperature of the second stage is 400-450°C, the reaction time is 30-200s, and the reaction pressure is 100-2000mtorr; of course, when the third semiconductor layer described in S105 needs to prepare an oxygen-doped third doped polycrystalline layer, different introduction gases can be selected to achieve this, and the oxygen source gas can be, for example, CO2, NO2, etc.

[0079] The deposition method, thickness, and corresponding doping concentration of the second semiconductor layer in S106 can be carried out according to the prior art, for example, the deposition method can be PECVD technology. The second doped crystalline silicon layer can be, for example, a doped amorphous or microcrystalline silicon layer. For example, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the second doped crystalline silicon layer is 10-35 nm, and the effective doping concentration of the second doped crystalline silicon layer is 1e19-4e20 cm -3 .

[0080] One of the second doped crystalline silicon layer and the first doped polysilicon layer is N-type, and the other is P-type. Exemplarily, the second doped crystalline silicon layer is P-type, the first doped polysilicon layer is N-type, and preferably the third doped polysilicon layer is N-type.

[0081] The present application may also include other conventional steps. For example, in some preferred embodiments of the present application, the single annealing preparation method further includes: S107, then performing a second etching opening on the back surface obtained in S106 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, followed by cleaning; and forming an isolation region between the second semiconductor opening region and the first semiconductor opening region. The second etching opening can be performed using laser or mask etching. Exemplarily, the laser is an ultraviolet or green laser with a pulse width of less than 50ns. The width Wn of the first semiconductor opening region can be, for example, 0.1-0.3 mm.

[0082] For example, in some preferred embodiments of the present application, the single annealing preparation method further includes: S108, depositing a transparent conductive film on the back surface obtained in S107. The transparent conductive film can be deposited using, for example, physical vapor deposition (PVD) or activated plasma deposition (RPD). The transparent conductive film can have a thickness of, for example, 40-80 nm. The transparent conductive film can be made of, for example, an indium oxide film doped with tin oxide, titanium oxide, zinc oxide, or gallium oxide, or a zinc oxide film doped with aluminum oxide, gallium oxide, or boron oxide.

[0083] For example, in some preferred embodiments of the present application, the single annealing preparation method further includes: S109, then performing a third etching opening in the isolation region to form an insulating trench located between the second semiconductor opening region and the first semiconductor opening region. The third etching opening can be performed, for example, by mask etching. Exemplarily, the mask etching conditions include: first printing or inkjet printing an acid-resistant mask material on the back of the silicon wafer to form an insulating trench pattern, then cleaning with an acid solution to remove the transparent conductive film in the opening region of the acid-resistant mask material, and then cleaning with an ink cleaner to remove the acid-resistant mask material. The acid solution is one of hydrochloric acid, sulfuric acid, and nitric acid, and the cleaning agent is at least one of sodium hydroxide, potassium hydroxide, an alkaline cleaning agent, and an oxidizing agent. The width Wi of the insulating trench can be, for example, 20-120 μm, and the resistance between the first semiconductor opening region and the second semiconductor opening region after etching is greater than 1 kΩ.

[0084] For example, in some preferred embodiments of the present application, the single annealing preparation method further includes: S110, forming a first metal electrode on the surface of the first semiconductor opening region on the back surface obtained in S109, and forming a second metal electrode on the surface of the second semiconductor opening region. The respective metal electrodes can be formed, for example, by screen printing or electroplating technology.

[0085] In a second aspect, the present application provides a combined passivation back contact cell, which is prepared by the single annealing preparation method described in the first aspect.

[0086] The combined passivation back contact cell provided in the present application adopts a specific single annealing preparation method, which improves the passivation level, reduces film defects, and improves the short-circuit current and battery conversion efficiency of the cell.

[0087] The embodiments of the present application are described in detail below. These embodiments are exemplary and are only used to explain the present application. They should not be construed as limiting the present application.

[0088] Example 1

[0089] A single annealing method for preparing a combined passivated back contact cell is shown in FIG11 and is specifically as follows:

[0090] S101 , as shown in FIG1 , double-sided polishing and cleaning of an N-type single crystal silicon wafer 10 , wherein the silicon wafer 10 is a Czochralski single crystal silicon wafer.

[0091] S102 , as shown in FIG. 2 , forming a first semiconductor layer and a mask layer 13 on the back side of the silicon wafer 10 , wherein the first semiconductor layer includes a first tunneling silicon oxide layer 11 and an N-type first doped polysilicon layer 12 . The first semiconductor layer is formed by tubular PECVD in-situ doping deposition. Annealing is not performed in this step, but annealing is performed together with the third semiconductor layer in S105. The tubular PECVD in-situ doping deposition process of this step is as follows: in the first stage, silane and nitrous oxide are introduced, glow is turned on, and a first tunneling silicon oxide layer 11 is formed by chemical reaction. The reaction temperature of the first stage is 400° C., the reaction pressure is 1000 mtorr, the time is 10s, and the thickness of the first tunneling silicon oxide layer 11 is 1nm; then the second stage is entered, silane, phosphine, methane, and hydrogen are introduced in the second stage, glow is turned on, and a carbon-doped N-type first doped polysilicon layer 12 is formed by chemical reaction. The reaction temperature of the second stage is 400° C., the reaction time is 800s, the reaction pressure is 500 mtorr, the thickness of the N-type first doped polysilicon layer 12 is 150nm, and the effective phosphorus doping concentration is 3e19cm -3 The mask layer 13 is silicon nitride and has a thickness of 50 nm.

[0092] S103. As shown in FIG3 , a laser is used to perform a first etching operation on the back side of the silicon wafer 10 to form a second semiconductor opening region. The second semiconductor opening region has a width Wp of 0.3 mm. The mask layer 13, the first N-type doped polysilicon layer 12, and the first tunneling silicon oxide layer 11 within the second semiconductor opening region Wp are etched away. The laser is an ultraviolet laser with a pulse width of 10 ns.

[0093] S104. As shown in FIG4 , the mask layer 13, the N-type first doped polysilicon layer 12 and the first tunneling silicon oxide layer 11 remaining in the second semiconductor opening region Wp are removed by texturing and cleaning. At the same time, a velvet surface is formed on the front side of the silicon wafer 10 and the second semiconductor opening region Wp. After that, the mask layer 13 outside the second semiconductor opening region Wp on the back side of the silicon wafer 10 is removed by cleaning with hydrofluoric acid.

[0094] S105. As shown in FIG5 , a third semiconductor layer is formed on the front surface of the silicon wafer 10. The third semiconductor layer includes a second tunneling oxide layer 14 and a carbon-doped N-type third doped polycrystalline layer 15. The third semiconductor layer is deposited by in-situ doping using tubular PECVD. The conditions include: in the first stage, silane and nitrous oxide are introduced, a glow light is turned on, and the second tunneling oxide layer 14 is formed by a chemical reaction. The reaction temperature in the first stage is 450° C., the reaction pressure is 1000 mtorr, the reaction time is 50 s, and the thickness of the second tunneling oxide layer 14 is 4 nm. Then, the process enters the second stage, in which silane, phosphine, methane, and hydrogen are introduced, a glow light is turned on, and a carbon-doped N-type polycrystalline silicon layer is formed by a chemical reaction. The reaction temperature in the second stage is 400° C., the reaction time is 100 s, the reaction pressure is 500 mtorr, the thickness of the carbon-doped N-type third doped polycrystalline layer 15 is 10 nm, and the effective phosphorus doping concentration is 2e19 cm -3 , the effective carbon doping concentration is 1e19cm -3 , the band gap width is 2.0eV.

[0095] The effective phosphorus doping concentration of the first doped polysilicon layer makes the ratio of the surface doping index of the third doped polysilicon layer to the first doped polysilicon layer be 10:1, wherein the surface doping index is the ratio of the effective phosphorus doping concentration of the corresponding doped layer to the thickness of the doped layer.

[0096] The first semiconductor layer and the third semiconductor layer are subjected to low-pressure annealing, with an annealing pressure of 2000 mtorr, an annealing temperature of 900° C., and an annealing time of 10 minutes.

[0097] An anti-reflection layer 16 (specifically a silicon nitride layer) is deposited on the surface of the third semiconductor layer using tubular PECVD deposition to a thickness of 700 nm. The silicon wafer is then cleaned to remove the backside coating.

[0098] S106. As shown in FIG6 , a second semiconductor layer is deposited on the back side of the silicon wafer by PECVD technology. The second semiconductor layer comprises an intrinsic amorphous silicon layer 17 and a P-type doped amorphous silicon layer 18. The intrinsic amorphous silicon layer 17 has a thickness of 10 nm, the P-type doped amorphous silicon layer 18 has a thickness of 10 nm, and the effective boron doping concentration in the P-type doped amorphous silicon layer 18 is 1e19 cm -3 .

[0099] S107. As shown in FIG7 , a second laser etching is performed on the back surface of silicon wafer 10. The laser is an ultraviolet laser with a pulse width of 10 ns. This forms a first semiconductor opening region Wn spaced apart from the second semiconductor opening region Wp, and then cleans the first semiconductor opening region Wn. The width of the first semiconductor opening region Wn is 0.1 mm. The second semiconductor layer on the upper surface of the first semiconductor opening region Wn is removed by etching.

[0100] S108 , as shown in FIG8 , a transparent conductive film 19 is deposited on the back of the silicon wafer 10 using physical vapor deposition (PVD) technology. The transparent conductive film 19 has a thickness of 40 nm and is made of a gallium oxide-doped indium oxide thin film.

[0101] S109. Using a masked etching method, an opening is etched on the surface of the isolation region Wg on the back of the silicon wafer 10 to form an insulating trench Wi between the first semiconductor opening region and the second semiconductor opening region. The width of Wi is 50 μm, and the resistance between the first semiconductor opening region and the second semiconductor opening region after etching is greater than 1 kΩ. The conditions for forming the masked etching include: as shown in Figures 9a and 9b, first printing an acid-resistant mask material 20 on the back of the silicon wafer 10 to form an insulating trench pattern, then cleaning with an acid solution to remove the transparent conductive film 19 in the opening region of the acid-resistant mask material, and then cleaning with an ink cleaning agent to remove the acid-resistant mask material. The acid solution is hydrochloric acid, and the cleaning agent is sodium hydroxide.

[0102] S110 , as shown in FIG10 , using screen printing technology, a first metal electrode 21 n is formed on the surface of the first semiconductor opening region Wn on the back side of the silicon wafer 10 , and a second metal electrode 21 p is formed on the surface of the second semiconductor opening region Wp.

[0103] Example 2

[0104] The method of Example 1 is followed, except that the thickness of the second tunnel oxide layer is increased to 5 nm so that the ratio of the thickness of the second tunnel oxide layer to the thickness of the carbon-doped third doped polycrystalline layer is 1:2; and the effective phosphorus doping concentration of the third doped polycrystalline layer is reduced to 1e19 cm -3 , the effective carbon doping concentration remains unchanged. In order to achieve the doping concentration adjustment, the process conditions that need to be changed accordingly are: the annealing temperature is adjusted to 910℃.

[0105] Example 3

[0106] The method of Example 2 is carried out, except that the thickness and doping concentration of the third doped polycrystalline layer are adjusted. Specifically, the thickness of the third doped polycrystalline layer is 8 nm, and the effective phosphorus doping concentration is 8e18 cm -3 , the effective carbon doping concentration is 1e19cm -3 In order to achieve the thickness and doping concentration adjustment, the process conditions that need to be changed accordingly are: the annealing temperature is adjusted to 880℃.

[0107] Example 4

[0108] The method of Example 2 is carried out, except that the thickness and doping concentration of the third doped polycrystalline layer are adjusted. Specifically, the thickness of the third doped polycrystalline layer is 4 nm, and the effective phosphorus doping concentration is 6e18 cm -3, the effective carbon doping concentration is 1e19cm -3 In order to achieve the thickness and doping concentration adjustment, the process conditions that need to be changed accordingly are: adjusting the annealing temperature to 850℃.

[0109] Example 5

[0110] The method of Example 2 is carried out, except that the thickness and doping concentration of the third doped polycrystalline layer are adjusted. Specifically, the thickness of the third doped polycrystalline layer is 12 nm, and the effective phosphorus doping concentration is 8e19 cm -3 , the effective carbon doping concentration is 1e19cm -3 In order to achieve the thickness and doping concentration adjustment, the process conditions that need to be changed accordingly are: adjusting the annealing temperature to 920℃.

[0111] Example 6

[0112] The method of Example 1 is followed, except that the third doped polycrystalline layer is oxygen-doped instead of carbon-doped as in Example 1. The corresponding process is adjusted as follows: methane in the gas introduced in the second stage is replaced by carbon dioxide, and the effective oxygen doping concentration is 1e19cm -3 , the band gap width is 2.05eV.

[0113] Example 7

[0114] The method of Example 2 is referred to, except that the effective phosphorus doping concentration of the first doped polysilicon layer is adjusted so that the ratio of the surface doping index of the third doped polysilicon layer to the first doped polysilicon layer is 2:1, wherein the surface doping index is the ratio of the effective phosphorus doping concentration of the corresponding doping layer to the thickness of the doping layer.

[0115] Comparative Example 1

[0116] The method of Example 1 is referred to, except that the conventional two-annealing process is used. Specifically, in S102, after the tubular PECVD in-situ doping deposition, the first annealing is performed. The conditions of the first annealing are an annealing pressure of 2000 mtorr, an annealing temperature of 900°C, and an annealing time of 10 min. In S105, after the third semiconductor layer is in-situ doped by tubular PECVD, a second annealing is performed. The process conditions of the second annealing are the same as those of Example 1 except that the thickness of the second tunnel oxide layer is 1 nm.

[0117] Comparative Example 2

[0118] The method of Example 1 is referred to, except that the thickness of the second tunnel oxide layer in S105 is 1 nm. In order to adjust the thickness, the process conditions that need to be changed accordingly are: the annealing temperature is 820°C.

[0119] Comparative Example 3

[0120] The method of Example 1 is referred to, except that the annealing temperature of the low-pressure annealing in S105 is 800°C.

[0121] Test Case

[0122] The combined passivated back contact cells obtained in the above examples and comparative examples were subjected to unified tests on corresponding performances, and the results are shown in Table 1.

[0123] Table 1

[0124] The above results show that, compared to the comparative example, the embodiment of the present application can ensure the passivation level while improving the crystallinity of the polysilicon layer, reducing absorption, and facilitating the increase of open circuit voltage and short circuit current, thereby further improving the battery conversion efficiency. Furthermore, according to the comparison between Example 2 and Examples 3-5, it can be seen that the preferred solution of the present application can maintain a high level of open circuit voltage and short circuit current, further improving the battery conversion efficiency.

[0125] The preferred embodiments of the present application are described in detail above, but the present application is not limited thereto. Within the technical concept of the present application, various simple modifications can be made to the technical solution of the present application, including combining the various technical features in any other appropriate manner. These simple modifications and combinations should also be regarded as the contents disclosed in the present application and fall within the scope of protection of the present application. Industrial Applicability

[0126] The present application increases the thickness of the second tunnel oxide layer arranged on the front side to 4-6nm, and cooperates with a third doped polycrystalline layer doped with carbon and / or oxygen, so that the short-circuit current is improved while ensuring the passivation level of the front side, and is more resistant to high temperatures. It can be annealed together with the thicker first doped polysilicon layer on the back side, and only one annealing is performed throughout the process, which greatly reduces the equipment cost and significantly reduces the damage to the first doped polysilicon layer caused by two annealings, thereby improving the open circuit voltage and fill factor; and the third doped polycrystalline layer arranged on the front side is combined with the use of a suitable high temperature annealing in one annealing to improve the short-circuit current of the battery. The thicker second tunnel oxide layer is resistant to high temperatures and will not be affected by the adverse effects such as passivation loss caused by annealing at this high temperature, thereby helping to take into account the improvement of the short-circuit current and battery conversion efficiency of the battery, and thus is conducive to promotion and application in industry.

Claims

1. A single annealing method for preparing a combined passivation back contact cell, characterized in that: The following steps are involved: S101, provide double-sided polished and cleaned silicon wafers; S102, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer, the first semiconductor layer comprising a first tunneling silicon oxide layer and a first doped polysilicon layer, the formation process of the first semiconductor layer comprising a first in-situ doping deposition without annealing; the thickness of the first tunneling silicon oxide layer is 1-2 nm, and the thickness of the first doped polysilicon layer is 150-300 nm; S103, performing a first etching opening on the back surface obtained in S102 to form a second semiconductor opening region; S104, then performing texturing and cleaning to remove the remaining mask layer and the first semiconductor layer in the second semiconductor opening region, and forming a texture surface on the front side of the silicon wafer and the second semiconductor opening region; then performing cleaning to remove the mask layer on the back side outside the second semiconductor opening region; S105, then forming a third semiconductor layer on the front side of the silicon wafer, the third semiconductor layer comprising a second tunneling oxide layer and a third doped polycrystalline layer doped with carbon and / or oxygen, the formation process of the third semiconductor layer comprising a second in-situ doping deposition; the second tunneling oxide layer is thickened and has a thickness of 4-6 nm, and the thickness of the third doped polycrystalline layer doped with carbon and / or oxygen is 4-15 nm; After the second in-situ doping deposition, the first semiconductor layer and the third semiconductor layer are subjected to a first annealing at low pressure, wherein the conditions of the first annealing include: an annealing pressure of 2000 mtorr to 1 atm, an annealing temperature of 850-950° C., and an annealing time of 10-60 min; Then, an anti-reflection layer is deposited on the surface of the third semiconductor layer; and then, the back side coating is removed by cleaning; S106 , then depositing a second semiconductor layer on the back surface obtained in S105 , wherein the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped crystalline silicon layer.

2. The one-time annealing preparation method of the combined passivation back contact cell according to claim 1, characterized in that: The thickness ratio of the second tunneling oxide layer to the third carbon-doped and / or oxygen-doped polycrystalline layer is 1:0.8-3.

3. The one-time annealing method for preparing a combined passivation back contact cell according to claim 1 or 2, characterized in that: S105 also includes: as the second tunnel oxide layer thickens, the thickness of the third doped polycrystalline layer is reduced and / or the effective phosphorus doping concentration is reduced, and the thickness of the third doped polycrystalline layer and the effective phosphorus doping concentration are adjusted to meet the following conditions: for every 1nm thickening of the second tunnel oxide layer, the thickness of the third doped polycrystalline layer is reduced by 1-6nm, and / or the effective phosphorus doping concentration is reduced by 20%-50%.

4. The one-time annealing method for preparing a combined passivation back contact cell according to claim 3, characterized in that: S105 also includes: as the second tunnel oxide layer thickens, the thickness of the third doped polycrystalline layer is reduced and / or the effective phosphorus doping concentration is reduced, and the thickness of the third doped polycrystalline layer and the effective phosphorus doping concentration are adjusted to meet the following conditions: for every 1nm thickening of the second tunnel oxide layer, the thickness of the third doped polycrystalline layer is reduced by 1-2nm, and / or the effective phosphorus doping concentration is reduced by 35%-50%.

5. The one-time annealing method for preparing a combined passivation back contact cell according to claim 3, characterized in that: The ratio of the surface doping index of the third doped polycrystalline layer doped with carbon and / or oxygen to the first doped polycrystalline silicon layer is 5-15:1, wherein the surface doping index is the ratio of the effective phosphorus doping concentration of the corresponding doped layer to the thickness of the doped layer.

6. The one-time annealing method for preparing a combined passivation back contact cell according to claim 5, characterized in that: The effective phosphorus doping concentration of the first doped polysilicon layer is 1e19-8e21cm -3 The effective phosphorus doping concentration of the carbon-doped and / or oxygen-doped third doped polycrystalline layer is 5e18-5e20cm -3 .

7. The one-time annealing method for preparing a combined passivation back contact cell according to any one of claims 1 to 6, characterized in that: The third doped polycrystalline layer is doped with carbon and its effective carbon doping concentration is 1e19-4e21cm -3 ; And / or, the third doped polycrystalline layer is doped with oxygen and its effective oxygen doping concentration is 1e19-3e20cm -3 .

8. The one-time annealing method for preparing a combined passivation back contact cell according to any one of claims 1 to 7, characterized in that: The band gap width of the third doped polycrystalline layer is 1.9-2.3 eV.

9. The one-time annealing method for preparing a combined passivation back contact cell according to any one of claims 1 to 8, characterized in that: The one-time annealing preparation method further comprises: S107, then performing a second etching opening on the back surface obtained in S106 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, followed by cleaning; forming an isolation region between the second semiconductor opening region and the first semiconductor opening region; S108, depositing a transparent conductive film on the back surface obtained in S107; S109, then performing a third etching opening at the isolation region to form an insulating groove located between the second semiconductor opening region and the first semiconductor opening region; S110, forming a first metal electrode on the surface of the first semiconductor opening region on the back side obtained in S109, and forming a second metal electrode on the surface of the second semiconductor opening region.

10. A combined passivation back contact cell, characterized in that: It is prepared by the single annealing preparation method as described in any one of claims 1 to 9.

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