Computing device and computing chip

Abstract

The present application relates to the technical field of computers, and provides a computing device and a computing chip. The computing device may comprise a digital-to-analog conversion module, an analog computation module and an analog-to-digital conversion module. The digital-to-analog conversion module can be used for converting a mantissa part of an input floating point number into an initial analog signal, and performing gain adjustment on the initial analog signal on the basis of an exponent part of the input floating point number to obtain an input analog signal; the analog computation module can be used for carrying out analog computation on the basis of the input analog signal to obtain a computation result analog signal; and the analog-to-digital conversion module can be used for converting the computation result analog signal into a result floating point number. The computing device converts the input floating point number into the input analog signal, performs floating point number computation in an analog domain, and can improve the computation efficiency of floating point computation compared with floating point number computation in a digital domain.

Description

Computing device and computing chip

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on October 27, 2023, with application number 202311429893.7 and application name "A Computing Device and Computing Chip", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a computing device and a computing chip. Background Art

[0004] In computer systems, floating point (FP) is an approximate numerical representation of real numbers. A real number can be represented by a significand plus a power. The significand is called the mantissa, and the power represents an integer power of a base, which is called the exponent. In other words, the significand multiplied by the integer power of a base yields a real number. Values ​​represented by floating point are called floating-point numbers or floating-point numbers.

[0005] Floating-point calculations are operations performed using floating-point numbers, and they typically include multiplication and addition. Currently, floating-point calculations are typically implemented in the digital domain. Multiplication in the digital domain requires adding the exponents of two floating-point numbers and multiplying their mantissas. Addition requires comparing the exponents of the two floating-point numbers, aligning the mantissas based on the comparison results, and then adding the two mantissas together. This floating-point calculation process in the digital domain is inefficient.

[0006] Summary of the Invention

[0007] The present application provides a computing device and a computing chip, which can improve the operational efficiency of floating-point calculations by converting floating-point numbers into analog signals and performing floating-point calculations in the analog domain.

[0008] In a first aspect, the present application provides a computing device that can be applied to a computing chip and can include a digital-to-analog conversion module, an analog computing module, and an analog-to-digital conversion module. The digital-to-analog conversion module can be used to convert the mantissa of an input floating-point number into an initial analog signal, and based on the exponent of the input floating-point number, perform gain adjustment on the initial analog signal to obtain an input analog signal; the analog computing module can be used to perform analog computing based on the input analog signal to obtain a computation result analog signal; and the analog-to-digital conversion module can be used to convert the computation result analog signal into a result floating-point number.

[0009] The computing device provided by the present application converts an input floating-point number into an input analog signal and performs floating-point calculations in the analog domain. Compared with performing floating-point calculations in the digital domain, the computing efficiency of floating-point calculations can be improved. At the same time, performing floating-point calculations in the analog domain is beneficial to reducing the power consumption of the computing device. In addition, when converting the input floating-point number into an input analog signal, the digital-to-analog conversion module first processes the mantissa of the input floating-point number and converts the mantissa of the input floating-point number into an initial analog signal. Then, based on the exponent of the input floating-point number, the initial analog signal is gain-adjusted in the analog domain to obtain the input analog signal. When the exponent of the input floating-point number is different, the gain multiples when the gain adjustment is performed on the initial analog signal are different, and the size of the input analog signal obtained is also different, so that multiple input floating-point numbers with different exponents can be converted into multiple input analog signals of different sizes, and floating-point calculations can be performed on multiple input floating-point numbers with different exponents in the analog domain, thereby expanding the scope of application of analog calculations.

[0010] The computing device provided in this application can be applied to the training or inference process of neural network models in the field of artificial intelligence. During the training or inference process of neural network models, large amounts of data are usually required for calculation, and convolution calculations include multiplication and addition operations. The simulation calculation module can perform simulation calculations on multiple data simultaneously in the simulation domain, which can significantly improve the efficiency of floating-point calculations.

[0011] In one possible implementation, the digital-to-analog conversion module may include a signal conversion unit and a mantissa output unit. The signal conversion unit may be configured to determine a voltage value corresponding to the mantissa of a resulting floating-point number based on a calculation result analog signal and output the exponent of the resulting floating-point number. The mantissa output unit may be configured to output the mantissa of the resulting floating-point number based on the voltage value corresponding to the mantissa of the resulting floating-point number.

[0012] In the above implementation, when converting the calculation result analog signal into the result floating-point number, the exponent part and the mantissa part of the result floating-point number are determined based on the calculation result analog signal, which helps to complete the floating-point calculation in the analog domain.

[0013] In one possible implementation, the calculation result analog signal may be an output current analog signal. The signal conversion unit may include a first conversion unit and a first dynamic adjustment unit. The first conversion unit may be configured to convert the output current analog signal into a voltage signal; the first dynamic adjustment unit may be configured to adjust a conversion ratio parameter of the first conversion unit for the output current analog signal based on changes in the voltage signal; the conversion ratio parameter is configured to represent the exponent portion of the resulting floating-point number; and the voltage signal output by the first conversion unit is configured to represent the voltage value corresponding to the mantissa portion of the resulting floating-point number.

[0014] In the above implementation, by detecting the voltage signal output by the first conversion unit, the first dynamic adjustment unit can timely adjust the conversion ratio parameter of the first conversion unit for the output current analog signal, and determine the exponent part of the result floating-point number according to the final conversion ratio parameter, and when the conversion ratio parameter is determined, the mantissa part of the result floating-point number is determined according to the voltage signal output by the first conversion unit, so that different result floating-point numbers can be obtained according to the different sizes of the output current analog signal, and the conversion from the calculation result analog signal to the result floating-point number in the digital domain is completed, so that the dynamic range of the result floating-point number read out based on different calculation result analog signals can be adaptively adjusted to support reading result floating-point numbers with different exponents.

[0015] In a possible implementation, the signal conversion unit may include a first quantization unit in addition to the first conversion unit and the first dynamic adjustment unit, wherein the first conversion unit is an active integration unit.

[0016] The active integration unit can be used to integrate the output current analog signal within a set time period to obtain a first voltage; the first quantization unit can be used to transmit a control signal to the first dynamic adjustment unit based on the change of the first voltage within the set time period; the first dynamic adjustment unit can be used to adjust the conversion ratio parameter of the active integration unit for the output current analog signal based on the control signal from the first quantization unit within the set time period.

[0017] The first quantization unit can also be used to determine the voltage value corresponding to the mantissa of the resulting floating-point number based on the first voltage output by the active integration unit at the arrival time of the set time length; the first dynamic adjustment unit can also be used to output the exponential part of the resulting floating-point number based on the conversion ratio parameter of the active integration unit for the output current analog signal at the arrival time of the set time length.

[0018] In the above implementation, the process of converting the output current analog signal into a result floating-point number can be divided into an adaptive stage and a quantization stage, wherein the stage within the set time length is the adaptive stage, and the stage after the set time length is the quantization stage. In the adaptive stage, the analog-to-digital conversion module can integrate the output current analog signal through the active integration unit and convert the output current analog signal into a first voltage. By detecting the first voltage output by the active integration unit, the first dynamic adjustment unit can timely adjust the conversion ratio parameter of the active integration unit to the output current analog signal until the set time length is reached. In the quantization stage, the first dynamic adjustment unit determines the exponential part of the result floating-point number based on the final conversion ratio parameter. When the first quantization unit is determined based on the conversion ratio parameter, the first voltage output by the active integration unit determines the mantissa part of the result floating-point number, so that different result floating-point numbers can be obtained according to the different sizes of the output current analog signal, completing the conversion from the calculation result analog signal to the result floating-point number.

[0019] Exemplarily, the active integration unit may include an integrator, and the integrator may be configured to receive the output current analog signal and output the first voltage based on the output current analog signal.

[0020] The first quantization unit may include a first comparator, wherein the first input terminal of the first comparator is connected to the output terminal of the integrator for receiving the first voltage output by the integrator, and the second input terminal of the first comparator is used to connect to a ramp signal generating circuit, and the ramp signal generating circuit is used to provide a constant voltage to the first comparator within a set time length, and after reaching the set time length, provide the first comparator with a ramp voltage that changes at a set rate.

[0021] The first dynamic adjustment unit includes multiple capacitor branches, the first end of each of the multiple capacitor branches is connected to the input end of the integrator, and the second end is connected to the output end of the integrator, and each capacitor branch is connected to a trigger, and the input end of each trigger is connected to the output end of the first comparator, and is used to control the corresponding capacitor branch to be connected or disconnected under the action of the control signal output by the first comparator, so as to adjust the conversion ratio parameter of the active integration unit for the output current analog signal.

[0022] In another possible implementation, the signal conversion unit may include a second quantization unit in addition to the first conversion unit and the first dynamic adjustment unit, wherein the first conversion unit is an operational amplifier unit.

[0023] The operational amplifier unit may be configured to output a second voltage based on the output current analog signal. The first dynamic adjustment unit may be configured to adjust a conversion ratio parameter of the operational amplifier unit for the output current analog signal based on a change in the second voltage until a change in the second voltage is less than or equal to a first set amplitude threshold.

[0024] The second quantization unit may be configured to determine a voltage value corresponding to the mantissa of the resulting floating-point number based on the second voltage having a variation amplitude less than or equal to the first set amplitude threshold. The first dynamic adjustment unit may also be configured to output an exponent of the resulting floating-point number based on a conversion ratio parameter of the output current analog signal of the operational amplifier unit when the variation amplitude of the second voltage is less than or equal to the first set amplitude threshold.

[0025] In the above implementation, the process of converting the output current analog signal into a result floating-point number can be divided into an adaptive stage and a quantization stage. In the adaptive stage, the operational amplifier unit can output a second voltage based on the output current analog signal. By detecting the second voltage output by the operational amplifier unit, the first dynamic adjustment unit can timely adjust the conversion ratio parameter of the operational amplifier unit to the output current analog signal until the change amplitude of the second voltage is less than or equal to the first set amplitude threshold, and the adaptive stage ends. In the quantization stage, the first dynamic adjustment unit can determine the exponent part of the result floating-point number based on the final determined conversion ratio parameter for the output current analog signal. The second quantization unit can determine the mantissa part of the result floating-point number based on the second voltage output by the operational amplifier unit when the conversion ratio parameter is determined, so that different result floating-point numbers can be obtained according to the different sizes of the output current analog signal, completing the conversion from the calculated result analog signal to the result floating-point number. This implementation supports reading result floating-point numbers with different exponent parts.

[0026] In a possible implementation, the operational amplifier unit may include a first operational amplifier, and the first operational amplifier is configured to receive the output current analog signal and output the second voltage.

[0027] The first dynamic adjustment unit may include a second comparator, a plurality of triggers, and a plurality of switch resistor branches. A first input of the second comparator is connected to the output of the first operational amplifier and is configured to receive a second voltage output by the first operational amplifier. A second input of the second comparator is configured to input a reference voltage, and the second comparator is configured to output a control signal based on a change in the second voltage.

[0028] A first end of each of the plurality of switch resistance branches is connected to the input end of the first operational amplifier, and a second end of each of the switch resistance branches is connected to the output end of the first operational amplifier.

[0029] The input ends of the above-mentioned multiple triggers are all connected to the output end of the second comparator, and the output end of each trigger in the multiple triggers is connected to the corresponding switch resistance branch in the multiple switch resistance branches, and is used to control the corresponding switch resistance branch to be connected or disconnected under the action of the control signal output by the second comparator, so as to adjust the conversion ratio parameter of the operational amplifier unit for the output current analog signal.

[0030] In the above implementation, since the second voltage output by the first operational amplifier stabilizes immediately after the RC response effect occurs each time the conversion ratio parameter of the output current analog signal is adjusted, there is no need to set a set duration for the adaptive phase. Instead, it is sufficient to ensure that the second voltage output by the first operational amplifier has reached a stable state. This implementation does not rely on the accuracy of the set duration, but rather on the stabilization of the voltage output by the first operational amplifier, thereby improving the accuracy of the floating-point result read.

[0031] In another possible implementation, the operational amplifier unit may include an operational amplifier negative feedback circuit, multiple transistor branches, and a current-voltage converter. The operational amplifier negative feedback circuit is configured to receive an output current analog signal, the multiple transistor branches are connected between an output terminal of the operational amplifier negative feedback circuit and an input terminal of the current-voltage converter, and the current-voltage converter is configured to convert the current signal output by the multiple transistor branches into a second voltage.

[0032] The first dynamic adjustment unit may include a third comparator and multiple triggers. The first input of the third comparator is connected to the output of the current-voltage converter and is configured to receive the second voltage output by the operational amplifier unit. The second input of the third comparator is configured to input a reference voltage. The inputs of the multiple triggers are each connected to the output of the third comparator, and the output of each of the multiple triggers is connected to a corresponding transistor branch in the multiple transistor branches. The control signal output by the third comparator controls the connection or disconnection of the corresponding transistor branch to adjust the conversion ratio parameter of the operational amplifier unit for the output current analog signal.

[0033] In the above implementation, since the current signals output by the multiple transistor branches immediately stabilize with each adjustment of the conversion ratio parameter for the output current analog signal, there is no need to set a set duration for the adaptive phase. Instead, it is sufficient to ensure that the second voltage converted from the current signals output by the multiple transistor branches has reached a stable state. This implementation does not rely on the accuracy of the set duration, but rather on the stabilization of the current signals output by the multiple transistor branches, thereby improving the accuracy of the floating-point number read out.

[0034] In one possible implementation, the calculation result analog signal may be an output optical analog signal. The signal conversion unit may include a first photoelectric conversion unit and an electrical-to-digital conversion unit. The first photoelectric conversion unit may be configured to convert the output optical analog signal into an output current analog signal; the electrical-to-digital conversion unit may be configured to determine a voltage value corresponding to the mantissa of the result floating-point number based on the output current analog signal, and output the exponent of the result floating-point number.

[0035] In the above implementations, when the computation result analog signal is an output optical analog signal, the first photoelectric conversion unit can first convert the output optical analog signal into an output current analog signal, which is then processed by the electrical-to-digital conversion unit. The electrical-to-digital conversion unit can be implemented by referring to the method for converting the output current analog signal into a result floating-point number provided in any of the above implementations. This implementation can complete the conversion from the output optical analog signal to the result floating-point number, making floating-point computations applicable to optical computing scenarios.

[0036] In one possible implementation, the calculation result analog signal may be an output optical analog signal. The signal conversion unit may include a second photoelectric conversion unit, a current-to-voltage conversion unit, a second dynamic adjustment unit, and a third quantization unit. The second photoelectric conversion unit may be configured to output a current signal based on the output optical analog signal; the current-to-voltage conversion unit may be configured to output a third voltage based on the current signal output by the second photoelectric conversion unit; and the second dynamic adjustment unit may be configured to adjust a conversion ratio parameter of the second photoelectric conversion unit for the output optical analog signal based on a change in the third voltage until the change in the third voltage is less than or equal to a second set amplitude threshold. The third quantization unit may be configured to determine a voltage value corresponding to the mantissa of a result floating-point number based on the third voltage having a change in amplitude less than or equal to the second set amplitude threshold. The second dynamic adjustment unit may also be configured to output an exponent of a result floating-point number based on the conversion ratio parameter of the second photoelectric conversion unit for the output optical analog signal when the change in the third voltage is less than or equal to the second set amplitude threshold.

[0037] In a possible implementation, when the second dynamic adjustment unit detects that the third voltage reaches a set voltage value, it can adjust the conversion ratio parameter of the second photoelectric conversion unit for the output optical analog signal by adjusting the bias voltage of the second photoelectric conversion unit.

[0038] In the above implementation, the process of converting the output optical analog signal into a floating-point result can be divided into an adaptive phase and a quantization phase. In the adaptive phase, the second photoelectric conversion unit can convert the output optical analog signal into a current signal, which is then converted into a third voltage by the current-to-voltage conversion unit. By detecting the third voltage output by the current-to-voltage conversion unit, the second dynamic adjustment unit can adjust the second photoelectric conversion unit's conversion ratio parameter for the output optical analog signal in a timely manner by adjusting the bias voltage of the second photoelectric conversion unit until the amplitude of the change in the third voltage is less than or equal to the second set amplitude threshold, at which point the adaptive phase ends. In the quantization phase, the second dynamic adjustment unit can determine the exponent portion of the floating-point result based on the finalized conversion ratio parameter for the output optical analog signal. When the conversion ratio parameter is determined, the second quantization unit can determine the mantissa portion of the floating-point result based on the third voltage output by the current-to-voltage conversion unit, thereby obtaining different floating-point result numbers based on the different magnitudes of the output optical analog signal, thus completing the conversion from the calculated analog signal to the floating-point result.

[0039] In one possible implementation, the digital-to-analog conversion module may include a mantissa conversion unit and a gain adjustment unit. The mantissa conversion unit may be configured to convert the mantissa portion of an input floating-point number into an initial analog signal; and the gain adjustment unit may be configured to perform gain adjustment on the initial analog signal based on the exponent portion of the input floating-point number to obtain the input analog signal.

[0040] In one possible implementation, the input analog signal may be an input voltage analog signal, and the initial analog signal may be an initial voltage analog signal. The mantissa conversion unit may include a gating unit and a reference unit. The reference unit may be configured to provide a differential voltage to the gating unit; the gating unit may be configured to convert the mantissa portion into the initial voltage analog signal based on the differential voltage provided by the reference unit.

[0041] In the above implementation, the gating unit can convert mantissa parts of different sizes into initial voltage analog signals of different sizes based on the equidistant voltage provided by the reference unit.

[0042] In one possible implementation, the gain adjustment unit may include a second operational amplifier and multiple feedback resistor branches. The first input of the second operational amplifier is connected to the output of the gating unit, and the second input of the first operational amplifier is connected to a reference resistor. The first ends of the multiple feedback resistor branches are each connected to the second input of the second operational amplifier, and the second ends of the multiple feedback resistor branches are each connected to the output of the second operational amplifier. The multiple feedback resistor branches connect some or all of the feedback resistor branches based on the exponential portion of the input floating-point number, and gain-adjust the initial voltage analog signal output by the gating unit to obtain the input voltage analog signal.

[0043] In the above implementation, the gain adjustment unit receives the exponential portion of the input floating-point number via multiple feedback resistor branches. Based on the exponential portion of the input floating-point number, some or all of the feedback resistor branches are connected to perform gain adjustment on the initial voltage analog signal output by the gating unit. When the exponential portions received by the multiple feedback resistor branches differ, the gain multipliers applied to the initial voltage analog signal output by the gating unit also differ. Thus, different input voltage analog signals can be obtained for input floating-point numbers with exponential portions of different sizes.

[0044] In a possible implementation, the analog computing module may use a resistive random access memory (RRAM) array.

[0045] In the above implementation, the analog computing module uses an RRAM array. The RRAM array can perform multiplication operations using Ohm's law and addition operations using Kirchhoff's law. This allows for rapid multiplication and addition operations, improving computational efficiency and reducing power consumption compared to floating-point calculations performed in the digital domain.

[0046] In a possible implementation, the input analog signal may be an input current analog signal, the initial analog signal may be an initial current analog signal, and the mantissa conversion unit may adopt a current mirror structure.

[0047] The current mirror structure may include a reference transistor and a plurality of output transistor branches. The plurality of output transistor branches may be configured to receive a mantissa portion of an input floating-point number and output an initial current analog signal.

[0048] In the above implementation, the mantissa of an input floating-point number is converted into an initial current analog signal using a current mirror structure. The current mirror structure receives the mantissa of the floating-point number through multiple output transistor branches and switches on some or all of the output transistor branches based on the mantissa of the input floating-point number. When the multiple output transistor branches receive different exponents, the gain multiples of the initial voltage analog signal output by the gating unit also differ, and the magnitude of the initial current analog signal output by the current mirror structure also differs. This allows mantissas of varying sizes to be converted into initial voltage analog signals of varying sizes.

[0049] In one possible implementation, the mantissa of the input floating-point number may include N bits. The current mirror structure may include N output transistor branches. Each of the N output transistor branches may be configured to receive one of the N bits.

[0050] In another possible implementation, the mantissa portion of the input floating-point number may include N bits. The current mirror structure may include M output transistor branches, and the M output transistor branches may be used to receive a thermometer code converted from the N bits of the mantissa portion, where the thermometer code may include M bits.

[0051] In one possible implementation, the gain adjustment unit may include multiple switch-controlled transistor branches. The multiple switch-controlled transistor branches may be configured to provide multiple gain adjustment coefficients, the multiple switch-controlled transistor branches being configured to determine a target gain adjustment coefficient based on an exponential portion of an input floating-point number, and to gain adjust an initial current analog signal using the target gain adjustment coefficient to obtain an input current analog signal.

[0052] In the above implementation, the gain adjustment unit may include multiple switch-controlled transistor branches, each of which may provide a gain adjustment coefficient, with different switch-controlled transistor branches providing different gain adjustment coefficients. The gain adjustment unit may, based on the exponential portion of the input floating-point number, turn on some or all of the switch-controlled transistor branches to determine a target gain adjustment coefficient, and then, based on the determined target gain adjustment coefficient, perform gain adjustment on the initial current analog signal output by the mantissa conversion unit. When the exponential portions received by the multiple switch-controlled transistor branches are different, the gain adjustment coefficients for the initial current analog signal output by the mantissa conversion unit are also different, thereby obtaining input current analog signals of different sizes for input floating-point numbers with exponential portions of different sizes.

[0053] In one possible implementation, the analog computing module may use a flash memory transistor array.

[0054] In the above implementation, the analog calculation module may use a flash memory transistor array, and the flash memory transistor array performs floating-point number calculations through analog calculations, thereby increasing the applicability of analog calculations.

[0055] In one possible implementation, the input analog signal may be an input optical analog signal. The digital-to-analog conversion module may include a mantissa conversion unit, a gain adjustment unit, and an electro-optical conversion unit. The mantissa conversion unit may be configured to convert the mantissa portion of an input floating-point number into an initial analog signal; the gain adjustment unit may be configured to perform gain adjustment on the initial analog signal based on the exponent portion of the input floating-point number to obtain an input electrical analog signal; and the electro-optical conversion unit may be configured to convert the input electrical analog signal into an input optical analog signal.

[0056] In the above implementations, the digital-to-analog conversion module can convert input floating-point numbers into input optical analog signals, and perform floating-point calculations using optical computing. The mantissa conversion unit can be implemented with reference to the mantissa conversion unit in the above implementations, and the gain adjustment unit can be implemented with reference to the gain adjustment unit in the above implementations.

[0057] In one possible implementation, the analog computing module uses an optical computing link.

[0058] In the above implementation, the analog computing module may use an optical computing link, which completes floating-point number calculations through analog computing, thereby further increasing the applicability of the analog computing.

[0059] In one possible implementation, the computing device may further include an exponential preprocessing module and an exponential postprocessing module. The exponential preprocessing module is connected to the digital-to-analog conversion module, and the exponential postprocessing module is connected to the analog-to-digital conversion module. The exponential preprocessing module may be configured to adjust the exponential portion of multiple floating-point numbers to be processed to obtain multiple input floating-point numbers, and then input the multiple input floating-point numbers into the digital-to-analog conversion module. The exponential postprocessing module may be configured to receive the result floating-point number output by the analog-to-digital conversion module and adjust the exponential portion of the result floating-point number to obtain a target result floating-point number.

[0060] In the above implementation, the exponential preprocessing module can perform exponential preprocessing on floating-point numbers in the digital domain, so that the exponential part of multiple floating-point numbers calculated in a single time can be increased or decreased as a whole, so that the input floating-point numbers can be more suitable for the simulation calculation module, so that the simulation calculation module can output more accurate calculation results, and improve the reliability of the simulation calculation process.

[0061] In one possible implementation, the exponent preprocessing module may be configured to, when the exponents of multiple floating-point numbers to be processed are all less than or equal to a set threshold, increase the exponents of the multiple floating-point numbers to be processed by the same reference value to obtain multiple input floating-point numbers. The reference value is determined based on a maximum value among the exponents of the multiple floating-point numbers to be processed.

[0062] The exponential post-processing module may be used to reduce the exponent part of the resulting floating-point number by the reference value.

[0063] In the above implementation method, when the exponential parts of multiple floating-point numbers to be processed are small, the exponential parts of the multiple floating-point numbers to be processed can be increased as a whole to obtain multiple input floating-point numbers, so that after the analog-to-digital conversion module converts the input floating-point numbers, the input analog signal obtained is relatively large, which can improve the signal-to-noise ratio of the analog calculation process.

[0064] In one possible implementation, the input floating-point numbers may include a first group of input floating-point numbers and a second group of input floating-point numbers. The simulation calculation module may be configured to perform vector multiplication on the first group of input floating-point numbers and the second group of input floating-point numbers. The exponent preprocessing module may be configured to adjust the exponents of a plurality of first floating-point numbers to be processed based on a first value to obtain the first group of input floating-point numbers, and to adjust the exponents of a plurality of second floating-point numbers to be processed based on a second value to obtain the second group of input floating-point numbers.

[0065] The exponential post-processing module may be configured to adjust an exponent portion of the resulting floating-point number based on the first value and the second value.

[0066] In the above implementation, when the first group of input floating-point numbers and the second group of input floating-point numbers are vector multiplied, if the exponent part of the first group of input floating-point numbers is adjusted based on the first numerical value, and the exponent part of the second group of input floating-point numbers is adjusted based on the second numerical value, then when outputting the calculation result, the exponent part of the result floating-point number can be adjusted based on the first numerical value and the second numerical value to obtain an accurate calculation result.

[0067] In a second aspect, the present application provides a computing chip, which may include the computing device provided in the first aspect.

[0068] In a third aspect, the present application provides a floating-point calculation method, which can be applied to the computing device provided in the first aspect or the computing chip provided in the second aspect. The method may include:

[0069] Convert the mantissa of the input floating-point number into the initial analog signal;

[0070] Based on the exponential part of the input floating-point number, the initial analog signal is gain-adjusted to obtain the input analog signal;

[0071] Perform analog calculation based on the input analog signal to obtain a calculation result analog signal;

[0072] Convert the calculated analog signal to a floating-point number.

[0073] In one possible implementation, when converting the calculation result analog signal into a result floating-point number, the voltage value corresponding to the mantissa part of the result floating-point number and the exponent part of the result floating-point number can be determined based on the calculation result analog signal, and then the mantissa part of the result floating-point number can be output based on the voltage value corresponding to the mantissa part of the result floating-point number.

[0074] In a possible implementation, the calculation result analog signal may be an output current analog signal, and the voltage value corresponding to the mantissa of the result floating-point number and the exponent of the result floating-point number may be determined respectively in the following manner:

[0075] Within a set time period, the following steps are executed cyclically: integrating the output current analog signal according to a first proportional parameter to obtain a first voltage, and adjusting the first proportional parameter based on a change in the first voltage;

[0076] Determine the voltage value corresponding to the mantissa of the resulting floating-point number based on the first voltage obtained at the time when the set duration arrives;

[0077] According to the first proportional parameter corresponding to the arrival time of the set duration, the exponential part of the resulting floating-point number is output.

[0078] In another possible implementation, the calculation result analog signal may be an output current analog signal, and the voltage value corresponding to the mantissa of the result floating-point number and the exponent of the result floating-point number may be determined respectively in the following manner:

[0079] The following steps are executed in a loop: converting the output current analog signal into a second voltage according to a second proportional parameter, and adjusting the second proportional parameter based on a change in the second voltage until a change in the second voltage is less than or equal to a set voltage amplitude threshold;

[0080] Determining a voltage value corresponding to the mantissa of the resulting floating-point number based on the second voltage whose variation amplitude is less than or equal to the set voltage amplitude threshold;

[0081] According to the second proportional parameter when the variation of the second voltage is less than or equal to the set voltage amplitude threshold, the exponential part of the resulting floating point number is output.

[0082] In another possible implementation, the calculation result analog signal may be an output current analog signal, and the voltage value corresponding to the mantissa of the result floating-point number and the exponent of the result floating-point number may be determined respectively in the following manner:

[0083] The following steps are performed in a loop: adjusting a first current obtained based on the output current analog signal according to a third proportional parameter, and adjusting the third proportional parameter based on a change in the first current until a change in the first current is less than or equal to a set current amplitude threshold;

[0084] Determine, based on the first current whose variation amplitude is less than or equal to the set current amplitude threshold, a voltage value corresponding to the mantissa of the resulting floating-point number;

[0085] According to the third proportional parameter when the variation amplitude of the first current is less than or equal to the set current amplitude threshold, the exponential part of the resulting floating-point number is output.

[0086] In a possible implementation, the input analog signal may be an input optical analog signal. When converting the input floating-point number into the input analog signal, the input floating-point number may be converted into an input electrical analog signal, and the input electrical analog signal may be converted into an input optical analog signal.

[0087] In one possible implementation, the calculation result analog signal can be an output optical analog signal. After obtaining the output optical analog signal, the voltage value corresponding to the mantissa part of the result floating-point number and the exponent part of the result floating-point number can be determined based on the output optical analog signal, and the mantissa part of the result floating-point number can be output based on the voltage value corresponding to the mantissa part of the result floating-point number.

[0088] In a possible implementation, the voltage value corresponding to the mantissa of the resulting floating-point number and the exponent of the resulting floating-point number may be determined as follows:

[0089] Converting the output optical analog signal into an output current analog signal;

[0090] Based on the output current analog signal, a voltage value corresponding to the mantissa portion of the result floating point number and an exponent portion of the result floating point number are determined.

[0091] In another possible implementation, the voltage value corresponding to the mantissa of the resulting floating-point number and the exponent of the resulting floating-point number may be determined separately in the following manner:

[0092] Looping the following steps: converting the output optical analog signal into a current signal according to a fourth proportional parameter, converting the current signal into a third voltage, and adjusting the fourth proportional parameter based on a change in the third voltage until a change in the third voltage is less than or equal to a set amplitude threshold;

[0093] Determining a voltage value corresponding to the mantissa of the resulting floating-point number based on the third voltage whose variation amplitude is less than or equal to the set amplitude threshold;

[0094] According to the fourth proportional parameter when the variation amplitude of the third voltage is less than or equal to the set amplitude threshold, the exponential part of the resulting floating-point number is output.

[0095] In one possible implementation, the input analog signal may be an input voltage analog signal. When converting the input floating-point number into the input analog signal, the mantissa of the input floating-point number may be converted into an initial voltage analog signal. Based on the exponential part of the input floating-point number, the initial voltage analog signal may be gain-adjusted to obtain the input voltage analog signal.

[0096] In one possible implementation, the input analog signal may be an input current analog signal. When converting the input floating-point number into the input analog signal, the mantissa of the input floating-point number may be converted into an initial current analog signal. Based on the exponential part of the input floating-point number, the initial current analog signal may be gain-adjusted to obtain the input current analog signal.

[0097] In a possible implementation, before converting the input floating-point number into an input analog signal, the floating-point calculation method may further include:

[0098] Get multiple floating-point numbers to be processed;

[0099] The exponent parts of multiple floating-point numbers to be processed are adjusted to obtain multiple input floating-point numbers.

[0100] In a possible implementation, after converting the calculation result analog signal into a result floating-point number, the floating-point calculation method may further include:

[0101] Adjust the exponent of the result floating-point number to obtain the target result floating-point number.

[0102] In one possible implementation, after obtaining multiple floating-point numbers to be processed, if the exponent parts of the multiple floating-point numbers to be processed are all less than or equal to a set threshold, a reference value can be determined based on the maximum value of the exponent parts of the multiple floating-point numbers to be processed; and the exponent parts of the multiple floating-point numbers to be processed are all increased by the reference value.

[0103] In a possible implementation, after the calculation result analog signal is converted into a result floating-point number, the exponent part of the result floating-point number may be reduced by the reference value to obtain a target result floating-point number.

[0104] The technical effects that can be achieved in any of the second to third aspects mentioned above can refer to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] FIG1 is a schematic diagram of the structure of a computing chip provided in an embodiment of the present application;

[0106] FIG2 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0107] FIG3 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0108] FIG4 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0109] FIG5 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0110] FIG6 is a schematic diagram of the circuit structure of a digital-to-analog conversion module provided in an embodiment of the present application;

[0111] FIG7 is a schematic diagram of a circuit structure of an analog computing module provided in an embodiment of the present application;

[0112] FIG8 is a schematic diagram of the circuit structure of another analog computing module provided in an embodiment of the present application;

[0113] FIG9 is a schematic diagram of a circuit structure of an analog-to-digital conversion module provided in an embodiment of the present application;

[0114] FIG10 is a diagram showing voltage changes at different stages of analog-to-digital conversion according to an embodiment of the present application;

[0115] FIG11 is a diagram showing voltage changes at different stages of another analog-to-digital conversion according to an embodiment of the present application;

[0116] FIG12 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0117] FIG13 is a schematic diagram of the circuit structure of another digital-to-analog conversion module provided in an embodiment of the present application;

[0118] FIG14 is a schematic diagram of the circuit structure of another digital-to-analog conversion module provided in an embodiment of the present application;

[0119] FIG15 is a schematic diagram of a circuit structure of a current mirror structure provided in an embodiment of the present application;

[0120] FIG16 is a schematic structural diagram of another analog-to-digital conversion module provided in an embodiment of the present application;

[0121] FIG17 is a schematic diagram of the circuit structure of another analog-to-digital conversion module provided in an embodiment of the present application;

[0122] FIG18 is a schematic diagram of the circuit structure of another analog-to-digital conversion module provided in an embodiment of the present application;

[0123] FIG19 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0124] FIG20 is a schematic diagram of the structure of an optical computing link provided in an embodiment of the present application;

[0125] FIG21 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0126] FIG22 is a schematic structural diagram of another analog-to-digital conversion module provided in an embodiment of the present application;

[0127] FIG23 is a diagram showing a corresponding relationship between a conversion ratio parameter and a bias voltage according to an embodiment of the present application;

[0128] FIG24 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0129] FIG25 is a schematic diagram of a flow chart of an index preprocessing process provided in an embodiment of the present application;

[0130] FIG26 is a flow chart of a floating-point calculation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0131] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The terms used in the implementation methods of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application.

[0132] In the embodiments of the present application, "multiple" refers to two or more. In view of this, in the embodiments of the present application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B and C, then the included ones may be A, B, C, A and B, A and C, B and C, or A, B and C. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0133] Unless otherwise specified, ordinal numbers such as "first" and "second" in the embodiments of the present application are used to distinguish multiple objects and are not used to limit the order, timing, priority or importance of multiple objects.

[0134] Currently, floating point numbers are widely used in computer systems. Usually, a floating point number can be represented by the mantissa and exponent. For example, a floating point number a can be represented as a=m×b e, where b is the base of the number system. In a number system, all floating-point numbers can use the same base, so when storing a floating-point number, there is no need to save the base value separately. In computer systems, binary representation is generally used, that is, b can take the value of 2. In different computer systems, the value of b can be different. For example, b can take the value of 3, 4, or 8. e is the value of the exponent part, which represents the integer power of b. m is the value of the mantissa part. m can be p digits such as ±dd...ddd. p is the precision, which indicates how many bits are used to store the floating-point number. Each digit d in the p digits can be an integer between 0 and b-1, including 0 and b-1. If the first digit of m is a non-zero integer, m can be called a normalized mantissa. To indicate the positive or negative value, some floating-point numbers can also include a separate sign bit s, which represents + or -. For example, in the IEEE-754 standard, a floating-point number can be represented as (-1) s ×m×b e .

[0135] To meet the varying data precision requirements of various businesses, computers support multiple floating-point types, such as single-precision floating point (32-bit) and double-precision floating point (64-bit). Each floating-point type has a different bit width, as shown in Table 1. BF16, also known as brain float16 or b float16, is a new floating-point representation type.

[0136] Table 1

[0137] Calculations performed using floating points can be called floating-point calculations, and floating-point calculations can generally include multiplication and addition. In order to improve the operational efficiency of the floating-point calculation process, an embodiment of the present application provides a computing device. The computing device provided in the embodiment of the present application is applicable to various fields that use floating-point calculations. For example, as shown in Figure 1, the computing device 100 provided in the embodiment of the present application can be applied to a computing chip 10. Exemplarily, the computing chip 10 can be a processor chip, such as a central processing unit (CPU) chip, an image processing unit (GPU) chip, a digital signal processor (DSP) chip, an artificial intelligence (AI) chip, and the like. The computing device 100 can be understood as a computing module in the computing chip 10. In addition to the computing device 100, the computing chip 10 shown in Figure 1 can also include multiple modules such as module A, template B, and module D. Module A, template B, and module D can be understood as functional modules in the computing chip 10.

[0138] For example, in some embodiments, when the computing chip 10 is a CPU chip, module A may be an address translation module, module B may be a memory read module, and module D may be a memory write module. When the computing chip 10 is used to perform floating-point calculations, module A may be used to determine the storage address of a floating-point number, module B may read the floating-point number from the storage address determined by module A, and input the read floating-point number into the computing device 100. The computing device 100 is used to perform floating-point calculations on the input floating-point number to obtain a result floating-point number, and transmit the result floating-point number to module D. Module D may be used to save the result floating-point number into memory.

[0139] The computing chip 10 shown in FIG1 is merely an example and does not constitute a specific limitation on the structure of the computing chip. In other embodiments of the present application, the computing chip may include more or fewer components than shown, or may combine or separate certain components, or may have different component arrangements, and this application does not limit this.

[0140] The internal structure of computing device 100 is shown in FIG2 , and may include a digital-to-analog conversion module 110, an analog calculation module 120, and an analog-to-digital conversion module 130. Specifically, digital-to-analog conversion module 110 may be used to convert an input floating-point number into an input analog signal; analog calculation module 120 may be used to perform analog calculations based on the input analog signal to obtain a calculation result analog signal; and analog-to-digital conversion module 130 may be used to convert the calculation result analog signal into a result floating-point number. Converting the input floating-point number into an input analog signal and performing floating-point calculations in the analog domain can improve computational efficiency. In some embodiments, computing device 100 may include one digital-to-analog conversion module 110, one analog calculation module 120, and one analog-to-digital conversion module 130. In other embodiments, computing device 100 may include multiple digital-to-analog conversion modules 110, and analog calculation module 120 may include multiple input terminals, each of which is connected to a digital-to-analog conversion module. In other embodiments, computing device 100 may include multiple analog-to-digital conversion modules 130, and analog-to-digital conversion module 130 may include multiple output terminals, each of which is connected to an analog-to-digital conversion module.

[0141] In some embodiments, as shown in FIG3 , the computing device 100 provided in an embodiment of the present application can be connected to a digital processing module 200. The digital processing module 200 can transmit floating-point numbers to the digital-to-analog conversion module 110 in the computing device 100. The digital-to-analog conversion module 110 can convert the input floating-point number into an input analog signal such as voltage, current, or light, and transmit the input analog signal to the analog computing module 120. The analog computing module 120 can perform analog computing based on the input analog signal to obtain a calculation result analog signal. The calculation result analog signal can be an analog signal such as voltage, current, or light. The analog computing module 120 transmits the calculation result analog signal to the analog-to-digital conversion module 130. The analog-to-digital conversion module 130 can convert the calculation result analog signal into a floating-point number, and then transmit it to the digital processing module 200, thereby completing the calculation process of the floating-point number.

[0142] When converting the input floating-point number into an input analog signal, the digital-to-analog conversion module 110 can process the mantissa portion of the input floating-point number and the exponent portion of the input floating-point number respectively. As shown in Figure 4, the digital-to-analog conversion module 110 can include a mantissa conversion unit 111 and a gain adjustment unit 112. Among them, the mantissa conversion unit 111 can be used to convert the mantissa portion of the input floating-point number into an initial analog signal, and the gain adjustment unit 112 can be used to perform gain adjustment on the initial analog signal based on the exponent portion of the input floating-point number to obtain the input analog signal. The analog calculation module 120 can perform analog calculation based on the input analog signal to obtain a calculation result analog signal.

[0143] When the analog-to-digital conversion module 130 converts the calculation result analog signal into the result floating-point number, it can determine the mantissa part of the result floating-point number and the exponent part of the result floating-point number respectively according to the calculation result analog signal. The analog-to-digital conversion module 130 can process analog signals with a large dynamic range. For example, taking the analog signal as a current analog signal as an example, there are several current analog signals as follows: [0, 100nA], [0, 400nA], [0, 6.4uA], which have a large dynamic range. The analog-to-digital conversion module 130 represents the current analog signal through floating point. In the floating point representation, these current analog signals can correspond to [0, 100nA] × 2 0 、[0,100nA]×2 2 、[0,100nA]×2 6, thus corresponding to the above-mentioned floating-point domain digital representation, by changing the exponent part of the result floating-point number, a floating-point number is used to represent an analog signal with a large dynamic range. As shown in Figure 4, the analog-to-digital conversion module 130 may include a signal conversion unit 131 and a mantissa output unit 132. Among them, the signal conversion unit 131 can be used to quickly match the proportional parameter corresponding to the calculation result analog signal based on the calculation result analog signal, so that the voltage value corresponding to the mantissa part of the result floating-point number is a value within a fixed dynamic range, and transmit the voltage value corresponding to the mantissa part of the result floating-point number to the mantissa output unit 132, and output the exponent part of the result floating-point number according to the proportional parameter finally matched by the calculation result analog signal; the mantissa output unit 132 can be used to output the mantissa part of the result floating-point number based on the voltage value corresponding to the mantissa part of the result floating-point number.

[0144] In some embodiments, if the calculated analog signal is an output current analog signal, the signal conversion unit may include a first conversion unit and a first dynamic adjustment unit. The first conversion unit may be configured to convert the output current analog signal into a voltage signal; the first dynamic adjustment unit may be configured to adjust a conversion ratio parameter of the first conversion unit for the output current analog signal based on changes in the voltage signal output by the first conversion unit. The conversion ratio parameter is used to represent the exponent portion of the resulting floating-point number, and the voltage signal output by the first conversion unit is used to represent the voltage value corresponding to the mantissa portion of the resulting floating-point number.

[0145] In other embodiments, if the calculation result analog signal is an output optical analog signal, the signal conversion unit may include a first photoelectric conversion unit and an electrical-to-digital conversion unit. The first photoelectric conversion unit may be configured to convert the output optical analog signal into an output current analog signal, and the electrical-to-digital conversion unit may be configured to determine a voltage value corresponding to the mantissa of the result floating-point number based on the output current analog signal, and output the exponent of the result floating-point number.

[0146] The structure of the computing device 100 is described in detail below through several optional specific embodiments, which are described by taking the floating point number base b as 2 as an example. First, the analog computing module 120 is described as an example in which both the input analog signal and the calculation result analog signal are electrical analog signals.

[0147] In a first alternative embodiment, as shown in FIG5 , the analog computing module may utilize a resistive random access memory (RRAM) array 121. The input analog signal of the RRAM array 121 may be a voltage analog signal. In other words, the digital-to-analog conversion module 110 may be configured to convert an input floating-point number into an input voltage analog signal.

[0148] As shown in FIG5 , the digital-to-analog conversion module 110 may include a mantissa conversion unit 113 and a gain adjustment unit 114. The mantissa conversion unit 113 may be used to convert the mantissa portion of the input floating-point number into an initial voltage analog signal. The gain adjustment unit 114 may be used to perform gain adjustment on the initial voltage analog signal based on the exponential portion of the input floating-point number to obtain an input voltage analog signal. The mantissa conversion unit 113 may be implemented by a fixed-point digital-to-analog converter (DAC), or may include a reference unit 1131 and a gating unit 1132, wherein the reference unit 1131 is used to provide an equidistant voltage to the gating unit 1132, and the gating unit 1132 is used to convert the mantissa portion of the input floating-point number into the initial voltage analog signal based on the equidistant voltage provided by the reference unit 1131.

[0149] In some embodiments, the circuit structure of the digital-to-analog conversion module 110 can be as shown in FIG6 , wherein the reference unit 1131 can generate multiple equidistant voltages in the form of resistor voltage division. The reference unit 1131 can include multiple resistors, such as resistors R11 to R1n as shown in FIG6 , wherein the multiple resistors are connected in series, and the resistance values ​​of the multiple resistors are the same. The connection point between two adjacent resistors is used to output a voltage, and the voltage values ​​output by the connection points between different resistors are different, thereby outputting multiple equidistant voltages. The selection unit 1132 can include multiple switch control branches, and the number of switch control branches can be determined according to the number of bits (i.e., precision p) of the mantissa part m of the input floating-point number. Assuming that the number of bits of the mantissa part m of the input floating-point number is 7 bits (bits), namely M0 to M6, the selection unit 1132 can include 7 switch control branches, each switch control branch corresponding to receiving data of one data bit of the mantissa part m of the input floating-point number, and the 7 switch control branches are respectively used to receive data of 7 data bits M0 to M6 of the mantissa part m. Each switch control branch includes a first branch and a second branch. The first branch is configured to receive data bits corresponding to the mantissa m of the input floating-point number, and the second branch is configured to receive data bits corresponding to the mantissa m of the input floating-point number via an inverter. Each of the first and second branches includes at least one switch. The first and second branches of the same switch control branch contain an equal number of switches. Different switch control branches contain a decreasing number of switches as their distance from the reference cell increases. The first and second branches of the switch control branch farthest from the reference cell each include one switch. The switches can be transistors or transistors. The switches in the multiple switch control branches are connected in cascade to the connection point between each two resistors in the reference cell 1131. The multiple switch control branches can control the corresponding switches to close or open based on the mantissa of the received input floating-point number, thereby controlling the magnitude of the initial voltage analog signal output based on the equidistant voltage.

[0150] For example, assuming that the two ends of the reference unit are connected to voltages of 1V and 2V respectively, the reference unit 1131 can generate multiple equal-difference voltages between 1V and 2V. If the number of bits of the mantissa part m of the input floating-point number is 7 bits, the reference unit 1131 can generate 2 equal-difference voltages between 1V and 2V. 7 = 128 equidistant voltages. At this time, the value represented by the 7 bits of the mantissa m of the input floating-point number can be between 0 and 128. Assuming that the value represented by the mantissa of the input floating-point number is 60, the magnitude of the initial voltage analog signal output by the gating unit 1132 can be:

[0151] The gain adjustment unit 114 can use a programmable gain amplifier (PGA), which performs gain adjustment through an operational amplifier (OPA) in combination with a multiplying resistor. As shown in Figure 6, the gain adjustment unit 114 can include an operational amplifier OPA1 and multiple feedback resistor branches. The first input terminal of the operational amplifier OPA1 is connected to the output terminal of the gating unit 1132, and the second input terminal of the operational amplifier OPA1 is connected to the reference resistor R21. Each feedback resistor branch of the multiple feedback resistor branches can include a switch and a feedback resistor connected in series. The switch can be a triode or a transistor. The resistance values ​​of the feedback resistors in the multiple feedback resistor branches are in a multiple relationship, which can be called a multiplying resistor. For example, the resistance value of resistor R22 in the first feedback resistor branch can be R, the resistance value of resistor R23 in the second feedback resistor branch can be R, the resistance value of resistor R24 ​​in the third feedback resistor branch can be 2R, and the resistance value of resistor R25 in the fourth feedback resistor branch can be 4R. The first ends of the multiple feedback resistor branches are all connected to the second input end of the operational amplifier OPA1, and the second ends of the multiple feedback resistor branches are all connected to the output end of the operational amplifier OPA1. The switches in the multiple feedback resistor branches can be connected to the output end of the OR gate, and the multiple input ends of the OR gate are used to receive the exponential part of the input floating-point number. The OR gate in the gain adjustment unit 114 shown in Figure 6 includes two input ends, which are respectively used to receive data of two data bits E0 and E1 of the exponential part of the input floating-point number. The output end of the OR gate is used to output a control signal based on the exponential part of the input floating-point number to control the closure of the switches of some or all of the feedback resistor branches in the multiple feedback resistor branches to perform gain adjustment on the initial voltage analog signal output by the selection unit 1132 to obtain the input voltage analog signal V DAC In the above example, the feedback resistor can be selected between R and 8R.

[0152] For example, the exponent of the input floating point number represents a value of 2, that is, 22 When , assuming that the resistance of the reference resistor R21 is R, the output end of the OR gate can close the switch of the feedback resistor branch to which the feedback resistor R25 with a resistance of 4R belongs according to the value 2 of the exponent part of the input floating-point number, that is, the resistance of the reference resistor is R, and the resistance of the feedback resistor is 4R, satisfying the ratio of the resistance of the feedback resistor to the resistance of the reference resistor is 4. At this time, the voltage analog signal output by the operational amplifier OPA1 is 4 times the initial voltage analog signal input to the operational amplifier OPA1. If the initial voltage analog signal output by the selection unit 1132 is 1.469V, the gain adjustment unit 114 can amplify the initial voltage analog signal of 1.469V to 5.875V. For another example, the value represented by the exponent part of the input floating-point number is -2, that is, 2 -2 When assuming that the resistance of reference resistor R21 is 4R, the output of the OR gate can close the switch of the feedback resistor branch to which feedback resistor R22, whose resistance is R, belongs based on the value of the exponent portion of the input floating-point number, -2. That is, the resistance of the reference resistor is 4R, and the resistance of the feedback resistor is R, satisfying that the ratio of the resistance of the feedback resistor to the resistance of the reference resistor is 1 / 4. At this time, the voltage analog signal output by operational amplifier OPA1 is 1 / 4 of the initial voltage analog signal input to operational amplifier OPA1. If the initial voltage analog signal output by selection unit 1132 is 1.469V, gain adjustment unit 114 can reduce the initial voltage analog signal of 1.469V to 0.367V.

[0153] In the above embodiment, the feedback resistor can be selected between R and 8R. In other embodiments, the feedback resistor can also be configured to be adjustable to R / 2R / 4R / 8R / 16R. For example, the gain adjustment unit 114 may include four feedback resistor branches, the resistance value of the resistor R22 in the first feedback resistor branch can be R, the resistance value of the resistor R23 in the second feedback resistor branch can be 2R, the resistance value of the resistor R24 ​​in the third feedback resistor branch can be 4R, and the resistance value of the resistor R25 in the fourth feedback resistor branch can be 8R.

[0154] In the embodiment shown in FIG6 , the reference resistor connected to the operational amplifier OPA1 has a fixed resistance, and the resistance of the feedback resistor is adjustable according to the exponential portion of the input floating-point number. In other embodiments, the feedback resistor connected to the operational amplifier OPA1 may have a fixed resistance, and the resistance of the reference resistor may be adjustable according to the exponential portion of the input floating-point number; or, the resistances of both the feedback resistor and the reference resistor connected to the operational amplifier OPA1 may be adjustable.

[0155] Through the above process, the digital-to-analog conversion module 110 can convert the input floating-point number into an input voltage analog signal V DAC , the input voltage analog signal V DACThe data is then transmitted to the analog computing module, namely the RRAM array 121 shown in Figure 5. The RRAM array 121 is a memory-computing integrated array composed of memory. It is a multiplier and accumulation hardware accelerator based on analog computing, used to implement data multiplication and addition operations using voltage analog signals. Data multiplication and addition operations are widely used in neural network computing.

[0156] In some embodiments, the structure of the RRAM array may be as shown in FIG. 7 . The RRAM array 121 may include a plurality of cells, such as G 11 , G 12 , G 21 Etc. The cell is located at the intersection of rows and columns of the RRAM array, and a conductive device can be used. Each row of the RRAM array can be called a word line (WL), and each column of the RRAM array can be called a bit line (BL). If the RRAM array 121 includes n rows and m columns, that is, n word lines WL1~WLn and m bit lines BL1~BLm, then the number of cells contained in the RRAM array 121 can be n*m. Before performing floating-point calculations, the analog value of the parameter data can be pre-stored in the RRAM array 121. For example, in the creation of neural network calculations, the parameter data can be the weights in the neural network model. The weights can be input into the RRAM array 121 from the bit lines (columns) of the RRAM array, so that each weight value in the weight is configured to the corresponding cell, that is, each weight value corresponds to a cell, and each weight value is stored in the corresponding cell in the form of conductance, which can be called the conductance value of the corresponding cell. In some embodiments, when performing floating-point calculations, multiple input floating-point numbers can be calculated simultaneously. For example, n input floating-point numbers can be converted into input voltage analog signals through n digital-to-analog conversion modules or one digital-to-analog conversion module, and n input voltage analog signals are obtained, namely V1, V2...V n The n input voltage analog signals are input into the RRAM array 121 through the word lines (rows) of the RRAM array. After the n input voltage analog signals pass through the RRAM array, a convergent current is generated on each column. According to Ohm's law, the current on the i-th column can be expressed as: I i =[V1 V2 … V n ]×G i

[0157] Among them, G i is a vector consisting of the conductance values ​​of each unit in the i-th column.

[0158] According to Kirchhoff's law, the current in each column can be accumulated, so the current analog signal output by the RRAM array can be expressed as:

[0159] Through the above process, multiple input floating-point numbers can be multiplied and added with the reference data pre-stored in the RRAM array, which is equivalent to implementing the convolution operation in the neural network. When the RRAM array contains a row of units, it can be considered as operating an input floating-point number with the reference data pre-stored in the RRAM array, and outputting the calculation result analog signal. The computing efficiency of the RRAM array is significantly improved compared to traditional floating-point calculations. When the RRAM array can achieve multi-bit programming, its computing efficiency can be continuously improved. Assuming that the RRAM array can reach 8 bits, and both the digital-to-analog conversion module and the analog-to-digital conversion module can achieve 8-bit data conversion, the RRAM array can achieve 8*8 multiplication on a single device, and an RRAM array can achieve 8-bit vector-matrix multiplication operations.

[0160] In other embodiments, the RRAM array 121 may also adopt a structure as shown in FIG8 . In the RRAM array shown in FIG8 , the number of word lines WL and bit lines BL is the same. Each cell G in the RRAM array may include a transistor in addition to a conductive device. Since a transistor has three terminals, the RRAM array includes source lines (SL) in addition to the word lines WL and bit lines BL. The number of source lines SL is also the same as the number of word lines WL and bit lines BL. After the RRAM array calculates an input analog signal and an analog value of pre-stored parameter data, the calculated analog signal may be output via the source line SL.

[0161] As can be seen from the above description, the calculation result analog signal output by the RRAM array 121 is a current analog signal. The RRAM array 121 outputs the calculation result analog signal to the analog-to-digital conversion module 130, which converts the calculation result analog signal into a floating-point result.

[0162] As shown in FIG5 , the analog-to-digital conversion module 130 may include a signal conversion unit 133 and a mantissa output unit 134. The signal conversion unit 133 may be configured to determine a voltage value corresponding to the mantissa of the resulting floating-point number based on the received analog signal of the calculation result, and output the exponent of the resulting floating-point number. The mantissa output unit 134 may be configured to output the mantissa of the resulting floating-point number based on the voltage value corresponding to the mantissa of the resulting floating-point number.

[0163] The signal conversion unit 133 may include an active integration unit 1331, a quantization unit 1332, and a dynamic adjustment unit 1333. The active integration unit 1331 may serve as a first conversion unit for converting the output current analog signal I received from the analog calculation module into a quantization unit 1333. MACThe quantization unit 1332 can be used as a first quantization unit, and the dynamic adjustment unit 1333 can be used as a first dynamic adjustment unit. The active integration unit 1331 is connected to the output end of the RRAM array 121 and is used to set the time length T s The output current analog signal is integrated to obtain a first voltage, and the first voltage is output to the quantization unit 1332. The quantization unit 1332 is used to set the time length T s Based on the change of the first voltage, a control signal is transmitted to the dynamic adjustment unit 1333. The dynamic adjustment unit 1333 can also be called an adaptive range adjustment unit. The dynamic adjustment unit 1333 is used to set the time length T s Based on the control signal from the quantization unit 1332, the range of the active integration unit 1331 is adjusted, that is, the conversion ratio parameter of the active integration unit 1331 for the output current analog signal is adjusted. s After that, the quantization unit 1332 can be used to calculate the value of the quantization unit 1332 according to the set time length T. s At the arrival time, the active integration unit 1331 outputs the first voltage, determines the voltage value corresponding to the mantissa of the result floating point number, and outputs the voltage value to the mantissa output unit 134. The dynamic adjustment unit 1333 can be used to adjust the voltage value according to the set time T. s At the arrival time of , the active integration unit 1331 outputs the exponential part of the resulting floating-point number according to the conversion ratio parameter of the output current analog signal.

[0164] For example, as shown in FIG9 , the active integration unit 1331 may include an integrator, which includes an operational amplifier OPA2 and a capacitor C1 connected between the negative input terminal and the output terminal of the operational amplifier OPA2. The negative input terminal of the operational amplifier OPA2 is connected to the output terminal of the RRAM array 121 to receive the calculation result analog signal I output by the RRAM array 121. MAC The positive input terminal of the operational amplifier OPA2 can be connected to a reference voltage generating circuit, which provides a reference voltage Vr for the operational amplifier OPA2. The active integration unit 1331 is used to output the current analog signal I MAC The quantization unit 1332 may include a first comparator, and the first input terminal of the first comparator may be connected to the first input terminal of the first comparator through the capacitor C cds The first comparator is connected to the output terminal of the integrator and is used to receive the first voltage Vo output by the integrator. The second input terminal of the first comparator is used to connect to the ramp signal generating circuit. The ramp signal generating circuit is used to set the time length T s The first comparator is provided with a constant voltage V th , and when the set time T is reached sAfterwards, a ramp voltage that changes at a set rate is provided to the first comparator. The output terminal of the first comparator can output a control signal to the dynamic adjustment unit 1333 based on the change of the first voltage Vo. In some embodiments, the computing device can include multiple analog-to-digital conversion modules, and a ramp signal generating circuit can be connected to the first comparators in the multiple analog-to-digital conversion modules to provide a constant voltage V for the multiple first comparators. th and a ramp voltage that changes at a set rate.

[0165] The dynamic adjustment unit 1333 may include multiple triggers and multiple capacitor branches, with the triggers and capacitor branches corresponding one to one. Each capacitor branch includes a capacitor and a switch device connected in series, the first end of each capacitor branch is connected to the input end of the integrator, the second end of each capacitor branch is connected to the output end of the integrator, and the switch device of each capacitor branch is connected to the output end of a trigger, and the input end of each trigger is connected to the output end of the first comparator, for controlling the switch device of the corresponding capacitor branch to close or open under the action of the control signal output by the first comparator, so that the corresponding capacitor branch is connected or disconnected, so as to adjust the conversion ratio parameter of the active integration unit 1331 for the output current analog signal. Figure 9 shows three triggers and three capacitor branches, wherein the first capacitor branch includes capacitor C2 and switch device sw1, the second capacitor branch includes capacitor C3 and switch device sw2, and the third capacitor branch includes capacitor C4 and switch device sw3. The output end of each trigger is connected to the switch device of the corresponding capacitor branch through an OR gate.

[0166] The dynamic adjustment unit 1333 may also include a decoding unit, which is connected to the output end of the OR gate corresponding to the multiple triggers. The decoding unit can use a circuit chip that converts the thermometer code into binary code, and is used to read the adjusted conversion ratio parameter and output the exponential part of the resulting floating point number according to the conversion ratio parameter.

[0167] Mantissa output unit 134 may include a counter configured to output the mantissa portion of the resulting floating-point number based on a voltage value corresponding to the mantissa portion of the resulting floating-point number output by the quantization unit. The counter may be connected to the output of the quantization unit via an inverter. The counter may be a Mbit counter.

[0168] Based on the circuit structure shown in FIG9 , the process of converting the analog signal of the calculation result into the floating-point number by the analog-to-digital conversion module 130 may include an adaptive phase and a quantization phase. Before each analog-to-digital conversion, the analog-to-digital conversion module may be reset by the RESET switch in the analog-to-digital conversion module to clear the data in the analog-to-digital conversion module and set the voltage at Vo to the initial value Vr. The set time T from the reset moment is s The period is the adaptive phase of the analog-to-digital conversion process.s The voltage variation curves in the adaptive phase and the quantization phase are shown in FIG10 .

[0169] Adaptive stage: After the reset operation, the switch devices in each capacitor branch are disconnected, the range of the active integration unit is minimum, and the conversion ratio parameter of the output current analog signal is maximum. Close the switch sw connected to the negative input terminal of the integrator in , the output current analog signal I of the analog calculation module MAC The input integrator integrates the received output current analog signal, stores the integrated charge in the capacitor C1, and outputs the first voltage Vo to the first input terminal of the first comparator. The more integrated charge in the capacitor C1, the greater the first voltage Vo. The first comparator is used to compare the first voltage Vo input to the first input terminal with the constant voltage V input to the second input terminal. th The first voltage Vo gradually increases, and when the first voltage Vo increases to a constant voltage V th When the first comparator outputs a high level (i.e., time T1), it can be understood that whenever the first voltage Vo increases to the constant voltage V th , the first comparator outputs a high-level control signal to the dynamic adjustment unit. When the dynamic adjustment unit receives the first high-level control signal, the first trigger outputs a high-level control signal accordingly, controlling the switch device sw1 in the first capacitor branch to close, and adjusting the range of the active integration unit to a larger level, or in other words, adjusting the conversion ratio parameter of the active integration unit for the output current analog signal to a lower level to obtain a new conversion ratio parameter. After the switch device sw1 is closed, the integrated charge is shared between capacitor C1 and capacitor C2, that is, the integrator integrates the received output current analog signal, and the integrated charge is stored in capacitor C1 and capacitor C2, and the first voltage Vo is instantly reduced to The integrator continues to integrate the received output current analog signal, and the first voltage Vo gradually increases. When the first voltage Vo increases to a constant voltage V th At time T2, the first comparator outputs a second high-level control signal to the dynamic adjustment unit, and the second trigger outputs a high-level control signal accordingly, controlling the switch device sw2 in the second capacitor branch to close, thereby increasing the range of the active integration unit by one gear, or in other words, reducing the conversion ratio parameter of the active integration unit for the output current analog signal by one gear. At this time, the first voltage Vo is instantly reduced to And so on, until the set time T is reached s .

[0170] Quantization stage: When the set time T is reached s Afterwards, assuming that the time duration T sAt the arrival time, the value of the first voltage Vo output by the integrator is V M , disconnect the switch sw connected to the negative input terminal of the integrator in , so that the first voltage Vo is maintained at V M To avoid interference and errors, set the time T s A short time later T c At this moment, the voltage V th The constant voltage is changed to a single slope voltage, that is, the single slope voltage connected to the second input of the first comparator gradually increases from 0 at a set rate until it reaches the original constant voltage V th In some embodiments, the ramp signal generating circuit connected to the second input terminal of the first comparator may include a constant voltage generating circuit and a single ramp voltage generating circuit, the constant voltage generating circuit is connected to the second input terminal of the first comparator through a first switch, and the single ramp voltage generating circuit is connected to the second input terminal of the first comparator through a second switch. c Before the moment, the first switch is closed and the second switch is open, and the constant voltage generating circuit provides a constant voltage V to the second input terminal of the first comparator. th , in T c After the time, the second switch is closed, the first switch is opened, and the single slope voltage generating circuit provides a uniformly changing single slope voltage to the second input terminal of the first comparator. c At the beginning of the moment, the counter in the mantissa output unit starts counting according to the set period. Every time a set period passes, the counter count value increases by 1 until the single slope voltage input to the second input terminal of the first comparator increases to the voltage value V M Time (ie T q At this moment, the comparator outputs a high-level control signal to control the counter to stop counting, and the mantissa output unit uses the calculated value of the counter as the mantissa of the result floating-point number D M Output. At T c At this moment, the decoding unit in the dynamic adjustment unit uses the combination of the values ​​output by the OR gates corresponding to the multiple triggers as the thermometer code. The thermometer code represents the current conversion ratio parameter. The decoding unit converts the thermometer code into binary code to obtain the exponential part D of the resulting floating point number. E .

[0171] FIG10 shows the voltage change waveform of the analog-to-digital conversion process corresponding to two analog signals of different calculation results. As shown in FIG10, when the current magnitudes I1 and I2 of the analog signals of the calculation results output by the analog calculation module are different, different gears will be triggered. For example, in the set time T sWithin the set time T, the current I1 can trigger the conversion from the first gear to the second gear at time T1, and trigger the conversion from the second gear to the third gear at time T2, that is, the current I1 can trigger the third gear. s Within the set time T, the current I2 can trigger the conversion from the first gear to the second gear at the time T1, that is, the current I2 can trigger the second gear. s Within this range, currents of different sizes will trigger different gears, corresponding to different conversion ratio parameters, and the exponent part of the resulting floating-point number will also be different in size.

[0172] Taking the floating point number base b as 2 as an example, in some embodiments, the reference voltage Vr connected to the integrator can be set to 0, and the constant voltage V connected to the second input terminal of the first comparator can be set to 0. th =2, set the capacitor shown in Figure 9 to C1 = C int , C2=C int ,C3=2C int ,C4=4C int , making the capacitance values ​​of each capacitor branch multiply. Thus, as shown in Figure 11, each time the conversion ratio parameter is adjusted, Vo instantly drops from 2V to 1V. Therefore, the capacitance values ​​of each capacitor branch are multiplied, which can be used to perform analog-to-digital conversion on floating-point numbers with a base b value of 2.

[0173] In the embodiment shown in FIG9 , the adaptation stage and the quantization stage share a first comparator, as described above. During the adaptation stage, the second input of the first comparator is connected to a constant voltage Vth; during the quantization stage, the second input of the first comparator is connected to a ramp voltage that changes at a set rate. In other embodiments, the adaptation stage and the quantization stage may each use a comparator. Specifically, the quantization unit 1332 may include a comparator A, whose first input may be connected to the output of the integrator to receive the first voltage Vo output by the integrator, whose second input may be connected to the constant voltage Vth, and whose output may be connected to a trigger to provide a control signal to the dynamic adjustment unit during the adaptation stage. The mantissa output unit 134 may also include a comparator B in addition to a counter. The first input of comparator B may be connected to the output of the integrator, whose second input may be connected to a ramp voltage that changes at a set rate, and whose output may be connected to the counter to provide a control signal to the mantissa output unit during the quantization stage.

[0174] In the above embodiment, when using floating-point numbers for calculation, the digital-to-analog conversion module first converts the input floating-point number into an input analog signal. The digital-to-analog conversion module includes a mantissa conversion unit and a gain adjustment unit. The mantissa conversion unit is used to process the mantissa part of the input floating-point number and convert the mantissa part of the input floating-point number into an initial analog signal. The gain adjustment unit can perform gain adjustment on the initial analog signal in the analog domain based on the exponential part of the input floating-point number to obtain an input analog signal. When the exponential part of the input floating-point number is different, the gain multiples of the initial analog signal by the gain adjustment unit are different, and the size of the input analog signal obtained is also different, thereby realizing the conversion of multiple input floating-point numbers with different exponential parts into multiple input analog signals of different sizes. After the input floating-point number is converted into the input analog signal, an analog calculation module can be used to perform analog calculation based on the input analog signal to obtain a calculation result analog signal. The analog computing module can utilize an RRAM array, which can perform multiplication operations using Ohm's law and addition operations using Kirchhoff's law. This allows for rapid multiplication and addition operations, improving computational efficiency and reducing power consumption compared to floating-point calculations performed in the digital domain. Furthermore, performing floating-point calculations based on analog computing enhances the applicability of analog computing.

[0175] The computing device provided in the embodiments of the present application can be applied to the training or inference process of neural network models in the field of artificial intelligence. During the training or inference process of neural network models, convolution calculations of large amounts of data are usually required, and convolution calculations include multiplication and addition operations. The RRAM array can utilize the multi-bit characteristics of the device to receive multiple input analog signals input by multiple digital-to-analog conversion modules in the computing device, and simultaneously complete analog calculations of multiple input floating-point numbers, thereby significantly improving computing efficiency. After the RRAM array performs analog calculations, the output calculation result analog signal is an output current analog signal. The analog-to-digital conversion module can integrate the output current analog signal through an active integration unit to convert the output current analog signal into a voltage signal. The voltage output by the active integration unit is detected and the dynamic adjustment unit timely adjusts the conversion ratio parameter of the active integration unit for the output current analog signal. The exponent part of the result floating-point number is determined according to the final conversion ratio parameter. When the conversion ratio parameter is determined, the mantissa part of the result floating-point number is determined according to the voltage output by the active integration unit. Therefore, different result floating-point numbers can be obtained according to different sizes of the output current analog signal, completing the floating-point number calculation in the analog domain. The dynamic range of the result floating-point number read out based on different calculation result analog signals can be adaptively adjusted, supporting the reading of result floating-point numbers with different exponents.

[0176] Since the integration capacitor of the active integration unit is continuously integrating during the sampling time (i.e., the set duration), the voltage output by the active integration unit is strongly correlated with the set duration. Therefore, the set duration can be pre-set based on experience or experimental test results.

[0177] In a second optional embodiment, as shown in FIG12 , the analog calculation module may use a flash memory transistor array 122. The input analog signal of the flash memory transistor array 122 may be a current analog signal. In this embodiment, the digital-to-analog conversion module 110 may be used to convert the input floating-point number into an input current analog signal.

[0178] As shown in FIG12 , the digital-to-analog conversion module 110 may include a mantissa conversion unit 115 and a gain adjustment unit 116. The mantissa conversion unit 115 may be configured to convert the mantissa portion of an input floating-point number into an initial current analog signal. The gain adjustment unit 116 may be configured to perform gain adjustment on the initial current analog signal based on the exponent portion of the input floating-point number to obtain an input current analog signal.

[0179] In some embodiments, the circuit structure of the digital-to-analog conversion module 110 may be as shown in FIG13 , wherein the mantissa conversion unit 115 may employ a current mirror structure. The current mirror structure may include a reference transistor Q1 and multiple output transistor branches, each of which is configured to receive the mantissa portion of an input floating-point number and output an initial current analog signal. In some embodiments, the number of output transistor branches included in the mantissa conversion unit 115 is equal to the length of the mantissa portion of the input floating-point number. For example, assuming that the mantissa portion of the input floating-point number includes N bits, where N is an integer greater than 1, the current mirror structure may include N output transistor branches, each of the N output transistor branches being configured to receive one of the N bits. The mantissa conversion unit 115 shown in FIG13 includes seven output transistor branches, capable of receiving a 7-bit mantissa portion of an input floating-point number. The seven output transistor branches are respectively configured to receive values ​​M0 to M6 of the mantissa portion. Each output transistor branch may include a first output transistor and a second output transistor, each having the same structure and connection method. Taking the first output transistor branch as an example, the first output transistor branch includes a first output transistor Q111 and a second output transistor Q112. The gate of the first output transistor Q111 is connected to the gate of the reference transistor Q1, and the gate and drain of the reference transistor Q1 are both used to access the reference current I refThe source of the first output transistor Q111 and the source of the reference transistor Q1 are both grounded. The drain of the first output transistor Q111 is connected to the source of the second output transistor Q112. The drain of the second output transistor Q112 can be connected to a power supply via another transistor Q3. The gate of the second output transistor Q112 is used to receive the value of the bit M0 of the mantissa of the input floating-point number. The current amplification factors of the first output transistors in the multiple output transistor branches are in a multiple relationship. As shown in Figure 13, the current amplification factor of the first output transistor Q111 of the first output transistor branch is 1× (times), the current amplification factor of the first output transistor Q121 of the second output transistor branch is 2×, the current amplification factor of the first output transistor Q131 of the third output transistor branch is 4×, and so on. The current amplification factor of the first output transistor Q171 of the seventh output transistor branch is 64×. The drain of the second output transistor in the multiple output transistor branches is an output terminal for outputting the initial current analog signal. The second output transistor in the multiple output transistor branches can be understood as a switching device, configured to control the on / off switching of the corresponding output transistor branch based on the value of the corresponding bit of the mantissa of the received input floating-point number, thereby controlling the magnitude of the output initial current analog signal. The output ends of the multiple output transistor branches can be grounded via transistor Q2, which has a current amplification factor of 128×.

[0180] The mantissa conversion unit 115 controls the magnitude of the initial current analog signal outputted by the switch devices on each output transistor branch. For example, when the values ​​of the 7 bits of the mantissa of the received input floating-point number are all 0, that is, M0 to M6 are all 0, at this time, each output transistor branch is in the off state, and the initial current analog signal outputted by the mantissa conversion unit 115 is 128*I ref When the 7-bit values ​​of the mantissa of the received input floating-point number are all 1, that is, M0 to M6 are all 1, at this time, each output transistor branch is in the on state, and the initial current analog signal output by the mantissa conversion unit 115 is 255*I ref , that is, the output end of multiple output transistor branches can output 128*I ref ~255*I ref The mantissa conversion unit 115 outputs the initial current analog signal I′ to the gain adjustment unit 116 .

[0181] The gain adjustment unit 116 may include multiple switch-controlled transistor branches. The multiple switch-controlled transistor branches are configured to provide multiple gain adjustment coefficients, and the multiple switch-controlled transistor branches are configured to determine a target gain adjustment coefficient based on the exponential portion of the input floating-point number, and to gain adjust the initial current analog signal using the target gain adjustment coefficient to obtain the input current analog signal.

[0182] In an optional embodiment, as shown in FIG13 , the gain adjustment unit 116 may include 8 switch control transistor branches. Assuming that the exponent part E of the input floating point number includes 3-bit data, the 3-bit exponent part E of the input floating point number may be converted into 8-bit data through a 3-8 decoder, which are E line1 to E line8 , each bit in the 8-bit corresponds to the input of 8 switch control transistor branches. The data converted by the 3-8 decoder can also be called a one-hot code. For example, when the exponent part of the input floating point number E=000, the data converted by the 3-8 decoder E line =00000001; When the exponent part of the input floating point number E=100, the data E converted by the 3-8 decoder line =00010000. Each switch-controlled transistor branch may include a first control transistor and a second control transistor, and the structure and connection method of each switch-controlled transistor branch are the same. Taking the first switch-controlled transistor branch as an example for explanation, the first switch-controlled transistor branch includes a first control transistor Q211 and a second control transistor Q212. Among them, the gate of the first control transistor Q211 is connected to the output end of the mantissa conversion unit 115, and is used to receive the initial current analog signal I' output by the mantissa conversion unit 115, the source of the first control transistor Q211 is connected to the power supply, the drain of the first control transistor Q211 is connected to the source of the second control transistor Q212, the drain of the second control transistor Q112 serves as the output end of the gain adjustment unit 116, and the gate of the second control transistor Q212 is used to receive the bit E after the exponent part of the input floating-point number is decoded. line1The current amplification factors of the first control transistors in the multiple switch-controlled transistor branches are in a multiple relationship. As shown in FIG13 , the current amplification factor of the first control transistor Q211 of the first switch-controlled transistor branch is 1×, the current amplification factor of the first control transistor Q221 of the second switch-controlled transistor branch is 2×, the current amplification factor of the first control transistor of the third switch-controlled transistor branch is 4×, and so on. The current amplification factor of the first control transistor Q281 of the eighth switch-controlled transistor branch is 128×. The current amplification factor of the first control transistor in each switch-controlled transistor branch can be understood as the gain adjustment factor provided by the corresponding switch-controlled transistor branch. Since the current amplification factors of the first control transistors in different switch-controlled transistor branches are different, it can be understood that the gain adjustment factors provided by different switch-controlled transistor branches are different. Multiple switch-controlled transistor branches can be used to provide multiple gain adjustment factors. The second control transistor in the multiple switch control transistor branches can be understood as a switch device, which is used to control the on and off of the corresponding switch control transistor branch based on the value of the bit corresponding to the exponential part of the received input floating-point number. Through switch control, any current of 1, 2, 4...128 times the current can be turned on, thereby controlling the gain adjustment coefficient of the initial current analog signal I' to obtain the input current analog signal I in The drain of the second regulating transistor in the plurality of switch control transistor branches is the output terminal, which is used to output the input current analog signal I in , or in other words, it is used to convert the input current analog signal I in The data is input to the flash memory transistor array 122 for operation.

[0183] In another optional embodiment, assuming that the exponent part of the input floating-point number includes 3 bits of data, the gain adjustment unit 116 may also include 3 switch-controlled transistor branches, each switch-controlled transistor branch is used to receive the value of one bit of the exponent part of the input floating-point number.

[0184] In other embodiments, the circuit structure of the digital-to-analog conversion module 110 may be as shown in FIG14 , and the gain adjustment unit 116 of the digital-to-analog conversion module shown in FIG14 has the same circuit structure as the gain adjustment unit shown in FIG13 . The difference between the digital-to-analog conversion module shown in FIG14 and the digital-to-analog conversion module shown in FIG13 is that the number of output transistor branches included in the current mirror structure of the mantissa conversion unit 115 is different. In the mantissa conversion unit 115 shown in FIG14 , the number of output transistor branches is greater than the length of the mantissa portion of the input floating-point number. Assuming that the mantissa portion of the input floating-point number includes N bits, the mantissa conversion unit 115 includes M output transistor branches, where M=2 N, the current amplification factor of the first output transistor in each output transistor branch can be the same. M output transistor branches are connected to the thermometer decoder, and the N bits of the mantissa of the input floating point number are input to the thermometer decoder, and converted into M bits by the thermometer decoder for output, and each of the M bits corresponds to an output transistor branch in the M output transistor branches. For example, the mantissa of the input floating point number includes 7 bits of data. The 7 bits of data are input to the thermometer decoder, and after conversion by the thermometer decoder, 2 7 =128-bit data, 128-bit data is output through 128 output branches. The mantissa conversion unit 115 may include 128 output transistor branches, the current amplification factor of the first output transistor in each output transistor branch is 1×, and the gate M of the second output transistor in each output transistor branch is 1×. th0 ~M th127 Each of the plurality of output transistor branches is connected to an output branch of the thermometer decoder. The second output transistor in the plurality of output transistor branches is used to receive the 128-bit data obtained by converting the mantissa of the input floating-point number by the thermometer decoder. The drain of the second output transistor in the plurality of output transistor branches serves as the output end. The output end of the plurality of output transistor branches can be grounded through the transistor Q2 with a current amplification factor of 128×. The second output transistor in the plurality of output transistor branches can be understood as a switching device, which is used to control the on-off of the corresponding output transistor branch based on the value of the corresponding bit in the received 128-bit data, thereby controlling the size of the output initial current analog signal I'. Similar to the mantissa conversion unit shown in FIG13 , the output end of the plurality of output transistor branches shown in FIG14 can also output 128*I ref ~255*I ref For example, assuming that the mantissa of the input floating-point number includes 7 bits of data, when the mantissa of the input floating-point number is M=0110000, the value represented by the mantissa is 48. The 128-bit data converted by the thermometer decoder includes 48 bits of 1, and the values ​​of the remaining 80 bits are 0. At this time, the magnitude of the initial current analog signal I' outputted from the output terminals of the multiple output transistor branches of the mantissa conversion unit is (128+48)*I ref The output terminals of the plurality of output transistor branches of the mantissa conversion unit transmit the initial current analog signal I′ to the gain adjustment unit 116 .

[0185] The gain adjustment unit 116 in FIG14 may also include multiple switch-controlled transistor branches. The multiple switch-controlled transistor branches are used to provide multiple gain adjustment coefficients, and the multiple switch-controlled transistor branches are used to determine the target gain adjustment coefficient based on the exponential part of the input floating-point number, and use the target gain adjustment coefficient to perform gain adjustment on the initial current analog signal to obtain the input current analog signal I in .

[0186] The above only introduces the circuit parts that are different between Figure 14 and Figure 13. The circuit parts that are the same between Figure 14 and Figure 13 can be implemented with reference to the circuit structure described in Figure 13 and will not be repeated here.

[0187] The digital-to-analog conversion module 110 converts the input floating-point number into an input current analog signal I in After that, the input current analog signal I in The current is transmitted to the flash memory transistor array 122, which performs calculations based on the input current analog signal and outputs a calculation result analog signal. The circuit structure of the flash memory transistor array 122 may include one or more current mirror units 1221. The structure of each current mirror unit 1221 is shown in FIG15 , and may include a calculation reference transistor Q4 and a calculation output transistor Q5. The calculation output transistor Q5 has a floating gate. The floating gate refers to an isolated charge storage area formed by adding a layer of insulating material between two metal layers in the calculation output transistor Q5. This charge storage area can be called a floating gate. The source of the calculation reference transistor Q4 is used to receive the input current analog signal I from the digital-to-analog conversion module 110. in , the parameter data used for operating with the input floating point number can be applied to the floating gate of the current mirror unit 1221 in the form of a control voltage. Under the action of the control voltage, the input current analog signal I in and the output current analog signal I out The relationship between can be expressed as:

[0188] In the above formula, I0 is the reference current value related to the transistor size, q, n, k B is a constant, T is the temperature coefficient, V th is the threshold voltage of each transistor, V GS is the gate-source voltage of the transistor. In the connection relationship described in Figure 15, V GS1 =V GS2 , and the input and output tubes have the same size, temperature and other operating conditions, but different threshold voltages. Therefore, the relationship between output current and input current can be simplified to:

[0189] Among them, the output current analog signal I out It can be regarded as the input current analog signal I in The product of the parameter data.

[0190] In some embodiments, if the flash memory transistor array 122 includes a current mirror unit, the output current analog signal I out Can be used as the calculation result analog signal I of the analog calculation module MAC In other embodiments, if the flash memory transistor array 122 includes multiple current mirror units, each current mirror unit can receive an input current analog signal I corresponding to an input floating point number. in The flash memory transistor array 122 can be used to simultaneously calculate multiple input floating point numbers and reference data, and the calculation result of the analog calculation module is an analog signal I MAC It can be the output current analog signal I output by each current mirror unit out sum.

[0191] Since the calculation result analog signal output by the flash memory transistor array 122 is also a current analog signal, the circuit structure of the analog-to-digital conversion module shown in Figure 12 can be implemented with reference to the circuit structure of the analog-to-digital conversion module 130 shown in the first optional embodiment, and will not be repeated here.

[0192] The above embodiment provides a method for converting input floating-point numbers into input current analog signals and performing analog calculations through a flash memory transistor array, which can improve calculation efficiency compared to completing floating-point number calculations in the digital domain.

[0193] In the first optional embodiment, the analog-to-digital conversion module 130 is in the form of current integration, and the value of the resulting floating-point number is strongly correlated with the set time duration Ts. In other embodiments, the adaptive phase may first wait for the output analog signal to stabilize, and then enter the quantization phase after the output analog signal stabilizes. In the quantization phase, the exponent and mantissa of the resulting floating-point number are determined.

[0194] In a third optional embodiment, another specific implementation is provided for the analog-to-digital conversion module 130 in the first optional embodiment and the second optional embodiment. As shown in Figure 16, in this embodiment, the analog-to-digital conversion module 130 may include a signal conversion unit 135 and a mantissa output unit 136. The signal conversion unit 135 can be used to determine the voltage value corresponding to the mantissa portion of the result floating-point number based on the received calculation result analog signal, and output the exponent portion of the result floating-point number. The mantissa output unit 136 can be used to output the mantissa portion of the result floating-point number based on the voltage value corresponding to the mantissa portion of the result floating-point number.

[0195] The signal conversion unit 135 may include an operational amplifier unit 1351, a dynamic adjustment unit 1352, and a quantization unit 1353. The operational amplifier unit 1351 may serve as another implementation of the first conversion unit, the dynamic adjustment unit 1352 may serve as another implementation of the first dynamic adjustment unit, and the quantization unit 1353 may serve as a second quantization unit. The operational amplifier unit may be configured to output a second voltage based on the output current analog signal; the first dynamic adjustment unit may be configured to adjust the conversion ratio parameter of the operational amplifier unit for the output current analog signal based on the change in the second voltage until the change in the second voltage is less than or equal to a first set amplitude threshold; the second quantization unit may be configured to determine the voltage value corresponding to the mantissa of the resulting floating-point number based on the second voltage whose change is less than or equal to the first set amplitude threshold; the first dynamic adjustment unit may also be configured to output the exponent of the resulting floating-point number based on the conversion ratio parameter of the output current analog signal of the operational amplifier unit when the change in the second voltage is less than or equal to the first set amplitude threshold.

[0196] In some embodiments, the circuit structure of the analog-to-digital conversion module 130 may be as shown in FIG. 17 , where the operational amplifier unit 1351 may include an operational amplifier OPA3, which may be used to receive the output current analog signal I MAC , convert the output current analog signal into a voltage signal and output the second voltage V O1 For example, the negative input terminal of the operational amplifier OPA3 is connected to the output terminal of the analog calculation module, and is used to receive the calculation result analog signal I output by the analog calculation module. MAC The positive input of the operational amplifier OPA3 can be connected to a reference voltage generating circuit, which provides a reference voltage V for the operational amplifier OPA3. ref .

[0197] The dynamic adjustment unit 1352 may include a comparator A, multiple triggers, and multiple switch resistor branches, with the triggers corresponding to the switch resistor branches. The first input terminal of the comparator A is connected to the output terminal of the operational amplifier OPA3 to receive the second voltage output by the operational amplifier OPA3, and the second input terminal of the comparator A is used to access the constant voltage V thComparator A is configured to output a control signal based on changes in the second voltage. Each of the multiple switch resistor branches may include a feedback resistor and a switch device connected in series, with the resistance values ​​of the feedback resistors in the multiple switch resistor branches being multiples. The first end of each switch resistor branch is connected to the input of operational amplifier OPA3, and the second end of each switch resistor branch is connected to the output of operational amplifier OPA3. The inputs of the multiple triggers are connected to the output of comparator A. The output of each of the multiple triggers is connected to the corresponding switch resistor branch in the multiple switch resistor branches, and is configured to control the connection or disconnection of the corresponding switch resistor branch under the influence of the control signal output by comparator A, thereby adjusting the conversion ratio parameter of operational amplifier unit 1351 for the output current analog signal. Figure 17 shows three triggers and three switch resistor branches, where the first switch resistor branch includes feedback resistor R1 and switch device SW1, the second switch resistor branch includes feedback resistor R2 and switch device SW2, and the third switch resistor branch includes feedback resistor R3 and switch device SW3. The resistance value of the feedback resistor R1 may be 4R, the resistance value of the feedback resistor R2 may be 2R, and the resistance value of the feedback resistor R3 may be R. The switching device may be a transistor, and the output end of each trigger is connected to the gate of the transistor of the corresponding switch resistance branch through an OR gate, and the drain of the transistor is connected to the resistor.

[0198] The dynamic adjustment unit 1352 may also include a decoding unit, which is connected to the output end of the OR gate corresponding to the multiple triggers. The decoding unit can use a circuit chip that converts the thermometer code into a binary code, and is used to read the adjusted conversion ratio parameter and output the exponential part of the resulting floating point number according to the conversion ratio parameter.

[0199] The quantization unit 1353 may include a comparator B, wherein a first input of the comparator B is connected to the output of the operational amplifier OPA3 for receiving the second voltage output by the operational amplifier OPA3. A second input of the comparator B is connected to a ramp signal generating circuit. The ramp signal generating circuit is configured to provide a ramp voltage that changes at a set rate to the comparator B after the amplitude of the change in the second voltage is less than or equal to a first set amplitude threshold. The output of the comparator B may output a control signal to the mantissa output unit 136 based on the change in the ramp voltage.

[0200] Mantissa output unit 136 may include a counter configured to output the mantissa of the resulting floating-point number based on a voltage value corresponding to the mantissa of the resulting floating-point number. The counter may be connected to the output of the quantization unit via an inverter. The counter may be a Mbit counter.

[0201] The process of converting the analog signal of the calculation result into the floating point number by the analog-to-digital conversion module 130 may include an adaptive phase and a quantization phase. In the adaptive phase, the operation principle of the operational amplifier unit 1351 and the dynamic adjustment unit 1352 is as follows: the output current analog signal I MAC The voltage is input from the analog calculation module to the negative input terminal of the operational amplifier OPA3. Due to the "virtual short" effect, the voltage level of the negative input terminal of the operational amplifier OPA3 is clamped. During initial operation, under the action of the trigger in the dynamic adjustment unit 1352, the switch device SW1 in the first switch resistor branch is closed, and the switch device SW2 in the second switch resistor branch and the switch device SW3 in the third switch resistor branch are disconnected. At this time, the first switch resistor branch is connected, and the resistance of the feedback resistor in the circuit is 4R. The conversion ratio parameter of the operational amplifier unit for the output current analog signal is in the first gear. Due to the "virtual short and virtual disconnection" characteristics of the operational amplifier, V O1 The voltage at (i.e., the second voltage) is determined as follows: V O1 =I MAC *4R+V ref

[0202] Since V O1 The value of has nothing to do with time, so in the actual operation process, V O1 The value of will quickly reach a steady state, for example, V O1 It can reach steady state within 5ns. After stabilization, V O1 The comparator A will compare with the constant voltage V th For comparison, when V O1 >V th When , comparator A outputs a high-level control signal. The high-level control signal disconnects the switch device SW1 in the first switch resistor branch and closes the switch device SW2 in the second switch resistor branch through the trigger. The resistance value of the feedback resistor connected to the circuit changes from 4R to 2R, thereby adjusting the conversion ratio parameter of the operational amplifier unit for the output current analog signal from the first gear to the second gear. At this time, V O1 is: V O1 =I MAC *2R+V ref

[0203] Similarly, when the updated V O1 Still greater than V thWhen the dynamic range of the analog signal of the calculation result to be processed is large, the number of switch resistance branches included in the dynamic adjustment unit 1352 can be larger, and the corresponding feedback resistors can be changed to [32R, 16R, 8R, 4R, 2R, R], etc.

[0204] When V O1 The value tends to be stable and is less than the constant voltage V th When the second voltage variation is less than or equal to the first set amplitude threshold, the adaptive stage can be considered to be completed, wherein the first set amplitude threshold is less than the constant voltage V th The value of .

[0205] In the above process, V O1 =V th It is the critical point for switching the conversion ratio parameter. After switching, the corresponding From this we can see that when I MAC When the change occurs, the final stable V O1 satisfy

[0206] After the adaptive stage is completed, the V output by the operational amplifier OPA3 can be quantized by the quantization unit 1353. O1 Quantization is performed, and the range of the quantization unit is The operational amplifier OPA3 outputs V O1 The second input of comparator B is connected to the ramp voltage, which gradually increases from 0 at the set rate until it reaches a constant voltage V th When the ramp voltage gradually increases from 0, the counter in the mantissa output unit 136 starts counting according to the set cycle. Every time a set cycle passes, the counter count value increases by 1 until the ramp voltage input to the second input terminal of comparator B increases to the voltage value V connected to the first input terminal of comparator B. O1 When the comparator B outputs a high-level control signal, the counter stops counting, and the mantissa output unit 136 uses the calculated value of the counter as the mantissa of the result floating-point number D. M Output. The decoding unit in the dynamic adjustment unit 1352 uses the combination of the values ​​output by the OR gates corresponding to the multiple triggers as a thermometer code. The thermometer code represents the current conversion ratio parameter. The decoding unit converts the thermometer code into a binary code to obtain the exponent part D of the resulting floating point number. E .

[0207] In the circuit structure shown in FIG17 , the dynamic adjustment unit 1352 and the quantization unit 1353 each use a comparator, with the dynamic adjustment unit 1352 using comparator A and the quantization unit 1353 using comparator B. In other embodiments, as shown in FIG9 , the dynamic adjustment unit 1352 and the quantization unit 1353 may share a single comparator. In the adaptive phase, the second input terminal of the comparator may be connected to a constant voltage Vth, and in the quantization phase, the second input terminal of the comparator may be connected to a ramp voltage that changes at a set rate.

[0208] In other embodiments, the circuit structure of the analog-to-digital conversion module 130 may be as shown in FIG18 , where the analog-to-digital conversion module 130 may include an operational amplifier unit 1354, a dynamic adjustment unit 1355, and a quantization unit 1356. The operational amplifier unit 1354 may include an operational amplifier negative feedback circuit, multiple transistor branches, and a current-to-voltage converter. The operational amplifier negative feedback circuit may include an operational amplifier OPA4, which may be used to receive the output current analog signal I MAC For example, the negative input terminal of the operational amplifier OPA4 is connected to the output terminal of the analog calculation module, and is used to receive the output current analog signal I output by the analog calculation module. MAC The positive input of the operational amplifier OPA4 can be connected to a reference voltage generating circuit, which provides a reference voltage V for the operational amplifier OPA4. init The output of the operational amplifier OPA4 is connected to a reference transistor Q6, the gate of the reference transistor Q6 is connected to the output of the operational amplifier OPA4, the source of the reference transistor Q6 is grounded, and the drain of the reference transistor Q6 is used to access the output current analog signal I MAC The plurality of transistor branches are connected between the output terminal of the operational amplifier negative feedback circuit and the input terminal of the current-voltage converter, and are used to adjust the output current analog signal I based on the control signal of the dynamic adjustment unit 1355. MAC The conversion ratio parameter corresponds to different output sizes of Io at different gears. The current-to-voltage converter is used to convert the current signal Io output by multiple transistor branches into a voltage signal, and the output voltage V O2 .

[0209] Exemplarily, each transistor branch in the plurality of transistor branches includes a first transistor and a second transistor, and the current amplification factors of the first transistors in the plurality of transistor branches are in a multiple relationship. The operational amplifier unit 1354 shown in FIG18 includes three transistor branches. The current amplification factor of the first transistor Q311 in the first transistor branch is 64×, the current amplification factor of the first transistor Q321 in the second transistor branch is 32×, and the current amplification factor of the first transistor Q331 in the third transistor branch is 16×. In other embodiments, the number of transistor branches may be greater. When the number of transistor branches is greater, the current amplification factors of the first transistors in each transistor branch decrease in multiples. The gates of the first transistors in the plurality of transistor branches are connected to the gate of the reference transistor Q6 and the output of the operational amplifier OPA4, and the gates of the second transistors are connected to the output of the corresponding trigger in the dynamic adjustment unit 1355. Taking the first transistor branch as an example, the gate of the first transistor Q311 in the first transistor branch is connected to the gate of the reference transistor Q6 and the output terminal of the operational amplifier OPA4. The source of the first transistor Q311 is grounded, and the drain of the first transistor Q311 is connected to the source of the second transistor Q312. The drain of the second transistor in the multiple transistor branches is the output terminal of the multiple transistor branches, which is used to output the current signal Io. The current-voltage converter is connected to the output terminals of the multiple transistor branches, which is used to convert the current signal Io into a voltage signal, and output the voltage V O2 .

[0210] The dynamic adjustment unit 1355 may include a comparator A and a plurality of triggers, and the triggers correspond to the transistor branches in the operational amplifier unit. The first input terminal of the comparator A is connected to the output terminal of the current-voltage converter to receive the voltage V output by the current-voltage converter. O2 The second input of comparator A is used to access the constant voltage V th , comparator A is used based on the voltage V O2 The output control signal is output according to the change of the current. The input terminals of the multiple triggers are all connected to the output terminal of the comparator A. The output terminal of each trigger in the multiple triggers is connected to the corresponding transistor branch in the multiple transistor branches, and is used to control the corresponding transistor branch to be connected or disconnected under the action of the control signal output by the comparator A, so as to adjust the conversion ratio parameter of the operational amplifier unit 1354 for the output current analog signal. Exemplarily, the output terminal of each trigger is connected to the gate of the second transistor in the corresponding transistor branch through an OR gate. The second transistor can be understood as a switching device, which is used to close or open under the control of the trigger to connect or disconnect the corresponding transistor branch, thereby adjusting the conversion ratio parameter of the operational amplifier unit 1354 for the output current analog signal.

[0211] The dynamic adjustment unit 1355 may also include a decoding unit, which is connected to the output end of the OR gate corresponding to the multiple triggers. The decoding unit can use a circuit chip that converts the thermometer code into a binary code, and is used to read the adjusted conversion ratio parameter and output the exponential part of the resulting floating-point number according to the conversion ratio parameter.

[0212] The specific circuit structure of the dynamic adjustment unit 1355 is not shown in Figure 18. Compared with the dynamic adjustment unit 1352 shown in Figure 17, the dynamic adjustment unit 1355 only reduces multiple switch resistance branches. The connection relationship between the comparator A and the trigger in the dynamic adjustment unit 1355 can be implemented with reference to the dynamic adjustment unit 1352.

[0213] The quantization unit 1356 may include a comparator B, a first input terminal of the comparator B is connected to the output terminal of the current-voltage converter, and is used to receive the voltage V output by the current-voltage converter. O2 The second input terminal of the comparator B is used to connect the ramp signal generating circuit, which is used to generate a ramp signal when the voltage V O2 After the change amplitude of is less than or equal to the first set amplitude threshold, a ramp voltage that changes at a set rate is provided to comparator B. The output terminal of comparator B can output a control signal to the mantissa output unit 136 based on the change of the ramp voltage.

[0214] Mantissa output unit 136 may include a counter configured to output the mantissa of the resulting floating-point number based on a voltage value corresponding to the mantissa of the resulting floating-point number. The counter may be connected to the output of the quantization unit via an inverter. The counter may be a Mbit counter.

[0215] The specific circuit structure of the quantization unit 1356 can be implemented with reference to the quantization unit 1356 in Figure 17, and the mantissa output unit 136 can be implemented with reference to the mantissa output unit 136 in Figure 17, which is not repeated in Figure 18.

[0216] The process of converting the analog signal of the calculation result into the floating-point number by the analog-to-digital conversion module 130 may include an adaptive phase and a quantization phase. In the adaptive phase, the operational amplifier unit 1334 and the dynamic adjustment unit 1355 operate as follows: the operational amplifier unit 1334 uses an operational amplifier and a multiple current mirror structure, and the multiple current mirror structure may include a reference transistor and multiple transistor branches. The operational amplifier clamps the voltage at point A in the circuit to V through a negative feedback circuit. init , to ensure the correctness of the operation result, and the voltage at the output of the operational amplifier OPA4 will change with the output current analog signal I MAC By changing the current mirror, the transistors [64×, 32×, 16×…] are generated. During initial operation, under the action of the trigger in the dynamic adjustment unit 1355, the second transistor Q312 in the first transistor branch is closed, the second transistor Q322 in the second transistor branch and the second transistor Q332 in the third transistor branch are disconnected. At this time, the first transistor branch is turned on, so that the output terminals of the multiple transistor branches output current. The conversion factor of the current-to-voltage converter is fixed and linear. Assuming the conversion factor is k, the voltage V output by the current-to-voltage converter is O2 =V init +I O *k. Due to the initial operation, the current therefore

[0217] When V O2 >V th When , comparator A outputs a high-level control signal to adjust the conversion ratio parameter. The high-level control signal turns off the second transistor Q312 in the first transistor branch and turns on the second transistor Q322 in the second transistor branch through the trigger, thereby adjusting the conversion ratio parameter of the operational amplifier unit for the output current analog signal from the first gear to the second gear. At this time, the current output from the output end of the multiple transistor branches is The voltage output of the current-to-voltage converter is switched to Similarly, when V O2 The value tends to be stable and is less than the constant voltage V th When the voltage V O2 When the change amplitude of is less than or equal to the set amplitude threshold, the adaptive stage can be considered completed. O2 satisfy That is, the amplitude threshold can be set in Within the range.

[0218] Among them, since the current-to-voltage converter outputs a voltage V O2 Fully reflects the current I output by multiple transistor branches O The size of the voltage V O2 The change of the current I can be used to adjust the conversion ratio parameter of the operational amplifier unit for the output current analog signal. It can also be understood that based on the current I O According to the change of , the conversion ratio parameter of the operational amplifier unit for the output current analog signal is adjusted.

[0219] After the adaptive stage is completed, the V output by the operational amplifier unit 1354 can be quantized by the quantization unit 1356. O2 Quantization is performed, and the range of the quantization unit 1356 is The V output of the op amp unit 1354 O2The second input of comparator B is connected to the ramp voltage, which gradually increases from 0 at the set rate until it reaches a constant voltage V th When the ramp voltage gradually increases from 0, the counter in the mantissa output unit 136 starts counting according to the set cycle. Every time a set cycle passes, the counter count value increases by 1 until the ramp voltage input to the second input terminal of comparator B increases to the voltage value V connected to the first input terminal of comparator B. O2 When the comparator B outputs a high-level control signal, the counter stops counting, and the mantissa output unit 136 uses the calculated value of the counter as the mantissa of the result floating-point number D. M Output. The decoding unit in the dynamic adjustment unit 1352 uses the combination of the values ​​output by the OR gates corresponding to the multiple triggers as a thermometer code. The thermometer code represents the current conversion ratio parameter. The decoding unit converts the thermometer code into a binary code to obtain the exponent part D of the resulting floating point number. E .

[0220] Similar to the dynamic adjustment unit 1352 and the quantization unit 1353 shown in FIG17 , in some embodiments, the dynamic adjustment unit 1355 and the quantization unit 1356 can each use a comparator. For example, the dynamic adjustment unit 1355 uses comparator A, and the quantization unit 1356 uses comparator B. In other embodiments, the dynamic adjustment unit 1355 and the quantization unit 1356 can share a comparator, as shown in FIG9 . In the adaptive stage, the second input terminal of the comparator can be connected to a constant voltage V th In the quantization stage, the second input of the comparator can be connected to a ramp voltage that changes at a set rate.

[0221] A third optional embodiment adopts a static readout method, and enables the analog-to-digital conversion module to support digital readout in the floating-point domain through a dynamic adjustment unit. With the static readout method, the output voltage or output current of the operational amplifier unit will tend to stabilize after the RC response effect. Therefore, there is no need to specify a specific sampling time as a certain value, but rather to ensure that the output voltage or output current is stable. If the overall stabilization time of the circuit is 20ns, then its sampling time can be [20ns, 200ns]. This method reduces the accuracy requirements of the sampling time and is based on the output voltage or output current being stable, which can improve the accuracy of the floating-point number read out.

[0222] The floating-point calculation of the embodiment of the present application can also be applied to the field of optical computing, and simulated optical computing is also a form of analog computing. The following describes a computing device for simulated optical computing.

[0223] In a fourth optional embodiment, as shown in Figures 19 and 21 , the analog computing module may use an optical computing link 123. The input analog signal of the optical computing link 123 may be an input optical analog signal, that is, the digital-to-analog conversion module 110 may be configured to convert the input floating-point number into the input optical analog signal.

[0224] As shown in Figures 19 and 21, the digital-to-analog conversion module 110 may include a mantissa conversion unit 117, a gain adjustment unit 118, and an electro-optical conversion unit 119. The mantissa conversion unit 117 may be used to convert the mantissa portion of an input floating-point number into an initial analog signal. The gain adjustment unit 118 may be used to perform gain adjustment on the initial analog signal based on the exponent portion of the input floating-point number to obtain an input electrical analog signal. The electro-optical conversion unit 119 may be used to convert the input electrical analog signal into an input optical analog signal. The electro-optical conversion unit 119 may be implemented using a laser and a modulator.

[0225] In some embodiments, the mantissa conversion unit 117 can be implemented with reference to the structure of the mantissa conversion unit 113 described above, and is configured to convert the mantissa portion of the input floating-point number into an initial voltage analog signal. The gain adjustment unit 118 can be implemented with reference to the structure of the gain adjustment unit 114 described above, and is configured to perform gain adjustment on the initial voltage analog signal based on the exponent portion of the input floating-point number to obtain an input voltage analog signal. The electro-optical conversion unit 119 can convert the input voltage analog signal into an input optical analog signal.

[0226] In other embodiments, the mantissa conversion unit 117 may be implemented with reference to the structure of the mantissa conversion unit 115 described above, and is configured to convert the mantissa portion of the input floating-point number into an initial current analog signal. The gain adjustment unit 118 may be implemented with reference to the structure of the gain adjustment unit 116 described above, and is configured to perform gain adjustment on the initial current analog signal based on the exponent portion of the input floating-point number to obtain an input current analog signal. The electro-optical conversion unit 119 may convert the input current analog signal into an input optical analog signal.

[0227] Through the above process, the digital-to-analog conversion module 110 can convert the input floating-point number into an input optical analog signal and transmit the input optical analog signal to the analog computing module, namely the optical computing link 123. The optical computing link 123 can include an optical modulator composed of multiple lenses. The input optical analog signal passing through the optical modulator can be equivalent to a multiplication operation in the frequency domain, thereby achieving convolution in the time domain. As shown in Figure 20, a beam of light A (input optical analog signal) passes through the first lens 1231, which is equivalent to completing a Fourier transform (FT) operation. It is then modulated by the variable b in the frequency domain, which is equivalent to completing a multiplication in the frequency domain. It then passes through the second lens 1232 to perform an inverse Fourier transform (IFT) operation, obtaining the output result C (output optical analog signal). The variable b can be understood as reference data pre-stored in the optical computing link. The conversion from the input optical analog signal A to the output optical analog signal C completes frequency multiplication, which is equivalent to completing a convolution operation in the time domain.

[0228] The calculation result analog signal output by the optical calculation link 123 is an optical analog signal. The optical calculation link 123 outputs the calculation result analog signal to the analog-to-digital conversion module 130, and the analog-to-digital conversion module 130 converts the calculation result analog signal into a result floating-point number.

[0229] In some embodiments, as shown in FIG19 , the analog-to-digital conversion module 130 may include a signal conversion unit 137 and a mantissa output unit 138. The signal conversion unit 137 may be configured to determine a voltage value corresponding to the mantissa of the resulting floating-point number based on the received output optical analog signal and output the exponent of the resulting floating-point number. The mantissa output unit 138 may be configured to output the mantissa of the resulting floating-point number based on the voltage value corresponding to the mantissa of the resulting floating-point number.

[0230] The signal conversion unit 137 may include a first photoelectric conversion unit 1371 and an electrical-to-digital conversion unit 1372. The first photoelectric conversion unit 1371 may be used to convert the output optical analog signal into an output current analog signal, and the electrical-to-digital conversion unit 1372 may be used to determine the voltage value corresponding to the mantissa of the resulting floating-point number based on the output current analog signal, and output the exponent of the resulting floating-point number. For example, the first photoelectric conversion unit 1371 may be a photodiode or a photodiode. The electrical-to-digital conversion unit 1372 may be implemented with reference to the structure of the above-mentioned signal conversion unit 133, or with reference to the structure of the above-mentioned signal conversion unit 135, and will not be described in detail here.

[0231] In other embodiments, as shown in FIG21 , the analog-to-digital conversion module 130 may include a signal conversion unit 139 and a mantissa output unit 138. The signal conversion unit 139 may be configured to determine a voltage value corresponding to the mantissa of the resulting floating-point number based on the received output optical analog signal and output the exponent of the resulting floating-point number. The mantissa output unit 138 may be configured to output the mantissa of the resulting floating-point number based on the voltage value corresponding to the mantissa of the resulting floating-point number.

[0232] The signal conversion unit 139 may include a second photoelectric conversion unit 1391, a current-voltage conversion unit 1392, a dynamic adjustment unit 1393, and a quantization unit 1394. The second photoelectric conversion unit 1391 may be configured to output a current signal based on the received output optical analog signal; the current-voltage conversion unit 1392 may be configured to output a third voltage based on the current signal output by the second photoelectric conversion unit; the dynamic adjustment unit 1393 may be configured to adjust a conversion ratio parameter of the second photoelectric conversion unit for the output optical analog signal based on a change in the third voltage until the change amplitude of the third voltage is less than or equal to a second set amplitude threshold; the quantization unit 1394 may be configured to determine a voltage value corresponding to the mantissa of a resulting floating-point number based on the third voltage having a change amplitude less than or equal to the second set amplitude threshold; and the dynamic adjustment unit 1393 may further be configured to output an exponent of a resulting floating-point number based on the conversion ratio parameter of the second photoelectric conversion unit 1391 for the output optical analog signal when the change amplitude of the third voltage is less than or equal to the second set amplitude threshold.

[0233] For example, as shown in FIG22 , the second photoelectric conversion unit 1391 can be a photodiode or photodiode PD1. One end of the photodiode PD1 is connected to a control voltage, and the output end of the photodiode PD1 is connected to a clamping voltage. The voltage difference between the control voltage and the clamping voltage is called the bias voltage of the photodiode PD1. A current-to-voltage conversion unit 1392 is connected to the output end of the photodiode PD1. The photodiode PD1 can receive the output optical analog signal of the optical computing link and convert the output optical analog signal into a current signal. The current-to-voltage conversion unit 1392 can convert the current signal into a voltage signal and output a third voltage. Applying different bias voltages to the photodiode PD1 can give the photodiode PD1 different conversion ratio parameters for the output optical analog signal. The dynamic adjustment unit 1393 is connected to the output end of the current-to-voltage conversion unit 1392 and receives the third voltage output by the current-to-voltage conversion unit 1392. When the dynamic adjustment unit 1393 detects that the third voltage has reached a set voltage value, it can adjust the conversion ratio parameter of the photodiode PD1 for the output optical analog signal by reducing the bias voltage of the photodiode PD1.

[0234] Exemplarily, the dynamic adjustment unit 1393 may include a bias voltage calculation unit and a bias voltage generation unit. During initial operation, the bias voltage of the photodiode PD1 is set to an initial value. The dynamic adjustment unit 1393 monitors in real time whether the third voltage reaches the set voltage value. If the third voltage reaches the set voltage value, the dynamic adjustment unit 1393 can determine the bias voltage of the next gear corresponding to the adjustment through the bias voltage calculation unit. The bias voltage calculation unit can determine the bias voltage corresponding to the conversion ratio parameter of the next gear of the current gear (gain reduced to half) by querying the corresponding relationship table of the conversion ratio parameter (gain) and bias voltage of different gears. The correspondence between gain and bias voltage can also be represented by the curve diagram shown in Figure 23. The conversion ratio parameters 100, 10, and 1 in Figure 23 correspond to the first gear, the second gear, and the third gear, respectively. The correspondence between gain and bias voltage is different at different temperatures. The bias voltage calculation unit can determine the bias voltage corresponding to the conversion ratio parameter of the next gear of the current gear based on the current temperature by looking up the table. Based on the bias voltage and the clamping voltage, the control voltage corresponding to the photodiode PD1 is determined. The control voltage is a digital signal. The bias voltage generation unit can use a digital-to-analog converter. The digital-to-analog converter can convert the digital signal into a voltage analog signal. The control voltage of the photodiode PD1 is adjusted using the voltage analog signal, thereby adjusting the bias voltage of the photodiode PD1 and adjusting the conversion ratio parameter from the current gear to the next gear, so that the conversion ratio parameter corresponds to the bias voltage. The above steps are executed cyclically until the change amplitude of the third voltage is less than or equal to the second set amplitude threshold and the third voltage is less than the set voltage value. The dynamic adjustment unit 1393 can output the exponential part of the resulting floating-point number based on the conversion ratio parameter of the output optical analog signal of the second photoelectric conversion unit 1391. The quantization unit 1394 can determine the voltage value corresponding to the mantissa part of the resulting floating-point number based on the third voltage whose change amplitude is less than or equal to the second set amplitude threshold, and the mantissa output unit 138 can be used to output the mantissa part of the resulting floating-point number based on the voltage value corresponding to the mantissa part of the resulting floating-point number.

[0235] The above embodiments can be applied to an analog optical computing system, so that optical computing can be used for floating-point processing, and a solution for implementing adaptive dynamic range adjustment on a photoelectric conversion unit is provided.

[0236] The transistors in the above embodiments may be PNP transistors or PNP triodes, or may be NPN transistors or NPN triodes.

[0237] In each of the above embodiments, the exponent portion of the input floating-point number is directly sent to the digital-to-analog conversion module for signal conversion. In a fifth optional embodiment, the exponent portion of the floating-point number can be adjusted first and then sent to the digital-to-analog conversion module for signal conversion. As shown in Figure 24, the computing device 300 provided in this embodiment may include: an exponent preprocessing module 310, a digital-to-analog conversion module 320, an analog calculation module 330, an analog-to-digital conversion module 340, and an exponential post-processing module 350. The exponent preprocessing module 310 is connected between the digital processing module 200 and the digital-to-analog conversion module 320. The exponent preprocessing module 310 is configured to receive multiple floating-point numbers to be processed input from the digital processing module 200, adjust the exponent portions of the multiple floating-point numbers to be processed, obtain multiple input floating-point numbers, and input the multiple input floating-point numbers into the digital-to-analog conversion module 320. The digital-to-analog conversion module 320 is configured to convert the input floating-point numbers into input analog signals. The digital-to-analog conversion module 320 can be implemented using the digital-to-analog conversion module provided in any of the above embodiments. The analog calculation module 330 is used to perform analog calculation based on the input analog signal to obtain a calculation result analog signal. The analog calculation module 330 can adopt the analog calculation module provided by any of the above embodiments. The analog-to-digital conversion module 340 is used to convert the calculation result analog signal into a result floating-point number. The analog-to-digital conversion module 340 can adopt the analog-to-digital conversion module provided by any of the above embodiments, which will not be repeated here. The exponential post-processing module 350 is connected between the analog-to-digital conversion module 340 and the digital processing module 200. The analog-to-digital conversion module 340 transmits the result floating-point number to the exponential post-processing module 350. The exponential post-processing module 350 is used to receive the result floating-point number output by the analog-to-digital conversion module, and adjust the exponent part of the result floating-point number to obtain the target result floating-point number, and transmit the target result floating-point number to the digital processing module 200.

[0238] In some embodiments, the exponent preprocessing module 310 may adjust the exponents of multiple floating-point numbers to be processed using the process shown in FIG25 . The process may include the following steps:

[0239] S251, receiving a plurality of floating-point numbers to be processed, and obtaining exponent parts of the plurality of floating-point numbers to be processed.

[0240] S252: Determine whether the exponents of the floating-point numbers to be processed are all less than or equal to a set threshold; if yes, execute step S254; if not, execute step S253.

[0241] When there are multiple floating-point numbers involved in the calculation, the exponent preprocessing module 310 receives the multiple floating-point numbers to be processed, where each floating-point number to be processed includes an exponent portion and a mantissa portion. The exponent preprocessing module 310 obtains the exponent portion of each floating-point number to be processed and determines whether the exponent portion of each floating-point number to be processed is less than or equal to a set threshold.

[0242] For example, assuming that the exponent of the floating point number to be processed is 3 bits, the dynamic range of the floating point number processed by the computing device is [2 0 ~2 7 ], that is, the maximum floating-point number processed by the computing device is 128 times the minimum floating-point number. For the floating-point number with the smallest exponent part (exponent part is 0), the signal is very small after being converted into an analog signal, and is greatly affected by noise. If the exponent parts of multiple floating-point numbers to be processed input in a certain calculation are all small, and are all less than or equal to the set threshold, then the exponent parts of multiple floating-point numbers to be processed can be increased. For example, the set threshold can be 3. Assume that the exponent parts of multiple floating-point numbers to be processed input in a certain calculation are all within [2 0 ~2 2 ], it is considered that the exponent parts of the multiple floating-point numbers to be processed are all less than or equal to the set threshold, and the exponent parts of the multiple floating-point numbers to be processed can be increased.

[0243] S253: Transmit the multiple floating-point numbers to be processed as multiple input floating-point numbers to the digital-to-analog conversion module.

[0244] If, among the multiple floating-point numbers to be processed, there is at least one floating-point number to be processed whose exponent part is greater than a set threshold, the exponent parts of the multiple floating-point numbers to be processed may not be adjusted, and the multiple floating-point numbers to be processed may be used as multiple input floating-point numbers and directly transmitted to the digital-to-analog conversion module.

[0245] S254 , increasing the exponent parts of the plurality of floating-point numbers to be processed by the same reference value to obtain a plurality of input floating-point numbers, and transmitting the plurality of input floating-point numbers to the digital-to-analog conversion module.

[0246] If the exponent parts of multiple floating-point numbers to be processed are all less than or equal to the set threshold, the exponent parts of the multiple floating-point numbers to be processed can be increased by the same reference value to obtain multiple input floating-point numbers. The reference value can be determined based on the difference between the maximum value of the exponent parts of the multiple floating-point numbers to be processed and the theoretical maximum exponent. Assuming that the maximum value of the exponent parts of the multiple floating-point numbers to be processed is A and the theoretical maximum exponent of the floating-point number is B, then the reference value C=BA. When the exponent part of the floating-point number is 3 bits, the dynamic range of the floating-point number processed by the computing device is [2 0 ~2 7 ], the theoretical maximum exponent B is 7. If the exponents of multiple floating-point numbers to be processed in a certain calculation are all within [2 0 ~2 2 ], that is, the maximum value A in the exponent part of the multiple floating-point numbers to be processed is 2. At this time, BA=7-2=5, that is, C is 5. The exponent preprocessing module 310 can save the value of C and increase the exponent part of the multiple floating-point numbers to be processed by 5 to obtain multiple input floating-point numbers. The exponent part of the multiple input floating-point numbers is between [25 ~2 7 ], at this time, multiple input floating-point numbers are transmitted to the digital-to-analog conversion module, and after being converted into analog signals by the digital-to-analog conversion module, the obtained analog signal is 2 times the original analog signal. 5 =32 times, which is less affected by noise and is more conducive to obtaining accurate calculation results.

[0247] Since the exponent portion of the floating-point number is adjusted when passing through the exponential pre-processing module 310, after obtaining the result floating-point number, the exponent portion of the result floating-point number can be adjusted by the exponential post-processing module 350. For example, after receiving the result floating-point number, the exponent post-processing module 350 can read the value of C stored in the exponential pre-processing module 310 and determine whether the value of C is 0. If the value of C is 0, the result floating-point number can be directly output to the digital calculation module. If the value of C is not 0, the exponent portion of the received result floating-point number can be reduced by the reference value C to obtain the target result floating-point number, and the target result floating-point number can be output to the digital calculation module.

[0248] The above embodiment can be applied to the application scenario where the analog calculation process is linear calculation. For example, when the analog calculation module adopts RRAM array, in the first or third optional embodiment, assuming that the analog calculation formula is MAC(IN)=OUT, then in the fifth optional embodiment, the analog calculation formula is {MAC(2 C *IN)}*2 -C =OUT, it can be seen that the floating-point number obtained after calculation remains unchanged.

[0249] In some embodiments, multiple input floating-point numbers can be calculated with reference data pre-stored in the analog calculation module. Assuming that the reference data is a floating-point number, the digital preprocessing module can adjust the exponential part of the parameter data before saving the reference data to the analog calculation module. Exemplarily, if the parameter data (parameter matrix G or original conductivity matrix G) is too large or too small as a whole, making it difficult to program it into the array device of the analog calculation module, the exponential transformation of the overall parameter matrix G can be moved to the exponential preprocessing module or the exponential post-processing module by an equivalent transformation. Exemplarily, the original calculation method is as follows:

[0250] If the overall parameter matrix G is moved to the exponential preprocessing module, assuming that the exponential preprocessing module increases the exponential part of multiple floating-point numbers to be processed by n to obtain multiple input floating-point numbers, then the exponential preprocessing module can reduce the exponential part of the parameter matrix G by n, which can be expressed as:

[0251] If the overall parameter matrix G is moved to the exponential post-processing module, assuming that the exponential part of the parameter matrix G is increased by n, then the exponential part of the result floating-point number received by the exponential post-processing module is increased by n. At this time, the exponential post-processing module can reduce the exponential part of the result floating-point number by n, which can be expressed as:

[0252] Through the above process, the parameter data or parameter matrix can be processed in a "floating point offset" manner, so that the parameter data or parameter matrix supports the "block floating point" data format.

[0253] In other embodiments, the simulation calculation module can calculate multiple groups of input floating-point numbers, each group of input floating-point numbers can include one or more floating-point numbers. Exemplarily, the simulation calculation module can first save the first group of input floating-point numbers received, and when receiving the second group of input floating-point numbers, the second group of input floating-point numbers and the first group of input floating-point numbers are calculated. When the simulation calculation module is used to calculate multiple groups of input floating-point numbers, the exponent part of the floating-point numbers can be adjusted by group. Exemplarily, the exponent pre-processing module can be used to adjust the exponent part of multiple first floating-point numbers to be processed based on a first numerical value to obtain the first group of input floating-point numbers, and adjust the exponent part of multiple second floating-point numbers to be processed based on a second numerical value to obtain the second group of input floating-point numbers. The exponent post-processing module can be used to adjust the exponent part of the result floating-point number based on the first numerical value and the second numerical value. The first numerical value and the second numerical value can be the same numerical value or different numerical values.

[0254] For example, the simulation calculation module can perform vector multiplication on the first group of input floating-point numbers and the second group of input floating-point numbers, which can be expressed by the formula Mul(X,Y)=Z, z[i]=x[i]*y[i]. Wherein, X represents the first group of input floating-point numbers, Y represents the second group of input floating-point numbers, x[i] represents the i-th input floating-point number in the first group of input floating-point numbers, and y[i] represents the i-th input floating-point number in the second group of input floating-point numbers. The exponential preprocessing module can execute the process shown in Figure 25 on the floating-point numbers to be processed corresponding to the first group of input floating-point numbers X and the floating-point numbers to be processed corresponding to the second group of input floating-point numbers Y, respectively, based on the first numerical value C X The exponent parts of the plurality of first floating-point numbers to be processed are adjusted to obtain a first set of input floating-point numbers. Y The exponent part of the plurality of second floating point numbers to be processed is adjusted to obtain a second set of input floating point numbers. The exponent post-processing module can be used to adjust the exponent part of the plurality of second floating point numbers to be processed to obtain a second set of input floating point numbers. X and the second value C Y , adjust the exponent part of the result floating point number. If the exponent preprocessing module increases the exponent part of the first floating point number to be processed by C X, increase the exponent part of the second floating point number to be processed by C Y , then the exponential post-processing module can reduce the exponential part of the result floating point number by C X +C Y The process can be expressed as

[0255] In other embodiments, in order to make it easier to input the input floating-point number into the simulation calculation module, the exponential preprocessing module may also reduce the exponential part of the floating-point number to be processed to obtain the input floating-point number.

[0256] In the above-described embodiment, the exponential preprocessing module performs exponential preprocessing on floating-point numbers in the digital domain, thereby increasing or decreasing the overall exponential portion of a vector composed of multiple floating-point numbers in a single calculation. For example, when the dynamic range of the input floating-point numbers is limited and the overall exponential portion is relatively small, the exponential portions of the multiple floating-point numbers can be increased, resulting in a relatively large input analog signal after conversion by the analog-to-digital conversion module, thereby improving the signal-to-noise ratio of the analog calculation.

[0257] The present application also provides a computing chip, which may be the computing chip 10 shown in FIG1 . The computing chip is provided with the computing device provided in the above embodiment, which may be understood as a computing module in the computing chip. The computing chip may be a processor chip, such as a CPU chip, a GPU chip, a DSP chip, an AI chip, and the like.

[0258] Based on the same design concept as the above embodiment, the embodiment of the present application further provides a floating-point calculation method, as shown in FIG26 , which may include the following steps:

[0259] S261, converting the mantissa of the input floating-point number into an initial analog signal.

[0260] S262 , performing gain adjustment on the initial analog signal based on the exponential part of the input floating-point number to obtain an input analog signal.

[0261] When performing calculations on floating-point numbers, a computing device receives an input floating-point number, which may include an exponent portion and a mantissa portion. The computing device may convert the mantissa portion M of the input floating-point number into an initial analog signal using a digital-to-analog conversion module, and perform gain adjustment on the initial analog signal based on the exponent portion E of the input floating-point number to obtain the input analog signal.

[0262] In some embodiments, the input analog signal may be an input voltage analog signal. The computing device may convert the mantissa portion M of the input floating point number into an initial voltage analog signal. The process may be expressed as: V in(M) = M. The computing device can adjust the gain of the initial voltage analog signal based on the exponential part E of the input floating point number to obtain the input voltage analog signal. In the floating point number computing scenario with base 2, the process can be expressed as: V in (E,M)=V in (M)*2 E =M*2 E .

[0263] In other embodiments, the input analog signal may be an input current analog signal. The computing device may convert the mantissa M of the input floating-point number into an initial current analog signal, and perform gain adjustment on the initial current analog signal based on the exponent E of the input floating-point number to obtain the input current analog signal.

[0264] In some other embodiments, the input analog signal may be an input optical analog signal. The computing device may convert the input floating point number into an input electrical analog signal, and then convert the input electrical analog signal into an input optical analog signal.

[0265] S263, performing analog calculation based on the input analog signal to obtain a calculation result analog signal.

[0266] The computing device can perform analog calculations such as multiplication, division, multiplication and addition, and nonlinearity based on the input analog signal through the analog computing module to obtain a calculation result analog signal.

[0267] S264, converting the calculation result analog signal into a result floating point number.

[0268] The computing device may determine the voltage value corresponding to the mantissa of the result floating point number and the exponent of the result floating point number based on the calculation result analog signal, and output the mantissa of the result floating point number based on the voltage value corresponding to the mantissa of the result floating point number. The process may be expressed as: V out (E,M)=M*2 E .

[0269] In some embodiments, the calculation result analog signal may be an output current analog signal. The computing device may cyclically execute the following steps within a set time period: integrating the output current analog signal according to a first proportional parameter to obtain a first voltage, adjusting the first proportional parameter based on a change in the first voltage; determining a voltage value corresponding to the mantissa of the result floating-point number based on the first voltage obtained at the time when the set time period expires; and outputting an exponent of the result floating-point number based on the first proportional parameter corresponding to the time when the set time period expires.

[0270] In other embodiments, the calculation result analog signal may be an output current analog signal. The computing device may cyclically perform the following steps: converting the output current analog signal into a second voltage according to a second proportional parameter, adjusting the second proportional parameter based on a change in the second voltage until the change in the second voltage is less than or equal to a set voltage amplitude threshold; determining a voltage value corresponding to the mantissa of the result floating-point number based on the second voltage whose change is less than or equal to the set voltage amplitude threshold; and outputting an exponent of the result floating-point number based on the second proportional parameter when the change in the second voltage is less than or equal to the set voltage amplitude threshold.

[0271] In other embodiments, the calculation result analog signal may be an output current analog signal. The computing device may cyclically perform the following steps: adjusting a first current obtained based on the output current analog signal according to a third proportional parameter to obtain a second current, adjusting the third proportional parameter based on a change in the second current until the change in the second current is less than or equal to a set current amplitude threshold; determining a voltage value corresponding to the mantissa of the result floating-point number based on the second current when the change in the second current is less than or equal to the set current amplitude threshold; and outputting an exponent of the result floating-point number based on the third proportional parameter when the change in the second current is less than or equal to the set current amplitude threshold.

[0272] In other embodiments, the calculation result analog signal may be an output optical analog signal. The computing device may determine, based on the output optical analog signal, a voltage value corresponding to the mantissa of the resultant floating-point number and an exponent of the resultant floating-point number, and output the mantissa of the resultant floating-point number based on the voltage value corresponding to the mantissa of the resultant floating-point number. For example, the computing device may convert the output optical analog signal into an output current analog signal, and determine, based on the output current analog signal, a voltage value corresponding to the mantissa of the resultant floating-point number and an exponent of the resultant floating-point number.

[0273] In other embodiments, the calculation result analog signal may be an output optical analog signal. The computing device may cyclically perform the following steps: converting the output optical analog signal into a current signal according to a fourth proportional parameter, converting the current signal into a third voltage, adjusting the fourth proportional parameter based on a change in the third voltage until the change amplitude of the third voltage is less than or equal to a set amplitude threshold; determining a voltage value corresponding to the mantissa portion of the result floating-point number based on the third voltage when the change amplitude is less than or equal to the set amplitude threshold; and outputting the exponent portion of the result floating-point number based on the fourth proportional parameter when the change amplitude of the third voltage is less than or equal to the set amplitude threshold.

[0274] In the above embodiment, the input floating-point number is converted into an input analog signal, and the floating-point number calculation is completed in the analog domain, which can improve the calculation efficiency. In addition, the mantissa portion of the input floating-point number is first processed to convert the mantissa portion of the input floating-point number into an initial analog signal. Then, based on the exponent portion of the input floating-point number, the initial analog signal is gain-adjusted in the analog domain to obtain the input analog signal. When the exponent portion of the input floating-point number is different, the gain adjustment unit applies different gain multiples to the initial analog signal, and the resulting input analog signal is also different in size. This allows multiple input analog signals with different exponent portions to be converted into multiple input analog signals with different sizes.

[0275] In some embodiments, before converting the input floating-point number into the input analog signal, the computing device may further perform exponential preprocessing on the floating-point number to be processed. The exponential preprocessing process may include obtaining multiple floating-point numbers to be processed and adjusting the exponential portions of the multiple floating-point numbers to be processed to obtain multiple input floating-point numbers. After obtaining the result floating-point number, the computing device may further perform exponential postprocessing on the result floating-point number. The exponential postprocessing process may include adjusting the exponential portion of the result floating-point number and outputting a target result floating-point number.

[0276] In an optional embodiment, when the exponents of multiple floating-point numbers to be processed are all less than or equal to a set threshold, the computing device may increase the exponents of the multiple floating-point numbers to be processed by the same reference value to obtain multiple input floating-point numbers. The reference value is determined based on the maximum value of the exponents of the multiple floating-point numbers to be processed. After converting the calculation result analog signal into a result floating-point number, the exponent of the result floating-point number may be reduced by the reference value to obtain a target result floating-point number.

[0277] In an optional embodiment, if the input floating-point numbers include a first group of input floating-point numbers and a second group of input floating-point numbers, the computing device may adjust the exponents of the plurality of first floating-point numbers to be processed based on the first numerical value to obtain the first group of input floating-point numbers, and adjust the exponents of the plurality of second floating-point numbers to be processed based on the second numerical value to obtain the second group of input floating-point numbers. After converting the calculation result analog signal into the result floating-point number, the exponent of the result floating-point number may be adjusted based on the first numerical value and the second numerical value.

[0278] The exponential pre-processing and exponential post-processing performed by the computing device described above are performed in the digital domain and may be performed using hardware, or by executing a computer program, i.e., using software, or a combination of software and hardware. Furthermore, the computing device may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0279] It should be noted that those skilled in the art may make various modifications and variations to this application without departing from the spirit and scope of this application. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application is intended to include such modifications and variations.

Claims

1. A computing device, characterized in that: include: A digital-to-analog conversion module, used for converting the mantissa of the input floating-point number into an initial analog signal, and performing gain adjustment on the initial analog signal based on the exponential part of the input floating-point number to obtain an input analog signal; An analog calculation module, used for performing analog calculation based on the input analog signal to obtain a calculation result analog signal; The analog-to-digital conversion module is used to convert the calculation result analog signal into a result floating-point number.

2. The computing device according to claim 1, wherein: The analog-to-digital conversion module comprises: A signal conversion unit, configured to determine a voltage value corresponding to a mantissa of the result floating-point number based on the calculation result analog signal, and output an exponent of the result floating-point number; The mantissa output unit is used to output the mantissa part of the result floating point number based on the voltage value corresponding to the mantissa part of the result floating point number.

3. The computing device according to claim 2, characterized in that The calculation result analog signal is an output current analog signal; the signal conversion unit includes a first conversion unit and a first dynamic adjustment unit; The first conversion unit is used to convert the output current analog signal into a voltage signal; The first dynamic adjustment unit is used to adjust a conversion ratio parameter of the first conversion unit for the output current analog signal based on a change in the voltage signal; the conversion ratio parameter is used to characterize an exponential part of the result floating point number; The voltage signal output by the first conversion unit is used to represent a voltage value corresponding to the mantissa of the resulting floating-point number.

4. The computing device according to claim 3, characterized in that The signal conversion unit further comprises a first quantization unit; the first conversion unit is an active integration unit; The active integration unit is used to integrate the output current analog signal within a set time period to obtain a first voltage; The first quantization unit is used to transmit a control signal to the first dynamic adjustment unit based on a change of the first voltage within the set time period; The first dynamic adjustment unit is used to adjust the conversion ratio parameter of the active integration unit for the output current analog signal based on the control signal from the first quantization unit within the set time period; The first quantization unit is further used to determine a voltage value corresponding to the mantissa of the result floating-point number according to the first voltage output by the active integration unit at the time when the set time length arrives; The first dynamic adjustment unit is further configured to output the exponential part of the result floating point number according to the conversion ratio parameter of the output current analog signal by the active integration unit at the time when the set time duration arrives.

5. The computing device according to claim 4, characterized in that: The active integration unit comprises an integrator, the integrator is used to receive the output current analog signal and output a first voltage based on the output current analog signal; The first quantization unit comprises a first comparator, wherein a first input terminal of the first comparator is connected to an output terminal of the integrator and is used to receive a first voltage output by the integrator, and a second input terminal of the first comparator is used to connect a ramp signal generating circuit, wherein the ramp signal generating circuit is used to provide a constant voltage to the first comparator within the set time period, and after reaching the set time period, provide the first comparator with a ramp voltage that changes at a set rate; The first dynamic adjustment unit includes multiple capacitor branches, a first end of each of the multiple capacitor branches is connected to the input end of the integrator, and a second end is connected to the output end of the integrator, and each capacitor branch is connected to a trigger, and the input end of each trigger is connected to the output end of the first comparator, and is used to control the corresponding capacitor branch to be connected or disconnected under the action of the control signal output by the first comparator, so as to adjust the conversion ratio parameter of the active integration unit for the output current analog signal.

6. The computing device according to claim 3, characterized in that: The signal conversion unit further includes a second quantization unit; the first conversion unit is an operational amplifier unit; The operational amplifier unit is used to output a second voltage based on the output current analog signal; The first dynamic adjustment unit is used to adjust the output current simulation of the operational amplifier unit based on the change of the second voltage. The conversion ratio parameter of the signal is adjusted until the variation amplitude of the second voltage is less than or equal to the first set amplitude threshold; The second quantization unit is used to determine the voltage value corresponding to the mantissa of the result floating-point number according to the second voltage whose variation amplitude is less than or equal to the first set amplitude threshold; The first dynamic adjustment unit is further configured to output the exponential part of the result floating point number according to the conversion ratio parameter of the output current analog signal by the operational amplifier unit when the change amplitude of the second voltage is less than or equal to a first set amplitude threshold.

7. The computing device according to claim 6, characterized in that: The operational amplifier unit includes a first operational amplifier, and the first operational amplifier is used to receive the output current analog signal and output a second voltage; The first dynamic adjustment unit includes a second comparator, multiple triggers and multiple switch resistance branches; the first input end of the second comparator is connected to the output end of the first operational amplifier, for receiving the second voltage output by the first operational amplifier, and the second input end of the second comparator is used to input a reference voltage; the second comparator is used to output a control signal based on the change of the second voltage; the first end of each switch resistance branch in the multiple switch resistance branches is connected to the input end of the first operational amplifier, and the second end is connected to the output end of the first operational amplifier; the input ends of the multiple triggers are all connected to the output end of the second comparator; the output end of each trigger in the multiple triggers is connected to the corresponding switch resistance branch in the multiple switch resistance branches, and is used to control the corresponding switch resistance branch to be connected or disconnected under the action of the control signal output by the second comparator, so as to adjust the conversion ratio parameter of the operational amplifier unit for the output current analog signal.

8. The computing device according to claim 6, wherein: The operational amplifier unit includes an operational amplifier negative feedback circuit, a plurality of transistor branches and a current-voltage converter, wherein the operational amplifier negative feedback circuit is used to receive the output current analog signal; the plurality of transistor branches are connected between the output end of the operational amplifier negative feedback circuit and the input end of the current-voltage converter, and the current-voltage converter is used to convert the current signal output by the plurality of transistor branches into a second voltage; The first dynamic adjustment unit includes a third comparator and multiple triggers; the first input end of the third comparator is connected to the output end of the current-voltage converter, and is used to receive the second voltage output by the operational amplifier unit, and the second input end of the third comparator is used to input a reference voltage; the input ends of the multiple triggers are all connected to the output end of the third comparator; the output end of each trigger in the multiple triggers is connected to the corresponding transistor branch in the multiple transistor branches, and is used to control the corresponding transistor branch to be connected or disconnected under the action of the control signal output by the third comparator, so as to adjust the conversion ratio parameter of the operational amplifier unit for the output current analog signal.

9. The computing device according to claim 2, characterized in that: The calculation result analog signal is an output optical analog signal; the signal conversion unit comprises: A first photoelectric conversion unit, used for converting the output light analog signal into an output current analog signal; The electric-to-digital conversion unit is used to determine the voltage value corresponding to the mantissa part of the result floating-point number based on the output current analog signal, and output the exponent part of the result floating-point number.

10. The computing device according to claim 2, wherein: The calculation result analog signal is an output optical analog signal; the signal conversion unit comprises: A second photoelectric conversion unit, configured to output a current signal based on the output optical analog signal; a current-to-voltage conversion unit, configured to output a third voltage based on the current signal output by the second photoelectric conversion unit; a second dynamic adjustment unit, configured to adjust a conversion ratio parameter of the second photoelectric conversion unit for the output optical analog signal based on a change in the third voltage, until a change amplitude of the third voltage is less than or equal to a second set amplitude threshold; A third quantization unit, used to determine a voltage value corresponding to the mantissa of the result floating-point number according to a third voltage whose variation amplitude is less than or equal to a second set amplitude threshold; The second dynamic adjustment unit is further configured to output the exponential part of the result floating point number according to the conversion ratio parameter of the output optical analog signal by the second photoelectric conversion unit when the variation amplitude of the third voltage is less than or equal to a second set amplitude threshold.

11. The computing device according to claim 10, characterized in that When the second dynamic adjustment unit detects that the third voltage reaches a set voltage value, the second dynamic adjustment unit adjusts the conversion ratio parameter of the second photoelectric conversion unit for the output optical analog signal by adjusting the bias voltage of the second photoelectric conversion unit.

12. The computing device according to any one of claims 1 to 8, characterized in that: The digital-to-analog conversion module includes a mantissa conversion unit and a gain adjustment unit: A mantissa conversion unit, used for converting the mantissa part of the input floating point number into an initial analog signal; The gain adjustment unit is used to perform gain adjustment on the initial analog signal based on the exponential part of the input floating point number to obtain the input analog signal.

13. The computing device according to claim 12, characterized in that: The input analog signal is an input voltage analog signal, and the initial analog signal is an initial voltage analog signal; the mantissa conversion unit includes a reference unit and a gating unit; The reference unit is used to provide an equidistant voltage for the gating unit; The gating unit is used to convert the mantissa part into the initial voltage analog signal based on the equidistant voltage.

14. The computing device according to claim 13, characterized in that: The gain adjustment unit includes a second operational amplifier and a plurality of feedback resistance branches; A first input terminal of the second operational amplifier is connected to an output terminal of the gating unit, and a second input terminal of the second operational amplifier is connected to a reference resistor; The first ends of the multiple feedback resistor branches are all connected to the second input end of the second operational amplifier, and the second ends of the multiple feedback resistor branches are all connected to the output end of the second operational amplifier; the multiple feedback resistor branches connect part or all of the feedback resistor branches based on the exponential part of the input floating-point number, and gain adjust the initial voltage analog signal output by the selection unit to obtain the input voltage analog signal.

15. The computing device according to any one of claims 12 to 14, characterized in that: The analog computing module adopts a resistive random access memory RRAM array.

16. The computing device according to claim 12, wherein: The input analog signal is an input current analog signal, and the initial analog signal is an initial current analog signal; the mantissa conversion unit adopts a current mirror structure; the current mirror structure includes a reference transistor and a plurality of output transistor branches; the plurality of output transistor branches are used to receive the mantissa part of the input floating-point number and output the initial current analog signal.

17. The computing device according to claim 16, characterized in that The mantissa of the input floating point number includes N bits; The current mirror structure includes N output transistor branches; each of the N output transistor branches is used to receive one bit among the N bits.

18. The computing device according to claim 16, wherein: The mantissa of the input floating point number includes N bits; The current mirror structure includes M output transistor branches; the M output transistor branches are used to receive a thermometer code converted from N bits of the mantissa; the thermometer code includes M bits.

19. The computing device according to any one of claims 16 to 18, characterized in that: The gain adjustment unit includes multiple switch-controlled transistor branches; the multiple switch-controlled transistor branches are used to provide multiple gain adjustment coefficients, and the multiple switch-controlled transistor branches are used to determine the target gain adjustment coefficient based on the exponential part of the input floating-point number, and use the target gain adjustment coefficient to gain adjust the initial current analog signal to obtain the input current analog signal.

20. The computing device according to any one of claims 16 to 19, characterized in that: The analog computing module uses a flash memory transistor array.

21. The computing device according to any one of claims 1 to 2 and 9 to 11, characterized in that: The input analog signal is an input optical analog signal, and the digital-to-analog conversion module includes: A mantissa conversion unit, used for converting the mantissa part of the input floating point number into an initial analog signal; A gain adjustment unit is used to perform gain adjustment on the initial analog signal based on the exponential part of the input floating point number to obtain an output Input power analog signal; The electro-optical conversion unit is used to convert the input electrical analog signal into the input optical analog signal.

22. The computing device according to claim 21, characterized in that The analog computing module uses an optical computing link.

23. The computing device according to any one of claims 1 to 22, characterized in that: The computing device further comprises an exponential preprocessing module and an exponential postprocessing module; the exponential preprocessing module is connected to the digital-to-analog conversion module; the exponential postprocessing module is connected to the analog-to-digital conversion module; The exponential preprocessing module is used to adjust the exponential parts of a plurality of floating-point numbers to be processed, obtain a plurality of input floating-point numbers, and input the plurality of input floating-point numbers into the digital-to-analog conversion module; The exponential post-processing module is used to receive the result floating-point number output by the analog-to-digital conversion module, and adjust the exponential part of the result floating-point number to obtain a target result floating-point number.

24. The computing device according to claim 23, characterized in that The exponential preprocessing module is used for increasing the exponential parts of the plurality of floating-point numbers to be processed by the same reference value to obtain the plurality of input floating-point numbers when the exponential parts of the plurality of floating-point numbers to be processed are all less than or equal to a set threshold; The reference value is determined according to the maximum value of the exponent parts of the plurality of floating point numbers to be processed; The exponential post-processing module is used to reduce the exponential part of the result floating point number by the reference value.

25. The computing device according to claim 23, characterized in that The input floating-point numbers include a first group of input floating-point numbers and a second group of input floating-point numbers; the simulation calculation module is used to perform vector multiplication on the first group of input floating-point numbers and the second group of input floating-point numbers; The exponential preprocessing module is used to adjust the exponent parts of the plurality of first floating-point numbers to be processed based on the first value to obtain the first group of input floating-point numbers, and to adjust the exponent parts of the plurality of second floating-point numbers to be processed based on the second value to obtain the second group of input floating-point numbers; The exponential post-processing module is used to adjust the exponent part of the result floating point number based on the first value and the second value.

26. A computing chip, characterized in that: A computing device comprising any one of claims 1 to 25.

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