Display panel and display apparatus

Abstract

A display panel and a display apparatus. Pulse width modulation modules of a plurality of sub-pixels comprised in a same sub-pixel group receive a same frequency sweep signal; and pulse width modulation modules and pulse amplitude modulation modules of a plurality of sub-pixels comprised in a same sub-pixel group receive a same light-emitting control signal. Time points at which pixel driving circuits comprised in at least two sub-pixel groups start to provide circulation paths for corresponding driving currents on the basis of corresponding light-emitting control signals are different.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Hybrid drive architectures that combine Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) drive architectures are becoming a hotly sought-after driver solution in the industry because they can improve characteristic drift in micro-LEDs and enhance grayscale segmentation capabilities.

[0003] However, hybrid drive architectures typically use a synchronous lighting mode (i.e., data must be written to all rows of sub-pixels before all rows of sub-pixels are collectively illuminated under the control of a global sweep signal). In this synchronous lighting mode, the lighting duration within a frame is affected by the data writing time. Short lighting durations require relatively high drive currents and voltage drops, making it difficult to achieve high-resolution displays. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a display panel and a display device, which are conducive to realizing a high-resolution display design of the display panel.

[0005] An embodiment of the present application provides a display panel comprising a plurality of light-emitting lines, a plurality of scanning lines, and a plurality of sub-pixel groups. The plurality of light-emitting lines are configured to transmit a plurality of light-emitting control signals, and the plurality of scanning lines are configured to transmit a plurality of scanning signals; each sub-pixel group comprises a plurality of sub-pixels, and each sub-pixel comprises a light-emitting device and a pixel driving circuit. The pixel driving circuit is configured to provide a flow path for a driving current that drives the light-emitting device to emit light according to the corresponding light-emitting control signal. The pixel driving circuit comprises a pulse amplitude modulation module and a pulse width modulation module. The pulse amplitude modulation module is configured to receive a corresponding pulse amplitude modulation voltage to control the pulse amplitude of the driving current. When the pixel driving circuit provides a flow path for the driving current according to the corresponding light-emitting control signal, the pulse width modulation module is configured to control the pulse width of the driving current through the pulse amplitude modulation module according to the corresponding scanning signal and pulse width modulation voltage. Among them, the pulse width modulation modules of the multiple sub-pixels included in the same sub-pixel group are used to receive the same scanning frequency signal, and the pulse width modulation modules and the pulse amplitude modulation modules of the multiple sub-pixels included in the same sub-pixel group are used to receive the same light-emitting control signal; the pixel driving circuits included in at least two sub-pixel groups have different starting times for providing flow paths for the corresponding driving currents according to the corresponding light-emitting control signals.

[0006] The present application also provides a display device, comprising any of the above-mentioned display panels. Beneficial effects

[0007] Compared with the prior art, the display panel and display device provided in the embodiments of the present application enable the pulse width modulation modules of multiple sub-pixels included in the same sub-pixel group to receive the same sweep frequency signal, and the pulse width modulation modules and pulse amplitude modulation modules of multiple sub-pixels included in the same sub-pixel group to receive the same light-emitting control signal. The pixel driving circuits included in at least two sub-pixel groups provide flow paths for corresponding driving currents according to the corresponding light-emitting control signals at different starting times, so that the multiple sub-pixels included in the same sub-pixel group emit light synchronously. The sub-pixels included in at least two sub-pixel groups start to emit light at different starting times, so that the display panel does not need to make all rows of sub-pixels emit light collectively under the control of a global sweep frequency signal after all sub-pixels have written data. This is conducive to realizing the regulation of the light-emitting duration of the sub-pixels in at least two sub-pixel groups, so that the display panel can achieve a high-resolution design. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG1A is a curve showing the electro-optical conversion efficiency and driving current of sub-pixels of different luminous colors;

[0009] FIG1B is a curve showing the variation of the emission wavelength and the driving current of sub-pixels of different emission colors;

[0010] FIG2 is a schematic diagram of a driving architecture of a display panel;

[0011] FIG3 is a timing diagram corresponding to the schematic diagram of the driving architecture of the display panel shown in FIG2 ;

[0012] 4A and 4B are schematic structural diagrams of a display panel provided in an embodiment of the present application;

[0013] FIG4C is a schematic diagram of a driving architecture of a display panel provided in an embodiment of the present application;

[0014] 5A and 5B are comparative schematic diagrams of display panel signal writing methods provided by embodiments of the present application;

[0015] 6A to 6E are comparative schematic diagrams of display panel splicing methods provided in embodiments of the present application;

[0016] 7A and 7B are schematic structural diagrams of a gate driving unit provided in an embodiment of the present application;

[0017] FIG8 is a timing diagram corresponding to the gate driving unit shown in FIG7B ;

[0018] 9A-9B are timing diagrams corresponding to the driving architecture diagram of the display panel shown in FIG4B ;

[0019] FIG10 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0020] FIG11 is a timing diagram corresponding to the pixel driving circuit shown in FIG10 . Modes for Carrying Out the Invention

[0021] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0022] Specifically, FIG1A is a curve showing the change of the electro-optical conversion efficiency and the driving current of sub-pixels of different luminous colors, and FIG1B is a curve showing the change of the luminous wavelength and the driving current of sub-pixels of different luminous colors.

[0023] In display panels whose sub-pixels are composed of inorganic light-emitting devices (including micro-LEDs that emit red, green, and blue light), the luminous efficiency and wavelength of the emitted light vary depending on the intensity or amplitude of the driving current I, reducing the reproducibility of image color. Therefore, the pulse amplitude modulation (PAM) method used for organic light-emitting devices (such as organic light-emitting diodes) to achieve sub-pixel grayscale expression is no longer suitable for display panels using micro-LEDs.

[0024] Pulse Width Modulation (PWM), which achieves grayscale segmentation by fixing the drive current I and varying the emission duration, can improve the problem of luminous efficiency and wavelength drift in micro-light-emitting devices as the drive current I changes. Figure 2 shows a schematic diagram of the display panel's drive architecture. Given the limited number of bits that can be achieved with pure pulse width modulation for grayscale segmentation, a hybrid drive scheme combining pulse width modulation and pulse amplitude modulation (PAM) can address the problem of characteristic drift in micro-light-emitting devices while also improving grayscale segmentation capabilities. Control signal 1 includes the pulse width modulation voltage PWDA, the gate control signal Scan_PWM(n) acting on the pulse width modulation module, the sweep signal Sweep, and the emission control signal EM_PWM. Control signal 2 includes the pulse amplitude modulation voltage PADA, the gate control signal Scan_PAM(n) acting on the pulse amplitude modulation module, and the emission control signal EM_PAM.

[0025] FIG3 is a timing diagram corresponding to the schematic diagram of the driving architecture of the display panel shown in FIG2 . In which, Vth represents the threshold voltage. The hybrid driving scheme shown in FIG2 is usually a synchronous light-emitting mode (i.e., it is necessary to first write the data of all rows (such as m rows) and then realize the collective light-emitting of all rows under the control of the global sweep signal Sweep). As a result, the light-emitting time of the sub-pixel within one frame is affected by the data writing time. The relatively short light-emitting time requires a relatively high driving current and voltage drop, which is disadvantageous, making it difficult to achieve high-resolution display. Therefore, in order to enable the display panel to achieve high-resolution display, the present application provides a display panel and a display device.

[0026] Figures 4A and 4B are schematic diagrams of the structure of a display panel provided in an embodiment of the present application, and Figure 4C is a schematic diagram of the driving architecture of a display panel provided in an embodiment of the present application. The present application provides a display panel comprising a plurality of emission lines EML, a plurality of scanning lines SWL, and a plurality of sub-pixel groups PiG.

[0027] The plurality of light emitting lines EML are configured to transmit a plurality of light emitting control signals EM. Optionally, each of the light emitting lines EML extends along a first direction D1, and the plurality of light emitting lines EML are arranged along a second direction D2.

[0028] The plurality of sweep lines SWL are configured to transmit a plurality of sweep signals Sweep. Optionally, the plurality of sweep signals Sweep may be generated by a driver chip.

[0029] Each of the sub-pixel groups PiG includes a plurality of sub-pixels Pi, and each of the sub-pixels Pi includes a light-emitting device Di and a pixel driving circuit 10 .

[0030] Optionally, the light-emitting device Di includes a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.

[0031] The pixel driving circuit 10 is configured to provide a flow path for a driving current for driving the light emitting device Di to emit light according to the corresponding light emitting control signal EM. The pixel driving circuit 10 includes a pulse amplitude modulation module 101 and a pulse width modulation module 102.

[0032] The pulse amplitude modulation module 101 is configured to receive a corresponding pulse amplitude modulation voltage PADA to control the pulse amplitude of the driving current. When the pixel driving circuit 10 provides a flow path for the driving current according to the corresponding light-emitting control signal EM, the pulse width modulation module 102 is configured to control the pulse width of the driving current through the pulse amplitude modulation module 101 according to the corresponding sweep signal Sweep and the pulse width modulation voltage PWDA.

[0033] Among them, the pulse width modulation module 102 of the multiple sub-pixels Pi included in the same sub-pixel group PiG is used to receive the same sweep signal Sweep, and the pulse width modulation module 102 and the pulse amplitude modulation module 101 of the multiple sub-pixels Pi included in the same sub-pixel group PiG are used to receive the same light-emitting control signal EM; the pixel driving circuit 10 included in at least two sub-pixel groups PiG has different starting moments for providing a flow path for the corresponding driving current according to the corresponding light-emitting control signal EM, so that the multiple sub-pixels Pi included in the same sub-pixel group PiG emit light synchronously, and the starting moments of the sub-pixels Pi included in at least two sub-pixel groups PiG are different, so that the display panel does not need to write data on all sub-pixels Pi, and then make all rows of sub-pixels Pi emit light collectively under the control of the global sweep signal, which is conducive to realizing the regulation of the light-emitting time of the sub-pixels Pi of at least two sub-pixel groups PiG, so that the display panel can achieve high-resolution design.

[0034] Optionally, the pixel driving circuits 10 included in different sub-pixel groups PiG have different starting moments for providing flow paths for the corresponding driving currents according to the corresponding light-emitting control signals EM, so that the multiple sub-pixels Pi included in the same sub-pixel group PiG emit light synchronously, while the sub-pixels Pi included in different sub-pixel groups PiG start to emit light at different starting moments, so that the display panel does not need to write data to all sub-pixels Pi before making all rows of sub-pixels Pi emit light collectively under the control of a global scanning signal, which is conducive to realizing the regulation of the light-emitting duration of the sub-pixels Pi of each sub-pixel group PiG, so that the display panel can achieve a high-resolution design.

[0035] Taking the display panel including two sub-pixel groups PiG as an example, the driving architecture of the display panel is described.

[0036] 4A to 4C , the plurality of light-emitting lines EML include a plurality of first light-emitting lines EML1 and a plurality of second light-emitting lines EML2 , wherein the plurality of first light-emitting lines EML1 are configured to transmit a first light-emitting control signal EM1 , and the plurality of second light-emitting lines EML2 are configured to transmit a second light-emitting control signal EM2 .

[0037] The plurality of sweep lines SWL include a plurality of first sweep lines SWL1 and a plurality of second sweep lines SWL2 , wherein the plurality of first sweep lines SWL1 are configured to transmit a first sweep signal Sweep1 , and the plurality of second sweep lines SWL2 are configured to transmit a second sweep signal Sweep2 .

[0038] The plurality of sub-pixel groups PiG include a first sub-pixel group PiG1 and a second sub-pixel group PiG2.

[0039] The pixel driving circuits 10 of the plurality of sub-pixels Pi included in the first sub-pixel group PiG1 are electrically connected to the plurality of first emission lines EML1, and the pulse width modulation modules 102 of the plurality of sub-pixels Pi included in the first sub-pixel group PiG1 are electrically connected to the plurality of first sweep lines SWL1. The pixel driving circuits 10 of the plurality of sub-pixels Pi included in the first sub-pixel group PiG1 are configured to provide a flow path for the corresponding drive current according to the first emission control signal EM1, and the pulse width modulation modules 102 of the plurality of sub-pixels Pi included in the first sub-pixel group PiG1 are configured to control the pulse width of the corresponding drive current through the pulse amplitude modulation modules 101 of the plurality of sub-pixels Pi included in the first sub-pixel group PiG1 according to the corresponding pulse width modulation voltage PWDA and the first sweep signal Sweep1. The first emission control signal EM1 may include a signal EM1_PAM acting on the pulse amplitude modulation module 101 and a signal EM1_PWM acting on the pulse width modulation module 102. Optionally, EM1_PAM and EM1_PWM may be the same signal or different signals.

[0040] The pixel driving circuits 10 of the plurality of sub-pixels Pi included in the second sub-pixel group PiG2 are electrically connected to the plurality of second emission lines EML2, and the pulse width modulation modules 102 of the plurality of sub-pixels Pi included in the second sub-pixel group PiG2 are electrically connected to the plurality of second sweep lines SWL2. The plurality of pixel driving circuits 10 included in the second sub-pixel group PiG2 are configured to provide a flow path for the corresponding drive current according to the second emission control signal EM2. The pulse width modulation modules 102 of the plurality of sub-pixels Pi included in the second sub-pixel group PiG2 are configured to control the pulse width of the corresponding drive current in coordination with the pulse amplitude modulation modules 101 of the plurality of sub-pixels Pi included in the second sub-pixel group PiG2 according to the corresponding pulse width modulation voltage PWDA and the second sweep signal Sweep2. The second emission control signal EM2 may include a signal EM2_PAM acting on the pulse amplitude modulation module 101 and a signal EM2_PWM acting on the pulse width modulation module 102. Optionally, EM2_PAM and EM2_PWM may be the same signal or different signals.

[0041] By making the multiple sub-pixels Pi included in the first sub-pixel group PiG1 and the multiple sub-pixels Pi included in the second sub-pixel group PiG2 use different light-emitting control signals EM and sweep signals Sweep, the light-emitting durations of the sub-pixels Pi included in the first sub-pixel group PiG1 and the second sub-pixel group PiG2 can be controlled separately, which is beneficial to reducing the influence of the data writing duration of the sub-pixels Pi on the light-emitting duration, and is beneficial to achieving high-resolution design of the display panel.

[0042] Optionally, each of the sub-pixel groups PiG includes at least a plurality of the sub-pixels Pi located in the same row, so that when the plurality of the sub-pixels Pi in the same row are scanned using the row-by-row scanning technology, the plurality of the sub-pixels Pi located in the same row and synchronously entering the data writing stage and the light-emitting stage belong to the same sub-pixel group PiG, which is beneficial to reducing control complexity.

[0043] Accordingly, still taking the display panel including two sub-pixel groups PiG (i.e., a first sub-pixel group PiG1 and a second sub-pixel group PiG2) as an example, the following describes a situation in which each sub-pixel group PiG includes at least a plurality of sub-pixels Pi located in the same row. The first sub-pixel group PiG1 includes at least a plurality of sub-pixels Pi located in the same row, and the second sub-pixel group PiG2 includes at least a plurality of sub-pixels Pi located in the same row. The plurality of sub-pixels Pi included in the first sub-pixel group PiG1 and the plurality of sub-pixels Pi included in the second sub-pixel group PiG2 are located in different rows.

[0044] Optionally, each sub-pixel group PiG may further include multiple rows of multiple sub-pixels Pi, so that the multiple sub-pixels Pi in the same sub-pixel group PiG are controlled by the same emission control signal EM and the same sweep signal Sweep, thereby reducing the number of control signals used by the display panel, which is beneficial for reducing power consumption of the control end and reducing the number of driver chips used by the control end. The control end includes a timing controller, a source driver chip, a power driver chip, etc. for controlling the display panel to achieve display.

[0045] Accordingly, still taking the display panel including two sub-pixel groups PiG (i.e., a first sub-pixel group PiG1 and a second sub-pixel group PiG2) as an example, a description will be given of a situation in which each sub-pixel group PiG includes multiple rows of multiple sub-pixels Pi. The multiple sub-pixels Pi included in the first sub-pixel group PiG1 are located in different rows, and the multiple sub-pixels Pi included in the second sub-pixel group PiG2 are located in different rows.

[0046] Optionally, each of the sub-pixel groups PiG includes a plurality of sub-pixels Pi in a plurality of consecutive rows, as shown in FIG4A ; or a plurality of sub-pixel groups PiG include a plurality of rows of sub-pixels Pi that may be alternately arranged, as shown in FIG4B .

[0047] 5A and 5B are comparative diagrams of display panel signal writing methods according to embodiments of the present invention, wherein AA represents a display area; the power supply voltage VDD in FIG5B includes a first power supply voltage Vdd_PAM and a second power supply voltage Vdd_PWM.

[0048] Optionally, the plurality of sub-pixel groups PiG include a plurality of sub-pixels Pi in a plurality of consecutive rows. For example, the first sub-pixel group PiG1 includes a plurality of sub-pixels Pi in a plurality of consecutive rows m1, and the second sub-pixel group PiG2 includes a plurality of sub-pixels Pi in a plurality of consecutive rows m2.

[0049] Optionally, the multiple sub-pixels Pi in multiple consecutive rows included in each of the sub-pixel groups PiG may be located in the same display area, so that the light-emitting actions of the multiple sub-pixels Pi in the same display area remain synchronized.

[0050] Accordingly, still taking the display panel including two sub-pixel groups PiG (i.e., a first sub-pixel group PiG1 and a second sub-pixel group PiG2) as an example, the following describes a situation in which multiple consecutive rows of sub-pixels Pi included in each sub-pixel group PiG are located within the same display area. The display panel includes a first display area AA1 and a second display area AA2 adjacent to each other along the second direction D2. The first display area AA1 includes multiple consecutive rows of sub-pixels Pi, and the second display area AA2 includes multiple consecutive rows of sub-pixels Pi. The first sub-pixel group PiG1 includes multiple sub-pixels Pi located in the first display area AA1, and the second sub-pixel group PiG2 includes multiple sub-pixels Pi located in the second display area AA2.

[0051] Optionally, when each of the sub-pixel groups PiG includes a plurality of sub-pixels Pi in a plurality of consecutive rows, control signals applied to the plurality of sub-pixel groups PiG may be transmitted from frames on different sides of the display panel into the display panel.

[0052] For example, the display panel includes a first sub-pixel group PiG1 and a second sub-pixel group PiG2. Please continue to refer to Figure 5B. In this application, the driver chip IC provided on the chip-on-film (COF) on the lower frame transmits the first sweep signal Sweep1, the first light-emitting control signal EM1, and the power supply voltage signals VDD and VSS to the display panel; the chip-on-film (COF) provided on the upper frame transmits the second sweep signal Sweep2, the second light-emitting control signal EM2, and the power supply voltage signals VDD and VSS to the display panel. Therefore, the upper frame of the display panel is provided with pins electrically connecting the chip-on-film (COF) and the display panel, so that the second sweep signal Sweep2 and the second light-emitting control signal EM2 supplied by the driver IC can be transmitted to the display panel via the corresponding pins.

[0053] In the existing design (as shown in Figure 5A), all rows of sub-pixels Pi in the display panel are scanned row by row using the input gate control signals Scan_PAM and Scan_PWM in a row-by-row scanning manner, and the data signals (including PADA and PWDA) are used in conjunction with the row-by-row scanning to write data to all rows of sub-pixels Pi. The driver chip IC on the chip-on-film COF on the lower frame transmits the global scan signal Sweep, the light-emitting control signal EM and the power supply voltage signals VDD and VSS to the display panel; the chip-on-film COF on the upper frame transmits the power supply voltage signals VDD and VSS to the display panel.

[0054] When the sweep signal Sweep and the light-emitting control signal EM are transmitted, there will be losses on the line. However, in the present application, the sweep signal Sweep and the light-emitting control signal EM adopt the design of FIG5B , which shortens the transmission path of the sweep signal Sweep and the light-emitting control signal EM compared to the design shown in FIG5A . Therefore, the losses on the line of the sweep signal Sweep and the light-emitting control signal EM can be reduced, which is beneficial to improving the display effect of the display panel.

[0055] Figures 6A to 6E are schematic diagrams comparing display panel splicing methods provided in embodiments of the present application. The side of the display panel where the driver IC is located is the proximal end, and the side away from the proximal end is the distal end. The driver IC and the display panel can be electrically connected via a chip-on-film (COF).

[0056] In a display panel including a first sub-pixel group PiG1 and a second sub-pixel group PiG2, wherein the first sub-pixel group PiG1 includes m1 consecutive rows of sub-pixels Pi, and the second sub-pixel group PiG2 includes m2 consecutive rows of sub-pixels Pi, and when m1=m2, a first sweep signal Sweep1 and a second sweep signal Sweep2 are transmitted into the display panel via chip-on-film (COF) disposed on opposite sides of the display panel (the upper and lower frames shown in FIG5B ) (as shown in FIG6A ). This ensures that the trace lengths of the traces within the display panel for transmitting the first sweep signal Sweep1 and the second sweep signal Sweep2 are consistent (i.e., L1=L2), and the RC (R represents resistance, C represents capacitance) loads are consistent (as shown in FIG6B ), thereby achieving consistent display effects for the first sub-pixel group PiG1 and the second sub-pixel group PiG2. However, because chip-on-film is disposed on both the upper and lower frames of the display panel, only left-right splicing of the display panel is possible, as shown in FIG6B .

[0057] If a top-to-bottom splicing design is required for the display panel, the COFs located on the upper and lower frames need to be moved to the same frame side, as shown in Figure 6C. However, to meet both top-to-bottom splicing requirements and left-to-right splicing requirements, the COFs located on the upper and lower frames of the display panel are moved to the same frame side (as shown in Figure 6D). This results in inconsistent trace lengths (i.e., L2 = 2L1) within the display panel for transmitting the first sweep signal Sweep1 and the second sweep signal Sweep2. This results in a significant difference in the RC loads of the first sub-pixel group PiG1 and the second sub-pixel group PiG2, leading to a severe split-screen phenomenon when the first sub-pixel group PiG1 and the second sub-pixel group PiG2 are displayed.

[0058] In order to improve the display split screen problem, the multiple rows of sub-pixels Pi included in the multiple sub-pixel groups PiG are alternately arranged.

[0059] Optionally, the display panel includes A sub-pixel groups PiG, and the ath sub-pixel group PiG includes a plurality of sub-pixels Pi located in rows a+yA, so that the rows of sub-pixels Pi included in the plurality of sub-pixel groups PiG are alternately arranged. A>1, A≥a≥1, and y≥0.

[0060] Correspondingly, when the display panel only includes the first sub-pixel group PiG1 and the second sub-pixel group PiG2, the first sub-pixel group PiG1 includes multiple sub-pixels Pi located in odd rows, and the second sub-pixel group PiG2 includes multiple sub-pixels Pi located in even rows.

[0061] Correspondingly, please continue to refer to Figure 6E. The chip-on-film (COF) is arranged on the lower frame (can also be the upper frame) of the display panel. The first scanning signal Sweep1 is electrically connected to the multiple sub-pixels Pi in the odd rows included in the first sub-pixel group PiG1, and the second scanning signal Sweep2 is electrically connected to the multiple sub-pixels Pi in the even rows included in the second sub-pixel group PiG2, so that the wiring lengths for transmitting the first scanning signal Sweep1 and the second scanning signal Sweep2 in the display panel are consistent, thereby ensuring that the RC loads of the sub-pixels Pi in the odd rows and the sub-pixels Pi in the even rows remain consistent, thereby improving the split screen phenomenon.

[0062] Similarly, when the display panel includes 3 or more sub-pixel groups PiG, and multiple rows of sub-pixels Pi included in multiple sub-pixel groups PiG are arranged alternately, the routing lengths for transmitting multiple sweep signals Sweep in the display panel can also be set to be consistent to improve the split-screen phenomenon.

[0063] Optionally, the split screen phenomenon can be improved by providing the same number of gate driving units as the number of the sub-pixel groups PiG to match the design of multiple sub-pixel groups PiG.

[0064] Taking the display panel including the first sub-pixel group PiG1 and the second sub-pixel group PiG2 as an example, the design of the gate drive unit included in the display panel is described. Figures 7A and 7B are schematic structural diagrams of the gate drive unit provided in an embodiment of the present application, and Figure 8 is a timing diagram corresponding to the gate drive unit shown in Figure 7B.

[0065] 7A illustrates the design of a corresponding gate drive unit when each sub-pixel group PiG includes multiple sub-pixels Pi in multiple consecutive rows. Specifically, the display panel includes a gate drive unit that includes multiple cascaded gate drive circuits GOA, each of which is configured to output a gate control signal Scan for transmission via a corresponding scan line to the pixel drive circuit 10 in the corresponding row. When each sub-pixel group PiG includes multiple sub-pixels Pi in multiple consecutive rows, the gate control signals Scan applied to the multiple sub-pixel groups PiG can still be generated by the same gate drive unit.

[0066] 4A and 7A , the pulse amplitude modulation module 101 of each pixel driving circuit 10 includes a first driving transistor Tdr1, a first data transistor Tda1, and a first reset transistor Ti1. The pulse width modulation module 102 of each pixel driving circuit 10 includes a second driving transistor Tdr2, a second data transistor Tda2, and a second reset transistor Ti2. Then, the control end of the first data transistor Tda1 of the multiple sub-pixels Pi located in the x-th row is electrically connected to the output end of the x-th gate drive circuit GOA(x) through the corresponding first scan line SL1, the control end of the second data transistor Tda2 of the multiple sub-pixels Pi located in the x-th row is electrically connected to the output end of the x-th gate drive circuit GOA(x) through the corresponding third scan line SL3, the control end of the first reset transistor Ti1 of the multiple sub-pixels Pi located in the x-th row is electrically connected to the output end of the x-1-th gate drive circuit GOA(x-1) through the corresponding second scan line SL2, and the control end of the first reset transistor Ti1 of the multiple sub-pixels Pi located in the x-th row is electrically connected to the output end of the x-1-th gate drive circuit GOA(x-1) through the corresponding fourth scan line SL4. Wherein, x>0.

[0067] If the first sub-pixel group PiG1 includes a plurality of sub-pixels Pi located in the x-1th row to the xth row, and the second sub-pixel group PiG2 includes a plurality of sub-pixels Pi located in the x+1th row to the x+2th row, then the plurality of sub-pixels Pi located in the x-1th row to the xth row receive the first scanning signal Sweep1, and the plurality of sub-pixels Pi located in the x+1th row to the x+2th row receive the second scanning signal Sweep2, and the control end of the first data transistor Tda1 and the control end of the second data transistor Tda2 of the plurality of sub-pixels Pi located in the x-1th row can be electrically connected to the output end of the x-1th level gate drive circuit GOA(x-1), and the control end of the first reset transistor Ti1 and the control end of the second reset transistor Ti2 of the plurality of sub-pixels Pi located in the x-1th row are electrically connected to the output end of the x-2th level gate drive circuit GOA(x-2); The control end of the first data transistor Tda1 and the control end of the second data transistor Tda2 of the multiple sub-pixels Pi in the row can be electrically connected to the output end of the x+1-th level gate driving circuit GOA(x+1), and the control end of the first reset transistor Ti1 and the control end of the second reset transistor Ti2 of the multiple sub-pixels Pi in the x+1-th row are electrically connected to the output end of the x-th level gate driving circuit GOA(x); the control end of the first data transistor Tda1 and the control end of the second data transistor Tda2 of the multiple sub-pixels Pi in the x+2-th row can be electrically connected to the output end of the x+2-th level gate driving circuit GOA(x+2), and the control end of the first reset transistor Ti1 and the control end of the second reset transistor Ti2 of the multiple sub-pixels Pi in the x+2-th row are electrically connected to the output end of the x+1-th level gate driving circuit GOA(x+1).

[0068] 4B and 7B , taking the display panel including the first sub-pixel group PiG1 and the second sub-pixel group PiG2 as an example, the design of a gate driving unit cooperating with multiple sub-pixel groups PiG to improve the split-screen phenomenon is described.

[0069] The display panel includes a first gate driving unit and a second gate driving unit.

[0070] Optionally, the first gate driving unit and the second gate driving unit may be located in the same side frame of the display panel (such as the first gate driving unit and the second gate driving unit are both located in the left frame, or both located in the right frame), or may be located in two opposite side frames (such as one of the first gate driving unit and the second gate driving unit is located in the left frame, and the other is located in the right frame).

[0071] The first gate driving unit includes a plurality of cascaded first gate driving circuits GOA1 , and the plurality of cascaded first gate driving circuits GOA1 are electrically connected to the plurality of sub-pixels Pi included in the first sub-pixel group PiG1 .

[0072] The second gate driving unit includes a plurality of cascaded second gate driving circuits GOA2, and the plurality of cascaded second gate driving circuits GOA2 are electrically connected to the plurality of sub-pixels Pi included in the second sub-pixel group PiG2.

[0073] Among them, the first sub-pixel group PiG1 includes multiple sub-pixels Pi located in the mth row, which are electrically connected to the first gate driving circuit GOA1(m) of the mth level through the corresponding first scanning line SL1, so that the control end of the first data transistor Tda1 of the multiple sub-pixels Pi located in the mth row included in the first sub-pixel group PiG1 is electrically connected to the first gate driving circuit GOA1(m) of the mth level.

[0074] The first sub-pixel group PiG1 includes multiple sub-pixels Pi located in the mth row, which are electrically connected to the first gate drive circuit GOA1(m-1) of the m-1th level through the corresponding second scanning line SL2, so that the control end of the first reset transistor Ti1 of the multiple sub-pixels Pi located in the mth row included in the first sub-pixel group PiG1 is electrically connected to the first gate drive circuit GOA1(m-1) of the m-1th level.

[0075] The second sub-pixel group PiG2 includes multiple sub-pixels Pi located in the nth row, which are electrically connected to the n-level second gate drive circuit GOA2(n) through the corresponding first scanning line SL1, so that the control end of the first data transistor Tda1 of the multiple sub-pixels Pi located in the nth row included in the second sub-pixel group PiG2 is electrically connected to the n-level second gate drive circuit GOA2(n).

[0076] The plurality of sub-pixels Pi in the nth row included in the second sub-pixel group PiG2 are electrically connected to the n-1th-stage second gate driver circuit GOA2(n-1) via the corresponding second scan line SL2, so that the control terminals of the second reset transistors Ti2 of the plurality of sub-pixels Pi in the nth row included in the second sub-pixel group PiG2 are electrically connected to the n-1th-stage second gate driver circuit GOA2(n-1). Here, m>0, n>0.

[0077] Optionally, the control end of the first data transistor Tda1 and the control end of the second data transistor Tda2 included in each of the pixel driving circuits 10 are electrically connected, and the control end of the first reset transistor Ti1 and the control end of the second reset transistor Ti2 included in each of the pixel driving circuits 10 are electrically connected, so as to reduce the number of gate driving units and reduce the border width of the display panel.

[0078] Correspondingly, the multiple sub-pixels Pi located in the mth row included in the first sub-pixel group PiG1 are electrically connected to the first gate driving circuit GOA1(m) of the mth level through the corresponding third scanning line SL3, so that the control end of the second data transistor Tda2 of the multiple sub-pixels Pi located in the mth row included in the first sub-pixel group PiG1 is electrically connected to the first gate driving circuit GOA1(m) of the mth level.

[0079] The first sub-pixel group PiG1 includes a plurality of sub-pixels Pi located in the mth row, which are electrically connected to the m-1th level first gate drive circuit GOA1(m-1) through the corresponding fourth scan line SL4, so that the control end of the second reset transistor Ti2 of the plurality of sub-pixels Pi located in the mth row included in the first sub-pixel group PiG1 is electrically connected to the m-1th level first gate drive circuit GOA1(m-1).

[0080] The second sub-pixel group PiG2 includes a plurality of sub-pixels Pi located in the nth row, which are electrically connected to the nth-level second gate drive circuit GOA2(n) through the corresponding third scan line SL3, so that the control end of the second data transistor Tda2 of the plurality of sub-pixels Pi located in the nth row included in the second sub-pixel group PiG2 is electrically connected to the nth-level second gate drive circuit GOA2(n).

[0081] The second sub-pixel group PiG2 includes a plurality of sub-pixels Pi located in the nth row, which are electrically connected to the n-1th level second gate drive circuit GOA2(n-1) through the corresponding fourth scanning line SL4, so that the control end of the second reset transistor Ti2 of the plurality of sub-pixels Pi located in the nth row included in the second sub-pixel group PiG2 is electrically connected to the n-1th level second gate drive circuit GOA2(n-1).

[0082] Figure 8 is a timing diagram corresponding to the gate drive unit shown in Figure 7B, where U represents voltage, t represents time, and CK and XCK represent clock signals. Optionally, to increase the light-emitting duty cycle of the light-emitting device Di, the first gate drive unit is configured to receive a first start signal STV1 to generate a plurality of first gate control signals, and the second gate drive unit is configured to receive a second start signal STV2 to generate a plurality of second gate control signals. Among them, the effective pulse of the second start signal STV2 lags behind the effective pulses of the multiple first gate control signals (before the tA moment in Figure 8, the effective pulses of the multiple first gate control signals have been output), so that after the multiple sub-pixels Pi included in the first sub-pixel group PiG1 have completed the data writing operation, the second gate driving unit is controlled to output multiple gate control signals to control the multiple sub-pixels Pi included in the second sub-pixel group PiG2 to complete the data writing operation again, and then the multiple sub-pixels Pi included in the first sub-pixel group PiG1 can first emit light after completing the data writing operation. While the multiple sub-pixels Pi included in the first sub-pixel group PiG1 are emitting light, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 synchronously perform the data writing operation; until the multiple sub-pixels Pi included in the second sub-pixel group PiG2 have completed the data writing operation, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 emit light, and at the same time, the multiple sub-pixels Pi included in the first sub-pixel group PiG1 synchronously perform the data writing operation; this cycle is repeated, thereby improving the duty cycle of the sub-pixels Pi within one frame.

[0083] 9A and 9B are timing diagrams corresponding to the driving structure diagram of the display panel shown in FIG 4B. Optionally, the light emitting phases corresponding to the sub-pixels Pi of the plurality of sub-pixel groups PiG may partially overlap or may be completely staggered.

[0084] Optionally, continuing with the example of the display panel including the first sub-pixel group PiG1 and the second sub-pixel group PiG2, a design in which the light-emitting phases corresponding to the sub-pixels Pi of the multiple sub-pixel groups PiG partially overlap is described. Specifically, referring to FIG9A , the multiple pixel driving circuits 10 included in the first sub-pixel group PiG1 provide a flow path for the corresponding driving current according to the first light-emitting control signal EM1 at a first starting time ts1; and the multiple pixel driving circuits 10 included in the second sub-pixel group PiG2 provide a flow path for the corresponding driving current according to the second light-emitting control signal EM2 at a second starting time ts2. Among them, within the time period corresponding to the first starting moment ts1 to the second starting moment ts2, the pixel driving circuit 10 of the multiple sub-pixels Pi included in the second sub-pixel group PiG2 sequentially receives the corresponding pulse amplitude modulation voltage PADA and the corresponding pulse width modulation voltage PWDA, so that the multiple sub-pixels Pi of the first sub-pixel group PiG1 can emit light while the multiple sub-pixels Pi included in the second sub-pixel group PiG2 can synchronously perform data writing operations, thereby advancing the light-emitting start moment of the first sub-pixel group PiG1. The light-emitting action of the multiple sub-pixels Pi of the second sub-pixel group PiG2 can end at the end moment of the initialization stage of the multiple sub-pixels Pi of the first sub-pixel group PiG2. Therefore, the light-emitting stage of the multiple sub-pixels Pi of the second sub-pixel group PiG2 (such as t3(PiG2) in Figure 9A) can partially overlap with the light-emitting stage of the multiple sub-pixels Pi of the first sub-pixel group PiG1 (such as t3(PiG1) in Figure 9A) and the initialization stage of the multiple sub-pixels Pi of the first sub-pixel group PiG1, thereby improving the light-emitting duration of the multiple sub-pixels Pi of the first sub-pixel group PiG1 and the multiple sub-pixels Pi of the second sub-pixel group PiG2.

[0085] Optionally, the light emitting action of the plurality of sub-pixels Pi of the second sub-pixel group PiG2 may be ended at the start time of the initialization phase for the plurality of sub-pixels Pi of the first sub-pixel group PiG2.

[0086] That is, the multiple sub-pixels Pi included in the first sub-pixel group PiG1 first perform the data writing action (such as the t2 (PiG1) stage in Figure 9A), and then the multiple sub-pixels Pi included in the first sub-pixel group PiG1 emit light while the multiple sub-pixels Pi included in the second sub-pixel group PiG2 perform the data writing action (such as the t2 (PiG2) stage in Figure 9A); thereafter, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 and the multiple sub-pixels Pi included in the first sub-pixel group PiG1 all keep emitting light; thereafter, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 keep emitting light, and the multiple sub-pixels Pi included in the first sub-pixel group PiG1 enter the initialization stage; thereafter, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 enter the initialization stage, and the multiple sub-pixels Pi included in the first sub-pixel group PiG1 enter the data writing stage; thereafter, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 enter the data writing stage, and the multiple sub-pixels Pi included in the first sub-pixel group PiG1 enter the light-emitting stage; following this cycle, the display working principle of the display panel is obtained.

[0087] Specifically, the first sub-pixel group PiG1 includes multiple sub-pixels Pi in rows 1 to 325, and the second sub-pixel group PiG2 includes multiple sub-pixels Pi in rows 326 to 650. Compared to the existing system in which all rows of sub-pixels Pi share a single global sweep signal (i.e., after 650 rows of data are written, they are synchronously illuminated, and the illumination time for all rows is equal to 1 frame time - 650 rows of data writing time), the first sweep signal Sweep1 and the second sweep signal Sweep2 split the 650 rows into two parts for separate illumination. That is, after the data writing operation is completed for the sub-pixels Pi in rows 1 to 325, the first sweep signal Sweep1 and the first light-emitting control signal EM1 applied by the first sub-pixel group PiG1 control the multiple sub-pixels Pi in rows 1 to 325 to collectively emit light, thereby extending the light-emitting time of the sub-pixels Pi in rows 1 to 325 within a frame. Similarly, after the data writing operation is completed for the sub-pixels Pi in rows 326 to 650, the second sweep signal Sweep2 and the second light-emitting control signal EM2 applied by the second sub-pixel group PiG2 control the multiple sub-pixels Pi in rows 326 to 650 to collectively emit light, thereby extending the light-emitting time of the sub-pixels Pi in rows 326 to 650 within a frame. Therefore, the light-emitting time corresponding to the sub-pixels Pi in rows 1 to 650 = the length of one frame - the data writing time of 325 rows. Compared to existing designs where all rows of sub-pixels Pi share a global sweep signal, the illumination time of all rows of sub-pixels Pi in this application extends by 325 rows of data writing time. The duration of one frame corresponds to the difference between the next illumination start time of sub-pixel Pi and the current illumination start time. For example, for each row, the refresh time can be maintained at 8.333ms, and the display panel refresh rate remains at 120Hz.

[0088] Specifically, the first sub-pixel group PiG1 includes a plurality of sub-pixels Pi in odd rows, and the second sub-pixel group PiG2 includes a plurality of sub-pixels Pi in even rows. After data is written to the plurality of sub-pixels Pi in the odd rows included in the first sub-pixel group PiG1, the first sub-pixel group PiG1 applies a first sweep signal Sweep1 and a first light-emitting control signal EM1 to control the plurality of sub-pixels Pi in the odd rows to emit light collectively, thereby extending the light-emitting time of the sub-pixels Pi in the odd rows within one frame; similarly, after data is written to the plurality of sub-pixels Pi in the even rows included in the second sub-pixel group PiG2, the second sweep signal Sweep2 and the second light-emitting control signal EM2 applied by the second sub-pixel group PiG2 to control the plurality of sub-pixels Pi in the even rows to emit light collectively, thereby extending the light-emitting time of the sub-pixels Pi in the even rows within one frame.

[0089] It can be understood that the present application only describes an embodiment in which the light-emitting stages corresponding to the first sub-pixel group PiG1 and the second sub-pixel group PiG2 partially overlap. When the number of sub-pixel groups PiG included in the display panel is greater than 2, the working principle of the partial overlap of the light-emitting stages of multiple sub-pixel groups PiG can be obtained by referring to the working principle of the partial overlap of the light-emitting stages of the first sub-pixel group PiG1 and the second sub-pixel group PiG2.

[0090] When multiple sub-pixels Pi emit light simultaneously, while this effectively increases the proportion of their light-emitting time, it also results in higher power consumption. Therefore, to reduce the total instantaneous current of the display panel, minimize voltage drop, and improve display uniformity, the light-emitting phases of the multiple sub-pixel groups PiG can be completely staggered.

[0091] 9B , still taking the display panel including the first sub-pixel group PiG1 and the second sub-pixel group PiG2 as an example, the design in which the light emitting phases corresponding to the sub-pixels Pi of the plurality of sub-pixel groups PiG do not overlap is described.

[0092] The plurality of pixel driving circuits 10 included in the first sub-pixel group PiG1 start generating the corresponding driving current according to the first light-emitting control signal EM1 at a first starting time ts1; the plurality of pixel driving circuits 10 included in the second sub-pixel group PiG2 start generating the corresponding driving current according to the second light-emitting control signal EM2 at a second starting time ts2. The plurality of pixel driving circuits 10 included in the first sub-pixel group PiG1 stop generating the corresponding driving current according to the second light-emitting control signal EM2 at the second starting time ts2.

[0093] That is, the multiple sub-pixels Pi included in the first sub-pixel group PiG1 first perform the data writing action (such as the t2 (PiG1) stage in Figure 9B), and then the multiple sub-pixels Pi included in the first sub-pixel group PiG1 emit light (such as the t3 (PiG1) stage in Figure 9B), and the multiple sub-pixels Pi included in the second sub-pixel group PiG2 perform the data writing action (such as the t2 (PiG2) stage in Figure 9B); thereafter, when the multiple sub-pixels Pi included in the first sub-pixel group PiG1 finish emitting light and enter the initialization stage, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 start to emit light; thereafter, the multiple sub-pixels Pi included in the second sub-pixel group PiG2 emit light (such as the t3 (PiG2) stage in Figure 9B), and the multiple sub-pixels Pi included in the first sub-pixel group PiG1 perform the initialization and data writing actions; thereafter, when the multiple sub-pixels Pi included in the second sub-pixel group PiG2 finish emitting light and enter the initialization stage, the multiple sub-pixels Pi included in the first sub-pixel group PiG1 start to emit light; following this cycle, the display working principle of the display panel is obtained.

[0094] Specifically, the first sub-pixel group PiG1 includes multiple sub-pixels Pi in rows 1 to 325, and the second sub-pixel group PiG2 includes multiple sub-pixels Pi in rows 326 to 650. After the sub-pixels Pi in rows 1 to 325 complete the data writing operation, the first sub-pixel group PiG1 applies the first sweep signal Sweep1 and the first light-emitting control signal EM1 to control the multiple sub-pixels Pi in rows 1 to 325 to collectively emit light, thereby extending the light-emitting time of the sub-pixels Pi in rows 1 to 325 within one frame; when the multiple sub-pixels Pi in rows 1 to 325 finish emitting light, the sub-pixels Pi in rows 326 to 650 begin to emit light. Therefore, the sub-pixels Pi included in the first sub-pixel group PiG1 and the sub-pixels Pi included in the second sub-pixel group PiG2 do not emit light at the same time, which can reduce the instantaneous total current of the display panel, reduce the voltage drop, and improve display uniformity.

[0095] Specifically, the first sub-pixel group PiG1 includes a plurality of sub-pixels Pi in odd-numbered rows, and the second sub-pixel group PiG2 includes a plurality of sub-pixels Pi in even-numbered rows. When the plurality of sub-pixels Pi in the odd-numbered rows included in the first sub-pixel group PiG1 stop emitting light, the plurality of sub-pixels Pi in the even-numbered rows included in the second sub-pixel group PiG2 begin emitting light, thereby reducing the instantaneous total current of the display panel, reducing voltage drop, and improving display uniformity.

[0096] It can be understood that the present application only describes an embodiment in which the light-emitting stages corresponding to the first sub-pixel group PiG1 and the second sub-pixel group PiG2 do not overlap. When the number of sub-pixel groups PiG included in the display panel is greater than 2, the working principle of the non-overlapping light-emitting stages of multiple sub-pixel groups PiG can be obtained by referring to the working principle of the non-overlapping light-emitting stages of the first sub-pixel group PiG1 and the second sub-pixel group PiG2.

[0097] Optionally, before writing data to the plurality of sub-pixel groups PiG, an initialization operation (such as the t1 stage in Figures 9A and 9B) can be performed synchronously to initialize the potential of the first node N1 and the fourth node N4 in the pixel driving circuit 10, so that the display panel has a better display foundation.

[0098] FIG10 is a schematic diagram of the structure of a pixel driving circuit 10 provided in an embodiment of the present application. The pixel driving circuit 10 shown in FIG10 is only used to illustrate the structure of the pixel driving circuit 10 applicable to the present application, and is not used to limit the structure of the pixel driving circuit 10 used in the present application.

[0099] Continuing to refer to FIG. 10 , the pulse amplitude modulation module 101 includes a first driving module, a first data writing module, a first compensation module, a first reset module, and a first switch module.

[0100] The first driving module is configured to generate a driving current for driving the light emitting device Di to emit light according to a pulse amplitude modulation voltage PADA.

[0101] Optionally, the first driving module includes a first driving transistor Tdr1 and a first capacitor C1.

[0102] A control terminal of the first driving transistor Tdr1 is electrically connected to the first node N1 , an input terminal of the first driving transistor Tdr1 is electrically connected to the second node N2 , and an output terminal of the first driving transistor Tdr1 is electrically connected to the third node N3 .

[0103] A first capacitor C1 , wherein a first end of the first capacitor C1 is electrically connected to the first node N1 , and a second end of the first capacitor C1 is electrically connected to the second power supply end Vdd_PWM.

[0104] The first data writing module is configured to transmit the pulse amplitude modulation voltage PADA to the second node N2 according to a corresponding gate control signal.

[0105] Optionally, the first data writing module includes a first data transistor Tda1, a control end of the first data transistor Tda1 is electrically connected to the first scan line SL1, an input end of the first data transistor Tda1 is configured to receive the pulse amplitude modulation voltage PADA, and an output end of the first data transistor Tda1 is electrically connected to the second node N2.

[0106] The first compensation module is configured to electrically connect the first node N1 and the third node N3 according to a corresponding gate control signal.

[0107] Optionally, the first compensation module includes a first compensation transistor Tc1, the control end of the first compensation transistor Tc1 is electrically connected to the first scan line SL1, the input end of the first compensation transistor Tc1 is electrically connected to the third node N3, and the output end of the first compensation transistor Tc1 is electrically connected to the first node N1.

[0108] The first switch module is configured to electrically connect the first driving transistor Tdr1 , the first power supply terminal Vdd_PAM and the light emitting device Di according to a corresponding light emitting control signal EM.

[0109] Optionally, the first switching module includes a first switching transistor Ts1 and a second switching transistor Ts2. A control terminal of the first switching transistor Ts1 is electrically connected to the corresponding light-emitting line EML, an input terminal of the first switching transistor Ts1 is electrically connected to the first power supply terminal Vdd_PAM, and an output terminal of the first switching transistor Ts1 is electrically connected to the second node N2. A control terminal of the second switching transistor Ts2 is electrically connected to the control terminal of the first switching transistor Ts1, an input terminal of the second switching transistor Ts2 is electrically connected to the third node N3, and an output terminal of the second switching transistor Ts2 is electrically connected to the corresponding light-emitting device Di.

[0110] The first reset module is configured to electrically connect the first node N1 and the first reset line VL1 according to a corresponding gate control signal to transmit a first reset voltage transmitted by the first reset line VL1 to the first node N1 to initialize the potential of the first node N1.

[0111] Optionally, the first reset module includes a first reset transistor Ti1, the control end of the first reset transistor Ti1 is electrically connected to the second scan line SL2, the input end of the first reset transistor Ti1 is electrically connected to the first reset line VL1, and the output end of the first reset transistor Ti1 is electrically connected to the first node N1.

[0112] Continuing to refer to FIG. 10 , the pulse width modulation module 102 includes a second driving module, a second data writing module, a second compensation module, a second reset module, and a second switch module.

[0113] The second driving module is configured to control the first driving transistor Tdr1 to be turned on and off according to a pulse width modulation voltage PWDA and a corresponding sweep signal Sweep.

[0114] Optionally, the second driving module includes a second driving transistor Tdr2 and a second capacitor C2.

[0115] A control terminal of the second driving transistor Tdr2 is electrically connected to the fourth node N4 , an input terminal of the second driving transistor Tdr2 is electrically connected to the fifth node N5 , and an output terminal of the second driving transistor Tdr2 is electrically connected to the sixth node N6 .

[0116] A first end of the second capacitor C2 is electrically connected to the corresponding sweep line SWL, and a second end of the second capacitor C2 is electrically connected to a fourth node N4.

[0117] The second data writing module is configured to transmit the pulse width modulation voltage PWDA to the input terminal of the second driving transistor Tdr2 according to the corresponding gate control signal.

[0118] Optionally, the second data writing module includes a second data transistor Tda2, the control end of the second data transistor Tda2 is electrically connected to the third scan line SL3, the input end of the second data transistor Tda2 is configured to receive the pulse width modulation voltage PWDA, and the output end of the second data transistor Tda2 is electrically connected to the fifth node N5.

[0119] The second compensation module is configured to electrically connect the control terminal of the second driving transistor Tdr2 and the output terminal of the second driving transistor Tdr2 according to a corresponding gate control signal.

[0120] The second compensation module includes a second compensation transistor Tc2, the control end of the second compensation transistor Tc2 is electrically connected to the third scan line SL3, the input end of the second compensation transistor Tc2 is electrically connected to the sixth node N6, and the output end of the second compensation transistor Tc2 is electrically connected to the fourth node N4.

[0121] The second switch module is configured to electrically connect the second driving transistor Tdr2 , the second power supply terminal Vdd_PWM, and the first driving transistor Tdr1 according to a corresponding light emitting control signal EM.

[0122] Optionally, the second switch module includes a third switch transistor Ts3 and a fourth switch transistor Ts4. The control terminal of the third switch transistor Ts3 is electrically connected to the control terminal of the first switch transistor Ts1, the input terminal of the third switch transistor Ts3 is electrically connected to the second power supply terminal Vdd_PWM, and the output terminal of the third switch transistor Ts3 is electrically connected to the fifth node N5. The control terminal of the fourth switch transistor Ts4 is electrically connected to the control terminal of the third switch transistor Ts3, the input terminal of the fourth switch transistor Ts4 is electrically connected to the sixth node N6, and the output terminal of the fourth switch transistor Ts4 is electrically connected to the first node N1.

[0123] The second reset module is configured to electrically connect the fourth node N4 and the first reset line VL1 according to a corresponding gate control signal to transmit the first reset voltage transmitted by the first reset line VL1 to the fourth node N4 to initialize the potential of the fourth node N4.

[0124] The second reset module includes a second reset transistor Ti2, a control end of the second reset transistor Ti2 is electrically connected to the fourth scan line SL4, an input end of the second reset transistor Ti2 is electrically connected to the first reset line VL1, and an output end of the second reset transistor Ti2 is electrically connected to the fourth node N4.

[0125] Optionally, the pulse amplitude modulation module 101 also includes a third reset module, which is configured to transmit the second reset signal transmitted by the second reset line VL2 to the anode of the corresponding light-emitting device Di according to the discharge control signal Disc transmitted by the discharge scanning line DisL, so as to initialize the anode potential of the light-emitting device Di.

[0126] Optionally, the third reset module includes a third reset transistor Ti3, the control end of the third reset transistor Ti3 is electrically connected to the discharge scan line DisL, the input end of the third reset transistor Ti3 is electrically connected to the second reset line VL2, and the output end of the third reset transistor Ti3 is electrically connected to the corresponding light-emitting device Di.

[0127] Optionally, in order for the light-emitting device Di to emit light normally, the voltage supplied by the first power supply terminal Vdd_PAM>the voltage supplied by the second power supply terminal Vdd_PWM>the voltage corresponding to the first reset signal>the voltage corresponding to the second reset signal.

[0128] Optionally, the cathode of the light-emitting device Di is electrically connected to the third power supply terminal VSS.

[0129] Optionally, in some embodiments, the pixel driving circuit 10 may not include the first compensation transistor Tc1 and the second compensation transistor Tc2 for compensating for the threshold voltage of the driving transistor.

[0130] Optionally, each transistor included in the pixel driving circuit 10 may be of N-type or P-type, and the process of the transistor may be LTPS, a-Si, IGZO, etc.

[0131] Optionally, the light-emitting devices Di are arranged in a pixel-level number in the display panel.

[0132] FIG11 is a timing diagram corresponding to the pixel driving circuit 10 shown in FIG10 , where the sub-pixel Pi is located in the nth row, the transistors included in the pixel driving circuit 10 are P-type transistors, the control end of the first data transistor Tda1 receives the gate control signal Scan_PAM(n) output by the nth-stage gate driving circuit through the first scan line SL1, the control end of the first reset transistor Ti1 receives the gate control signal Scan_PAM(n-1) output by the n-1th-stage gate driving circuit through the second scan line SL2, and the control end of the second data transistor Tda2 receives the gate control signal Scan_PAM(n-1) output by the n-1th-stage gate driving circuit through the third scan line SL3. Scan_PWM(n), the control end of the second reset transistor Ti2 receives the gate control signal Scan_PWM(n-1) output by the n-1th level gate driving circuit through the fourth scan line SL4, the control end of the first switching transistor Ts1 and the control end of the second switching transistor Ts2 receive the light control signal EM through the corresponding light-emitting line EML as EM_PAM(n), the control end of the third switching transistor Ts3 and the control end of the fourth switching transistor Ts4 receive the light control signal EM through the corresponding light-emitting line EML as EM_PWM(n) as an example, the working principle of the pixel driving circuit 10 shown in Figure 10 is explained.

[0133] Initialization stage t1: the gate control signal Scan_PAM(n) received by the control end of the first data transistor Tda1 is high, and the gate control signal Scan_PWM(n) received by the control end of the second data transistor Tda2 is high; the gate control signal Scan_PAM(n-1) received by the control end of the first reset transistor Ti1 is low, and the gate control signal Scan_PWM(n-1) received by the control end of the second reset transistor Ti2 is low; the light-emitting control signal EM_PAM(n) received by the control end of the first switch transistor Ts1 and the control end of the second switch transistor Ts2 is high, and the light-emitting control signal EM_PWM(n) received by the control end of the third switch transistor Ts3 and the control end of the fourth switch transistor Ts4 is high.

[0134] The first reset transistor Ti1 and the second reset transistor Ti2 are turned on, and the first reset voltage transmitted by the first reset line VL1 is transmitted to the first node N1 through the first reset transistor Ti1, and the first reset voltage is transmitted to the fourth node N4 through the second reset transistor Ti2 to initialize the potential of the first node N1 and the fourth node N4.

[0135] Data writing stage t2: the gate control signal Scan_PAM(n) received by the control end of the first data transistor Tda1 is low, and the gate control signal Scan_PWM(n) received by the control end of the second data transistor Tda2 is low; the gate control signal Scan_PAM(n-1) received by the control end of the first reset transistor Ti1 is high, and the gate control signal Scan_PWM(n-1) received by the control end of the second reset transistor Ti2 is high; the light-emitting control signal EM_PAM(n) received by the control end of the first switch transistor Ts1 and the control end of the second switch transistor Ts2 is high, and the light-emitting control signal EM_PWM(n) received by the control end of the third switch transistor Ts3 and the control end of the fourth switch transistor Ts4 is high.

[0136] The first data transistor Tda1, the second data transistor Tda2, the first compensation transistor Tc1 and the second compensation transistor Tc2 are turned on, the first driving transistor Tdr1 and the second driving transistor Tdr2 are turned on, the pulse amplitude modulation voltage PADA compensates for the threshold voltage of the first driving transistor Tdr1, and the pulse width modulation voltage PWDA compensates for the threshold voltage of the second driving transistor Tdr2.

[0137] Optionally, the discharge control signal Disc transmitted by the discharge scanning line DisL has a low level state in at least one of the initialization stage and the data writing stage, so that the third reset transistor Ti3 is turned on, and the second reset signal transmitted by the second reset line VL2 is transmitted to the corresponding anode of the light-emitting device Di to initialize the anode potential of the light-emitting device Di.

[0138] Emission stage t3: The gate control signal Scan_PAM(n) received by the control terminal of the first data transistor Tda1 is at a high level, and the gate control signal Scan_PWM(n) received by the control terminal of the second data transistor Tda2 is at a high level; the gate control signal Scan_PAM(n - 1) received by the control terminal of the first reset transistor Ti1 is at a high level, the gate control signal Scan_PWM(n - 1) received by the control terminal of the second reset transistor Ti2 is at a high level, and the discharge control signal Disc is at a high level; the emission control signal EM_PAM(n) received by the control terminals of the first switching transistor Ts1 and the second switching transistor Ts2 is at a low level, and the emission control signal EM_PWM(n) received by the control terminals of the third switching transistor Ts3 and the fourth switching transistor Ts4 is at a low level.

[0139] The first switching transistor Ts1 to the fourth switching transistor Ts4 are turned on, and the driving current flows through the light-emitting device Di, causing the light-emitting device Di to start emitting light. The third switching transistor Ts3 and the fourth switching transistor Ts4 are turned on, and the gate-source voltage difference of the second driving transistor Tdr2 is greater than or equal to the threshold voltage of the second driving transistor Tdr2 (i.e., Vgs_Tdr2 ≥ Vth_Tdr2), and the second driving transistor Tdr2 remains in the cut-off state. The voltage of the sweep signal Sweep received by the pixel driving circuit 10 starts to decrease, and the potential of the fourth node N4 is coupled through the second capacitor C2. When the gate-source voltage difference of the second driving transistor Tdr2 is less than the threshold voltage of the second driving transistor Tdr2 (Vgs_Tdr2 < Vth_Tdr2), the second driving transistor Tdr2 is turned on, and the high voltage supplied by the second power supply terminal Vdd_PWM is transmitted to the first node N1 through the third switching transistor Ts3, the second driving transistor Tdr2, and the fourth switching transistor Ts4, making the gate-source voltage difference of the first driving transistor Tdr1 greater than or equal to the threshold voltage of the first driving transistor Tdr (i.e., Vgs_Tdr1 ≥ Vth_Tdr1), and the first driving transistor Tdr1 is turned off, and the light-emitting device Di stops emitting light.

[0140] Among them, different emission durations can be switched by setting different pulse width modulation voltages PWDA. That is, given different pulse width modulation voltages PWDA, the duration for which the second driving transistor Tdr2 is turned on is controlled by the corresponding sweep signal Sweep. Correspondingly, the working time of the pulse amplitude modulation module 101 is also different, so as to achieve the purpose of adjusting the emission duration.

[0141] Optionally, when the display panel displays at a high grayscale, the display brightness is primarily determined by the magnitude of the driving current, i.e., it is controlled solely by the pulse amplitude modulation module 101 (the magnitude of the current flowing through the light-emitting device Di can be varied by writing different pulse amplitude modulation voltages PADA). When the display panel displays at a high grayscale, to ensure a constant light-emitting time, the pulse width modulation module 102 can write a constant pulse width modulation high voltage to prevent the second driving transistor Tdr2 from turning on, thereby preventing it from acting on the pulse amplitude modulation module 101.

[0142] Optionally, when the display panel displays at a low grayscale, in order to ensure the stability of the luminous efficiency of the light-emitting device Di, it is necessary to adjust the luminous time while keeping the current unchanged to change the brightness, that is, the pulse amplitude modulation module 101 is used to ensure that the driving current remains unchanged, and the pulse width modulation module 102 is used to act on the pulse amplitude modulation module 101 to control the pulse amplitude modulation module 101 to be turned off in advance, thereby changing the luminous duration of the light-emitting device Di.

[0143] The present application also provides a display device comprising any of the above-mentioned display panels. Optionally, the display device comprises a mobile phone, a computer, a wristband, etc.

[0144] For those skilled in the art, according to the concept of this application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A display panel, wherein: include: A plurality of light-emitting lines configured to transmit a plurality of light-emitting control signals; A plurality of sweep frequency lines are configured to transmit a plurality of sweep frequency signals; A plurality of sub-pixel groups, each of which includes a plurality of sub-pixels, and each of which includes a light-emitting device and a pixel driving circuit; The pixel driving circuit is configured to provide a flow path for a driving current for driving the light-emitting device to emit light according to the corresponding light-emitting control signal, and the pixel driving circuit includes a pulse amplitude modulation module and a pulse width modulation module, and the pulse amplitude modulation module is configured to receive a corresponding pulse amplitude modulation voltage to control the pulse amplitude of the driving current; When the pixel driving circuit provides a flow path for the driving current according to the corresponding light emitting control signal, the pulse width modulation module is configured to cooperate with the pulse amplitude modulation module to control the pulse width of the driving current according to the corresponding frequency sweep signal and the pulse width modulation voltage; Among them, the pulse width modulation modules of the multiple sub-pixels included in the same sub-pixel group are used to receive the same scanning frequency signal, and the pulse width modulation modules and the pulse amplitude modulation modules of the multiple sub-pixels included in the same sub-pixel group are used to receive the same light-emitting control signal; the pixel driving circuits of at least two sub-pixel groups have different starting times for providing flow paths for the corresponding driving currents according to the corresponding light-emitting control signals.

2. The display panel according to claim 1, wherein: The plurality of light-emitting lines include a plurality of first light-emitting lines and a plurality of second light-emitting lines, the plurality of first light-emitting lines are configured to transmit a first light-emitting control signal, and the plurality of second light-emitting lines are configured to transmit a second light-emitting control signal; The plurality of frequency sweep lines include a plurality of first frequency sweep lines and a plurality of second frequency sweep lines, the plurality of first frequency sweep lines are configured to transmit first frequency sweep signals, and the plurality of second frequency sweep lines are configured to transmit second frequency sweep signals; The plurality of sub-pixel groups include a first sub-pixel group and a second sub-pixel group, the pixel driving circuits of the plurality of sub-pixels included in the first sub-pixel group are electrically connected to the plurality of first light-emitting lines, and the pulse width modulation modules of the plurality of sub-pixels included in the first sub-pixel group are electrically connected to the plurality of first scanning lines; the pixel driving circuits of the plurality of sub-pixels included in the second sub-pixel group are electrically connected to the plurality of second light-emitting lines, and the pulse width modulation modules of the plurality of sub-pixels included in the second sub-pixel group are electrically connected to the plurality of second scanning lines; The plurality of pixel driving circuits included in the first sub-pixel group are configured to provide a flow path for the corresponding driving current according to the first light-emitting control signal, and the pulse width modulation modules of the plurality of sub-pixels included in the first sub-pixel group are configured to control the pulse width of the corresponding driving current through the pulse amplitude modulation modules of the plurality of sub-pixels included in the first sub-pixel group according to the corresponding pulse width modulation voltage and the first sweep signal; The plurality of pixel driving circuits included in the second sub-pixel group are configured to provide a flow path for the corresponding driving current according to the second light-emitting control signal, and the pulse width modulation modules of the plurality of sub-pixels included in the second sub-pixel group are configured to control the pulse width of the corresponding driving current through the pulse amplitude modulation modules of the plurality of sub-pixels included in the second sub-pixel group according to the corresponding pulse width modulation voltage and the second scanning signal.

3. The display panel according to claim 2, wherein: The first sub-pixel group includes at least a plurality of sub-pixels located in the same row, and the second sub-pixel group includes at least a plurality of sub-pixels located in the same row; The plurality of sub-pixels included in the first sub-pixel group and the plurality of sub-pixels included in the second sub-pixel group are located in different rows.

4. The display panel according to claim 3, wherein: The plurality of sub-pixels included in the first sub-pixel group are located in different rows, and the plurality of sub-pixels included in the second sub-pixel group are located in different rows.

5. The display panel according to claim 4, wherein: The first sub-pixel group includes a plurality of sub-pixels located in odd-numbered rows, and the second sub-pixel group includes a plurality of sub-pixels located in even-numbered rows.

6. The display panel according to claim 4, wherein: Each of the light-emitting lines extends along a first direction, and a plurality of the light-emitting lines are arranged along a second direction; the display panel comprises a first display area and a second display area adjacent to each other along the second direction, the first display area comprises a plurality of continuous rows of sub-pixels, and the second display area comprises a plurality of continuous rows of sub-pixels; The first sub-pixel group includes a plurality of sub-pixels located in the first display area, and the second sub-pixel group includes a plurality of sub-pixels located in the second display area.

7. The display panel according to claim 2, wherein: The plurality of pixel driving circuits included in the first sub-pixel group provide a flow path for the corresponding driving current according to the first light emitting control signal at a first starting moment; the plurality of pixel driving circuits included in the second sub-pixel group provide a flow path for the corresponding driving current according to the second light emitting control signal at a second starting moment; Wherein, during the time period from the first starting moment to the second starting moment, the pixel driving circuits of the plurality of sub-pixels included in the second sub-pixel group sequentially receive the corresponding pulse amplitude modulation voltage and the corresponding pulse width modulation voltage.

8. The display panel according to claim 2, wherein: The plurality of pixel driving circuits included in the first sub-pixel group start generating the corresponding driving current according to the first light emitting control signal at a first starting time; the plurality of pixel driving circuits included in the second sub-pixel group start generating the corresponding driving current according to the second light emitting control signal at a second starting time; The plurality of pixel driving circuits included in the first sub-pixel group stop generating the corresponding driving current according to the second light emitting control signal at the second starting moment.

9. The display panel according to claim 5, wherein: The pulse amplitude modulation module comprises: a first driving transistor, wherein a control terminal of the first driving transistor is electrically connected to a first node, an input terminal of the first driving transistor is electrically connected to a second node, and an output terminal of the first driving transistor is electrically connected to a third node; a first data transistor, wherein a control terminal of the first data transistor is electrically connected to the first scan line, an input terminal of the first data transistor is configured to receive the pulse amplitude modulation voltage, and an output terminal of the first data transistor is electrically connected to the second node; a first compensation transistor, wherein a control terminal of the first compensation transistor is electrically connected to the first scan line, an input terminal of the first compensation transistor is electrically connected to the third node, and an output terminal of the first compensation transistor is electrically connected to the first node; a first switch transistor, wherein a control terminal of the first switch transistor is electrically connected to the corresponding light-emitting line, an input terminal of the first switch transistor is electrically connected to a first power supply terminal, and an output terminal of the first switch transistor is electrically connected to the second node; a second switch transistor, wherein a control terminal of the second switch transistor is electrically connected to a control terminal of the first switch transistor, an input terminal of the second switch transistor is electrically connected to the third node, and an output terminal of the second switch transistor is electrically connected to the corresponding light emitting device; a first reset transistor, wherein a control terminal of the first reset transistor is electrically connected to the second scan line, an input terminal of the first reset transistor is electrically connected to the first reset line, and an output terminal of the first reset transistor is electrically connected to the first node; and A first capacitor, wherein a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to a second power supply end.

10. The display panel according to claim 9, wherein: The pulse width modulation module comprises: a second driving transistor, wherein a control terminal of the second driving transistor is electrically connected to the fourth node, an input terminal of the second driving transistor is electrically connected to the fifth node, and an output terminal of the second driving transistor is electrically connected to the sixth node; a second data transistor, wherein a control terminal of the second data transistor is electrically connected to the third scan line, an input terminal of the second data transistor is configured to receive the pulse width modulation voltage, and an output terminal of the second data transistor is electrically connected to the fifth node; a second compensation transistor, wherein a control terminal of the second compensation transistor is electrically connected to the third scan line, an input terminal of the second compensation transistor is electrically connected to the sixth node, and an output terminal of the second compensation transistor is electrically connected to the fourth node; a third switch transistor, wherein a control terminal of the third switch transistor is electrically connected to the control terminal of the first switch transistor, an input terminal of the third switch transistor is electrically connected to the second power supply terminal, and an output terminal of the third switch transistor is electrically connected to the fifth node; a fourth switch transistor, wherein a control terminal of the fourth switch transistor is electrically connected to the control terminal of the third switch transistor, an input terminal of the fourth switch transistor is electrically connected to the sixth node, and an output terminal of the fourth switch transistor is electrically connected to the first node; a second reset transistor, wherein a control terminal of the second reset transistor is electrically connected to the fourth scan line, an input terminal of the second reset transistor is electrically connected to the first reset line, and an output terminal of the second reset transistor is electrically connected to the fourth node; and A second capacitor, wherein a first end of the second capacitor is electrically connected to the corresponding frequency scanning line, and a second end of the second capacitor is electrically connected to a fourth node.

11. The display panel according to claim 10, wherein: The display panel comprises: A first gate driving unit, comprising a plurality of cascaded first gate driving circuits, wherein the plurality of cascaded first gate driving circuits are electrically connected to the plurality of sub-pixels included in the first sub-pixel group; A second gate driving unit, comprising a plurality of cascaded second gate driving circuits, wherein the plurality of cascaded second gate driving circuits are electrically connected to the plurality of sub-pixels included in the second sub-pixel group; The plurality of sub-pixels in the m-th row included in the first sub-pixel group are electrically connected to the first gate driving circuit of the m-th level through the corresponding first scanning line, and the plurality of sub-pixels in the m-th row included in the first sub-pixel group are electrically connected to the first gate driving circuit of the m-1-th level through the corresponding second scanning line; The second sub-pixel group includes a plurality of sub-pixels located in the nth row, which are electrically connected to the second gate driving circuit of the nth level through the corresponding first scanning line, and the second sub-pixel group includes a plurality of sub-pixels located in the nth row, which are electrically connected to the second gate driving circuit of the n-1th level through the corresponding second scanning line; m>0, n>0.

12. The display panel according to claim 11, wherein: The multiple sub-pixels located in the m-th row included in the first sub-pixel group are electrically connected to the first gate driving circuit of the m-th level through the corresponding third scanning line, and the multiple sub-pixels located in the m-th row included in the first sub-pixel group are electrically connected to the first gate driving circuit of the m-1-th level through the corresponding fourth scanning line; the multiple sub-pixels located in the n-th row included in the second sub-pixel group are electrically connected to the second gate driving circuit of the n-th level through the corresponding third scanning line, and the multiple sub-pixels located in the n-th row included in the second sub-pixel group are electrically connected to the second gate driving circuit of the n-1-th level through the corresponding fourth scanning line.

13. The display panel according to claim 11, wherein: The first gate driving unit is configured to receive a first start signal to generate a plurality of first scanning signals, and the second gate driving unit is configured to receive a second start signal to generate a plurality of second scanning signals; The effective pulse of the second start signal lags behind the effective pulses of the first scan signals.

14. The display panel according to claim 10, wherein: The pulse amplitude modulation module comprises: A third reset transistor, wherein the control end of the third reset transistor is electrically connected to the discharge scan line, the input end of the third reset transistor is electrically connected to the second reset line, and the output end of the third reset transistor is electrically connected to the corresponding light emitting device.

15. A display device, wherein: A display panel is included, wherein the display panel includes: A plurality of light-emitting lines configured to transmit a plurality of light-emitting control signals; A plurality of sweep frequency lines are configured to transmit a plurality of sweep frequency signals; A plurality of sub-pixel groups, each of the sub-pixel groups includes a plurality of sub-pixels, each of the sub-pixels includes a light-emitting device and a pixel driving circuit; the pixel driving circuit is configured to provide a flow path for a driving current that drives the light-emitting device to emit light according to the corresponding light-emitting control signal, the pixel driving circuit includes a pulse amplitude modulation module and a pulse width modulation module, the pulse amplitude modulation module is configured to receive a corresponding pulse amplitude modulation voltage to control the pulse amplitude of the driving current; when the pixel driving circuit provides a flow path for the driving current according to the corresponding light-emitting control signal, the pulse width modulation module is configured to cooperate with the pulse amplitude modulation module to control the pulse width of the driving current according to the corresponding sweep signal and the pulse width modulation voltage; Among them, the pulse width modulation modules of the multiple sub-pixels included in the same sub-pixel group are used to receive the same scanning frequency signal, and the pulse width modulation modules and the pulse amplitude modulation modules of the multiple sub-pixels included in the same sub-pixel group are used to receive the same light-emitting control signal; the pixel driving circuits of at least two sub-pixel groups have different starting times for providing flow paths for the corresponding driving currents according to the corresponding light-emitting control signals.

16. The display device according to claim 15, wherein: The plurality of light-emitting lines include a plurality of first light-emitting lines and a plurality of second light-emitting lines, the plurality of first light-emitting lines are configured to transmit a first light-emitting control signal, and the plurality of second light-emitting lines are configured to transmit a second light-emitting control signal; The plurality of frequency sweep lines include a plurality of first frequency sweep lines and a plurality of second frequency sweep lines, the plurality of first frequency sweep lines are configured to transmit first frequency sweep signals, and the plurality of second frequency sweep lines are configured to transmit second frequency sweep signals; The plurality of sub-pixel groups include a first sub-pixel group and a second sub-pixel group, the pixel driving circuits of the plurality of sub-pixels included in the first sub-pixel group are electrically connected to the plurality of first light-emitting lines, and the pulse width modulation modules of the plurality of sub-pixels included in the first sub-pixel group are electrically connected to the plurality of first scanning lines; the pixel driving circuits of the plurality of sub-pixels included in the second sub-pixel group are electrically connected to the plurality of second light-emitting lines, and the pulse width modulation modules of the plurality of sub-pixels included in the second sub-pixel group are electrically connected to the plurality of second scanning lines; The plurality of pixel driving circuits included in the first sub-pixel group are configured to provide a flow path for the corresponding driving current according to the first light-emitting control signal, and the pulse width modulation modules of the plurality of sub-pixels included in the first sub-pixel group are configured to control the pulse width of the corresponding driving current through the pulse amplitude modulation modules of the plurality of sub-pixels included in the first sub-pixel group according to the corresponding pulse width modulation voltage and the first sweep signal; The plurality of pixel driving circuits included in the second sub-pixel group are configured to provide a flow path for the corresponding driving current according to the second light-emitting control signal, and the pulse width modulation modules of the plurality of sub-pixels included in the second sub-pixel group are configured to control the pulse width of the corresponding driving current through the pulse amplitude modulation modules of the plurality of sub-pixels included in the second sub-pixel group according to the corresponding pulse width modulation voltage and the second scanning signal.

17. The display device according to claim 16, wherein: The first sub-pixel group includes a plurality of sub-pixels located in odd-numbered rows, and the second sub-pixel group includes a plurality of sub-pixels located in even-numbered rows.

18. The display device according to claim 16, wherein: The first sub-pixel group includes at least a plurality of sub-pixels located in the same row, and the second sub-pixel group includes at least a plurality of sub-pixels located in the same row; The plurality of sub-pixels included in the first sub-pixel group and the plurality of sub-pixels included in the second sub-pixel group are located in different rows.

19. The display device according to claim 16, wherein: The plurality of pixel driving circuits included in the first sub-pixel group provide a flow path for the corresponding driving current according to the first light emitting control signal at a first starting moment; the plurality of pixel driving circuits included in the second sub-pixel group provide a flow path for the corresponding driving current according to the second light emitting control signal at a second starting moment; Wherein, during the time period from the first starting moment to the second starting moment, the pixel driving circuits of the plurality of sub-pixels included in the second sub-pixel group sequentially receive the corresponding pulse amplitude modulation voltage and the corresponding pulse width modulation voltage.

20. The display device according to claim 16, wherein: The plurality of pixel driving circuits included in the first sub-pixel group start generating the corresponding driving current according to the first light emitting control signal at a first starting time; the plurality of pixel driving circuits included in the second sub-pixel group start generating the corresponding driving current according to the second light emitting control signal at a second starting time; The plurality of pixel driving circuits included in the first sub-pixel group stop generating the corresponding driving current according to the second light emitting control signal at the second starting moment.

Images