Array substrate and display panel

Abstract

An array substrate, comprising: a substrate (400), a plurality of scanning lines (100), a plurality of data lines (200), and a plurality of pixel units (300). Each pixel unit (300) comprises a thin film transistor (310), a transfer electrode (330), and a pixel electrode (340); each transfer electrode (330) comprises a first sub-transfer electrode (331) and a second sub-transfer electrode (332); the first sub-transfer electrode (331) is electrically connected to the thin film transistor (310) by means of a first via hole (320); and the second sub-transfer electrode (332) is electrically connected to the first sub-transfer electrode (331). The length (L1) of first sub-transfer electrode (331) in a row direction is greater than the length (L2) of second sub-transfer electrode (332) in the row direction, so as to prevent an etching solution used for etching the transfer electrodes (330) from entering the first via holes (320) to etch thin film transistors (310), thereby avoiding the problem of dark spot defect on a display panel. Two adjacent transfer electrodes (330) located in the row direction are arranged on two sides of a corresponding scanning line (100), and the distance between the two adjacent transfer electrodes (330) is increased, thereby reducing the probability of short circuit or open circuit. Also provided is a display panel comprising the array substrate.

Description

Array substrate and display panel

[0001] This application claims priority to Chinese patent application No. 202311437452.1 filed on October 30, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of display panels, and in particular to an array substrate and a display panel. Background Art

[0003] The pixel density of LCD displays for VR (Virtual Reality) products has exceeded 1500PPI (Pixels Per Inc) and will develop towards 1700PPI and 2000PPI.

[0004] As the PPI of an LCD display increases, the size of the pixel units within the LCD display decreases. Due to process limitations, the size of two adjacent through-holes along the row direction on the array substrate cannot be reduced as the size of the pixel units decreases. As a result, the distance between the first via hole and the data line on the array substrate, as well as the distance between the first via hole and the transfer electrode, cannot meet the safety distance. During the manufacturing process of the array substrate, if a manufacturing error occurs, the transfer electrode will not be able to completely cover the first via hole. When etching the transfer electrode, the etching solution used to etch the transfer electrode will enter the first via hole and etch the drain of the thin-film transistor, causing the transfer electrode to be unable to charge, resulting in dark spots on the display panel. SUMMARY OF THE INVENTION

[0005] The purpose of the present application is to provide an array substrate and a display panel to solve the problem of dark spots on the display panel.

[0006] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0007] substrate;

[0008] A plurality of scanning lines, wherein the plurality of scanning lines are arranged on the substrate at intervals along a column direction;

[0009] a plurality of data lines, wherein the plurality of data lines are arranged on the substrate at intervals along a row direction;

[0010] A plurality of pixel units, wherein the pixel unit is arranged between two adjacent data lines, the pixel unit includes a thin film transistor, a switching electrode and a pixel electrode, the thin film transistor is electrically connected to the scan line and the data line, the pixel electrode is electrically connected to the switching electrode, and two adjacent switching electrodes located in the row direction are arranged on both sides of the scan line, the switching electrode includes a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating a film layer located between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, the second sub-switching electrode is electrically connected to the first sub-switching electrode, and the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction.

[0011] In a second aspect, the present application further provides a display panel, which includes the array substrate. Beneficial effects

[0012] The present application provides an array substrate, comprising: a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units; the plurality of scan lines are arranged on the substrate at intervals along the column direction; the plurality of data lines are arranged on the substrate at intervals along the row direction; the pixel unit is arranged between two adjacent data lines, the pixel unit comprises a thin film transistor, a switching electrode and a pixel electrode, the thin film transistor is electrically connected to the scan line and the data line, the pixel electrode is electrically connected to the switching electrode, two adjacent switching electrodes located in the row direction are arranged on both sides of the scan line, the switching electrode comprises a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating a film layer between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, and the second The sub-switching electrode is electrically connected to the first sub-switching electrode, and the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction; by setting the switching electrode to include a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating the film layer between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, the second sub-switching electrode is electrically connected to the first sub-switching electrode, the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction, when etching the switching electrode, it can prevent the etching liquid for etching the switching electrode from entering the first via hole to etch the thin film transistor, causing the switching electrode to be unable to charge, resulting in the problem of dark spots on the display panel, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a top view of an array substrate in the prior art;

[0014] FIG2 is a top view of an array substrate in the prior art when a transfer electrode does not completely cover a first via hole;

[0015] FIG3 is a scanning electron microscope image of the array substrate shown in FIG2 when the transfer electrode does not completely cover the first via hole;

[0016] FIG4 is a top view of a first structure of an array substrate in the present application;

[0017] FIG5 is a top view of a second structure of an array substrate in the present application;

[0018] FIG6 is a cross-sectional view of the array substrate shown in FIG5 ;

[0019] FIG7 is a top view of a third structure of an array substrate in the present application;

[0020] FIG8 is a top view of a fourth structure of an array substrate in the present application;

[0021] FIG9 is a top view of a fifth structure of an array substrate in the present application;

[0022] FIG10 is a top view of a sixth structure of an array substrate in the present application.

[0023] Description of reference numerals:

[0024] 100-scanning line; 200-data line; 300-pixel unit, 310-thin film transistor, 311-substrate, 312-first gate insulating layer, 313-gate metal layer, 314-second gate insulating layer, 315-semiconductor layer, 316-third gate insulating layer, 317-first interlayer insulating layer, 318-second interlayer insulating layer, 319-source metal, 320-first via, 330-transfer electrode, 331-first sub-transfer electrode, 3311-first protruding portion, 3312-second protruding portion, 3313-third protruding portion, 332-second sub-transfer electrode, 340-pixel electrode, 400-substrate; 500-reference axis. Modes for Carrying Out the Invention

[0025] The meanings of the terms used in this specification and claims correspond to those commonly understood by persons of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are intended solely to facilitate the description and understanding of this application and are not intended to limit this application to the narrow interpretations of the specific terms used in the specification and claims.

[0026] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0027] When the PPI of the LCD display is higher, the size of the pixel unit 300 in the LCD display will be smaller. Referring to Figures 1 to 3, the size of two adjacent through holes along the row direction on the array substrate is limited by the process and cannot be reduced as the size of the pixel unit 300 is reduced, resulting in the distance between the first via hole 320 and the data line 200 on the array substrate and the distance between the first via hole 320 and the transfer electrode 330 also failing to meet the safety distance. During the manufacturing process of the array substrate, once an error occurs in the process, that is, the transfer electrode 330 is offset toward one side of the reference axis 500, the transfer electrode 330 cannot completely cover the first via hole 320. When etching the transfer electrode 330, the etching solution for etching the transfer electrode 330 will enter the first via hole 320 and etch the drain of the thin film transistor 310, causing the transfer electrode 330 to be unable to charge, resulting in dark spots on the display panel.

[0028] Therefore, an embodiment of the present application provides a display panel. Referring to Figure 4, the display panel includes an array substrate, an opposing substrate and a liquid crystal layer, and the liquid crystal layer is arranged between the array substrate and the opposing substrate; the array substrate includes a substrate, multiple scan lines 100, multiple data lines 200 and multiple pixel units 300.

[0029] 4 , in this embodiment, a plurality of scan lines 100 are arranged on a substrate at intervals along a column direction; a plurality of data lines 200 are arranged on the substrate at intervals along a row direction; a pixel unit 300 is arranged between two adjacent data lines 200, and the pixel unit 300 includes a thin film transistor 310, a switching electrode 330, and a pixel electrode 340. The thin film transistor 310 is electrically connected to the scan line 100 and the data line 200, and the pixel electrode 340 is electrically connected to the switching electrode 330. The switching electrode 330 is connected to the thin film transistor 310 via a first via hole 320 that penetrates a film layer between the thin film transistor 310 and the switching electrode 330, and the switching electrode 330 covers the first via hole 320. In the positive direction of the row direction, the switching electrode 330 extends a first protruding portion 3311 relative to the first via hole 320, and in the negative direction of the row direction, the switching electrode 330 extends a second protruding portion 3312 relative to the first via hole 320.

[0030] In the positive direction of the row direction, the transfer electrode 330 is provided with a first protruding portion 3311 extending relative to the first via hole 320, and in the negative direction of the row direction, the transfer electrode 330 is provided with a second protruding portion 3312 extending relative to the first via hole 320. This increases the area of ​​the transfer electrode 330, so that the transfer electrode 330 can better cover the first via hole 320. When etching the transfer electrode 330, it can prevent the etching solution for etching the transfer electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, causing the transfer electrode 330 to be unable to charge, resulting in the problem of dark spots on the display panel, thereby improving the display effect of the display panel.

[0031] 5 , in this embodiment, a plurality of scan lines 100 are arranged on a substrate at intervals along a column direction; a plurality of data lines 200 are arranged on a substrate at intervals along a row direction; a pixel unit 300 is arranged between two adjacent data lines 200, and the pixel unit 300 includes a thin film transistor 310, a switching electrode 330, and a pixel electrode 340. The thin film transistor 310 is electrically connected to the scan line 100 and the data line 200, and the pixel electrode 340 is electrically connected to the switching electrode 330. The switching electrode 330 includes A first sub-switch electrode 331 and a second sub-switch electrode 332 are provided. The first sub-switch electrode 331 is connected to the thin film transistor 310 via a first via hole 320 that penetrates the film layer between the thin film transistor 310 and the switching electrode 330 . The first sub-switch electrode 331 covers the first via hole 320 . The second sub-switch electrode 332 is electrically connected to the first sub-switch electrode 331 . The length L1 of the first sub-switch electrode 331 in the row direction is greater than the length L2 of the second sub-switch electrode 332 in the row direction.

[0032] By providing the transfer electrode 330 to include a first sub-transfer electrode 331 and a second sub-transfer electrode 332, the first sub-transfer electrode 331 is connected to the thin film transistor 310 through a first via hole 320 that penetrates the film layer between the thin film transistor 310 and the transfer electrode 330, and the first sub-transfer electrode 331 covers the first via hole 320. The second sub-transfer electrode 332 is electrically connected to the first sub-transfer electrode 331. The length L1 of the first sub-transfer electrode 331 in the row direction is greater than the length L2 of the second sub-transfer electrode 332 in the row direction. When etching the transfer electrode 330, it is possible to prevent the etching solution for etching the transfer electrode 330 from entering the first via hole 320 to etch the thin film transistor 310, causing the transfer electrode 330 to be unable to charge, resulting in the problem of dark spots on the display panel, thereby improving the display effect of the display panel.

[0033] 6 , in this embodiment, the array substrate includes a substrate 400, a buffer layer 311 disposed on the substrate 400, a first gate insulating layer 312, a gate metal layer 313, a second gate insulating layer 314, a semiconductor layer 315, a third gate insulating layer 316, a first interlayer insulating layer 317, a second interlayer insulating layer 318, a source metal layer 319, a transfer electrode 330 (drain metal layer), and a pixel electrode 340. The source metal layer 319 is connected to the source electrode of the semiconductor layer 315 through a second via hole, and the transfer electrodes 330-320 are connected to the drain electrode in the semiconductor layer 315 through a first via hole 320. Specifically, the first via 320 penetrates the second interlayer insulating layer 318, the first interlayer insulating layer 317 and the third gate insulating layer 316, so that the transfer electrode 330 is electrically connected to the drain of the semiconductor layer 315. The transfer electrode 330 is electrically connected to the drain of the semiconductor layer 315 through the first through hole 320, and the pixel electrode 340 is electrically connected to the transfer electrode 330. The second via penetrates the first interlayer insulating layer 317 and the third gate insulating layer 316, so that the source metal 319 is electrically connected to the source on the semiconductor layer 315.

[0034] In this embodiment, the length L1 of the first sub-transfer electrode 331 in the row direction is greater than the length L2 of the second sub-transfer electrode 332 in the row direction. Although this reduces the distance between two adjacent transfer electrodes 330, it can easily cause the transfer electrodes 330 of two adjacent pixel units 300 on the array substrate to short-circuit, resulting in a short circuit in the pixel units 300. Therefore, two adjacent transfer electrodes 330 in the row direction are arranged on both sides of the scan line 100 to increase the distance between the two adjacent transfer electrodes 330 and reduce the probability of line short circuit or open circuit.

[0035] It should be noted that, since the first sub-switch electrode 331 covers the first via hole 320 , two adjacent first via holes 320 in the row direction are staggered, which increases the distance between the two first via holes 320 and reduces the difficulty of manufacturing the pixel unit 300 .

[0036] 5 , 7 , 8 , and 10 , in this embodiment, the orthographic projection of the first sub-switch electrode 331 on the substrate 400 is located on one side of the orthographic projection of the scan line 100 on the substrate 400 , and the orthographic projection of the second sub-switch electrode 332 on the substrate 400 overlaps with the orthographic projection of the scan line 100 on the substrate 400 .

[0037] Referring to Figure 9 , in this embodiment, when the switching electrode 330 is directly opposite the scan line 100, charge forms a short circuit path between the switching electrode 330 and the scan line 100, causing charge to flow from the switching electrode 330 to the scan line 100, disrupting the normal operation of other pixel units 300. Therefore, the orthographic projections of the first sub-switching electrode 331 and the second sub-switching electrode 332 on the substrate 400 are both located on one side of the orthographic projection of the scan line 100 on the substrate 400. This prevents interference with the operation of the pixel units 300, thereby improving the operational stability of the array substrate.

[0038] Referring to FIG. 7 , in this embodiment, the first sub-switch electrode 331 has a first protruding portion 3311 relative to the first via hole 320 along the positive row direction. The provision of the first protruding portion 3311 increases the square area of ​​the first sub-switch electrode 331 in the row direction, thereby preventing the first sub-switch electrode 331 of the switching electrode 330 from being too small in the positive row direction, thereby preventing the first sub-switch electrode 331 of the switching electrode 330 from completely covering the first via hole 320. This prevents the etching solution used to etch the switching electrode 330 from entering the first via hole 320 and etching the thin-film transistor 310, thereby improving the display quality of the display panel.

[0039] Referring to FIG. 8 , in this embodiment, the first sub-transfer electrode 331 has a second protruding portion 3312 opposite the first via hole 320 in the direction opposite the row direction. The provision of the second protruding portion 3312 increases the area of ​​the first sub-transfer electrode 331 in the direction opposite the row direction. This prevents the area of ​​the first sub-transfer electrode 331 of the transfer electrode 330 in the direction opposite the row direction from being too small, resulting in the first sub-transfer electrode 331 of the transfer electrode 330 not being able to completely cover the first via hole 320. This prevents the etching solution used to etch the transfer electrode 330 from entering the first via hole 320 and etching the thin-film transistor 310, thereby improving the display quality of the display panel.

[0040] Referring to FIG. 5 , in this embodiment, the first sub-switch electrode 331 has a third protruding portion 3313, parallel to the column direction and facing away from the second sub-switch electrode 332, relative to the first via hole 320. The provision of the third protruding portion 3313 increases the area of ​​the first sub-switch electrode 331 in a direction away from the second sub-switch electrode 332. This prevents the area of ​​the first sub-switch electrode 331 of the switching electrode 330 from being too small in the direction away from the second sub-switch electrode 332, resulting in the first sub-switch electrode 331 of the switching electrode 330 not being able to fully cover the first via hole 320. This prevents the etching solution used to etch the switching electrode 330 from entering the first via hole 320 and etching the thin-film transistor 310, thereby improving the display quality of the display panel.

[0041] Referring to FIG. 10 , in this embodiment, the first sub-transfer electrode 331 has a first protruding portion 3311 relative to the first via hole 320 along the positive row direction, and has a second protruding portion 3312 relative to the first via hole 320 along the negative row direction. The provision of the first protruding portion 3311 and the second protruding portion 3312 simultaneously increases the area of ​​the first sub-transfer electrode 331 in both the row direction and the negative row direction. This prevents the area of ​​the first sub-transfer electrode 331 in the positive or negative row direction of the first sub-transfer electrode 330 from being too small, resulting in the first sub-transfer electrode 331 of the transition electrode 330 not being able to fully cover the first via hole 320. This prevents the etching solution used to etch the transition electrode 330 from entering the first via hole 320 and etching the thin-film transistor 310, thereby improving the display quality of the display panel.

[0042] In this embodiment, the first protruding portion 3311 and the second protruding portion 3312 have the same shape and the same size.

[0043] 5 , in this embodiment, the transition electrodes 330 are T-shaped or inverted T-shaped. Specifically, the array substrate has a plurality of pixel units 300 arranged along the column and row directions. For the transition electrodes 330 in the column direction, the plurality of transition electrodes 330 in the same column direction have the same shape, while two adjacent transition electrodes 330 in the same row direction have different shapes. That is, the plurality of transition electrodes 330 in the same column direction are all T-shaped or inverted T-shaped, while one of the two adjacent transition electrodes 330 in the same row direction is T-shaped and the other is inverted T-shaped.

[0044] Referring to Figure 10 , in this embodiment, the edges of the first protruding portion 3311 and the second protruding portion 3312 are both arc-shaped. By setting the edges of the first protruding portion 3311 and the second protruding portion 3312 to be arc-shaped, the distance between the first sub-transfer electrode 331 and the data line 200 can be increased, preventing a short circuit between the transfer electrode 330 and the data line 200, and reducing parasitic capacitance, thereby improving the stability of the array substrate.

[0045] 10 , in this embodiment, the first sub-switch electrode 331 has a first protruding portion 3311 extending in the positive direction of the row direction, the first sub-switch electrode 331 has a second protruding portion 3312 extending in the negative direction of the row direction, and the first sub-switch electrode 331 has a third protruding portion 3313 extending in the direction away from the second sub-switch electrode 332 . By providing the first protruding portion 3311, the second protruding portion 3312 and the third protruding portion 3313, the area of ​​the first sub-transfer electrode 331 in the row direction and the opposite direction of the row direction is increased at the same time, thereby preventing the first sub-transfer electrode 331 of the transfer electrode 330 from having an area that is too small in the positive direction of the row direction and the opposite direction of the row direction, and an area that is too small in the direction away from the second sub-transfer electrode 332, resulting in the first sub-transfer electrode 331 of the transfer electrode 330 not being able to completely cover the first via hole 320, thereby preventing the etching solution for etching the transfer electrode 330 from entering the first via hole 320 and etching the thin film transistor 310, thereby improving the display effect of the display panel.

[0046] In this embodiment, the first protruding portion 3311 , the second protruding portion 3312 and the third protruding portion 3313 have the same shape and the same size.

[0047] Referring to Figure 10 , in this embodiment, the edges of the first protruding portion 3311, the second protruding portion 3312, and the third protruding portion 3313 are all arc-shaped. By configuring the edges of the first protruding portion 3311 and the second protruding portion 3312 to be arc-shaped, the distance between the first sub-transfer electrode 331 and the data line 200 can be increased, preventing short circuits between the transfer electrode 330 and the data line 200. Parasitic capacitance can also be reduced, thereby improving the stability of the array substrate.

[0048] Referring to Figure 5 , in this embodiment, two adjacent switching electrodes 330 located in the row direction are centrally symmetric about the intersection of the scan line 100 and the data line 200. Specifically, a plurality of data lines 200 are arranged at equal intervals on the array substrate, and two adjacent switching electrodes 330 located in the row direction are centrally symmetric about the intersection of the scan line 100 and the data line 200. Therefore, the first sub-switching electrodes 331 on the two adjacent switching electrodes 330 are at the same distance from the same data line 200, and the second sub-switching electrodes 332 on the two adjacent switching electrodes 330 are at the same distance from the same data line 200.

[0049] In this embodiment, the data lines 200 located on both sides of the switching electrode 330 are spaced equal to the switching electrode 330 , that is, the switching electrode 330 is located in the middle of the region formed by two adjacent data lines 200 .

[0050] In this embodiment, the data lines 200 located on both sides of the switching electrode 330 are spaced apart from the switching electrode 330 , that is, the switching electrode 330 is offset toward the data line 200 on one side.

[0051] 5 , in this embodiment, the second sub-transfer electrodes 332 of two adjacent transfer electrodes 330 in the column direction are both located on the same side of the first sub-transfer electrode 331 of the transfer electrode 330. Specifically, the second sub-transfer electrodes 332 of multiple transfer electrodes 330 in the same column direction all extend in the positive direction of the column direction or in the negative direction of the column direction.

[0052] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, wherein: include: substrate; A plurality of scanning lines, wherein the plurality of scanning lines are arranged on the substrate at intervals along a column direction; A plurality of data lines, wherein the plurality of data lines are arranged on the substrate at intervals along a row direction; A plurality of pixel units, wherein the pixel unit is arranged between two adjacent data lines, the pixel unit includes a thin film transistor, a switching electrode and a pixel electrode, the thin film transistor is electrically connected to the scan line and the data line, the pixel electrode is electrically connected to the switching electrode, two adjacent switching electrodes located in the row direction are arranged on both sides of the scan line, the switching electrode includes a first sub-switching electrode and a second sub-switching electrode, the first sub-switching electrode is electrically connected to the thin film transistor through a first via hole penetrating a film layer between the thin film transistor and the switching electrode, and the first sub-switching electrode covers the first via hole, the second sub-switching electrode is electrically connected to the first sub-switching electrode, and the length of the first sub-switching electrode in the row direction is greater than the length of the second sub-switching electrode in the row direction.

2. The array substrate according to claim 1, wherein: The orthographic projection of the first sub-switching electrode on the substrate is located on one side of the orthographic projection of the scanning line on the substrate, and the orthographic projection of the second sub-switching electrode on the substrate overlaps with the orthographic projection of the scanning line on the substrate.

3. The array substrate according to claim 1, wherein: The orthographic projections of the first sub-switching electrode and the second sub-switching electrode on the substrate are both located on one side of the orthographic projection of the scanning line on the substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: Along the positive direction of the row direction, the first sub-switching electrode has a first protruding portion relative to the first via hole.

5. The array substrate according to any one of claims 1 to 3, wherein: Along the opposite direction of the row direction, the first sub-switching electrode has a second protruding portion relative to the first via hole.

6. The array substrate according to any one of claims 1 to 3, wherein: Along the positive direction of the row direction, the first sub-switching electrode has a first protruding portion relative to the first via hole, and along the negative direction of the row direction, the first sub-switching electrode has a second protruding portion relative to the first via hole.

7. The array substrate according to claim 6, wherein: The first protruding portion and the second protruding portion have the same shape and the same size.

8. The array substrate according to claim 6, wherein: The edges of the first protruding portion and the second protruding portion are both arc-shaped.

9. The array substrate according to claim 6, wherein: The first sub-switching electrode has a third protruding portion relative to the first via hole, parallel to the column direction and facing away from the second sub-switching electrode.

10. The array substrate according to claim 9, wherein: The first protruding portion, the second protruding portion and the third protruding portion have the same shape and are equal in size.

11. The array substrate according to claim 9, wherein: The edges of the first protruding portion and the second protruding portion are both arc-shaped.

12. The array substrate according to claim 1, wherein: Two adjacent switching electrodes located in the row direction are centrally symmetrical with respect to the intersection of the scanning line and the data line.

13. The array substrate according to claim 12, wherein: The shapes of the switching electrodes in the same column direction are the same, and the shapes of two adjacent switching electrodes in the same row direction are different.

14. The array substrate according to claim 13, wherein: The switching electrode is in a T-shape or an inverted T-shape.

15. The array substrate according to claim 1, wherein: The second sub-switching electrodes of two adjacent switching electrodes in the column direction are both located on the same side of the first sub-switching electrodes of the switching electrodes.

16. The array substrate according to claim 15, wherein: The second sub-switching electrodes of the plurality of switching electrodes in the same column direction all extend toward the positive direction of the column direction or the reverse direction of the column direction.

17. The array substrate according to claim 1, wherein: The data lines located at both sides of the switching electrode are spaced equal to the switching electrode.

18. The array substrate according to claim 1, wherein: The data lines located at two sides of the switching electrode are spaced apart from the switching electrode.

19. A display panel, wherein: The display panel comprises the array substrate according to any one of claims 1 to 18.

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