Display panel and display device having same

Abstract

Disclosed in the embodiments of the present disclosure are a display panel and a display device having same. The display panel comprises an array substrate, the array substrate comprising a base substrate, and a plurality of thin film transistors, a plurality of first signal lines extending in a first direction and spaced apart in a second direction, a plurality of second signal lines extending in a second direction and spaced apart in the first direction, and a plurality of metal blocks spaced apart in the first direction, which are arranged on the base substrate, wherein the orthographic projections of the first signal lines on the base substrate intersect with the orthographic projections of the second signal lines on the base substrate; the orthographic projections of the metal blocks on the base substrate overlap the orthographic projections of the first signal lines on the base substrate; and the orthographic projections of the metal blocks on the base substrate do not overlap the orthographic projections of the second signal lines on the base substrate.

Description

Display panel and display device thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on November 1, 2023, with application number 202311443485.7 and invention name "Display panel and display device thereof", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device thereof. Background Art

[0004] With the rapid development of science and technology, various display devices have gradually developed, such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). During the manufacturing process of both LCD and OLED displays, a flat layer is often formed. If the flatness of the flat layer is not sufficient, unevenness may easily appear within the pixels, which can seriously affect the performance and display effect of the display device.

[0005] Summary of the Invention

[0006] The display panel provided by the embodiment of the present disclosure includes:

[0007] An array substrate includes: a base substrate and a plurality of thin film transistors arranged on the base substrate, a plurality of first signal lines extending along a first direction and spaced apart along a second direction, a plurality of second signal lines extending along the second direction and spaced apart along the first direction, and a plurality of metal blocks spaced apart along the first direction;

[0008] The orthographic projection of the first signal line on the substrate intersects with the orthographic projection of the second signal line on the substrate; the orthographic projection of the metal block on the substrate overlaps with the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal block on the substrate does not overlap with the orthographic projection of the second signal line on the substrate.

[0009] In some embodiments, the first signal line and the second signal line are arranged in different layers; the metal block and the second signal line are arranged in the same layer;

[0010] The first signal lines include: a plurality of first gate lines, a plurality of second gate lines, a plurality of first power supply voltage signal lines, a plurality of first reference voltage signal lines, a plurality of initialization voltage signal lines, and a plurality of light emitting control signal lines;

[0011] The second signal lines include: a plurality of data lines, a plurality of second power supply voltage signal lines and a plurality of second reference voltage signal lines;

[0012] The first power supply voltage signal line is connected to the second power supply voltage signal line through a first via hole; the orthographic projection of the first via hole on the base substrate is located at the intersection of the orthographic projection of the first power supply voltage signal line and the second power supply voltage signal line on the base substrate;

[0013] The first reference voltage signal line is connected to the second reference voltage signal line through a second via hole; the orthographic projection of the second via hole on the base substrate is located at the intersection of the orthographic projection of the first reference voltage signal line and the second reference voltage signal line on the base substrate.

[0014] In some embodiments, the metal block includes: a plurality of first electrode blocks, wherein the orthographic projections of the first electrode blocks on the base substrate overlap with the orthographic projections of the first power supply voltage signal line and the light emitting control signal line on the base substrate;

[0015] Or, the orthographic projection of the first electrode block on the base substrate overlaps with the orthographic projections of the first power supply voltage signal line, the light emitting control signal line, and the first gate line on the base substrate;

[0016] Alternatively, the orthographic projection of the first electrode block on the base substrate overlaps with the orthographic projections of the light emitting control signal line and the first gate line on the base substrate.

[0017] In some embodiments, the orthographic projection of the first electrode block on the base substrate and the orthographic projection of the second signal line on the base substrate are spaced apart from each other.

[0018] In some embodiments, the first electrode block and the second power supply voltage signal line are connected to form a whole;

[0019] The orthographic projection of the first electrode block on the base substrate is spaced apart from the orthographic projections of the data line and the second reference voltage signal line on the base substrate.

[0020] In some embodiments, the first electrode block and the second reference voltage signal line are connected to form a whole;

[0021] The orthographic projection of the first electrode block on the base substrate is spaced apart from the orthographic projections of the data line and the second power supply voltage signal line on the base substrate.

[0022] In some embodiments, the first electrode block includes a first opening region, and an orthographic projection of the first opening region on the base substrate overlaps with an orthographic projection of the first gate line on the base substrate.

[0023] In some embodiments, the array substrate further includes a plurality of first connection portions provided on the base substrate, the first connection portions being spaced apart along the first direction; the first connection portions being connected to the initialization voltage signal line through a third via hole; and the first connection portions being connected to the active area of ​​the thin film transistor through a fourth via hole.

[0024] The orthographic projection of the third via hole on the base substrate is located at the intersection of the first connecting portion and the orthographic projection of the initialization voltage signal line on the base substrate;

[0025] The orthographic projection of the fourth via hole on the base substrate is located at an overlapping position of the orthographic projection of the first connecting portion and the active region of the thin film transistor on the base substrate.

[0026] In some embodiments, the metal block further includes: a plurality of second electrode blocks, wherein the orthographic projections of the second electrode blocks on the base substrate overlap with the orthographic projections of the second gate line, the first reference voltage signal line, and the initialization voltage signal line on the base substrate;

[0027] Or, the orthographic projection of the second electrode block on the base substrate overlaps with the orthographic projections of the first reference voltage signal line and the initialization voltage signal line on the base substrate;

[0028] An orthographic projection of the second electrode block on the base substrate and an orthographic projection of the second signal line on the base substrate are spaced apart from each other.

[0029] In some embodiments, an orthographic projection of the second electrode block on the base substrate and an orthographic projection of the first connecting portion on the base substrate are spaced apart from each other.

[0030] In some embodiments, the second electrode block is connected to the first connecting portion to form a whole.

[0031] In some embodiments, the second electrode block includes a second opening region, and an orthographic projection of the second opening region on the base substrate overlaps with an orthographic projection of the second gate line on the base substrate.

[0032] In some embodiments, the metal block further includes: a plurality of third electrode blocks, wherein the orthographic projections of the third electrode blocks on the base substrate overlap with the orthographic projections of the first gate line on the base substrate;

[0033] The third electrode block is connected to the first gate line through a fifth via hole, and the orthographic projection of the fifth via hole on the base substrate overlaps with the orthographic projection of the third electrode block on the base substrate;

[0034] The orthographic projection of the third electrode block on the base substrate is spaced apart from the orthographic projections of the second signal line, the first electrode block, and the second electrode block on the base substrate.

[0035] In some embodiments, the metal block further includes: a plurality of fourth electrode blocks, wherein the orthographic projections of the fourth electrode blocks on the base substrate overlap with the orthographic projections of the second gate lines on the base substrate;

[0036] The fourth electrode block is connected to the second gate line through a sixth via hole, and the orthographic projection of the sixth via hole on the base substrate overlaps with the orthographic projection of the fourth electrode block on the base substrate;

[0037] The orthographic projection of the fourth electrode block on the base substrate is spaced apart from the orthographic projections of the second signal line, the first electrode block, and the second electrode block on the base substrate.

[0038] In some embodiments, the array substrate further comprises: a plurality of first electrodes disposed on the base substrate, wherein an orthographic projection of the first electrodes on the base substrate overlaps with an orthographic projection of the gate of the thin film transistor on the base substrate;

[0039] The orthographic projections of the first gate line and the second gate line on the base substrate are respectively located on different sides of the orthographic projection of the first electrode on the base substrate;

[0040] The orthographic projection of the light emitting control signal line on the base substrate is located between the orthographic projection of the first power supply voltage signal line and the first gate line on the base substrate;

[0041] The orthographic projection of the first reference voltage signal line on the base substrate is located between the orthographic projection of the initialization voltage signal line and the second gate line on the base substrate.

[0042] In some embodiments, the first electrode and the first electrode block and the second electrode block are spaced apart from each other.

[0043] In some embodiments, the first electrode extends along the second direction to the position of the first electrode block and is connected to the first electrode block to form a whole, and / or the first electrode extends along the second direction to the position of the second electrode block and is connected to the second electrode block to form a whole.

[0044] In some embodiments, the array substrate further includes: a plurality of second connection portions arranged on the base substrate, the second connection portions being arranged at intervals along the first direction; the second connection portions being connected to the active area of ​​the thin film transistor through a seventh via hole; the second connection portion being connected to the active area of ​​the thin film transistor through an eighth via hole; the orthographic projections of the seventh via hole and the eighth via hole on the base substrate being located on different sides of the orthographic projection of the first gate line on the base substrate.

[0045] In some embodiments, the device further comprises: a plurality of sub-pixels, at least one of the plurality of sub-pixels comprising a pixel circuit and a light-emitting device; the sub-pixel comprising the plurality of thin-film transistors and a storage capacitor; wherein the plurality of thin-film transistors comprises: a first transistor, a second transistor, a third transistor, and a driving transistor;

[0046] The gate of the first transistor is coupled to the first gate line, the first electrode of the first transistor is coupled to the data line, and the second electrode of the first transistor is coupled to the gate of the driving transistor;

[0047] The gate of the second transistor is coupled to the second gate line, the first electrode of the second transistor is coupled to the first reference voltage signal line, and the second electrode of the second transistor is coupled to the gate of the driving transistor;

[0048] The gate of the third transistor is coupled to the light emitting control signal line, the first electrode of the third transistor is coupled to the first power supply voltage signal line, and the second electrode of the third transistor is coupled to the first electrode of the driving transistor;

[0049] The gate of the driving transistor is coupled to the first electrode of the storage capacitor, and the second electrode of the driving transistor is coupled to the light emitting device;

[0050] The second electrode of the storage capacitor is coupled to the initialization voltage signal line.

[0051] In some embodiments, the array substrate further includes:

[0052] a light shielding layer, located on the base substrate;

[0053] a buffer layer, located on a side of the light shielding layer facing away from the base substrate;

[0054] an active layer, located on a side of the buffer layer facing away from the base substrate, the active layer including an active region of the thin film transistor;

[0055] a gate insulating layer, located on a side of the active layer facing away from the substrate;

[0056] a first conductive layer, located on a side of the gate insulating layer away from the base substrate, the first conductive layer including the first signal line and the gate of the thin film transistor;

[0057] an interlayer insulating layer, located on a side of the first conductive layer facing away from the base substrate;

[0058] a second conductive layer, located on a side of the interlayer insulating layer away from the base substrate, the second conductive layer comprising the second signal line, a first connecting portion, a second connecting portion, the metal block, and a first electrode;

[0059] a planarization layer, located on a side of the second conductive layer facing away from the base substrate;

[0060] an anode layer, located on a side of the planarization layer facing away from the substrate;

[0061] The pixel defining layer is provided on the same layer as the anode layer, and the orthographic projection of the pixel defining layer on the base substrate does not overlap with the orthographic projection of the anode layer on the base substrate.

[0062] In some embodiments, the anode layer is connected to the first electrode through an anode via;

[0063] The anode via hole is close to the second gate line, and the orthographic projection of the anode via hole on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate;

[0064] Alternatively, the anode via hole is close to the light-emitting control signal line, and the orthographic projection of the anode via hole on the base substrate overlaps with the orthographic projections of the first electrode block and the first power supply voltage signal line on the base substrate;

[0065] Alternatively, the anode via hole is close to the first gate line, and the orthographic projection of the anode via hole on the base substrate overlaps with the orthographic projections of the first electrode block and the light emitting control signal line on the base substrate.

[0066] In some embodiments, the array substrate further comprises: a pixel definition layer, disposed on the same layer as the anode layer;

[0067] The orthographic projection of the pixel definition layer on the base substrate does not overlap with the orthographic projections of the anode layer, the metal block, the first connecting portion, the second connecting portion, and the first electrode on the base substrate;

[0068] The orthographic projection of the pixel definition layer on the base substrate overlaps with the orthographic projections of the second signal line and the first power supply voltage signal line on the base substrate.

[0069] In some embodiments, the invention further includes: an opposite substrate, wherein the opposite substrate includes a black matrix area;

[0070] The orthographic projection of the black matrix region on the base substrate overlaps with the orthographic projection of the pixel definition layer on the base substrate.

[0071] In some embodiments, the orthographic projection of the black matrix area on the base substrate overlaps with the orthographic projections of the light emitting control signal line and the anode via on the base substrate.

[0072] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] FIG1 is a schematic structural diagram of some display panels provided by an embodiment of the present disclosure;

[0074] FIG2 is a schematic structural diagram of other display panels provided by an embodiment of the present disclosure;

[0075] FIG3 is a schematic structural diagram of pixel circuits in some sub-pixels provided by an embodiment of the present disclosure;

[0076] FIG4 is a schematic diagram of some cross-sectional structures in the schematic diagram of the layout structure shown in FIG2 ;

[0077] FIG5 is a schematic diagram of other cross-sectional structures in the schematic diagram of the layout structure shown in FIG2 ;

[0078] FIG6 is a schematic structural diagram of other display panels provided by an embodiment of the present disclosure;

[0079] FIG7 is a schematic diagram of some cross-sectional structures in the schematic diagram of the layout structure shown in FIG6;

[0080] FIG8 is a schematic diagram of other cross-sectional structures in the schematic diagram of the layout structure shown in FIG6;

[0081] FIG9 is a schematic diagram of other cross-sectional structures in the schematic diagram of the layout structure shown in FIG6 ;

[0082] FIG10 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0083] FIG11 is a schematic diagram of some cross-sectional structures in the schematic diagram of the layout structure shown in FIG10;

[0084] FIG12 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0085] FIG13 is a schematic diagram of some cross-sectional structures in the schematic diagram of the layout structure shown in FIG12;

[0086] FIG14 is a schematic diagram of other cross-sectional structures of the layout structure schematic diagram shown in FIG12;

[0087] FIG15 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0088] FIG16 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0089] FIG17 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0090] FIG18 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0091] FIG19 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0092] FIG20 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0093] FIG21 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0094] FIG22 is a schematic diagram of some cross-sectional structures in the schematic diagram of the layout structure shown in FIG21;

[0095] FIG23 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure;

[0096] FIG24 is a schematic diagram of some cross-sectional structures in the schematic diagram of the layout structure shown in FIG23;

[0097] FIG25 is another schematic cross-sectional view of the layout structure diagram shown in FIG23;

[0098] FIG26 is a schematic structural diagram of some further display panels provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0099] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0100] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0101] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0102] The present disclosure provides a display panel, as shown in FIG1 and FIG2 , including:

[0103] The array substrate 100 includes: a base substrate 10; a plurality of thin film transistors (e.g., T0, T1, T2, and T3 in FIG2 ) disposed on the base substrate 10; a plurality of first signal lines S1 extending along a first direction F1 and spaced apart along a second direction F2; a plurality of second signal lines S2 extending along the second direction F2 and spaced apart along the first direction F1; and a plurality of metal blocks (e.g., SD1 and SD2 in FIG2 ) spaced apart along the first direction F1.

[0104] Among them, the orthographic projection of the first signal line S1 on the base substrate 10 intersects with the orthographic projection of the second signal line S2 on the base substrate 10; the orthographic projection of the metal block (such as SD1 and SD2 in Figure 2) on the base substrate 10 overlaps with the orthographic projection of the first signal line S1 on the base substrate 10, and the orthographic projection of the metal block (such as SD1 and SD2 in Figure 2) on the base substrate 10 does not overlap with the orthographic projection of the second signal line S2 on the base substrate 10.

[0105] In the embodiment of the present disclosure, a plurality of thin film transistors, a plurality of first signal lines extending in a first direction and spaced apart in a second direction, a plurality of second signal lines extending in a second direction and spaced apart in the first direction, and a plurality of metal blocks spaced apart in the first direction are provided on a base substrate. Furthermore, the orthographic projections of the metal blocks on the base substrate are made to overlap with the orthographic projections of the first signal lines on the base substrate, while the orthographic projections of the metal blocks on the base substrate and the orthographic projections of the second signal lines on the base substrate do not overlap. This improves the flatness of the planar layer of the pixels and avoids the occurrence of unevenness within the pixels, thereby improving the performance and display effect of the display device.

[0106] In addition, in addition to improving flatness, the metal block of the embodiment of the present disclosure can also serve as a shielding electrode, shielding crosstalk between multiple signal lines, and shielding crosstalk between multiple signal lines and other conductive layers (such as the anode of the light-emitting device), thereby improving display quality.

[0107] In some embodiments of the present disclosure, as shown in FIG1 and FIG2, the first signal line S1 and the second signal line S2 are arranged in different layers; the metal block (such as SD1 and SD2 in FIG2) is arranged in the same layer as the second signal line S2; wherein the first signal line S1 includes: a plurality of first gate lines GA1, a plurality of second gate lines GA2, a plurality of first power supply voltage signal lines VDD1, a plurality of first reference voltage signal lines VREF1, a plurality of initialization voltage signal lines VINIT and a plurality of light emitting control signal lines EM; wherein the second signal line S2 includes: a plurality of data lines DA, a plurality of second power supply voltage signal lines VDD2 and a plurality of second reference voltage signal lines VDD1, a plurality of first reference voltage signal lines VREF1, a plurality of first reference voltage signal lines VINIT and a plurality of light emitting control signal lines EM; wherein the second signal line S2 includes: a plurality of data lines DA, a plurality of second power supply voltage signal lines VDD2 and a plurality of second reference voltage signal lines VDD1, a plurality of first reference voltage signal lines V signal line VREF2; the first power supply voltage signal line VDD1 is connected to the second power supply voltage signal line VDD2 through the first via K1; the orthographic projection of the first via K1 on the base substrate 10 is located at the intersection of the orthographic projections of the first power supply voltage signal line VDD1 and the second power supply voltage signal line VDD2 on the base substrate 10; the first reference voltage signal line VREF1 is connected to the second reference voltage signal line VREF2 through the second via K2; the orthographic projection of the second via K2 on the base substrate 10 is located at the intersection of the orthographic projections of the first reference voltage signal line VREF1 and the second reference voltage signal line VREF2 on the base substrate 10.

[0108] In some embodiments of the present disclosure, as shown in FIG. 2 , the metal block includes: a plurality of first electrode blocks SD1 , the orthographic projections of the first electrode blocks SD1 on the base substrate 10 overlap with the orthographic projections of the first power supply voltage signal line VDD1 and the light emitting control signal line EM on the base substrate 10 .

[0109] In some embodiments of the present disclosure, as shown in FIG. 2 , an orthographic projection of the first electrode block SD1 on the base substrate 10 and an orthographic projection of the second signal line S2 on the base substrate 10 are spaced apart from each other.

[0110] In some embodiments of the present disclosure, as shown in Figure 2, the array substrate 100 also includes a plurality of first connection portions L1 arranged on the base substrate 10, and the first connection portions L1 are arranged at intervals along the first direction F1; the first connection portion L1 is connected to the initialization voltage signal line VINIT through the third via K3; the first connection portion L1 is connected to the active area of ​​the thin film transistor (for example, T0 in Figure 2) through the fourth via K4; the orthographic projection of the third via K3 on the base substrate 10 is located at the intersection of the first connection portion L1 and the orthographic projection of the initialization voltage signal line VINIT on the base substrate 10; the orthographic projection of the fourth via K4 on the base substrate 10 is located at the overlap of the first connection portion L1 and the orthographic projection of the active area of ​​the thin film transistor (for example, T0 in Figure 2) on the base substrate 10.

[0111] In some embodiments of the present disclosure, as shown in Figure 2, the array substrate 100 further includes: a plurality of second connection portions L2 arranged on the base substrate 10, and the second connection portions L2 are arranged at intervals along the first direction F1; the second connection portion L2 is connected to the active area of ​​the thin film transistor (for example, T0 in Figure 2) through the seventh via hole K7; the second connection portion L2 is connected to the active area of ​​the thin film transistor (for example, T3 in Figure 2) through the eighth via hole K8; the orthographic projections of the seventh via hole K7 and the eighth via hole K8 on the base substrate 10 are located on different sides of the orthographic projection of the first gate line GA1 on the base substrate 10.

[0112] In some embodiments of the present disclosure, as shown in Figure 2, the metal block also includes: a plurality of second electrode blocks SD2, the orthographic projections of the second electrode blocks SD2 on the base substrate 10 overlap with the orthographic projections of the second gate line GA2, the first reference voltage signal line VREF1 and the initialization voltage signal line VINIT on the base substrate 10; the orthographic projections of the second electrode blocks SD2 on the base substrate 10 are spaced from each other.

[0113] In some embodiments of the present disclosure, as shown in Figure 2, the array substrate 100 further includes: a plurality of first electrodes D1 arranged on the base substrate 10, the orthographic projection of the first electrode D1 on the base substrate 10 overlapping with the orthographic projection of the gate of the thin film transistor (for example, T0, T1, T2 in Figure 2) on the base substrate 10; wherein, the orthographic projections of the first gate line GA1 and the second gate line GA2 on the base substrate 10 are respectively located on different sides of the orthographic projection of the first electrode D1 on the base substrate 10; the orthographic projection of the light emitting control signal line EM on the base substrate 10 is located between the first power supply voltage signal line VDD1 and the orthographic projection of the first gate line GA1 on the base substrate 10; the orthographic projection of the first reference voltage signal line VREF1 on the base substrate 10 is located between the orthographic projection of the initialization voltage signal line VINIT and the orthographic projection of the second gate line GA2 on the base substrate 10.

[0114] In some embodiments of the present disclosure, as shown in FIG. 2 , the first electrode D1 and the first electrode block SD1 and the second electrode block SD2 are spaced apart from each other.

[0115] The display panel provided by the embodiment of the present disclosure, the base substrate 10 may include a display area and a non-display area. The non-display area may surround the display area. The display area may include a plurality of pixel units, and the pixel unit may include a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0116] The display panel provided by the embodiment of the present disclosure, as shown in FIG3 , may include at least one of the multiple sub-pixels: a pixel circuit 110 and a light-emitting device L. The pixel circuit 110 includes a thin-film transistor (e.g., T0, T1, T2, T3 in FIG3 ) and a storage capacitor Cst. The interaction between the thin-film transistor and the storage capacitor Cst generates an electrical signal, which is input into the first electrode of the light-emitting device L. A corresponding voltage is applied to the second electrode of the light-emitting device L, thereby driving the light-emitting device L to emit light. The light-emitting device L may include at least one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro LED), and a mini light-emitting diode (Mini LED). The light-emitting device L may include a first electrode, a light-emitting functional layer, and a second electrode arranged in a stacked manner. For example, the first electrode may be an anode, and the second electrode may be a cathode. The light-emitting functional layer may include a light-emitting layer. Furthermore, the light-emitting functional layer may also include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. Of course, in actual applications, the light-emitting device L can be designed and determined according to the requirements of the actual application environment, and is not limited here.

[0117] In some embodiments of the present disclosure, as shown in Figure 3, multiple thin film transistors include: a first transistor T1, a second transistor T2, a third transistor T3, and a driving transistor T0; wherein, the gate of the first transistor T1 is coupled to the first gate line GA1, the first electrode of the first transistor T1 is coupled to the data line DA, and the second electrode of the first transistor T1 is coupled to the gate of the driving transistor T0; the gate of the second transistor T2 is coupled to the second gate line GA2, the first electrode of the second transistor T2 is coupled to the first reference voltage signal line VREF1, and the second electrode of the second transistor T2 is coupled to the gate of the driving transistor T0; the gate of the third transistor T3 is coupled to the light emitting control signal line EM, the first electrode of the third transistor T3 is coupled to the first power supply voltage signal line VDD1, and the second electrode of the third transistor T3 is coupled to the first electrode of the driving transistor T0; the gate of the driving transistor T0 is coupled to the first electrode of the storage capacitor Cst, and the second electrode of the driving transistor T0 is coupled to the light emitting device L; the second electrode of the storage capacitor Cst is coupled to the initialization voltage signal line VINIT.

[0118] For example, the first electrode and the second electrode of the transistor can be determined as a source or a drain according to actual application, which is not limited here.

[0119] In some embodiments of the present disclosure, as shown in FIG4 and FIG5 , the array substrate 100 further includes:

[0120] The light shielding layer 15 is located on the base substrate 10;

[0121] The buffer layer 20 is located on the side of the light shielding layer 15 facing away from the base substrate 10;

[0122] The active layer 25 is located on the side of the buffer layer 20 facing away from the substrate 10 . The active layer 25 includes active regions of the thin film transistor (e.g., a0 , a1 , a2 , and a3 in the figure).

[0123] The gate insulating layer 30 is located on a side of the active layer 25 facing away from the substrate 10;

[0124] A first conductive layer 35 is located on a side of the gate insulating layer 30 facing away from the substrate 10 . The first conductive layer 35 includes a first signal line S1 and a gate of a thin film transistor.

[0125] an interlayer insulating layer 40 , located on a side of the first conductive layer 35 facing away from the substrate 10 ;

[0126] The second conductive layer 45 is located on a side of the interlayer insulating layer 40 facing away from the base substrate 10 . The second conductive layer 45 includes a second signal line S2 , a first connecting portion L1 , a second connecting portion L2 , metal blocks (such as SD1 and SD2 in the figure), and a first electrode D1 .

[0127] a planarization layer 50 , located on a side of the second conductive layer 45 facing away from the base substrate 10 ;

[0128] an anode layer 55 , located on a side of the planarization layer 50 facing away from the substrate 10 ;

[0129] The pixel defining layer 60 is provided on the same layer as the anode layer 55 , and the orthographic projection of the pixel defining layer 60 on the base substrate 10 does not overlap with the orthographic projection of the anode layer 55 on the base substrate 10 .

[0130] Exemplarily, in combination with Figures 3 to 5, the active layer 25 can be formed by patterning a semiconductor material. The active layer 25 can be used to produce the active area a1 of the first transistor T1, the active area a2 of the second transistor T2, the active area a3 of the third transistor T3, and the active area a4 of the driving transistor T0. Each active area may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layer of some transistors can be provided in one piece. Exemplarily, the active layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0131] For example, as shown in Figures 4 and 5, the materials of the first conductive layer 35, the second conductive layer 45, and the anode layer 55 can be conductive materials. For example, the conductive material can include metal materials or alloy materials such as aluminum, molybdenum, and titanium, and can also include metal oxides such as indium tin oxide (ITO). The embodiments of the present disclosure do not limit the materials of the functional layers.

[0132] For example, as shown in Figures 4 and 5, the light-shielding layer 15, the buffer layer 20, the gate insulating layer 30, the interlayer insulating layer 40, the planarization layer 50, the pixel defining layer 60, etc. are all formed of insulating materials. According to needs, organic insulating materials such as polyimide, resin materials, etc. can be selected, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. can be selected. The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0133] The various structures in the first conductive layer 35 and the second conductive layer 45 can be formed using a patterning process, and the vias can be formed using an etching process. It should be noted that the patterning process may include only photolithography, or may include both photolithography and etching steps, and may also include other processes such as printing and inkjet printing to form a predetermined pattern. Photolithography refers to a process that uses photoresist, a mask, and an exposure machine, including film formation, exposure, and development processes, to form a pattern. In specific implementations, the corresponding patterning process can be selected based on the structure formed in this disclosure.

[0134] It should be noted that, as shown in Figure 5, the orthographic projection of the first conductive layer 35 on the base substrate 10 and the orthographic projection of the first electrode D1 in the second conductive layer 45 on the base substrate 10 have an overlapping area; the first electrode D1 in the second conductive layer 45 and the second conductive layer 45 can constitute a storage capacitor Cst, wherein the first conductive layer 35 can serve as the first electrode of the storage capacitor, and the first electrode D1 in the second conductive layer 45 can serve as the second electrode of the storage capacitor Cst.

[0135] In some embodiments of the present disclosure, as shown in Figures 2, 4 and 5, the anode layer 55 is connected to the first electrode D1 through the anode via K55; wherein, the anode via K55 is close to the second gate line GA2, and the orthographic projection of the anode via K55 on the base substrate 10 overlaps with the orthographic projection of the first electrode D1 on the base substrate 10.

[0136] It should be noted that, as shown in Figures 2, 4 and 5, the anode via K55 penetrates the planarization layer 50; the first via K1, the second via K2 and the third via K3 penetrate the interlayer insulating layer 40; the fourth via K4, the seventh via K7 and the eighth via K8 penetrate the interlayer insulating layer 40 and the gate insulating layer 30.

[0137] The structural diagrams of other display panels provided by the embodiments of the present disclosure are shown in Figures 6 to 9, which are modifications of the implementation of the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0138] In other embodiments of the present disclosure, as shown in Figures 6 to 9, the second electrode block SD2 is connected to the first connection portion L1 to form a whole. Exemplarily, since the second electrode block SD2 and the first connection portion L1 are integrally formed, the second electrode block SD2 is electrically connected to the initialization voltage signal line VINIT through the third via K3.

[0139] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figures 10 and 11, which are modifications of the implementation of the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0140] In some further embodiments of the present disclosure, as shown in Figures 10 and 11 , the first electrode block SD1 is connected to the second power supply voltage signal line VDD2 to form a single unit; the orthographic projection of the first electrode block SD1 on the substrate 10 is spaced from the orthographic projections of the data line DA and the second reference voltage signal line VREF1 on the substrate 10. Exemplarily, because the first electrode block SD1 and the second power supply voltage signal line VDD2 are formed as a single unit, the first electrode block SD1 is connected to the first power supply voltage signal line VDD1 via a first via K1. Furthermore, the first electrode block SD1 is also connected to the first power supply voltage signal line VDD1 via a first conductive via DK1, which extends through the interlayer insulating layer 40.

[0141] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figures 12 to 14, which are modifications of the implementation of the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0142] In some further embodiments of the present disclosure, as shown in Figures 12 to 14 , the first electrode block SD1 and the second reference voltage signal line VREF2 are connected to form a single unit; the orthographic projection of the first electrode block SD1 on the substrate 10 is spaced from the orthographic projections of the data line DA and the second power supply voltage signal line VDD2 on the substrate 10. Exemplarily, because the first electrode block SD1 and the second reference voltage signal line VREF2 are formed as a single unit, the first electrode block SD1 is connected to the first reference voltage signal line VREF1 via a second via K2. The second electrode block SD2 is connected to the first reference voltage signal line VREF1 via a second conductive via DK2, which penetrates the interlayer insulating layer 40.

[0143] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figures 15 and 16, which are modifications of the implementation of the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0144] In some other embodiments of the present disclosure, as shown in FIG. 15 , the orthographic projection of the first electrode block SD1 on the base substrate 10 overlaps with the orthographic projections of the first power voltage signal line VDD1 , the light emitting control signal line EM and the first gate line G1 on the base substrate 10 .

[0145] In some further embodiments of the present disclosure, as shown in FIG15 , the first electrode D1 extends along the second direction F2 to the position of the first electrode block SD1 and is connected to the first electrode block SD1 to form a single unit. Exemplarily, because the first electrode D1 and the first electrode block SD1 are integrally formed, and the first electrode D1 is connected to the active layer of the thin-film transistor, the first electrode block SD1 is connected to the active layer of the thin-film transistor. Furthermore, the second electrode block SD2 is connected to the first connection portion L1 to form a single unit. Exemplarily, because the second electrode block SD2 and the first connection portion L1 are integrally formed, the second electrode block SD2 is electrically connected to the initialization voltage signal line VINIT via the third via K3.

[0146] In some other embodiments of the present disclosure, as shown in Figure 15, the anode via K55 is close to the light emitting control signal line EM, and the positive projection of the anode via K55 on the base substrate 10 overlaps with the positive projection of the first electrode block SD1 and the first power supply voltage signal line VDD1 on the base substrate 10.

[0147] In some further embodiments of the present disclosure, as shown in FIG16 , the array substrate further includes a counter substrate 200 including a black matrix region 210. The orthographic projection of the black matrix region 210 on the base substrate overlaps with the orthographic projections of the first power supply voltage signal line VDD1 and the second signal line S2 on the base substrate 10. Furthermore, the orthographic projection of the black matrix region 210 on the base substrate overlaps with the orthographic projection of the anode via K55 on the base substrate 10. Exemplarily, the counter substrate is disposed opposite the array substrate.

[0148] The embodiment of the present disclosure improves the poor flatness caused by the large depth of the anode via by making the orthographic projection of the black matrix area on the base substrate overlap with the orthographic projection of the anode via on the base substrate, reduces the impact of flatness on light output efficiency, and thus improves display quality.

[0149] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figures 17 and 18, which are modifications of the implementation of the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0150] In some other embodiments of the present disclosure, as shown in FIG. 17 , the orthographic projection of the first electrode block SD1 on the base substrate 10 overlaps with the orthographic projections of the light emitting control signal line EM and the first gate line GA1 on the base substrate 10 .

[0151] In some further embodiments of the present disclosure, as shown in FIG17 , the first electrode D1 extends along the second direction F2 to the position of the first electrode block SD1 and is connected to the first electrode block SD1 to form a single unit. Exemplarily, since the first electrode D1 and the first electrode block SD1 are integrally formed, and the first electrode D1 is connected to the active layer of the thin-film transistor, the first electrode block SD1 is connected to the active layer of the thin-film transistor. Furthermore, the second electrode block SD2 is connected to the first connection portion L1 to form a single unit. Exemplarily, since the second electrode block SD2 and the first connection portion L1 are integrally formed, the second electrode block SD2 is electrically connected to the initialization voltage signal line VINIT via the third via K3.

[0152] In some other embodiments of the present disclosure, as shown in FIG. 17 , the anode via K55 is close to the first gate line GA1 , and the orthographic projection of the anode via K55 on the base substrate 10 overlaps with the orthographic projections of the first electrode block SD1 and the light emitting control signal line EM on the base substrate 10 .

[0153] In some other embodiments of the present disclosure, as shown in Figure 17, the array substrate 100 also includes: a pixel definition layer 65, which is arranged on the same layer as the anode layer 55; the orthographic projection of the pixel definition layer 65 on the base substrate 10 does not overlap with the orthographic projection of the anode layer 55, the metal block (for example, SD1 and SD2 in the figure), the first connection part L1, the second connection part L2 and the first electrode D1 on the base substrate 10; wherein, the orthographic projection of the pixel definition layer 65 on the base substrate 10 overlaps with the orthographic projection of the second signal line S2 and the first power supply voltage signal line VDD1 on the base substrate 10.

[0154] In some other embodiments of the present disclosure, as shown in FIG. 18 , the counter substrate 200 includes a black matrix region 210 , wherein the orthographic projection of the black matrix region 210 on the base substrate 10 overlaps with the orthographic projection of the pixel definition layer 65 on the base substrate 10 .

[0155] In some other embodiments of the present disclosure, as shown in FIG. 18 , the orthographic projection of the black matrix region 210 on the base substrate 10 overlaps with the orthographic projections of the light emitting control signal line EM and the anode via K55 on the base substrate.

[0156] The embodiment of the present disclosure ensures that the orthographic projection of the pixel definition layer 65 on the substrate 10 does not overlap with the orthographic projection of the anode layer 55, the metal block (such as SD1 and SD2 in the figure), the first connection part L1, the second connection part L2 and the first electrode D1 on the substrate 10; and ensures that the orthographic projection of the black matrix area 210 on the substrate 10 overlaps with the orthographic projection of the light-emitting control signal line EM and the anode via K55 on the substrate; even if all the non-luminous areas are arranged in the area wired along the first direction, the influence of unevenness on the light extraction efficiency, luminous efficiency, uniformity and life of the light-emitting device is reduced, and at the same time the aperture ratio of the light extraction is kept unchanged.

[0157] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figures 19 and 20, which are modifications of the implementation of the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0158] In some other embodiments of the present disclosure, as shown in FIG19 , the first electrode D1 extends along the second direction F2 to the first electrode block SD1 and is connected to the first electrode block SD1 to form a single unit. Furthermore, the first electrode D1 extends along the second direction F2 to the second electrode block SD2 and is connected to the second electrode block SD2 to form a single unit. Exemplarily, since the first electrode D1, the first electrode block SD1, and the second electrode block SD2 form a single unit and the first electrode D1 is connected to the active layer of the thin film transistor, the first electrode block SD1 and the second electrode block SD2 are connected to the active layer of the thin film transistor.

[0159] In some other embodiments of the present disclosure, as shown in FIG. 19 , the orthographic projection of the first electrode block SD1 on the base substrate 10 overlaps with the orthographic projections of the light emitting control signal line EM and the first gate line GA1 on the base substrate 10 .

[0160] In some other embodiments of the present disclosure, as shown in FIG. 19 , the anode via K55 is close to the first gate line GA1 , and the orthographic projection of the anode via K55 on the base substrate 10 overlaps with the orthographic projections of the first electrode block SD1 and the light emitting control signal line EM on the base substrate 10 .

[0161] In some other embodiments of the present disclosure, as shown in Figure 19, the array substrate 100 also includes: a pixel definition layer 65, which is arranged on the same layer as the anode layer 55; the orthographic projection of the pixel definition layer 65 on the base substrate 10 does not overlap with the orthographic projection of the anode layer 55, the metal block (for example, SD1 and SD2 in the figure), the first connection part L1, the second connection part L2 and the first electrode D1 on the base substrate 10; wherein, the orthographic projection of the pixel definition layer 65 on the base substrate 10 overlaps with the orthographic projection of the second signal line S2 and the first power supply voltage signal line VDD1 on the base substrate 10.

[0162] In some other embodiments of the present disclosure, as shown in Figure 20, the opposing substrate 200 includes a black matrix area 210; wherein the orthographic projection of the black matrix area 210 on the base substrate 10 overlaps with the orthographic projection of the pixel definition layer 65 on the base substrate 10.

[0163] In some other embodiments of the present disclosure, as shown in FIG. 20 , the orthographic projection of the black matrix region 210 on the base substrate 10 overlaps with the orthographic projections of the light emitting control signal line EM and the anode via K55 on the base substrate.

[0164] The embodiment of the present disclosure ensures that the orthographic projection of the pixel definition layer 65 on the substrate 10 does not overlap with the orthographic projection of the anode layer 55, the metal block (such as SD1 and SD2 in the figure), the first connection part L1, the second connection part L2 and the first electrode D1 on the substrate 10; and ensures that the orthographic projection of the black matrix area 210 on the substrate 10 overlaps with the orthographic projection of the light-emitting control signal line EM and the anode via K55 on the substrate; even if all the non-luminous areas are arranged in the area wired along the first direction, the influence of unevenness on the light extraction efficiency, luminous efficiency, uniformity and life of the light-emitting device is reduced, and at the same time the aperture ratio of the light extraction is kept unchanged.

[0165] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figures 21 and 22, which are modifications of the implementation of the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0166] In some other embodiments of the present disclosure, as shown in FIG. 21 and FIG. 22 , the first electrode block SD1 includes a first opening area H1 , and an orthographic projection of the first opening area H1 on the base substrate 10 overlaps with an orthographic projection of the first gate line GA1 on the base substrate 10 .

[0167] In some other embodiments of the present disclosure, as shown in FIG. 21 and FIG. 22 , the second electrode block SD2 includes a second opening area H2 , and the orthographic projection of the second opening area H2 on the base substrate 10 overlaps with the orthographic projection of the second gate line GA2 on the base substrate 10 .

[0168] Exemplarily, as shown in FIG. 21 , the second power supply voltage signal line VDD2 may also include an opening area, the orthographic projection of the opening area on the base substrate 10 overlaps with the orthographic projections of the first gate line GA1 and the second gate line GA2 on the base substrate 10 .

[0169] Illustratively, the embodiment of the present disclosure makes the orthographic projection of the first opening area H1 on the base substrate 10 overlap with the orthographic projection of the first gate line GA1 on the base substrate 10, and makes the orthographic projection of the second opening area H2 on the base substrate 10 overlap with the orthographic projection of the second gate line GA2 on the base substrate 10; thereby further reducing the load of the first gate line GA1 and the second gate line GA2, thereby improving the display quality.

[0170] Exemplarily, the shapes of the above-mentioned opening areas include: rectangle, diamond, square, circle, grid, etc. The specific shape of the opening area can be set according to needs and is not limited here.

[0171] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figures 23 to 25, which are modifications of the implementation of the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0172] In some other embodiments of the present disclosure, as shown in FIG. 23 to FIG. 25 , the orthographic projection of the second electrode block SD2 on the base substrate 10 overlaps with the orthographic projections of the first reference voltage signal line VREF1 and the initialization voltage signal line VINIT on the base substrate 10 .

[0173] In some further embodiments of the present disclosure, as shown in Figures 23 to 25 , the first electrode block SD1 is connected to the second power supply voltage signal line VDD2 to form a single unit; wherein the orthographic projection of the first electrode block SD1 on the base substrate 10 is spaced from the orthographic projections of the data line DA and the second reference voltage signal line VREF1 on the base substrate 10. Exemplarily, because the first electrode block SD1 and the second power supply voltage signal line VDD2 are formed as a single unit, the first electrode block SD1 is connected to the first power supply voltage signal line VDD1 through a first via K1.

[0174] In some further embodiments of the present disclosure, as shown in Figures 23 to 25 , the metal block further includes: a plurality of third electrode blocks SD3, wherein the orthographic projections of the third electrode blocks SD3 on the substrate 10 overlap with the orthographic projections of the first gate line GA1 on the substrate 10; wherein the third electrode blocks SD3 are connected to the first gate line GA1 via fifth vias K5, wherein the orthographic projections of the fifth vias K5 on the substrate 10 overlap with the orthographic projections of the third electrode blocks SD3 on the substrate 10; and the orthographic projections of the third electrode blocks SD3 on the substrate 10 are spaced apart from the orthographic projections of the second signal line S2, the first electrode blocks SD1, and the second electrode blocks SD2 on the substrate 10. Exemplarily, the fifth vias K5 penetrate the interlayer insulating layer 40.

[0175] In some further embodiments of the present disclosure, as shown in Figures 23 to 25 , the metal block further includes: a plurality of fourth electrode blocks SD4, wherein the orthographic projections of the fourth electrode blocks SD4 on the base substrate 10 overlap with the orthographic projections of the second gate line GA2 on the base substrate 10; wherein the fourth electrode blocks SD4 are connected to the second gate line GA2 via sixth vias K6, wherein the orthographic projections of the sixth vias K6 on the base substrate 10 overlap with the orthographic projections of the fourth electrode blocks SD4 on the base substrate 10; and the orthographic projections of the fourth electrode blocks SD4 on the base substrate 10 are spaced apart from the orthographic projections of the second signal line S2, the first electrode blocks SD1, and the second electrode blocks SD2 on the base substrate 10. Exemplarily, the sixth vias K6 penetrate the interlayer insulating layer 40.

[0176] Illustratively, the embodiment of the present disclosure sets a plurality of third electrode blocks SD3, the orthographic projection of the third electrode block SD3 on the base substrate 10 overlaps with the orthographic projection of the first gate line GA1 on the base substrate 10; and sets a plurality of fourth electrode blocks SD4, the orthographic projection of the fourth electrode block SD4 on the base substrate 10 overlaps with the orthographic projection of the second gate line GA2 on the base substrate 10; that is, separate metal blocks are set above the first gate line GA1 and the second gate line GA2, respectively, thereby reducing the load and influence of the pulse AC signal on the first gate line GA1 and the second gate line GA2, and improving the display quality.

[0177] The structural diagrams of some other display panels provided by the embodiments of the present disclosure are shown in Figure 26, which are modifications of the implementation of the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0178] In some other embodiments of the present disclosure, as shown in FIG. 26 , the orthographic projection of the first electrode block SD1 on the base substrate 10 overlaps with the orthographic projections of the light emitting control signal line EM and the first gate line GA1 on the base substrate 10 .

[0179] In some other embodiments of the present disclosure, as shown in FIG26 , the first electrode D1 extends along the second direction F2 to the first electrode block SD1 and is connected to the first electrode block SD1 to form a single unit. Furthermore, the first electrode D1 extends along the second direction F2 to the second electrode block SD2 and is connected to the second electrode block SD2 to form a single unit. Exemplarily, since the first electrode D1, the first electrode block SD1, and the second electrode block SD2 form a single unit and the first electrode D1 is connected to the active layer of the thin film transistor, the first electrode block SD1 and the second electrode block SD2 are connected to the active layer of the thin film transistor.

[0180] In some other embodiments of the present disclosure, as shown in FIG. 26 , the anode via K55 is close to the first gate line GA1 , and the orthographic projection of the anode via K55 on the base substrate 10 overlaps with the orthographic projections of the first electrode block SD1 and the light emitting control signal line EM on the base substrate 10 .

[0181] In some other embodiments of the present disclosure, as shown in FIG. 26 , the first electrode block SD1 includes a first opening area H1 , and an orthographic projection of the first opening area H1 on the base substrate 10 overlaps with an orthographic projection of the first gate line GA1 on the base substrate 10 .

[0182] In some other embodiments of the present disclosure, as shown in FIG. 26 , the second electrode block SD2 includes a second opening area H2 , and the orthographic projection of the second opening area H2 on the base substrate 10 overlaps with the orthographic projection of the second gate line GA2 on the base substrate 10 .

[0183] In some other embodiments of the present disclosure, as shown in Figure 26, the array substrate 100 also includes: a pixel definition layer 65, which is arranged on the same layer as the anode layer 55; the orthographic projection of the pixel definition layer 65 on the base substrate 10 does not overlap with the orthographic projection of the anode layer 55, the metal block (for example, SD1 and SD2 in the figure), the first connection part L1, the second connection part L2 and the first electrode D1 on the base substrate 10; wherein, the orthographic projection of the pixel definition layer 65 on the base substrate 10 overlaps with the orthographic projection of the second signal line S2 and the first power supply voltage signal line VDD1 on the base substrate 10.

[0184] Illustratively, the embodiment of the present disclosure makes the orthographic projection of the first opening area H1 on the base substrate 10 overlap with the orthographic projection of the first gate line GA1 on the base substrate 10, and makes the orthographic projection of the second opening area H2 on the base substrate 10 overlap with the orthographic projection of the second gate line GA2 on the base substrate 10; thereby further reducing the load of the first gate line GA1 and the second gate line GA2, thereby improving the display quality.

[0185] Exemplarily, the shapes of the above-mentioned opening areas include: rectangle, diamond, square, circle, grid, etc. The specific shape of the opening area can be set according to needs and is not limited here.

[0186] Based on the same inventive concept, the present disclosure also provides a display device including the display panel provided in the present disclosure. The implementation of the display device can refer to the above-mentioned display panel embodiment, and the repeated parts will not be repeated.

[0187] In specific implementations, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, an electronic watch, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0188] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0189] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, wherein: include: An array substrate, comprising: a base substrate and a plurality of thin film transistors arranged on the base substrate, a plurality of first signal lines extending along a first direction and arranged at intervals along a second direction, a plurality of second signal lines extending along the second direction and arranged at intervals along the first direction, and a plurality of metal blocks arranged at intervals along the first direction; Among them, the orthographic projection of the first signal line on the substrate intersects with the orthographic projection of the second signal line on the substrate; the orthographic projection of the metal block on the substrate overlaps with the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal block on the substrate does not overlap with the orthographic projection of the second signal line on the substrate.

2. The display panel according to claim 1, wherein: The first signal line and the second signal line are arranged in different layers; the metal block and the second signal line are arranged in the same layer; The first signal lines include: a plurality of first gate lines, a plurality of second gate lines, a plurality of first power supply voltage signal lines, a plurality of first reference voltage signal lines, a plurality of initialization voltage signal lines and a plurality of light emitting control signal lines; The second signal lines include: a plurality of data lines, a plurality of second power supply voltage signal lines and a plurality of second reference voltage signal lines; The first power supply voltage signal line is connected to the second power supply voltage signal line through a first via hole; the orthographic projection of the first via hole on the substrate is located at the intersection of the orthographic projection of the first power supply voltage signal line and the second power supply voltage signal line on the substrate; The first reference voltage signal line is connected to the second reference voltage signal line through a second via hole; the orthographic projection of the second via hole on the substrate is located at the intersection of the orthographic projection of the first reference voltage signal line and the second reference voltage signal line on the substrate.

3. The display panel according to claim 2, wherein: The metal block comprises: a plurality of first electrode blocks, the orthographic projections of the first electrode blocks on the base substrate overlap with the orthographic projections of the first power supply voltage signal line and the light emitting control signal line on the base substrate; Or, the orthographic projection of the first electrode block on the base substrate overlaps with the orthographic projections of the first power supply voltage signal line, the light emitting control signal line and the first gate line on the base substrate; Alternatively, the orthographic projection of the first electrode block on the base substrate overlaps with the orthographic projections of the light emitting control signal line and the first gate line on the base substrate.

4. The display panel according to claim 3, wherein: An orthographic projection of the first electrode block on the base substrate and an orthographic projection of the second signal line on the base substrate are spaced apart from each other.

5. The display panel according to claim 3, wherein: The first electrode block is connected to the second power supply voltage signal line to form a whole; The orthographic projection of the first electrode block on the base substrate is spaced apart from the orthographic projections of the data line and the second reference voltage signal line on the base substrate.

6. The display panel according to claim 3, wherein: The first electrode block is connected to the second reference voltage signal line to form a whole; The orthographic projection of the first electrode block on the base substrate is spaced apart from the orthographic projections of the data line and the second power supply voltage signal line on the base substrate.

7. The display panel according to claim 3, wherein: The first electrode block includes a first opening area, and an orthographic projection of the first opening area on the base substrate overlaps with an orthographic projection of the first gate line on the base substrate.

8. The display panel according to any one of claims 3 to 7, wherein: The array substrate further comprises a plurality of first connection portions arranged on the base substrate, the first connection portions being arranged at intervals along the first direction; the first connection portions being connected to the initialization voltage signal line through a third via hole; and the first connection portions being connected to the active region of the thin film transistor through a fourth via hole; The orthographic projection of the third via hole on the base substrate is located at the intersection of the orthographic projection of the first connecting portion and the initialization voltage signal line on the base substrate; The orthographic projection of the fourth via hole on the base substrate is located at an overlapped position of the orthographic projection of the first connecting portion and the active region of the thin film transistor on the base substrate.

9. The display panel according to claim 8, wherein: The metal block further includes: a plurality of second electrode blocks, the orthographic projections of the second electrode blocks on the base substrate overlap with the orthographic projections of the second gate line, the first reference voltage signal line and the initialization voltage signal line on the base substrate; Or, the orthographic projection of the second electrode block on the base substrate overlaps with the orthographic projections of the first reference voltage signal line and the initialization voltage signal line on the base substrate; An orthographic projection of the second electrode block on the base substrate and an orthographic projection of the second signal line on the base substrate are spaced apart from each other.

10. The display panel according to claim 9, wherein: An orthographic projection of the second electrode block on the base substrate and an orthographic projection of the first connecting portion on the base substrate are spaced apart from each other.

11. The display panel according to claim 9, wherein: The second electrode block is connected to the first connecting portion to form a whole.

12. The display panel according to claim 9, wherein: The second electrode block includes a second opening area, and an orthographic projection of the second opening area on the base substrate overlaps with an orthographic projection of the second gate line on the base substrate.

13. The display panel according to any one of claims 3 to 12, wherein: The metal block further includes: a plurality of third electrode blocks, wherein the orthographic projection of the third electrode block on the base substrate overlaps with the orthographic projection of the first gate line on the base substrate; The third electrode block is connected to the first gate line through a fifth via hole, and the orthographic projection of the fifth via hole on the base substrate overlaps with the orthographic projection of the third electrode block on the base substrate; The orthographic projection of the third electrode block on the base substrate is spaced apart from the orthographic projections of the second signal line, the first electrode block, and the second electrode block on the base substrate.

14. The display panel according to any one of claims 3 to 12, wherein: The metal block further includes: a plurality of fourth electrode blocks, wherein the orthographic projection of the fourth electrode block on the base substrate overlaps with the orthographic projection of the second gate line on the base substrate; The fourth electrode block is connected to the second gate line through a sixth via hole, and the orthographic projection of the sixth via hole on the base substrate overlaps with the orthographic projection of the fourth electrode block on the base substrate; The orthographic projection of the fourth electrode block on the base substrate is spaced apart from the orthographic projections of the second signal line, the first electrode block, and the second electrode block on the base substrate.

15. The display panel according to any one of claims 2 to 12, wherein: The array substrate further comprises: a plurality of first electrodes disposed on the base substrate, wherein the orthographic projection of the first electrodes on the base substrate overlaps with the orthographic projection of the gate of the thin film transistor on the base substrate; The orthographic projections of the first gate line and the second gate line on the base substrate are respectively located on different sides of the orthographic projection of the first electrode on the base substrate; The orthographic projection of the light emitting control signal line on the base substrate is located between the orthographic projection of the first power supply voltage signal line and the first gate line on the base substrate; The orthographic projection of the first reference voltage signal line on the base substrate is located between the orthographic projection of the initialization voltage signal line and the second gate line on the base substrate.

16. The display panel according to claim 15, wherein: The first electrode and the first electrode block and the second electrode block are arranged to be spaced apart from each other.

17. The display panel according to claim 15, wherein: The first electrode extends along the second direction to the position of the first electrode block and is connected to the first electrode block to form a whole, and / or the first electrode extends along the second direction to the position of the second electrode block and is connected to the second electrode block to form a whole.

18. The display panel according to any one of claims 2 to 12, wherein: The array substrate also includes: a plurality of second connection portions arranged on the base substrate, the second connection portions being arranged at intervals along the first direction; the second connection portions being connected to the active area of ​​the thin film transistor through a seventh via hole; the second connection portions being connected to the active area of ​​the thin film transistor through an eighth via hole; the orthographic projections of the seventh via hole and the eighth via hole on the base substrate being located on different sides of the orthographic projection of the first gate line on the base substrate.

19. The display panel according to any one of claims 1 to 18, wherein: Also includes: a plurality of sub-pixels, at least one of the plurality of sub-pixels comprising a pixel circuit and a light-emitting device; The sub-pixel includes the plurality of thin film transistors and a storage capacitor; wherein the plurality of thin film transistors include: a first transistor, a second transistor, a third transistor, and a driving transistor; The gate of the first transistor is coupled to the first gate line, the first electrode of the first transistor is coupled to the data line, and the second electrode of the first transistor is coupled to the gate of the driving transistor; The gate of the second transistor is coupled to the second gate line, and the first electrode of the second transistor coupled to the first reference voltage signal line, and the second electrode of the second transistor is coupled to the gate of the driving transistor; The gate of the third transistor is coupled to the light emitting control signal line, the first electrode of the third transistor is coupled to the first power supply voltage signal line, and the second electrode of the third transistor is coupled to the first electrode of the driving transistor; The gate electrode of the driving transistor is coupled to the first electrode of the storage capacitor, and the second electrode of the driving transistor is coupled to the light emitting device; The second electrode of the storage capacitor is coupled to the initialization voltage signal line.

20. The display panel according to any one of claims 2 to 19, wherein: The array substrate further includes: A light shielding layer, located on the substrate; A buffer layer, located on a side of the light shielding layer away from the substrate; An active layer, located on a side of the buffer layer away from the substrate, the active layer including an active region of the thin film transistor; A gate insulating layer, located on a side of the active layer away from the substrate; A first conductive layer, located on a side of the gate insulating layer away from the base substrate, the first conductive layer comprising the first signal line and a gate of the thin film transistor; an interlayer insulating layer, located on a side of the first conductive layer away from the substrate; A second conductive layer, located on a side of the interlayer insulating layer away from the base substrate, the second conductive layer comprising the second signal line, a first connecting portion, a second connecting portion, the metal block and a first electrode; A planarization layer, located on a side of the second conductive layer away from the substrate; an anode layer, located on a side of the planarization layer away from the substrate; The pixel defining layer is arranged in the same layer as the anode layer, and the orthographic projection of the pixel defining layer on the base substrate does not overlap with the orthographic projection of the anode layer on the base substrate.

21. The display panel according to claim 20, wherein: The anode layer is connected to the first electrode through an anode via; The anode via hole is close to the second gate line, and the orthographic projection of the anode via hole on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate; Or, the anode via hole is close to the light-emitting control signal line, and the orthographic projection of the anode via hole on the base substrate overlaps with the orthographic projection of the first electrode block and the first power supply voltage signal line on the base substrate; Alternatively, the anode via hole is close to the first gate line, and the orthographic projection of the anode via hole on the base substrate overlaps with the orthographic projections of the first electrode block and the light emitting control signal line on the base substrate.

22. The display panel according to claim 21, wherein: The array substrate further comprises: a pixel definition layer, which is arranged on the same layer as the anode layer; The orthographic projection of the pixel definition layer on the base substrate does not overlap with the orthographic projection of the anode layer, the metal block, the first connecting portion, the second connecting portion and the first electrode on the base substrate; The orthographic projection of the pixel definition layer on the base substrate overlaps with the orthographic projections of the second signal line and the first power supply voltage signal line on the base substrate.

23. The display panel according to claim 22, wherein: Also includes: an opposite substrate, the opposite substrate comprising a black matrix area; The orthographic projection of the black matrix region on the base substrate overlaps with the orthographic projection of the pixel definition layer on the base substrate.

24. The display panel according to claim 23, wherein: The orthographic projection of the black matrix area on the base substrate overlaps with the orthographic projection of the light emitting control signal line and the anode via on the base substrate.

25. A display device, wherein: Comprising a display panel as described in any one of claims 1-24.

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