Memory module

Abstract

Provided is a memory module that expands the bandwidth of an input / output signal of a memory die. In a memory module 100, a stacked memory die 110 and a logic die 120 are aligned in a first direction on an interposer 130, and the stacked memory die 110 has a plurality of memory dies 10 that are stacked. The logic die 120 comprises input / output terminals 122 disposed on the end on the stacked memory die side in the first direction, and an input / output circuit 124 disposed on the stacked memory die side in the first direction. The stacked memory die 110 comprises: a plurality of memory elements 12 disposed in each of the memory dies 10; input / output terminals 112 disposed on the end on the logic die side in the first direction; a plurality of input / output circuits 14 disposed on the logic die side in the first direction in each of the memory dies 10; and via channels 16 that are disposed at the end on the logic die side in the first direction, penetrate the memory dies 10, and connect the input / output circuits 14 and the input / output terminals 112.

Description

memory modules

[0001] The present invention relates to a memory module.

[0002] In memory modules, a 3D or 2.5D packaging technology is known in which multiple memory dies and logic dies are mounted on a silicon interposer using TSV (Through Silicon Via) technology. This packaging technology allows for high-density wiring to be formed for multiple memory dies and logic dies, thereby achieving miniaturization, thinning, and broadband.

[0003] Patent Document 1 discloses such a memory module. In this memory module, multiple memory dies are stacked on a silicon interposer via a base die (stacked memory dies), and the stacked memory dies and a logic die are arranged side by side on the silicon interposer. In the stacked memory dies, the multiple memory dies and the base die are electrically connected using TSV (Through Silicon Via) technology.

[0004] US Patent Application Publication No. 2019 / 0278511

[0005] In such memory modules, there is a demand for expanding the bandwidth of input / output signals of the memory die in order to improve the performance of the logic die and increase the number of computing cores. Since the bandwidth of the input / output signals is determined by (the number of input / outputs x the data rate of the input / output signals), it is conceivable to expand the bandwidth of the input / output signals of the memory die by increasing the number of input / outputs, i.e., the number of input / output channels, or by increasing the data rate of the input / output signals.

[0006] In the memory module of Patent Document 1, the TSVs are arranged in the center of the memory die in the juxtaposition direction of the memory die and the logic die. Therefore, when increasing the number of IOs, it is expected that the signal paths will become congested in the center of the memory die, making it difficult to increase the number of IOs. On the other hand, when increasing the data rate of input / output signals, it is expected that the signal paths between the stacked memory die 110 and the logic die 120 will be long, making it difficult to increase the data rate of the input / output signals.

[0007] SUMMARY OF THE INVENTION An object of the present invention is to provide a memory module that extends the bandwidth of input / output signals of a memory die.

[0008] The module of the present invention includes a stacked memory die having a plurality of stacked memory dies, a logic die, and an interposer electrically connecting the stacked memory die and the logic die, the stacked memory die and the logic die being juxtaposed on the interposer in a first direction along a main surface of the interposer. The logic die is arranged at an end of the stacked memory die in the first direction and has logic input / output terminals electrically connected to the interposer, and logic input / output circuits arranged on the stacked memory die in the first direction and connected to the logic input / output terminals. The stacked memory die has a plurality of memory elements arranged on each of the plurality of memory dies, memory input / output terminals arranged at an end of the logic die in the first direction and electrically connected to the interposer, a plurality of memory input / output circuits arranged on the logic die in the first direction on each of the plurality of memory dies and connected to each of the plurality of memory elements, and via channels arranged at an end of the logic die in the first direction and passing through the plurality of memory dies to electrically connect the plurality of memory input / output circuits to the memory input / output terminals.

[0009] Another module according to the present invention includes a stacked memory die having a plurality of stacked memory dies and a base die, a logic die, and an interposer electrically connecting the stacked memory die and the logic die, the stacked memory die and the logic die being juxtaposed on the interposer in a first direction along a main surface of the interposer. The logic die is arranged at an end on the stacked memory die side in the first direction and has logic input / output terminals electrically connected to the interposer, and a logic input / output circuit arranged on the stacked memory die side in the first direction and connected to the logic input / output terminals. The stacked memory die includes a plurality of pairs of first and second memory elements, each pair of the plurality of pairs of first and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; memory input / output terminals arranged on the logic die side of the base die in the first direction and electrically connecting to the interposer; a first memory input / output circuit and a second memory input / output circuit arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; first via channels arranged at an end on the logic die side in the first direction, passing through the plurality of memory dies and the base die to electrically connect the plurality of first memory elements to the first memory input / output circuit; and second via channels arranged at an end on the opposite side of the logic die in the first direction, passing through the plurality of memory dies and the base die to electrically connect the plurality of second memory elements to the second memory input / output circuit.

[0010] Another module according to the present invention includes a stacked memory die having a plurality of stacked memory dies and a base die, a logic die, and an interposer electrically connecting the stacked memory die and the logic die, the stacked memory die and the logic die being juxtaposed on the interposer in a first direction along a main surface of the interposer. The logic die is arranged at an end on the stacked memory die side in the first direction and has logic input / output terminals electrically connected to the interposer, and a logic input / output circuit arranged on the stacked memory die side in the first direction and connected to the logic input / output terminals. the stacked memory die includes a plurality of pairs of first and second memory elements, each pair of the plurality of pairs of first and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; memory input / output terminals arranged on the logic die side of the base die in the first direction and electrically connecting to the interposer; a first memory input / output circuit and a second memory input / output circuit arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; first via channels arranged at an end of the logic die side in the first direction, passing through the plurality of memory dies and the base die to electrically connect the plurality of first memory elements to the first memory input / output circuit; and second via channels arranged between each pair of the plurality of pairs of first and second memory elements in the first direction, passing through the plurality of memory dies and the base die to electrically connect the plurality of second memory elements to the second memory input / output circuit.

[0011] Another module according to the present invention includes a stacked memory die having a plurality of stacked memory dies and a base die, and a logic die, wherein the base die is disposed across the plurality of memory dies and the logic die, and the plurality of memory dies and the logic die are juxtaposed on the base die in a first direction along a main surface of the base die. The logic die is disposed at an end on the side of the plurality of memory dies in the first direction and has logic input / output terminals electrically connected to the base die, and a logic input / output circuit disposed on the side of the plurality of memory dies in the first direction and connected to the logic input / output terminals. The stacked memory die includes a plurality of pairs of first and second memory elements, each pair of the plurality of pairs of first and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; memory input / output terminals arranged on the logic die side of the base die in the first direction and electrically connected to the logic input / output terminals; a memory input / output circuit arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; first via channels arranged at an end of the logic die side in the first direction, passing through the plurality of memory dies and electrically connecting the plurality of first memory elements to the memory input / output circuit; and second via channels arranged between each of the plurality of pairs of first and second memory elements in the first direction, passing through the plurality of memory dies and electrically connecting the plurality of second memory elements to the memory input / output circuit.

[0012] Another module according to the present invention includes a stacked memory die having a plurality of stacked memory dies and a base die, and a logic die, wherein the base die is disposed across the plurality of memory dies and the logic die, and the plurality of memory dies and the logic die are juxtaposed on the base die in a first direction along a main surface of the base die. The logic die is disposed at an end on the side of the plurality of memory dies in the first direction and has logic input / output terminals electrically connected to the base die, and a logic input / output circuit disposed on the side of the plurality of memory dies in the first direction and connected to the logic input / output terminals. The stacked memory die includes a plurality of pairs of first and second memory elements, each pair of the plurality of pairs of first and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; memory input / output terminals arranged on the logic die side of the base die in the first direction and electrically connected to the logic input / output terminals; a memory input / output circuit arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; and via channels arranged between each pair of the plurality of pairs of first and second memory elements in the first direction, passing through the plurality of memory dies and electrically connecting the plurality of first memory elements and the plurality of second memory elements to the memory input / output circuit.

[0013] According to the present invention, the bandwidth of input / output signals of a memory die can be expanded in a memory module.

[0014] 1. A schematic cross-sectional view showing a memory module according to the first embodiment. A schematic exploded perspective view of the memory module shown in FIG. 1. A schematic exploded perspective view of a memory module according to a modified example of the first embodiment. A schematic cross-sectional view showing a memory module according to a second embodiment. A schematic exploded perspective view of the memory module shown in FIG. 4. A schematic exploded perspective view of a memory module according to a modified example of the second embodiment. A schematic cross-sectional view showing a memory module according to a third embodiment. A schematic exploded perspective view of the memory module shown in FIG. 7. A schematic exploded perspective view of a memory module according to a modified example of the third embodiment. A schematic cross-sectional view showing a memory module according to a fourth embodiment. A schematic exploded perspective view of the memory module shown in FIG. 10. A schematic cross-sectional view of a memory module according to a fifth embodiment. A schematic exploded perspective view of the memory module shown in FIG. 12.

[0015] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0016] First Embodiment Fig. 1 is a schematic cross-sectional view showing a memory module according to a first embodiment, and Fig. 2 is a schematic exploded perspective view of the memory module shown in Fig. 1. As shown in Figs. 1 and 2, the memory module 100 includes stacked memory dies 110, a logic die 120, and an interposer 130. Note that an XYZ Cartesian coordinate system is shown in Figs. 1 and 2, as well as in figures described below. The X direction (first direction) and the Y direction (second direction) are directions along the main surface of the interposer 130 (or the main surface of a base die described below), and the Z direction is the stacking direction of the stacked memory dies 110.

[0017] The shapes of the stacked memory die 110 (and the memory die described below), the logic die 120, and the interposer 130 are not particularly limited, but may be, for example, rectangular. Each of the stacked memory die 110 (and the memory die described below), the logic die 120, and the interposer 130 is made of, for example, a silicon substrate (wafer), but is not particularly limited.

[0018] The stacked memory die 110 and the logic die 120 are arranged side by side in the X direction (first direction) on the main surface of the interposer 130. This allows the stacked memory die 110 and the logic die 120 to communicate with each other via the interposer 130 using high-frequency signals.

[0019] The stacked memory die 110 includes multiple memory dies 10 stacked in the Z direction (stacking direction) and input / output terminals 112. The stacked memory die 110 is electrically connected to the interposer 130 face-down via the input / output terminals 112. The input / output terminals 112 are, for example, microbumps.

[0020] The memory die 10 is, for example, a DRAM, an SRAM, or the like, and includes a memory element 12, an input / output circuit 14, a plurality of vias 17, and a plurality of bumps 18. The memory die 10 is electrically connected to adjacent memory dies 10 in a face-down manner via the bumps 18 in cascade. The bumps 18 are, for example, microbumps. In this embodiment, the bumps 18 of the memory die 10 closest to the interposer 130 function as the input / output terminals 112 of the stacked memory die 110 described above.

[0021] 2 does not show the bumps 18 of each memory die 10. Also, in FIG. 2, the memory elements 12 and input / output circuits 14 of the memory dies 10 other than the memory die 10 in the top layer are omitted.

[0022] In this manner, the stacked memory die 110 has a plurality of memory elements 12 , a plurality of input / output circuits 14 , and a via channel 16 made up of a plurality of vias 17 and a plurality of bumps 18 .

[0023] The memory elements 12 are disposed on each of the memory dies 10. The input / output circuits 14 are also disposed on each of the memory dies 10. This allows the base die to be omitted.

[0024] In each memory die 10, input / output circuitry 14 is connected to memory elements 12. Input / output circuitry 14 may be configured with a one-to-one signal output circuit and a one-to-one signal input circuit. Alternatively, input / output circuitry 14 may be configured with a signal output circuit that is a two-to-one multiplexer and a signal input circuit that is a one-to-two demultiplexer. Alternatively, input / output circuitry 14 may be configured with a signal output circuit that is a four-to-one multiplexer and a signal input circuit that is a one-to-four demultiplexer.

[0025] As described above, the via channel 16 is composed of a plurality of vias 17 and a plurality of bumps 18. The vias 17 are TSVs (Through Silicon Vias). As a result, the via channel 16 penetrates a plurality of memory dies 10 and electrically connects a plurality of input / output circuits 14 and the input / output terminals 112.

[0026] The via channels 16 and the input / output terminals 112 are arranged at the end of the logic die 120 in the X direction (first direction), thereby shortening the path of high-frequency signals.

[0027] Furthermore, the input / output circuit 14 is disposed near the via channel 16, i.e., on the logic die 120 side in the X direction (first direction). This allows the path of high-frequency signals on the input / output side of the input / output circuit 14, which have relatively high frequencies, to be shortened when the input / output circuit 14 is configured with a multiplexer and a demultiplexer.

[0028] The logic die 120 is a logic die including a logic circuit, and has input / output terminals 122 and an input / output circuit 124. The logic die 120 is electrically connected to the interposer 130 face-down via the input / output terminals 122. The input / output terminals 122 are, for example, microbumps.

[0029] The input / output circuit 124 is connected to the input / output terminal 122. The input / output circuit 124 may be configured with a one-to-one signal output circuit and a one-to-one signal input circuit. Alternatively, the input / output circuit 124 may be configured with a signal output circuit that is a two-to-one multiplexer and a signal input circuit that is a one-to-two demultiplexer. Alternatively, the input / output circuit 124 may be configured with a signal output circuit that is a four-to-one multiplexer and a signal input circuit that is a one-to-four demultiplexer.

[0030] The input / output terminals 122 are arranged at the end on the stacked memory die 110 side in the X direction (first direction). This allows the path of high-frequency signals to be short. Furthermore, the input / output circuit 124 is arranged near the input / output terminals 122, i.e., on the stacked memory die 110 side in the X direction (first direction). This allows the path of high-frequency signals on the input / output side of the input / output circuit 124, which has a relatively high frequency, to be short when the input / output circuit 124 is configured with a multiplexer and a demultiplexer.

[0031] The interposer 130 is a passive element and has wiring 132 and pad electrodes 134. The interposer 130 is electrically connected to the stacked memory die 110 and the logic die 120 via the pad electrodes 134 in a face-up manner.

[0032] The wiring 132 electrically connects the stacked memory die 110 and the logic die 120. Specifically, the wiring 132 connects the input / output terminals 112 of the stacked memory die 110 and the input / output terminals 122 of the logic die 120.

[0033] The pad electrodes 134 are arranged exposed on the surface, and electrically connect the wiring 132 to the input / output terminals 112 of the stacked memory die 110, and also electrically connect the wiring 132 to the input / output terminals 122 of the logic die 120. The wiring 132 is made of a metal such as Cu, and the pad electrodes 134 are made of a metal such as Cu or Al.

[0034] As described above, according to the memory module 100 of the first embodiment, the via channels 16 are arranged at the end of the stacked memory die 110 on the logic die 120 side in the X direction (first direction). This shortens the signal path between the stacked memory die 110 and the logic die 120, allowing the signal frequency to be increased. This allows the bandwidth (number of IOs x data rate of the input / output signals) of the input / output signals of the memory die 10 to be expanded.

[0035] Furthermore, according to the memory module 100 of the first embodiment, each of the memory dies 10 in the stacked memory dies 110 has an input / output circuit 14. This makes it possible to eliminate the base die (active element) made of a relatively expensive silicon substrate (wafer), thereby realizing cost reduction.

[0036] 3 is a schematic exploded perspective view of a memory module according to a modification of the first embodiment. As shown in FIG. 3 , in the memory module 100, the length of the interposer 130 in the X direction (first direction) is shorter than the length from the end of the stacked memory die 110 opposite the logic die 120 to the end of the logic die 120 opposite the stacked memory die 110. Furthermore, the length of the interposer 130 in the Y direction (second direction) may be shorter than the lengths of the stacked memory die 110 and the logic die 120.

[0037] This makes it possible to reduce the number of interposers (passive elements) made of relatively expensive silicon substrates (wafers), thereby achieving cost reductions.

[0038] Second Embodiment Fig. 4 is a schematic cross-sectional view showing a memory module according to a second embodiment, and Fig. 5 is a schematic exploded perspective view of the memory module shown in Fig. 4. A memory module 100A of the second embodiment shown in Figs. 4 and 5 differs from the memory module 100 of the first embodiment shown in Figs. 1 and 2 in that it includes stacked memory dies 110A instead of stacked memory dies 110. The other configuration of the memory module 100A of the second embodiment is the same as the configuration of the memory module 100 of the first embodiment.

[0039] The stacked memory die 110A differs from the stacked memory die 110 of the first embodiment shown in FIGS. 1 and 2 in that it has a plurality of memory dies 10A instead of the plurality of memory dies 10, and further has a base die 30.

[0040] Compared to the memory die 10 of the first embodiment shown in Figures 1 and 2, the memory die 10A differs in that in addition to the first memory element 12, multiple first vias 17, and multiple first bumps 18, it further includes a second memory element 22 of the same shape, multiple second vias 27, and multiple second bumps 28, and does not include an input / output circuit.

[0041] The base die 30 is an active element and has a first input / output circuit 14 , a second input / output circuit 24 , a first via 17 , a second via 28 , and an input / output terminal 112 .

[0042] In this manner, the stacked memory die 110A has multiple pairs of first memory elements 12 and second memory elements 22, a first via channel 16 formed of multiple first vias 17 and multiple first bumps 18, and a second via channel 26 formed of multiple second vias 27 and multiple second bumps 28.

[0043] The first memory element 12 and the second memory element 22 are arranged side by side in the X direction (first direction) in each of the multiple memory dies 10A. The first memory element 12 communicates with the logic die 120 through the first via channel 16 and the base die 30. The second memory element 22 communicates with the logic die 120 through the second via channel 26 and the base die 30.

[0044] As described above, the first via channel 16 is composed of a plurality of first vias 17 and a plurality of first bumps 18. The first vias 17 are TSVs (Through Silicon Vias), and the first bumps 18 are microbumps. As a result, the first via channel 16 penetrates the plurality of memory dies 10 and the base die 30 to electrically connect the first memory element 12 and the first input / output circuit 14.

[0045] As described above, the second via channel 26 is composed of a plurality of second vias 27 and a plurality of second bumps 28. The second vias 27 are TSVs (Through Silicon Vias), and the second bumps 28 are microbumps. As a result, the second via channel 26 penetrates the plurality of memory dies 10 and the base die 30 to electrically connect the second memory element 22 and the second input / output circuit 24.

[0046] The first input / output circuit 14 and the second input / output circuit 24 are connected to the input / output terminal 112. The first input / output circuit 14 may be configured with a one-to-one signal output circuit and a one-to-one signal input circuit. Alternatively, the first input / output circuit 14 may be configured with a signal output circuit that is a two-to-one multiplexer and a signal input circuit that is a one-to-two demultiplexer. Alternatively, the first input / output circuit 14 may be configured with a signal output circuit that is a four-to-one multiplexer and a signal input circuit that is a one-to-four demultiplexer.

[0047] The second input / output circuit 24 may be configured with a one-to-one signal output circuit and a one-to-one signal input circuit. Alternatively, the second input / output circuit 24 may be configured with a signal output circuit that is a two-to-one multiplexer and a signal input circuit that is a one-to-two demultiplexer. Alternatively, the second input / output circuit 24 may be configured with a signal output circuit that is a four-to-one multiplexer and a signal input circuit that is a one-to-four demultiplexer.

[0048] The first via channel 16 is arranged at an end on the logic die 120 side in the X direction (first direction). The second via channel 26 is arranged at an end on the opposite side of the logic die 120 in the X direction (first direction). In other words, the first via channel 16 and the second via channel 26 are arranged separately in the first direction. This makes it possible to prevent signal paths from becoming congested in the center of the memory die 10 in the first direction.

[0049] The input / output terminal 112 is disposed on the logic die 120 side of the base die 30 in the X direction (first direction). The first input / output circuit 14 and the second input / output circuit 24 are disposed near the input / output terminal 112, i.e., on the logic die 120 side of the base die 30 in the X direction (first direction). The first input / output circuit 14 and the second input / output circuit 24 are disposed on either side of the input / output terminal 112. This arrangement shortens the paths of high-frequency signals on the input / output sides of the first input / output circuit 14 and the second input / output circuit 24, which have relatively high frequencies, when the first input / output circuit 14 and the second input / output circuit 24 are configured as multiplexers and demultiplexers. This arrangement also prevents signal paths from becoming congested near the first input / output circuit 14 and the second input / output circuit 24 of the base die 30, thereby increasing the number of I / Os for input / output signals.

[0050] As described above, in the memory module 100A of the second embodiment, the first via channels 16 and the second via channels 26 are arranged separately in the X direction (first direction) in the stacked memory die 110A. This prevents signal paths from becoming congested in the center of the memory die 10A in the X direction (first direction). Furthermore, it prevents signal paths from becoming congested near the first input / output circuit 14 and the second input / output circuit 24 of the base die 30, thereby increasing the number of input / output (IO) signals. This allows the bandwidth (number of IOs × data rate of the I / O signals) of the I / O signals of the stacked memory die 110A to be expanded.

[0051] Furthermore, in the memory module 100A of the second embodiment, the input / output terminals 112 of the base die 30 are arranged on the logic die 120 side in the X direction (first direction), and the first input / output circuit 14 and the second input / output circuit 24 are arranged near the input / output terminals 112. The first input / output circuit 14 and the second input / output circuit 24 are arranged on either side of the input / output terminal 112. This shortens the paths of high-frequency signals on the input / output sides of the first input / output circuit 14 and the second input / output circuit 24, which have relatively high frequencies, when the input / output circuit 14 is configured as a multiplexer and a demultiplexer, thereby increasing the signal frequency. This allows the input / output signal bandwidth (number of IOs × data rate of the input / output signals) of the stacked memory die 110A to be expanded.

[0052] 6 is a schematic exploded perspective view of a memory module according to a modification of the second embodiment. As shown in FIG. 6, in the memory module 100A, the length of the interposer 130 in the X direction (first direction) is shorter than the length from the end of the stacked memory die 110A opposite the logic die 120 to the end of the logic die 120 opposite the stacked memory die 110A. In addition, the length of the interposer 130 in the Y direction (second direction) may be shorter than the lengths of the stacked memory die 110A and the logic die 120.

[0053] This makes it possible to reduce the number of interposers (passive elements) made of relatively expensive silicon substrates (wafers), thereby achieving cost reductions.

[0054] Third Embodiment Fig. 7 is a schematic cross-sectional view showing a memory module according to a third embodiment, and Fig. 8 is a schematic exploded perspective view of the memory module shown in Fig. 7. The memory module 100A of the third embodiment shown in Figs. 7 and 8 differs from the memory module 100A of the second embodiment shown in Figs. 4 and 5 in the arrangement of the second via channels 26 in the stacked memory die 110A. The other configurations of the memory module 100A of the third embodiment are the same as those of the memory module 100A of the second embodiment.

[0055] The second via channel 26 is arranged on the logic die 120 side in the X direction (first direction) with respect to the second memory element 22. In other words, the second via channel 26 is arranged between the first memory element 12 and the second memory element 22 in the X direction (first direction).

[0056] In the memory module 100A of the third embodiment, the first via channels 16 and the second via channels 26 are also arranged separately in the X direction (first direction) in the stacked memory die 110A. This prevents signal paths from becoming congested in the center of the memory die 10A in the X direction (first direction), allowing the number of IOs for input / output signals to be increased. This allows the bandwidth (number of IOs x data rate of the input / output signals) of the memory die 10A to be expanded.

[0057] In the memory module 100A of the third embodiment, the input / output terminals 112 of the base die 30 are arranged on the logic die 120 side in the X direction (first direction), and the first input / output circuit 14 and the second input / output circuit 24 are arranged near the input / output terminals 112. The first input / output circuit 14 and the second input / output circuit 24 are arranged on either side of the input / output terminal 112. This arrangement shortens the paths of high-frequency signals on the input / output sides of the first input / output circuit 14 and the second input / output circuit 24, which have relatively high frequencies, when the input / output circuit 14 is configured as a multiplexer and a demultiplexer, thereby increasing the frequency of the input / output signals. This arrangement also prevents signal path congestion near the first input / output circuit 14 and the second input / output circuit 24 of the base die 30, thereby increasing the number of input / output (IO) signals. This allows the input / output signal bandwidth (number of IOs × data rate of the input / output signals) of the stacked memory die 110A to be expanded.

[0058] 9 is a schematic exploded perspective view of a memory module according to a modification of the third embodiment. As shown in FIG. 9 , in the memory module 100A, the length of the interposer 130 in the X direction (first direction) is shorter than the length from the end of the stacked memory die 110A opposite the logic die 120 to the end of the logic die 120 opposite the stacked memory die 110A. Furthermore, the length of the interposer 130 in the Y direction (second direction) may be shorter than the lengths of the stacked memory die 110A and the logic die 120.

[0059] This makes it possible to reduce the number of interposers (passive elements) made of relatively expensive silicon substrates (wafers), thereby reducing costs.

[0060] (Fourth Embodiment) Fig. 10 is a schematic cross-sectional view showing a memory module according to a fourth embodiment, and Fig. 11 is a schematic exploded perspective view of the memory module shown in Fig. 10. A memory module 100B of the fourth embodiment shown in Fig. 10 and Fig. 11 differs from the memory module 100A of the third embodiment shown in Fig. 7 and Fig. 8 in that it includes a base die 30A instead of the base die 30 and does not include an interposer 130. The other configuration of the memory module 100B of the fourth embodiment is the same as the configuration of the memory module 100A of the third embodiment.

[0061] The base die 30A is disposed across the multiple memory dies 10A and the logic die 120. As a result, the multiple memory dies 10A and the logic die 120 are juxtaposed in the X direction (first direction) on the base die 30A.

[0062] The base die 30A has a pad electrode 134, an input / output circuit 14, and an input / output terminal 112. The pad electrode 134 is electrically connected to the first via channel 16 and the second via channel 26 of the memory die 10A.

[0063] The input / output circuit 14 is connected between the pad electrode 134 and the input / output terminal 112. The input / output terminal 112 is a pad electrode, and is electrically connected to the logic input / output terminal 122.

[0064] The input / output terminals 112 are arranged on the logic die 120 side in the X direction (first direction) of the base die 30A. The input / output circuit 14 is arranged near the input / output terminals 112, i.e., on the logic die 120 side in the X direction (first direction) of the base die 30A. This allows the path of high-frequency signals on the input / output sides of the input / output circuit 14, which have relatively high frequencies, to be shortened when the input / output circuit 14 is configured with a multiplexer and a demultiplexer.

[0065] As described above, in the memory module 100B of the fourth embodiment, the base die 30A is disposed below the logic die 120. This shortens the signal path between the stacked memory die 110B and the logic die 120, allowing the frequency of input / output signals to be increased. This allows the bandwidth (number of IOs x data rate of the input / output signals) of the input / output signals of the stacked memory die 110B to be expanded.

[0066] Furthermore, in the memory module 100B of the fourth embodiment, the input / output terminals 112 of the base die 30A are arranged on the logic die 120 side in the X direction (first direction), and the input / output circuit 14 is arranged near the input / output terminals 112. This allows the path of high-frequency signals on the input / output side of the input / output circuit 14, which have relatively high frequencies, to be shortened when the input / output circuit 14 is configured with a multiplexer and a demultiplexer, thereby increasing the frequency of the input / output signals. This allows the input / output signal bandwidth (number of IOs x data rate of the input / output signals) of the stacked memory die 110B to be expanded.

[0067] Furthermore, in the memory module 100B of the fourth embodiment, the first via channels 16 and the second via channels 26 are arranged separately in the X direction (first direction) in the stacked memory die 110B. This prevents signal paths from becoming congested in the center of the memory die 10A in the X direction (first direction), allowing the number of signal I / Os to be increased. This allows the bandwidth (number of I / Os x data rate of the I / O signals) of the stacked memory die 110B to be expanded.

[0068] Furthermore, according to the memory module 100B of the fourth embodiment, it is possible to eliminate the interposer (passive element) made of a relatively expensive silicon substrate (wafer), thereby reducing costs.

[0069] Fifth Embodiment Fig. 12 is a schematic cross-sectional view showing a memory module according to a fifth embodiment, and Fig. 13 is a schematic exploded perspective view of the memory module shown in Fig. 12. The memory module 100B of the fifth embodiment shown in Figs. 12 and 13 differs from the memory module 100B of the fourth embodiment shown in Figs. 10 and 11 in the arrangement of the first via channels 16 in the memory die 10A of the stacked memory die 110B. The other configuration of the memory module 100B of the fifth embodiment is the same as the configuration of the memory module 100B of the fourth embodiment.

[0070] The first via channel 16 is arranged on the opposite side of the logic die 120 in the X direction (first direction) with respect to the first memory element 12. In other words, the first via channel 16 is arranged between the first memory element 12 and the second memory element 22 in the X direction (first direction).

[0071] In the memory module 100B of the fifth embodiment, the base die 30A is also disposed across the multiple memory dies 10A and the logic die 120. This shortens the signal path between the stacked memory die 110B and the logic die 120, allowing for higher input / output signal frequencies. This allows for an expansion of the input / output signal bandwidth (number of IOs x data rate of the input / output signals) of the memory die 10.

[0072] Furthermore, in the memory module 100B of the fifth embodiment, the input / output terminals 112 of the base die 30A are arranged on the logic die 120 side in the X direction (first direction), and the input / output circuit 14 is arranged near the input / output terminals 112. This allows the path of high-frequency signals on the input / output side of the input / output circuit 14, which have relatively high frequencies, to be shortened when the input / output circuit 14 is configured with a multiplexer and a demultiplexer, thereby increasing the frequency of the input / output signals. This allows the bandwidth (number of IOs x data rate of the input / output signals) of the input / output signals of the memory die 10 to be expanded.

[0073] Furthermore, the memory module 100B of the fifth embodiment can also increase the number of IOs for input / output signals, thereby expanding the bandwidth (number of IOs x data rate of input / output signals) of the input / output signals of the stacked memory die 110B.

[0074] Furthermore, in the memory module 100B of the fifth embodiment, the interposer (passive element) made of a relatively expensive silicon substrate (wafer) can also be eliminated, making it possible to achieve cost reduction.

[0075] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the features of the above-described embodiments may be combined and applied.

[0076] 10, 10A Memory die 12 Memory element, first memory element 14 Input / output circuit, first input / output circuit (memory input / output circuit, first memory input / output circuit) 16 Via channel, first via channel 17 Via, first via 18 Bump, first bump 22 Second memory element 24 Second input / output circuit (second memory input / output circuit) 26 Second via channel 27 Second via 28 Second bump 30, 30A Base die 100, 100A, 100B Memory module 110, 110A, 110B Stacked memory die 112 Input / output terminal (memory input / output terminal) 120 Logic die 122 Input / output terminal (logic input / output terminal) 124 Input / output circuit (logic input / output circuit) 130 Interposer 132 Wiring 134 Pad electrode

Claims

1. A stacked memory die having a plurality of stacked memory dies; a logic die; and an interposer electrically connecting the stacked memory die and the logic die, wherein the stacked memory die and the logic die are juxtaposed on the interposer in a first direction along a main surface of the interposer, the logic die having: a logic input / output terminal disposed at an end of the stacked memory die side in the first direction and electrically connected to the interposer; and a logic input / output circuit disposed on the stacked memory die side in the first direction and connected to the logic input / output terminal; the stacked memory die having: a plurality of memory elements disposed on each of the plurality of memory dies; a memory input / output terminal disposed at an end of the logic die side in the first direction and electrically connected to the interposer; a plurality of memory input / output circuits disposed on the logic die side in the first direction in each of the plurality of memory dies and connected to each of the plurality of memory elements; and a via channel disposed at an end of the logic die side in the first direction and penetrating the plurality of memory dies and electrically connecting the plurality of memory input / output circuits to the memory input / output terminal. Memory modules.

2. The memory module according to claim 1, wherein said interposer includes wiring that connects said memory input / output terminals and said logic input / output terminals.

3. The memory module of claim 1, wherein in the first direction, a length of the interposer is shorter than a length from an end of the stacked memory die opposite the logic die to an end of the logic die opposite the stacked memory die.

4. A stacked memory die having a plurality of stacked memory dies and a base die; a logic die; and an interposer electrically connecting the stacked memory die and the logic die, wherein the stacked memory die and the logic die are juxtaposed on the interposer in a first direction along a main surface of the interposer, and the logic die has: a logic input / output terminal disposed at an end of the stacked memory die side in the first direction and electrically connected to the interposer; and a logic input / output circuit disposed on the stacked memory die side in the first direction and connected to the logic input / output terminal, wherein the stacked memory die comprises: a plurality of pairs of first memory elements and second memory elements, each pair of the plurality of pairs of first memory elements and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; a memory input / output terminal disposed on the logic die side of the base die in the first direction and electrically connected to the interposer, a first memory input / output circuit and a second memory input / output circuit arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; a first via channel arranged on an end of the base die on the logic die side in the first direction, passing through the multiple memory dies and the base die to electrically connect the multiple first memory elements to the first memory input / output circuit; and a second via channel arranged on an end opposite the logic die in the first direction, passing through the multiple memory dies and the base die to electrically connect the multiple second memory elements to the second memory input / output circuit.

5. A stacked memory die having a plurality of stacked memory dies and a base die; a logic die; and an interposer electrically connecting the stacked memory die and the logic die, wherein the stacked memory die and the logic die are juxtaposed on the interposer in a first direction along a main surface of the interposer, the logic die having: a logic input / output terminal disposed at an end of the stacked memory die side in the first direction and electrically connected to the interposer; and a logic input / output circuit disposed on the stacked memory die side in the first direction and connected to the logic input / output terminal, wherein the stacked memory die comprises: a plurality of pairs of first memory elements and second memory elements, each pair of the plurality of pairs of first memory elements and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; a memory input / output terminal disposed on the logic die side of the base die in the first direction and electrically connected to the interposer, a first memory input / output circuit and a second memory input / output circuit, the first memory input / output circuit being arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; a first via channel, the first via channel being arranged on an end of the logic die side in the first direction and penetrating the plurality of memory dies and the base die to electrically connect the plurality of first memory elements to the first memory input / output circuit; and a second via channel, the second via channel being arranged between each pair of the plurality of pairs of first memory elements and second memory elements in the first direction and penetrating the plurality of memory dies and the base die to electrically connect the plurality of second memory elements to the second memory input / output circuit.

6. The memory module according to claim 4 or 5, wherein said interposer includes wiring that connects said memory input / output terminals and said logic input / output terminals.

7. The memory module of claim 4 or 5, wherein in the first direction, the length of the interposer is shorter than the length from the end of the stacked memory die opposite the logic die to the end of the logic die opposite the stacked memory die.

8. The memory module of claim 4 or claim 5, wherein the first memory device communicates with the logic die through the first via channel and the base die, and the second memory device communicates with the logic die through the second via channel and the base die.

9. A stacked memory die having a plurality of stacked memory dies and a base die; and a logic die, wherein the base die is disposed across the plurality of memory dies and the logic die, and the plurality of memory dies and the logic die are juxtaposed on the base die in a first direction along a main surface of the base die, and the logic die has: a logic input / output terminal disposed at an end of the plurality of memory dies in the first direction and electrically connected to the base die; and a logic input / output circuit disposed on the plurality of memory dies in the first direction and connected to the logic input / output terminal, wherein the stacked memory die comprises: a plurality of pairs of first memory elements and second memory elements, each pair of the plurality of pairs of first memory elements and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; a memory input / output terminal disposed on the logic die side of the base die in the first direction and electrically connected to the logic input / output terminal, a memory input / output circuit arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; a first via channel arranged at an end of the logic die side in the first direction, passing through the memory dies to electrically connect the plurality of first memory elements to the memory input / output circuit; and a second via channel arranged between each pair of the plurality of pairs of first memory elements and second memory elements in the first direction, passing through the memory dies to electrically connect the plurality of second memory elements to the memory input / output circuit.

10. A stacked memory die having a plurality of stacked memory dies and a base die; and a logic die, wherein the base die is disposed across the plurality of memory dies and the logic die, and the plurality of memory dies and the logic die are juxtaposed on the base die in a first direction along a main surface of the base die, and the logic die has: a logic input / output terminal disposed at an end of the plurality of memory dies in the first direction and electrically connected to the base die; and a logic input / output circuit disposed on the plurality of memory dies in the first direction and connected to the logic input / output terminal, wherein the stacked memory die comprises: a plurality of pairs of first memory elements and second memory elements, each pair of the plurality of pairs of first memory elements and second memory elements being juxtaposed in the first direction in each of the plurality of memory dies; a memory input / output terminal disposed on the logic die side of the base die in the first direction and electrically connected to the logic input / output terminal, a memory input / output circuit arranged on the logic die side of the base die in the first direction and connected to the memory input / output terminals; and a via channel arranged between each pair of the plurality of pairs of first memory elements and second memory elements in the first direction, penetrating the plurality of memory dies to electrically connect the plurality of first memory elements and the plurality of second memory elements to the memory input / output circuit.

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