Control device for multi-level power conversion system and multi-level power conversion system

Abstract

This control device for a multi-level power conversion system is a control device in a multi-level power conversion system having a multi-level power converter and a control device and using a carrier level shift modulation method, said multi-level power converter having a plurality of semiconductor switching elements and a plurality of neutral point elements. The control device performs: a process for generating a modulation wave on the basis of a voltage command value of each phase; a process for generating a carrier wave that is a triangular wave signal having a predetermined carrier period; a process for generating an injection carrier that is a signal that varies in a predetermined amplitude range and has the same carrier period as and an opposite phase to the carrier wave; a process for generating a modulated wave by performing a carrier injection control for superimposing the modulation wave and the injection carrier; and a process for generating a gate signal for controlling the operations of the plurality of semiconductor switching elements and the plurality of neutral point elements in the multi-level power converter, on the basis of the result of comparing the modulated wave obtained by the carrier injection control with a plurality of carrier waves.

Description

Multilevel power conversion system control device and multilevel power conversion system

[0001] The present invention relates to a control device for a multilevel power conversion system and a multilevel power conversion system.

[0002] Conventionally, for example, a multilevel power converter has been known that includes a plurality of DC capacitors, two or more of which are connected in series on the DC side, and a plurality of semiconductor switching elements connected to a series connection point of the plurality of DC capacitors (see, for example, Patent Document 1). Note that, hereinafter, in this specification and drawings, the DC connection point of the plurality of DC capacitors is also referred to as a "DC neutral point," and the plurality of semiconductor switching elements connected to the DC connection point (DC neutral point) of the plurality of DC capacitors are also referred to as "neutral point elements."

[0003] Japanese Patent Application Publication No. 2003-319662

[0004] FIG. 31 is a diagram illustrating an example of the configuration of a multilevel power converter 130A according to one aspect. As a first example of the configuration of the multilevel power converter, FIG. 31 illustrates a configuration of a three-level NPP (Neutral Point Piloted) multilevel power converter 130A for three phases. As illustrated in FIG. 31 , in the multilevel power converter 130A, two DC capacitors Cp and Cn are connected in series via a DC neutral point C, and two semiconductor switching elements (neutral point elements) Q2 and Q3 are connected in anti-series to the DC neutral point C for each of the three phases. Note that in the example illustrated in FIG. 31 , the semiconductor switching elements (neutral point elements) Q2 and Q3 are connected in anti-series with a common collector side of an IGBT (Insulated Gate Bipolar Transistor). However, this is not limiting, and although not illustrated, the semiconductor switching elements (neutral point elements) Q2 and Q3 may also be connected in anti-series with a common emitter side.

[0005] Fig. 32 is a diagram showing an example of the configuration of a multilevel power converter 130B according to another aspect. Fig. 32 shows a configuration of a three-level NPC (Neutral Point Clamped) multilevel power converter 130B for three phases as configuration example 2 of the multilevel power converter. As shown in Fig. 32, in the multilevel power converter 130B, two DC capacitors Cp and Cn are connected in series via a DC neutral point C, and the neutral point potential of the DC neutral point C is clamped by diodes D5 and D6. With this configuration, the multilevel power converter 130B uses this DC neutral point C to generate voltages at multiple levels.

[0006] FIG. 33 is a diagram illustrating an example of the configuration of a multilevel power converter 130C according to another embodiment. FIG. 33C illustrates one phase of a five-level NPP multilevel power converter 130C as a third example of the multilevel power converter. As illustrated in FIG. 33 , in the multilevel power converter 130C, a total of four DC capacitors Cp, Cn are connected in series via three DC neutral points C, and two semiconductor switching elements (neutral point elements) Q2, Q3 are connected in anti-series to each DC neutral point C. In the example illustrated in FIG. 33 , the semiconductor switching elements (neutral point elements) Q2, Q3 are connected in anti-series with the collector side of the IGBT in common. However, this is not limiting, and although not illustrated, the semiconductor switching elements (neutral point elements) Q2, Q3 may also be connected in anti-series with the emitter side in common.

[0007] FIG. 34 is a diagram showing an example of the configuration of a multilevel power converter 130D according to another aspect. In the upper part of FIG. 34 , a three-phase configuration of a nine-level MMC (Modular Multilevel Converter) multilevel power converter 130D is shown as Configuration Example 4 of a multilevel power converter. As shown in the upper part of FIG. 34 , in the multilevel power converter 130D, multiple chopper cells Cell #1 to Cell #4 of the same element are connected to form arms. Note that the lower part of FIG. 34 shows an example of a half-bridge chopper cell and an example of a full-bridge chopper cell. In the MMC multilevel power converter 130D shown in the upper part of FIG. 34 , for example, either a half-bridge chopper cell or a full-bridge chopper cell shown in the lower part of FIG. 34 is arranged inside chopper cells Cell #1 to Cell #4.

[0008] Incidentally, conventionally, carrier level shift modulation, for example, is used in the multilevel power converters 130A to 130D shown in Figures 31 to 34. In the multilevel power converters 130A to 130D that use the carrier level shift modulation, harmonics that are integer multiples of the carrier frequency and sidebands that are harmonics generated due to the relationship between the carrier frequency and the fundamental wave frequency (modulation wave frequency) are generated in the output voltage of each phase.

[0009] For example, harmonic components in relatively high frequency bands are not a major problem because their energy can be easily attenuated using filters. On the other hand, attenuating harmonic components in relatively low frequency bands requires large filters, which can lead to increased equipment size and costs. For this reason, many power conversion systems are required to suppress harmonics near the carrier frequency, which are harmonic components in relatively low frequency bands.

[0010] Therefore, an object of the present disclosure is to suppress harmonics near the carrier frequency, which are harmonic components in a relatively low frequency band, more than ever before in a multilevel power converter that uses a carrier level shift modulation method.

[0011] A control device for a multilevel power conversion system according to one aspect is a control device for a multilevel power conversion system using a carrier level shift modulation method, the control device including a multilevel power converter having a plurality of semiconductor switching elements and a plurality of neutral point elements, and a control device, and is characterized by performing the following processes: generating a modulated wave based on a voltage command value for each phase; generating a carrier wave that is a triangular wave signal having a predetermined carrier period; generating an injected carrier that is a signal that changes within a predetermined amplitude range and has the same carrier period but an opposite phase to the carrier wave; generating a modulated wave that has undergone carrier injection control to superimpose the modulated wave and the injected carrier; and generating a gate signal that controls the operation of the plurality of semiconductor switching elements and the plurality of neutral point elements in the multilevel power converter based on a result of comparing the modulated wave that has undergone carrier injection control with the plurality of carrier waves.

[0012] a control device that performs the following processes: generating a modulated wave based on a voltage command value of each phase; generating a carrier wave that is a triangular wave signal having a predetermined carrier period; generating an injected carrier that is a signal that changes within a predetermined amplitude range and has the same carrier period as but is in opposite phase to the carrier wave; generating a modulated wave that has undergone carrier injection control to superimpose the modulated wave and the injected carrier; and generating a gate signal that controls operations of the semiconductor switching elements and the neutral point elements in the multilevel power converter based on a result of comparing the modulated wave that has undergone carrier injection control with the plurality of carrier waves.

[0013] According to the present disclosure, in a multilevel power converter using a carrier level shift modulation method, harmonics near the carrier frequency, which are harmonic components in a relatively low frequency band, can be suppressed more than ever before.

[0014] 1. A diagram showing an example of the configuration of a multilevel power conversion system according to an embodiment. It is a circuit diagram showing an example of the circuit configuration of a multilevel power converter in the multilevel power conversion system shown in FIG. 1. It is a diagram showing an example of the configuration of a control device in the multilevel power conversion system shown in FIG. 1. It is a diagram showing an example of the control configuration of a voltage command generating unit of the control unit shown in FIG. 3. It is a diagram showing an example of the control configuration of a gate signal generating unit of the control unit shown in FIG. 3. It is a diagram showing an example of the control configuration of a gate signal generating unit according to a comparative example. It is a diagram showing an example of carrier level shift modulation in the gate signal generating unit according to the comparative example shown in FIG. 6. It is a diagram showing an example of a switching pattern in carrier level shift modulation. It is a diagram showing an example of each gate signal of each semiconductor element in carrier level shift modulation of the switching pattern shown in FIG. 8. It is an image diagram of each phase output voltage harmonic spectrum of a power converter using carrier level shift modulation. It is a diagram showing an enlarged view near the zero crossing of FIG. 7 and an example of each gate signal of each semiconductor element at that time. It is a schematic diagram showing an example of the relationship between the modulated wave, the carrier wave, and each phase output voltage near the peak of the modulated wave shown in FIG. 7. It is a diagram showing an example of Fourier series expansion of the rectangular wave of the each phase output voltage shown in FIG. 12. It is a diagram showing an example of the relationship between the sign of the modulated wave and the slope of the modulated wave. 19 is a schematic diagram showing an example of the relationship between a modulated wave, a carrier wave, and each phase output voltage in pattern 1 shown in FIG. 14. FIG. 19 is a schematic diagram showing an example of the relationship between a modulated wave, a carrier wave, and each phase output voltage in pattern 2 shown in FIG. 14. FIG. 19 is a schematic diagram showing an example of the relationship between a modulated wave, a carrier wave, and each phase output voltage in pattern 3 shown in FIG. 14. FIG. 19 is a schematic diagram showing an example of the relationship between a modulated wave, a carrier wave, and each phase output voltage in pattern 4 shown in FIG. 14. FIG. 19 is an enlarged view of the vicinity of the zero crossing in FIG. 19 and an example of each gate signal of each semiconductor element at that time. FIG. 19 is a schematic diagram showing an example of the relationship between a modulated wave, a carrier wave, and each phase output voltage in a period when the slope of the modulated wave is negative. FIG. 19 is a schematic diagram showing an example of the relationship between a modulated wave, a carrier wave, and each phase output voltage in a period when the slope of the modulated wave is positive.26A and 26B are diagrams illustrating an example of a harmonic spectrum of a line-to-line output voltage normalized by a DC voltage when carrier injection control is not performed and when carrier injection control is performed. 27A and 27B are diagrams illustrating an example of a carrier wave and a modulated wave under a condition where the DC voltage is small relative to the AC output voltage. 27B are diagrams illustrating an enlarged view of the vicinity of the peak of the modulated wave in FIG. 24 and an example of a gate signal at that time. 27C are diagrams illustrating an example of a carrier wave and a modulated wave subjected to carrier injection control under a condition where the DC voltage is small relative to the AC output voltage. 27D are diagrams illustrating an enlarged view of the vicinity of the peak of the modulated wave in FIG. 26 and an example of a gate signal at that time. 27D are diagrams illustrating an example of charging and discharging the voltage of a DC capacitor in a circuit configuration for one phase of the three-level NPP system illustrated in FIG. 2. 27E are diagrams illustrating an example of a control configuration of a gate signal generating unit according to a modified example of an embodiment. 27F are conceptual diagrams illustrating an example of a hardware configuration of a processing circuit included in a control device in the embodiment and its modified examples illustrated in FIGS. 1 to 5 and 19 to 29. 27F are diagrams illustrating an example of a configuration of a multilevel power converter according to one aspect. 27F are diagrams illustrating an example of a configuration of a multilevel power converter according to another ...

[0015] Hereinafter, embodiments of a control device for a multilevel power conversion system and a multilevel power conversion system according to the present disclosure will be described with reference to the drawings.

[0016] <Configuration Example of One Embodiment> FIG. 1 is a diagram showing an example of the configuration of a multilevel power conversion system 20 according to one embodiment.

[0017] As shown in Fig. 1 , the multilevel power conversion system 20 is connected to a solar cell 11 via a DC cable 12 on the DC side on the left side in Fig. 1 . The multilevel power conversion system 20 is also connected to an AC power grid 15 via an AC cable 13 and a transformer 14 on the AC side on the right side in Fig. 1 . The multilevel power conversion system 20 converts, for example, DC power acquired from the solar cell 11 into AC power and outputs the converted AC power to the AC power grid 15 via the transformer 14. Hereinafter, in the present specification and drawings, the multilevel power conversion system 20 is also referred to as "power conversion system 20".

[0018] The solar cell (PV: Photovoltaics) 11 is also called a solar cell panel, and is connected to an input end (DC input / output unit 31 (see FIG. 2 )) on one end side of the power conversion system 20 via a DC cable 12. The solar cell 11 generates electricity using sunlight, and the generated DC power is supplied to the power conversion system 20 via the DC cable 12. The solar cell 11 is an example of a "DC power source or DC load," which may be, for example, a DC power source such as an "Energy Storage System (ESS)," or another DC load.

[0019] One end of the DC cable 12 is connected to the solar cell 11, and the other end is connected to a DC end (DC input / output unit 31 (see FIG. 2 )) of a multilevel power converter 30 (described later) in the power conversion system 20. The DC cable 12 has a positive cable and a negative cable, and supplies DC power from the solar cell 11 to the multilevel power converter 30 (described later).

[0020] One end of the AC cable 13 is connected to an AC end (AC input / output unit 32 (see FIG. 2 )) of a multilevel power converter 30 (described later) in the power conversion system 20, and the other end is connected to the AC power grid 15 via a transformer 14. The AC cable 13 is, for example, a three-phase, three-wire, three-phase AC circuit that supplies three-phase AC power, which is a combination of three systems of single-phase AC with mutually shifted phases of current or voltage, using three electric wires, cables, and conductors. The AC cable 13 supplies AC power converted by the multilevel power converter 30 (described later) to the AC power grid 15 side.

[0021] One end of the transformer 14 is connected to the output side, which is the other end of the power conversion system 20, via the AC cable 13, and the other end is connected to the AC power grid 15. The transformer 14 transforms the AC power output from the power conversion system 20 to a predetermined voltage level and outputs it to the AC power grid 15.

[0022] The AC power system (power system) 15 is connected to the transformer 14 and is a system that integrates power generation, power transformation, power transmission, and power distribution for supplying AC power transformed by the transformer 14 to power receiving equipment of consumers, and is connected to, for example, an unspecified load. Hereinafter, in the present specification and drawings, the AC power system 15 is also simply referred to as the "power system 15" or "system 15." Note that the power system 15 is an example of an "AC power source or AC load," which may be a power system or, for example, an electric motor, a generator, or other AC load.

[0023] The multilevel power conversion system (power conversion system) 20 is, for example, a power conversion system for photovoltaic power generation (solar cell). The power conversion system 20 converts DC power supplied from a solar cell 11 into AC power and outputs the converted AC power to a power grid 15 via a transformer 14. The power conversion system 20 is not limited to a system for photovoltaic power generation, and may be, for example, a power conversion system for a storage battery. Hereinafter, in the present specification and drawings, the power conversion system 20 is also referred to as a "PCS (Power Conditioning System) 20." A power conversion system for photovoltaic power generation is also referred to as a "PV-PCS (Photovoltaics-Power Conditioning System)." A power conversion system for a storage battery is also referred to as an "ESS-PCS (Energy Storage System-Power Conditioning System)."

[0024] The multilevel power conversion system (power conversion system) 20 includes a DC switch 21, an AC reactor 22, an AC capacitor 23, an AC switch 24, a DC voltage sensor 25, an AC current sensor 26, a multilevel power converter 30, and a control device 40. The DC switch 21 and the DC voltage sensor 25 are arranged on a DC cable 12 between a solar cell 11 and the multilevel power converter 30. The AC reactor 22, the AC capacitor 23, the AC switch 24, and the AC current sensor 26 are arranged on an AC cable 13 between the multilevel power converter 30 and a transformer 14. Hereinafter, in this specification and the drawings, the multilevel power converter 30 will also be referred to as an "n-level power converter 30," "power converter 30," or "inverter 30."

[0025] The multilevel power conversion system 20 may be a system that converts AC power into DC power. In this case, for example, in Fig. 1, the power grid 15 may be an AC power source that supplies AC power, and a DC load may be connected to the DC cable 12 instead of the solar cell 11.

[0026] The DC switch (DC circuit breaker) 21 is provided in series in the DC cable 12 between the solar cell 11 and the power converter 30. The DC switch 21 is, for example, an electrical contactor that can be opened or closed in response to an instruction from the control device 40. The DC switch 21 closes (connects) or opens (disconnects) the DC cable 12 between the solar cell 11 and the power converter 30 in accordance with an opening or closing instruction from, for example, the control device 40, a higher-level device (not shown), or an operator. Note that the DC switch 21 may be, for example, a DC circuit breaker that is normally manually opened or closed and automatically shuts off the DC cable 12 when an overcurrent such as a short-circuit current is detected. When the DC switch 21 is opened, the DC power supplied from the solar cell 11 is blocked from flowing into the power converter 30.

[0027] The AC reactor 22 is connected in series to the AC cables 13 of each phase at the output end (AC input / output unit 32 (see FIG. 2 )) of the power converter 30. The AC reactor 22 is a smoothing element that has the effect of reducing noise and suppressing surge voltage, for example. The AC reactor 22, together with an AC capacitor 23 connected in an L-shape, constitutes an LC filter circuit (filter circuit) that reduces ripples (vibrations) that occur when semiconductor switching elements (described below) of the power converter 30 switch on and off.

[0028] The AC capacitors 23 are connected in an L-shape to the AC cables 13 of each phase at the output end of the power converter 30 via branch points. The AC capacitors 23 are electronic components that store or release electricity (charges). For example, the AC capacitors 23, together with the AC reactors 22 connected in an L-shape, constitute an LC filter circuit (filter circuit) that reduces ripples (vibrations) that occur when semiconductor switching elements (described below) of the power converter 30 switch. The AC capacitors 23, together with the AC reactors 22, constitute a filter circuit, thereby suppressing the outflow of harmonics (harmonic currents) to the power grid 15.

[0029] The AC switch (AC circuit breaker) 24 is provided in series in the AC cable 13 of each phase between the AC reactor 22 (filter circuit) and the transformer 14. The AC switch 24 closes (connects) or opens (disconnects) the AC cable 13 between the power converter 30 and the power grid 15, for example, in accordance with an AC switch operation signal from the control device 40 or an open instruction or close instruction from a higher-level device (not shown) or an operator. When the AC switch 24 is opened, the AC power supplied from the power converter 30 is blocked from flowing out to the power grid 15.

[0030] The DC voltage sensor 25 is, for example, a known DC voltmeter or DC voltage sensor, and is disposed between the solar cell 11 and the power converter 30 to detect the DC voltage value Vdc. The position at which the DC voltage sensor 25 is disposed is not limited to the position shown in FIG. 1 , and may be any position at which the DC voltage value Vdc can be detected. Hereinafter, in the present specification and drawings, the DC voltage value Vdc is also referred to as the "DC voltage Vdc," "measured voltage Vdc," or simply "voltage Vdc." The DC voltage Vdc detected by the DC voltage sensor 25 is acquired by the control device 40.

[0031] The AC current sensor 26 is, for example, a known AC ammeter or AC current sensor, and is disposed between the power converter 30 and the transformer 14 to detect three-phase AC current values ​​Iu, Iv, and Iw. The location of the AC current sensor 26 is not limited to the location shown in FIG. 1 , and may be any location where the three-phase AC current values ​​Iu, Iv, and Iw can be detected. Hereinafter, in this specification and drawings, the AC current values ​​Iu, Iv, and Iw are also referred to as "AC currents Iu, Iv, and Iw," "current measurement values ​​Iu, Iv, and Iw," or simply "currents Iu, Iv, and Iw." The AC currents Iu, Iv, and Iw detected by the AC current sensor 26 are acquired by the control device 40.

[0032] One end of the multilevel power converter (power converter) 30, which is a DC end (DC input / output unit 31 (see FIG. 2 )), is connected to the DC switch 21 via the DC cable 12. The other end of the power converter 30, which is an AC end (AC input / output unit 32 (see FIG. 2 )), is connected to the AC reactor 22 (filter circuit) via the AC cable 13. The power converter 30 is configured with a plurality of semiconductor switching elements (switching elements) such as IGBTs. The power converter 30 is controlled by, for example, a pulse width modulation (PWM) signal, which is a gate drive signal (gate signal G) for the switching elements generated by the control device 40. That is, the power converter 30 is controlled by the gate signal G for operating the power converter 30.

[0033] The power converter 30 acquires DC power supplied from the solar cell 11 from one end serving as an input end, and converts the acquired DC power into AC power under control of a pulse width modulation signal (gate signal G), and outputs the AC power from the other end serving as an output end to be supplied to the AC cable 13. In other words, the power converter 30 is operated under control of the gate signal G. Note that the power converter 30 may also convert AC power into DC power. Details of the power converter 30 will be described later (see FIG. 2, etc.).

[0034] The control device 40 is provided, for example, inside or outside the power conversion system 20, and although some wiring and the like are omitted in the figure, it is electrically connected to each component of the power conversion system 20, including the power converter 30, via wired or wireless connections. The control device 40 may be realized as a function of an inverter control circuit (not shown). The control device 40 may also operate, for example, in accordance with instructions from a higher-level device (not shown) or instructions from an operator (not shown) via an operation unit (not shown). The higher-level device (not shown) may, for example, monitor and control multiple power conversion systems 20 in an integrated manner, and may be connected to each power conversion system 20 via wired or wireless connections.

[0035] Fig. 2 is a circuit diagram showing an example of a circuit configuration of the multilevel power converter 30 in the multilevel power conversion system 20 shown in Fig. 1. For the sake of simplicity, Fig. 3 shows a circuit configuration (circuit diagram) of one phase (e.g., U-phase) of a three-level NPP system as an example of the circuit configuration of the multilevel power converter 30.

[0036] In reality, the multilevel power converter 30 has a three-phase circuit configuration in which, for example, three circuits shown on the AC side in Fig. 2 are arranged and the DC sides are connected in parallel (see, for example, Fig. 31, etc.). However, in the present disclosure, the number of phases in the circuit configuration of the multilevel power converter 30 is not limited to three phases, and may be a single phase or multiple phases other than three phases.

[0037] In the following description, a three-level power converter 30 will be described as an example of the multilevel power converter 30. However, in the present disclosure, the multilevel power converter 30 is not limited to the three-level power converter 30, and may be an n-level power converter 30 other than the three-level power converter 30.

[0038] 2 , the power converter 30 has a DC input / output unit 31 and an AC input / output unit 32. The power converter 30 also has a positive terminal P, a negative terminal N, a DC capacitor Cp, a DC capacitor Cn, and a DC neutral point C. The power converter 30 also has semiconductor switching elements Q1 and Q4, semiconductor switching elements (neutral point elements) Q2 and Q3, an AC terminal AC, and a non-connection terminal NC. In this specification and the drawings, the AC terminal AC is also referred to as an "AC (Alternating Current) terminal," and the non-connection terminal NC is also referred to as an "NC (No Connection) terminal."

[0039] The DC input / output unit 31 is the DC end of the power converter 30, and has a positive terminal P and a negative terminal N connected to the solar cell 11 (DC power source or DC load).

[0040] The AC input / output unit 32 is an AC end of the power converter 30 and has an AC terminal AC to be connected to the power system 15 (AC power source or AC load).

[0041] The positive terminal P and the negative terminal N are connected to the positive (P pole) side and the negative (N pole) side of a solar cell (DC power source) 11 via a DC cable 12, respectively.

[0042] Between the positive electrode terminal P and the negative electrode terminal N, a DC capacitor Cp and a DC capacitor Cn are connected in series via a DC neutral point C. Furthermore, between the positive electrode terminal P and the negative electrode terminal N, a semiconductor switching element Q1 and a semiconductor switching element Q4 are connected in series with the same polarity via an AC terminal AC (AC terminal).

[0043] Between the DC neutral point C and the AC terminal AC, a semiconductor switching element (neutral point element) Q3 and a semiconductor switching element (neutral point element) Q2 are connected in series with opposite polarity via a non-connection terminal NC (NC terminal).

[0044] The semiconductor switching elements Q1 to Q4 have respective freewheeling diodes D1 to D4, which are connected in anti-parallel to the semiconductor switching elements Q1 to Q4. The semiconductor switching elements Q1 to Q4 are semiconductor switching elements formed, for example, by IGBTs or the like, and their on / off (conducting / non-conducting) operation is controlled by a gate signal G (see FIG. 1, etc.) output from the control device 40.

[0045] In the following description and drawings, the semiconductor switching elements Q1 and Q4 are also referred to as "semiconductor elements Q1 and Q4" or simply as "elements Q1 and Q4", respectively. The semiconductor switching elements Q2 and Q3 are also referred to as "neutral point elements Q2 and Q3", "semiconductor elements Q2 and Q3", or simply as "elements Q2 and Q3", respectively.

[0046] The freewheeling diodes D1 to D4 are connected in anti-parallel to the semiconductor switching elements Q1 to Q4, respectively, and are freewheeling diodes that freewheel energy when, for example, the IGBTs are turned off (non-conducting). Note that hereinafter in this specification and drawings, the freewheeling diodes D1 to D4 are also referred to as "anti-parallel diodes D1 to D4" or simply as "diodes D1 to D4," respectively.

[0047] FIG. 3 is a diagram showing an example of the configuration of the control device 40 in the multilevel power conversion system 20 shown in FIG.

[0048] The control device 40 acquires the DC voltage Vdc detected by the DC voltage sensor 25 and the AC currents Iu, Iv, and Iw detected by the AC current sensor 26, and outputs a gate signal G (see FIG. 1 , etc.) according to a control method described below. The control device 40 has an acquisition unit 41, an output unit 42, a storage unit 43, a system bus 45, and a control unit 50. The acquisition unit 41, the output unit 42, the storage unit 43, and the control unit 50 are connected to each other via the system bus 45.

[0049] The acquisition unit 41 is connected to the DC voltage sensor 25, the AC current sensor 26, and the system bus 45. The acquisition unit 41 may be connected to a higher-level device (not shown), etc. The acquisition unit 41 acquires, for example, the DC voltage Vdc detected by the DC voltage sensor 25 and the AC currents Iu, Iv, and Iw detected by the AC current sensor 26. The acquisition unit 41 outputs, for example, the acquired voltage values ​​and current values ​​to each component of the control device 40 via the system bus 45.

[0050] The output unit 42 is connected to the AC switch 24, the power converter 30, and the system bus 45. The output unit 42 may be connected to a higher-level device (not shown), etc. The output unit 42 outputs a gate signal G to the power converter 30 in accordance with, for example, an instruction received from the control unit 50 via the system bus 45.

[0051] The storage unit 43 is a volatile or non-volatile storage medium such as a hard disk drive (HDD), a solid state drive (SSD), or other semiconductor memory, and is connected to the system bus 45. The storage unit 43 stores, for example, programs necessary for the operation of each unit of the control device 40, and various pieces of information are written to and read from the storage unit 43 by each unit of the control device 40. The storage unit 43 also stores, for example, values ​​detected by each sensor such as the DC voltage sensor 25 and the AC current sensor 26, instructions given by a higher-level device (not shown) or an operator, various arithmetic expressions and coefficients used in calculations by the control unit 50, predetermined thresholds, judgment values, and the like.

[0052] The storage unit 43 is connected to each unit of the control device 40 via a system bus 45 or the like so as to enable input and output of various information. The storage unit 43 may be provided outside the control device 40 and connected to the control device 40 by wire or wirelessly. The storage unit 43 may be an external storage medium such as a memory card or a DVD (Digital Versatile Disc), or may be online storage. The storage unit 43 may also be a memory 92 (see FIG. 30 ) described below.

[0053] The system bus (bus) 45 is a data transmission path (bus) that connects each component within the control device 40, and interconnects the acquisition unit 41, output unit 42, memory unit 43, and control unit 50 so that various types of information can be input and output.

[0054] The control unit 50 includes a processor 91 (see FIG. 30 ), which will be described later, such as a CPU (Central Processing Unit) that operates by executing a program. The control unit 50 executes a predetermined program stored in the storage unit 43 or a memory 92 (see FIG. 30 ), which will be described later, to operate the processor 91 and comprehensively control the operation of the power conversion system 20. Note that the control unit 50 may control the operation of the power conversion system 20 in accordance with instructions received from a higher-level device (not shown) or instructions received from an operator (not shown) via an operation unit (not shown).

[0055] The control unit 50 functions as the following units by executing a predetermined program stored in the storage unit 43 or a memory 92 (see FIG. 30 ), which will be described later. The control unit 50 functions as, for example, an operation control unit 51, a voltage command generation unit 52, and a gate signal generation unit 53. Note that each of the above functions may be realized by a program executed by a processor 91 (see FIG. 30 ), which will be described later, in a processing circuit 90 (see FIG. 30 ), which is included in the control device 40, or may be realized by hardware 93 (see FIG. 30 ), which will be described later. Note that the operation control unit 51, the voltage command generation unit 52, and the gate signal generation unit 53 execute the predetermined program to perform the following processes.

[0056] The operation control unit 51 outputs an AC switch operation signal (see FIG. 1 etc.) to the AC switch 24 based on predetermined conditions, for example, and also controls the overall operation of each unit of the power conversion system 20.

[0057] The voltage command generating unit 52 generates three-phase voltage command values ​​Vu_ref, Vv_ref, and Vw_ref based on, for example, a predetermined output power command value P_ref and three-phase AC currents Iu, Iv, and Iw detected by the AC current sensor 26. Then, the voltage command generating unit 52 outputs the generated three-phase voltage command values ​​Vu_ref, Vv_ref, and Vw_ref to the gate signal generating unit 53. Note that details of the control configuration or processing (operation) of the voltage command generating unit 52 in the control unit 50 (control block) will be described later (see FIG. 4 , etc.).

[0058] The gate signal generation unit 53 acquires the voltage command values ​​Vu_ref, Vv_ref, and Vw_ref output from the voltage command generation unit 52 and the DC voltage Vdc detected by the DC voltage sensor 25. The gate signal generation unit 53 also acquires triangular wave carriers (carrier waves) CA1 and CA2 having a predetermined carrier period and an injection carrier CAin for predetermined carrier injection control. Note that in this specification and drawings, the injection carrier CAin is a triangular wave signal that is in opposite phase to the triangular wave carriers (carrier waves) CA1 and CA2, and the carrier injection control refers to control that superimposes (injects) the injection carrier CAin onto the modulation waves Du, Dv, and Dw.

[0059] The gate signal generating unit 53 generates a gate signal G (see FIG. 1, etc.) based on, for example, the voltage command values ​​Vu_ref, Vv_ref, and Vw_ref, the DC voltage Vdc, the triangular wave carriers CA1 and CA2, and a predetermined injection carrier CAin. The gate signal generating unit 53 outputs the generated gate signal G to the power converter 30 to control the on / off (conduction / non-conduction) operation of the semiconductor switching elements Q1 to Q4 (see FIG. 2, etc.). Details of the control configuration or processing (operation) of the gate signal generating unit 53 in the control unit 50 (control block) will be described later (see FIGS. 5, 19 to 22, etc.).

[0060] <Example of control configuration of one embodiment> Fig. 4 is a diagram showing an example of the control configuration in the voltage command generating unit 52 of the control unit 50 shown in Fig. 3. Fig. 4 shows examples of the control configuration for each of the three phases, U phase, V phase, and W phase, but in the following explanation, the control common to each phase will be explained using the control of the U phase as an example.

[0061] In step S11, the voltage command generating unit 52 acquires a predetermined output power command value P_ref and outputs a U-phase current command value Iu_ref based on the acquired output power command value P_ref. Note that the predetermined output power command value P_ref is acquired based on, for example, maximizing the amount of power generated by the solar cell 11, a predetermined calculation result based on a predetermined power supply or power demand, or the like, or is acquired from the storage unit 43, a higher-level device (not shown), or the like.

[0062] In step S12, the voltage command generation unit 52 acquires the U-phase current command value Iu_ref output in the processing of step S11. The voltage command generation unit 52 also acquires the U-phase AC current Iu (U-phase current measurement value Iu) detected by the AC current sensor 26 (see FIG. 1) via, for example, the acquisition unit 41 (see FIG. 3). The voltage command generation unit 52 then subtracts the acquired U-phase current measurement value Iu from the acquired U-phase current command value Iu_ref and outputs the subtracted value.

[0063] In step S13, the voltage command generating unit 52 performs proportional control based on the value output in the processing of step S12 and the proportional control gain Kp, and outputs the U-phase voltage command value Vu_ref obtained by the proportional control to the gate signal generating unit 53 (see Figures 3, 5, etc.).

[0064] In addition, in steps S11 to S13, the voltage command generating unit 52 calculates the V-phase voltage command value Vv_ref and the W-phase voltage command value Vw_ref, as with the U-phase, and outputs the calculated V-phase voltage command value Vv_ref and W-phase voltage command value Vw_ref to the gate signal generating unit 53.

[0065] The process performed by the voltage command generating unit 52 described with reference to FIG. 4 is similar to the process generally performed in the control of a normal power converter.

[0066] Fig. 5 is a diagram showing an example of a control configuration in the gate signal generating unit 53 of the control unit 50 shown in Fig. 3. Fig. 5 shows examples of control configurations for three phases, namely, the U phase, the V phase, and the W phase, but in the following explanation, the control common to each phase will be explained using the control of the U phase as an example.

[0067] In step S21, the gate signal generation unit 53 acquires the U-phase voltage command value Vu_ref(x) output from the voltage command generation unit 52 (see FIGS. 3 and 4 , etc.). The gate signal generation unit 53 also acquires a value (y) obtained by halving the DC voltage Vdc detected by the DC voltage sensor 25 after applying a low-pass filter to the DC voltage Vdc. The gate signal generation unit 53 divides the acquired value (x) by the acquired value (y) using a divider (x / y) to obtain a U-phase modulated wave Du, and outputs the obtained U-phase modulated wave Du. The modulated wave D is, for example, a voltage command value normalized by half the DC voltage. In this case, the modulated wave D is obtained by dividing the voltage command value V_ref by half the DC voltage Vdc after applying a low-pass filter to the DC voltage Vdc.

[0068] In step S22, the gate signal generation unit 53 acquires the U-phase modulated wave Du output in the processing of step S21 and the injection carrier CAin generated by the injection carrier generator 60. The gate signal generation unit 53 adds the acquired U-phase modulated wave Du and the acquired injection carrier CAin using an adder to perform carrier injection control in which the U-phase modulated wave Du is superimposed on the injection carrier CAin, thereby generating a U-phase modulated wave Duca that has undergone carrier injection control. The gate signal generation unit 53 outputs the generated U-phase modulated wave Duca that has undergone carrier injection control.

[0069] Here, the injection carrier generator 60 generates an injection carrier CAin, which is a triangular wave signal that changes between a and -a, in the same carrier period as the carrier generators 61 and 62 that generate the triangular wave carriers (carrier waves) CA1 and CA2. The injection carrier CAin is a triangular wave signal that is in opposite phase to the triangular wave carriers (carrier waves) CA1 and CA2. The injection carrier generator 60 is added to the gate signal generation unit 53, for example, by software. Note that "between a and -a" is an example of a "predetermined amplitude range."

[0070] The value of a may be a value determined by calculation, experiment, simulation, or the like based on, for example, power demand and power supply, or may be a value instructed by a higher-level device (not shown) or an operator. The value of a is at least a value between 0 and 1, for example, 0.2 to 0.3 (20 to 30% of the amplitude of the carrier waves CA1 and CA2). That is, the injection carrier CAin generated by the injection carrier generator 60 varies, for example, between 0.2 to 0.3 (a) and -0.2 to -0.3 (-a) (a predetermined amplitude range), and is a triangular wave signal with the same carrier period and opposite phase as the carrier waves CA1 and CA2.

[0071] The value of a may not be a fixed value but may be dynamically varied depending on the DC voltage status, modulation rate, etc. For example, when the DC voltage is low, increasing the value of a may increase the capacitor current, whereas when the DC voltage is high, increasing the value of a may decrease the capacitor current. Therefore, from the perspective of suppressing the capacitor current, the value of a may be decreased when the DC voltage is low and increased when the DC voltage is high. For example, the gate signal generating unit 53 may decrease the value of a when the DC voltage Vdc detected by the DC voltage sensor 25 is lower than a predetermined threshold, and increase the value of a when the DC voltage Vdc is higher than the predetermined threshold. In this way, by dynamically varying the value of a depending on, for example, the DC voltage status, modulation rate, etc., rather than using a fixed value, the capacitor current can be suppressed more appropriately than in the past.

[0072] In step S23a, the gate signal generation unit 53 uses a comparator to compare the U-phase modulated wave Duca, which has undergone carrier injection control and is output in the process of step S22, with the triangular wave carrier CA1 generated by the carrier generator 61. The gate signal generation unit 53 outputs a signal of 1 when the U-phase modulated wave Duca, which has undergone carrier injection control, is greater than the triangular wave carrier CA1, and outputs a signal of 0 when the U-phase modulated wave Duca is smaller than the triangular wave carrier CA1. The triangular wave carrier CA1 is a triangular wave signal that changes between 0 and 1 over a fixed carrier period, i.e., an upper carrier wave. Hereinafter, in this specification and drawings, the triangular wave carrier CA1 is also referred to as the "upper carrier wave CA1" or simply as the "carrier wave CA1."

[0073] In step S23b, the gate signal generation unit 53 uses a comparator to compare the U-phase modulated wave Duca, which has undergone carrier injection control and is output in the process of step S22, with the triangular wave carrier CA2 generated by the carrier generator 62. The gate signal generation unit 53 then outputs a signal of 1 when the U-phase modulated wave Duca, which has undergone carrier injection control, is greater than the triangular wave carrier CA2, and outputs a signal of 0 when the U-phase modulated wave Duca is smaller than the triangular wave carrier CA2. The triangular wave carrier CA2 is a triangular wave signal that changes between -1 and 0 over a fixed carrier period, i.e., a lower carrier wave. Hereinafter, in this specification and drawings, the triangular wave carrier CA2 is also referred to as the "lower carrier wave CA2" or simply as the "carrier wave CA2."

[0074] In step S24a, the gate signal generating unit 53 generates a signal by delaying the value of the signal output in the process of step S23a using a dead time generator, and outputs the signal as gate signal Gu1. Here, gate signal Gu1 is gate signal G1 that controls the switching operation of semiconductor switching element Q1 of the U phase (see FIG. 2, etc.). The dead time generator is used to prevent short circuits caused by simultaneous conduction of semiconductor switching elements Q1 to Q4, and outputs a signal by delaying the rise time of the pulse command value.

[0075] In step S24b, the gate signal generating unit 53 generates a signal by delaying the negative logic (NOT) value of the signal output in the processing of step S23a using a dead time generator, and outputs the signal as gate signal Gu3. That is, the gate signal generating unit 53 generates a signal by delaying the dead time generator to 1 when the signal output in step S23a is 0, and to 0 when the signal is 1, and outputs the signal as gate signal Gu3. Here, gate signal Gu3 is gate signal G3 that controls the switching operation of semiconductor switching element (neutral point element) Q3 of the U phase (see FIG. 2, etc.).

[0076] In step S24c, the gate signal generator 53 generates a signal by delaying the signal output in the process of step S23b using a dead time generator, and outputs the delayed signal as the gate signal Gu2. Here, the gate signal Gu2 is the gate signal G2 that controls the switching operation of the U-phase semiconductor switching element (neutral element) Q2 (see FIG. 2, etc.).

[0077] In step S24d, the gate signal generating unit 53 generates a signal by delaying the negative logic (NOT) value of the signal output in the processing of step S23b using a dead time generator, and outputs the generated signal as gate signal Gu4. That is, the gate signal generating unit 53 generates a signal by delaying the dead time generator to 1 when the signal output in step S23b is 0, and to 0 when the signal is 1, and outputs the generated signal as gate signal Gu4. Here, gate signal Gu4 is gate signal G4 that controls the switching operation of semiconductor switching element Q4 of the U phase (see FIG. 2, etc.).

[0078] The gate signal generating unit 53 performs the processes shown in steps S21 to S24d for the V-phase and W-phase in the same manner as for the U-phase. That is, the gate signal generating unit 53 generates and outputs gate signals Gv1 to Gv4 and Gw1 to Gw4 (G1 to G4) that control the operation of the V-phase and W-phase semiconductor switching elements Q1 to Q4 in the same manner as for the U-phase.

[0079] 1 to 5, the control configuration example of one embodiment includes control content different from that of a three-level (multilevel) power converter that uses a normal carrier level shift modulation method. That is, normally, the control is performed by comparing the modulation wave D, which is obtained by normalizing the voltage command value V_ref of each phase, with the triangular wave carriers CA1 and CA2, and then inputting the result into a dead time generator to generate and output gate signals G1 to G4.

[0080] On the other hand, in the embodiment shown in FIGS. 1 to 5 , the gate signal generation unit 53 acquires a modulated wave D obtained by normalizing the voltage command value V_ref for each phase and an injected carrier CAin generated by the injected carrier generator 60. The injected carrier CAin varies between a and −a (a predetermined amplitude range) and is a triangular wave signal having the same carrier period and opposite phase as the carrier waves CA1 and CA2. The gate signal generation unit 53 then performs carrier injection control to superimpose the modulated wave D on the injected carrier CAin, thereby generating a modulated wave Dca that has undergone carrier injection control. The gate signal generation unit 53 then compares the modulated wave Dca that has undergone carrier injection control with the triangular wave carriers CA1 and CA2, inputting the result into a dead time generator, and then generates and outputs gate signals G1 to G4.

[0081] That is, in one embodiment, the gate signal generating unit 53 has a characteristic configuration of an injection carrier generator 60 that generates an injection carrier CAin that is a triangular wave signal that changes between a and −a and has the same carrier cycle as but is in the opposite phase to the carrier waves CA1 and CA2. The gate signal generating unit 53 is characterized in that it generates and outputs gate signals G1 to G4 based on a modulated wave Dca that has been subjected to carrier injection control in which the modulated wave D is superimposed on the injection carrier CAin.

[0082] <Principle of Harmonic Generation> Here, before describing the processing (operation) and effects of the embodiment shown in Figures 1 to 5, the principle of harmonic generation will be described using a multilevel power conversion system 120 according to a comparative example in which a normal carrier level shift modulation method is used. Note that, similar to the embodiment shown in Figures 1 to 5, the comparative example below will be described using a three-level power conversion system 120 as an example of the multilevel power conversion system 120. Note that, hereinafter, in this specification and drawings, the multilevel power conversion system 120 and the three-level power conversion system 120 will also be simply referred to as the "power conversion system 120."

[0083] Fig. 6 is a diagram showing an example of a control configuration in the gate signal generating unit 153 according to the comparative example. Fig. 6 shows examples of control configurations for three phases, namely, U phase, V phase, and W phase, but in the following explanation, the control common to each phase will be explained using the control of the U phase as an example.

[0084] In the comparative example below, the gate signal generating unit 53 shown in Figures 3 and 5 in the power conversion system 20 according to the embodiment shown in Figures 1 to 5 is replaced with a gate signal generating unit 153. Other configurations in the power conversion system 120 according to the comparative example below are the same as or similar to the configurations in the power conversion system 20 according to the embodiment shown in Figures 1 to 5. Therefore, in the comparative example below, configurations that are the same as or similar to those in the power conversion system 20 according to the embodiment shown in Figures 1 to 5 are denoted by the same reference numerals, and detailed description and illustration thereof will be omitted.

[0085] In step S121, the same or similar processing as in step S21 shown in Fig. 5 is performed, and therefore description thereof will be omitted. Here, as shown in Fig. 6, the gate signal generation unit 153 according to the comparative example does not have the injection carrier generator 60, unlike the gate signal generation unit 53 according to the embodiment shown in Fig. 5. Therefore, the gate signal generation unit 153 according to the comparative example shown in Fig. 6 does not perform the processing of step S22 in the gate signal generation unit 53 according to the embodiment shown in Fig. 5.

[0086] In step S123a, the gate signal generation unit 153 uses a comparator to compare the U-phase modulated wave Du output in the processing of step S121 with the triangular wave carrier (upper carrier wave) CA1 generated by the carrier generator 61. Then, the gate signal generation unit 153 outputs a signal of 1 when the U-phase modulated wave Du is greater than the triangular wave carrier CA1, and outputs a signal of 0 when the U-phase modulated wave Du is smaller than the triangular wave carrier CA1.

[0087] In step S123b, the gate signal generation unit 153 uses a comparator to compare the U-phase modulated wave Du output in the processing of step S121 with the triangular wave carrier (lower carrier wave) CA2 generated by the carrier generator 62. Then, the gate signal generation unit 153 outputs a signal of 1 when the U-phase modulated wave Du is greater than the triangular wave carrier CA2, and outputs a signal of 0 when the U-phase modulated wave Du is smaller than the triangular wave carrier CA2.

[0088] In step S124a, the gate signal generating unit 153 generates a signal by delaying the value of the signal output in the process of step S123a using a dead time generator, and outputs the delayed signal as the gate signal Gu1.

[0089] In step S124b, the gate signal generating unit 153 generates a signal by delaying the negative logic (NOT) value of the signal output in the processing of step S123a using a dead time generator, and outputs the delayed signal as gate signal Gu3.

[0090] In step S124c, the gate signal generating unit 153 generates a signal by delaying the signal output in the process of step S123b using a dead time generator, and outputs the delayed signal as the gate signal Gu2.

[0091] In step S124d, the gate signal generating unit 153 generates a signal by delaying the negative logic (NOT) value of the signal output in the processing of step S123b using a dead time generator, and outputs the delayed signal as gate signal Gu4.

[0092] The gate signal generating unit 153 performs the processes shown in steps S121 to S124d for the V-phase and W-phase in the same manner as for the U-phase, and generates and outputs the gate signals Gv1 to Gv4 and Gw1 to Gw4.

[0093] 7 is a diagram showing an example of carrier level shift modulation in the gate signal generation unit 153 according to the comparative example shown in FIG. 6. In FIG. 7, the vertical axis represents voltage, and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave D, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2. In the following description, the circuit configuration of the power converter (inverter) 30 in which carrier level shift modulation is performed is assumed to be the three-level NPP circuit configuration shown in FIG. 2.

[0094] 7, the carrier level shift modulation method is a modulation method that generates gate signals G1 to G4 for each of the semiconductor elements Q1 to Q4 by comparing carrier waves CA1 and CA2, on which a DC offset has been superimposed, with a modulated wave D. That is, in carrier level shift modulation, a DC offset is evenly superimposed on each of the carrier waves CA1 and CA2, and the magnitudes of the carrier waves CA1 and CA2 and the modulated wave D are compared to generate a gate signal G according to a predetermined switching pattern, which will be described later (see FIG. 8).

[0095] Fig. 8 is a diagram showing an example of a switching pattern in carrier level shift modulation. In Fig. 8, Uu represents the voltage of the upper carrier wave CA1 shown in Fig. 7, Ul represents the voltage of the lower carrier wave CA2 shown in Fig. 7, and Um represents the voltage of the modulated wave D shown in Fig. 7. Also in Fig. 8, Q1 to Q4 represent the semiconductor elements Q1 to Q4 shown in Fig. 2, and ON / OFF represents the on / off of the gate signals G1 to G4 of the semiconductor elements Q1 to Q4.

[0096] 8, for example, when Um > Uu > Ul, semiconductor element Q1 is ON (conductive), semiconductor element Q2 is ON (conductive), semiconductor element Q3 is OFF (non-conductive), and semiconductor element Q4 is OFF (non-conductive). Similarly, for example, when Uu > Um > Ul, semiconductor element Q1 is OFF (non-conductive), semiconductor element Q2 is ON (conductive), semiconductor element Q3 is ON (conductive), and semiconductor element Q4 is OFF (non-conductive). Similarly, for example, when Uu > Ul > Um, semiconductor element Q1 is OFF (non-conductive), semiconductor element Q2 is OFF (non-conductive), semiconductor element Q3 is ON (conductive), and semiconductor element Q4 is ON (conductive).

[0097] Fig. 9 is a diagram showing an example of the gate signals G1 to G4 of the semiconductor elements Q1 to Q4 in the carrier level shift modulation of the switching pattern shown in Fig. 8. In Fig. 9, Fig. 9(a) shows an example of carrier level shift modulation in the three-level NPP system according to the comparative example shown in Fig. 7, and Figs. 9(b) to 9(e) show examples of the gate signals G1 to G4 of the semiconductor elements Q1 to Q4 corresponding to Fig. 9(a). In Fig. 9(b) to 9(e), when the pulse line is located at the top of each gate signal G1 to G4, it indicates that the gate signal G1 to G4 is ON (1), and when it is located at the bottom, it indicates that the gate signal G1 to G4 is OFF (0).

[0098] As shown in Fig. 9, the gate signals G1 to G4 of the semiconductor elements Q1 to Q4 are generated according to the predetermined switching pattern shown in Fig. 8. Note that ON (1) and OFF (0) of the gate signals G1 to G4 correspond to ON (conducting) and OFF (non-conducting) of the semiconductor elements Q1 to Q4.

[0099] 8 and 9, for example, gate signal G1 is ON (1) when Um>Uu>Ul, OFF (0) when Uu>Um>Ul, and OFF (0) when Uu>Ul>Um. Similarly, for example, gate signal G2 is ON (1) when Um>Uu>Ul, ON (1) when Uu>Um>Ul, and OFF (0) when Uu>Ul>Um. Similarly, for example, gate signal G3 is OFF (0) when Um>Uu>Ul, ON (1) when Uu>Um>Ul, and ON (1) when Uu>Ul>Um. Similarly, for example, gate signal G4 is OFF (0) when Um>Uu>Ul, OFF (0) when Uu>Um>Ul, and ON (1) when Uu>Ul>Um.

[0100] 10 is a conceptual diagram of the harmonic spectrum of the output voltage of each phase of a power converter 30 using carrier level shift modulation. In FIG. 10, the vertical axis represents the magnitude of the harmonic spectrum, and the horizontal axis represents frequency. Furthermore, fc represents the carrier frequency, and fo represents the fundamental frequency (modulation frequency).

[0101] As shown in Fig. 10, the output voltage of each phase includes harmonics that are integer multiples of the carrier frequency fc, and harmonics called sidebands that arise due to the relationship between the carrier frequency fc and the fundamental frequency fo. For example, in Fig. 10, harmonics that are integer multiples of the carrier frequency fc are, for example, 3fc. Note that 2fc is not shown in Fig. 10 because it has a plus-minus relationship and disappears when calculated (added). Also, in Fig. 10, harmonics called sidebands refer to frequency components that occur in the high and low ranges centered around the carrier frequency fc (or frequency components that are integer multiples of the carrier frequency fc), such as fc±2fo.

[0102] Here, a low-pass filter (filter) such as an LC filter is used as the filter of the power converter (inverter) 30 to suppress harmonic components of the output voltage. Harmonic components in a relatively high frequency band (e.g., the right side of FIG. 10 ) do not pose a major problem because their energy can be easily attenuated by the filter. On the other hand, harmonic components in a relatively low frequency band (e.g., the left side of FIG. 10 ) pose a problem because a large filter is required to attenuate them.

[0103] That is, for signals above the cutoff frequency, a low-pass filter can attenuate the energy of the signal as the frequency increases. Therefore, while it is easy for a low-pass filter to attenuate high-frequency components, it is difficult to attenuate low-frequency components. To attenuate low-frequency components, for example, in the case of an LC filter, the L and C can be increased, thereby physically increasing the size of the filter. However, this leads to an increase in the size and cost of the device. Therefore, there is a need to suppress harmonics near the carrier frequency fc, which are harmonic components in a relatively low frequency band.

[0104] 11A and 11B are enlarged views of the vicinity of the zero crossing in FIG. 7 and examples of the gate signals G1 to G4 of the semiconductor elements Q1 to Q4 at that time. FIG. 11A shows an enlarged view of the vicinity of the zero crossing in FIG. 7. FIG. 11B shows an example of the gate signals G1 and G4 of the semiconductor elements Q1 and Q4 corresponding to FIG. 11A. FIG. 11C shows an example of the gate signals G2 and G3 of the semiconductor elements Q2 and Q3 corresponding to FIG. 11A.

[0105] In Fig. 11(a), as in Fig. 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave D, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2. In Figs. 11(b) and (c), as in Figs. 9(b) to 9(e), the gate signals G1 to G4 of semiconductor elements Q1 to Q4 are generated according to the predetermined switching pattern shown in Fig. 8.

[0106] 11(a) to 11(c) show that in the comparative example in which carrier injection control is not performed, the number of switching events is small near the zero crossing. On the other hand, when the carrier injection control according to one embodiment is performed, due to the influence of the injected carriers CAin, a period occurs in which the semiconductor elements Q1 and Q4 are conductive instead of the semiconductor elements (neutral point elements) Q2 and Q3 near the zero crossing. As a result, when the carrier injection control according to one embodiment is performed, as described below, the number of switching events increases near the zero crossing, for example, by about two times (see FIG. 20, etc.).

[0107] Fig. 12 is a schematic diagram showing an example of the relationship between modulated wave D, carrier waves CA1 and CA2, and each phase output voltage near the peak of modulated wave D shown in Fig. 7. In Fig. 12, as in Fig. 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper row represents the waveform of modulated wave D, the dashed line in the upper row represents the waveform of upper carrier wave CA1, the solid line in the middle represents the waveform of lower carrier wave CA2, and the dashed line in the lower row represents the output voltage pulse of each phase.

[0108] 12, the slope of modulated wave D is nearly zero near the peak of modulated wave D in the upper part, and the center of the output voltage pulse of each phase in the lower part coincides with the trough of the carrier of carrier waves CA1 and CA2. In this case, the fundamental frequency fo of each phase voltage becomes the carrier frequency fc.

[0109] Fig. 13 is a diagram showing an example of a Fourier series expansion of the rectangular wave of each phase output voltage shown in Fig. 12. In Fig. 13, the vertical axis represents voltage, and the horizontal axis represents time. In Fig. 13, the rectangular waves drawn with solid lines represent the waveforms of each phase output voltage, and each sine wave represents a component resulting from Fourier series expansion of each phase output voltage. The largest sine wave drawn with a large dashed line represents a carrier frequency fc, the slightly smaller sine wave drawn with a solid line represents a frequency 3fc that is three times the carrier frequency, and the smallest sine wave drawn with a fine dashed line represents a frequency 5fc that is five times the carrier frequency.

[0110] As shown in Fig. 13, the output voltage of each phase is Fourier transformed (expanded into a Fourier series) to have frequency components that are integer multiples of the carrier frequency fc. The harmonics (3fc, 5fc, etc.) that are integer multiples of the carrier frequency fc described in Fig. 10 are generated by the principle shown in Fig. 13.

[0111] Here, the slope of modulated wave D is almost 0 (zero) near the peak of modulated wave D, but gradually changes significantly as it approaches the zero crossing. Therefore, next, the vicinity of the zero crossing of modulated wave D will be examined.

[0112] Fig. 14 is a diagram showing an example of the relationship between the sign of modulated wave D and the slope of modulated wave D. The center column of Fig. 14 shows whether the sign of modulated wave D is positive or negative, the right column of Fig. 14 shows whether the slope of modulated wave D is positive or negative, and the left column of Fig. 14 shows each pattern of these relationships.

[0113] As shown in Figure 14, pattern 1 is when the sign of modulated wave D is positive and the slope of modulated wave D is also positive. Similarly, pattern 2 is when the sign of modulated wave D is positive and the slope of modulated wave D is negative, pattern 3 is when the sign of modulated wave D is negative and the slope of modulated wave D is also negative, and pattern 4 is when the sign of modulated wave D is negative and the slope of modulated wave D is positive. When examining the vicinity of the zero crossing of modulated wave D, the sign and slope of modulated wave D are taken into consideration, and the four pattern sections shown in Figure 14 will be examined below.

[0114] Fig. 15 is a schematic diagram showing an example of the relationship between modulated wave D, carrier waves CA1 and CA2, and each phase output voltage in pattern 1 shown in Fig. 14. In Fig. 15, as in Fig. 12, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper row represents the waveform of modulated wave D, the dashed line in the upper row represents the waveform of upper carrier wave CA1, the solid line in the middle represents the waveform of lower carrier wave CA2, and the dashed line in the lower row represents each phase output voltage pulse. Note that Fig. 15 shows the case where modulated wave D crosses the upper carrier wave CA1, so the upper portion of the pulse represented by the dashed line in the lower row is a DC voltage, and the lower portion of the pulse is a 1 / 2 DC voltage.

[0115] As shown in Figure 15, in pattern 1, where modulated wave D has a positive sign and a positive slope, the center of the output voltage pulse for each phase shifts to the right. This causes a phase difference between the center of the output voltage pulse for each phase in the lower row and the carrier valleys of carrier waves CA1 and CA2. Furthermore, since the slope of a sine wave increases as it approaches the zero crossing, it is believed that the pulse closer to the zero crossing has a larger phase shift. Therefore, the period T of the output voltage for each phase becomes shorter than the carrier period.

[0116] 15, the period T from the center of the output voltage pulse to the center of the next output voltage pulse is shorter than the period from the broken line extending downward from the carrier trough to the broken line extending downward from the next carrier trough. In other words, in the section of pattern 1, the frequency of the output voltage of each phase is higher than the carrier frequency. This causes the generation of sidebands, which are high- and low-frequency components centered around the carrier frequency.

[0117] Fig. 16 is a schematic diagram showing an example of the relationship between modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase in pattern 2 shown in Fig. 14. In Fig. 16, the vertical axis, horizontal axis, and lines indicate the same things as in Fig. 15. Note that Fig. 16 shows the case where modulated wave D crosses the upper carrier wave CA1, so the upper part of the pulse of the dashed dotted line in the lower row is a DC voltage, and the lower part of the pulse is a 1 / 2 DC voltage.

[0118] As shown in Figure 16, in pattern 2, where modulated wave D has a positive sign and a negative slope, the center of the output voltage pulse for each phase shifts to the left. This causes a phase difference between the center of the output voltage pulse for each phase in the lower row and the carrier valleys of carrier waves CA1 and CA2. Furthermore, since the slope of a sine wave increases as it approaches the zero crossing, it is believed that the pulse closer to the zero crossing has a larger phase shift. Therefore, the period T of the output voltage for each phase becomes shorter than the carrier period.

[0119] 16, the period T from the center of the output voltage pulse to the center of the next output voltage pulse is shorter than the period from the broken line extending downward from the carrier trough to the broken line extending downward from the next carrier trough. In other words, in the section of pattern 2, the frequency of the output voltage of each phase is higher than the carrier frequency. This causes the generation of sidebands, which are high- and low-frequency components centered around the carrier frequency.

[0120] Fig. 17 is a schematic diagram showing an example of the relationship between modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase in pattern 3 shown in Fig. 14. In Fig. 17, the vertical axis, horizontal axis, and lines represent the same as those in Fig. 15. Note that Fig. 17 shows the case where modulated wave D crosses the lower carrier wave CA2, so the upper part of the pulse indicated by the dashed dotted line in the lower row is 1 / 2 DC voltage, and the lower part of the pulse is 0.

[0121] As shown in Figure 17, in pattern 3, where modulated wave D has a negative sign and a negative slope, the center of the output voltage pulse for each phase shifts to the left. This causes a phase difference between the center of the output voltage pulse for each phase in the lower row and the carrier valleys of carrier waves CA1 and CA2. Furthermore, since the slope of a sine wave increases as it approaches the zero crossing, it is believed that the pulse closer to the zero crossing has a larger phase shift. Therefore, the period T of the output voltage for each phase becomes longer than the period of the carrier.

[0122] 17, the period T from the center of the output voltage pulse to the center of the next output voltage pulse is longer than the period from the broken line extending downward from the carrier trough to the broken line extending downward from the next carrier trough. In other words, in the section of pattern 3, the frequency of the output voltage of each phase is lower than the carrier frequency. This causes sidebands, which are high- and low-frequency components centered around the carrier frequency.

[0123] Fig. 18 is a schematic diagram showing an example of the relationship between modulated wave D, carrier waves CA1 and CA2, and the output voltages of each phase in pattern 4 shown in Fig. 14. In Fig. 18, the vertical axis, horizontal axis, and lines indicate the same things as in Fig. 15. Note that Fig. 18 shows the case where modulated wave D crosses the lower carrier wave CA2, so the upper part of the pulse of the lower dashed dotted line is 1 / 2 DC voltage, and the lower part of the pulse is 0.

[0124] As shown in Figure 18, in pattern 4, where the sign of modulated wave D is negative and the slope of modulated wave D is positive, the center of the output voltage pulse of each phase shifts to the right. As a result, a phase difference occurs between the center of the output voltage pulse of each phase in the lower row and the carrier valleys of carrier waves CA1 and CA2. Furthermore, since the slope of a sine wave increases as it approaches the zero crossing, it is thought that the pulse closer to the zero crossing has a larger phase shift. Therefore, the period T of the output voltage of each phase becomes longer than the carrier period.

[0125] 18, the period T from the center of the output voltage pulse to the center of the next output voltage pulse is longer than the period from the broken line extending downward from the carrier trough to the broken line extending downward from the next carrier trough. In other words, in the section of pattern 4, the frequency of the output voltage of each phase is lower than the carrier frequency. This causes the generation of sidebands, which are high- and low-frequency components centered around the carrier frequency.

[0126] As described above, as shown in Fig. 14 to Fig. 18, in the section where the slope of the modulated wave D is large, the frequency of the output voltage of each phase deviates slightly from the carrier frequency fc. These frequency components slightly deviated from the carrier frequency fc become sideband components. In other words, when the output voltage of each phase, which has frequency components slightly deviated from the carrier frequency, is Fourier transformed (Fourier series expanded) as shown in Fig. 13, it is decomposed into frequency components slightly deviated from the harmonic components shown in Fig. 13. These frequency components slightly deviated from the harmonic components become sideband components.

[0127] Furthermore, sideband components with large spectra close to the carrier frequency fc occur near the zero crossing where the rate of change of the slope is small. That is, as explained for patterns 1 to 4 in Figures 15 to 18, the change in slope of modulated wave D causes the frequency of the output voltage of each phase to deviate from the carrier frequency fc, and this frequency deviation is the cause of the sideband waves.

[0128] Here, the magnitude of the frequency deviation becomes smaller as the rate of change of the slope of modulated wave D becomes smaller. Near the zero crossing of modulated wave D, the rate of change of the slope is small, so the frequency deviation of the output voltage of each phase becomes relatively small. Therefore, it is thought that sideband waves having a relatively low frequency band (frequency components relatively close to carrier frequency fc) in FIG. 10 occur near the zero crossing of modulated wave D. On the other hand, near the peak of modulated wave D, the rate of change of the slope is large, so the frequency deviation of the output voltage of each phase becomes relatively large. Therefore, it is thought that sideband waves having a relatively high frequency band (frequency components relatively far from carrier frequency fc) in FIG. 10 occur near the peak of modulated wave D.

[0129] As described with reference to FIG. 10 , harmonic components in a relatively high frequency band (e.g., the right side of FIG. 10 ) do not pose a major problem because their energy can be easily attenuated using a filter. On the other hand, harmonic components in a relatively low frequency band (e.g., the left side of FIG. 10 ) pose a problem because a large filter is required to attenuate them. In this regard, when the carrier injection control according to an embodiment is performed, the switching pattern changes near the zero crossing, allowing pinpoint measures to be taken near the zero crossing (see FIG. 20 , etc.). As a result, when the carrier injection control according to an embodiment is performed, it is possible to pinpoint and effectively suppress large sideband components in the spectrum near the carrier frequency fc, which is a relatively high frequency band (see FIG. 23 , etc.).

[0130] <Processing (Operation) of One Embodiment> Based on the principle of harmonic generation explained above using the comparative examples shown in FIGS. 6 to 18, processing (operation) of one embodiment shown in FIGS. 1 to 5 will now be described.

[0131] Fig. 19 is a diagram showing an example of the relationship between carrier waves CA1 and CA2 and modulated wave Dca when carrier injection control is performed in gate signal generating unit 53 according to the embodiment shown in Fig. 5. In Fig. 19, as in Fig. 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave Dca subjected to carrier injection control, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2.

[0132] As shown in FIG. 19, the carrier level shift modulation method when carrier injection control is performed is a modulation method in which the gate signals G1 to G4 of each semiconductor element Q1 to Q4 are generated by comparing carrier waves CA1 and CA2 with a modulated wave Dca obtained by carrier injection control. That is, in carrier level shift modulation with carrier injection control, as described in FIG. 5, the gate signal generation unit 53 superimposes a modulated wave D on the injected carrier CAin to obtain a modulated wave Dca obtained by carrier injection control. The gate signal generation unit 53 then compares the magnitude of the carrier waves CA1 and CA2 generated by the carrier generators 61 and 62 with the obtained modulated wave Dca, and generates gate signals G1 to G4 according to, for example, a predetermined switching pattern shown in FIG. 8. As described in FIG. 5, the injected carrier CAin varies between a and -a (within a predetermined amplitude range) and is a triangular wave signal that is opposite in phase to and has the same carrier period as the triangular wave carriers (carrier waves) CA1 and CA2.

[0133] 20A and 20B are enlarged views of the vicinity of the zero crossing in FIG. 19 and examples of the gate signals G1 to G4 of the semiconductor elements Q1 to Q4 at that time. FIG. 20A shows an enlarged view of the vicinity of the zero crossing in FIG. 19. FIG. 20B shows examples of the gate signals G1 and G4 of the semiconductor elements Q1 and Q4 corresponding to FIG. 20A. FIG. 20C shows examples of the gate signals G2 and G3 of the semiconductor elements Q2 and Q3 corresponding to FIG. 20A.

[0134] In Fig. 20(a), as in Fig. 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave Dca subjected to carrier injection control, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2. In Figs. 20(b) and (c), as in Figs. 11(b) and (c), the gate signals G1 to G4 of semiconductor elements Q1 to Q4 are generated according to, for example, the predetermined switching pattern shown in Fig. 8.

[0135] 20(a) to 20(c), when carrier injection control is performed, the number of switching events increases, for example, by about twice as much, near the zero crossing compared to when carrier injection control shown in FIGS. 11(a) to 11(c) is not performed. This is because when carrier injection control is performed, an interval occurs near the zero crossing where semiconductor elements Q1 and Q4 are conductive instead of semiconductor elements (neutral point elements) Q2 and Q3 due to the influence of injected carriers CAin.

[0136] Figure 21 is a schematic diagram showing an example of the relationship between the modulated wave Dca, carrier waves CA1 and CA2, and the output voltages of each phase during a period when the slope of the modulated wave Dca is negative. In Figure 21, as in Figures 15 to 18, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper row represents the waveform of the modulated wave Dca subjected to carrier injection control, the dashed line in the upper row represents the waveform of the upper carrier wave CA1, the solid line in the middle represents the waveform of the lower carrier wave CA2, and the dashed lines in the lower row represent the output voltage pulses of each phase. Note that Figure 21 shows a case in which the modulated wave Dca crosses both the upper carrier wave CA1 and the lower carrier wave CA2, so the top of the pulse represented by the dashed line in the lower row is DC voltage, the center of the pulse is 1 / 2 DC voltage, and the bottom of the pulse is 0.

[0137] As shown in Fig. 21, in the case of patterns 2 and 3 shown in Fig. 14, in which the slope of the modulated wave Dca is negative, the center of the peak of the output voltage pulse of each phase shifts to the left from the valley of the carrier. On the other hand, in this case, the center of the valley of the output voltage pulse of each phase shifts to the right from the peak of the carrier. Therefore, the output voltage frequency of each phase in section T1 is smaller than the carrier frequency fc. On the other hand, the frequency of the output voltage of each phase in section T2 is larger than the carrier frequency fc.

[0138] 21, when the slope of modulated wave Dca is negative, section T1 from the center of the peak of the left-hand output voltage pulse to the center of the valley of the next output voltage pulse is longer than the period from the dashed line extending downward from the valley of the left-hand carrier to the dashed line extending downward from the peak of the next carrier. In other words, as shown in FIG. 21, section T1 is longer than half the period of carrier waves CA1 and CA2, and therefore the frequency of the output voltage of each phase in section T1 is smaller than carrier frequency fc.

[0139] On the other hand, in this case, in Fig. 21, the section T2 from the center of the valley of the central output voltage pulse to the center of the peak of the next output voltage pulse is shorter than the period from the dashed line extending downward from the central carrier peak to the dashed line extending downward from the valley of the next carrier. In other words, as shown in Fig. 21, since the section T2 is shorter than half the period of the carrier waves CA1 and CA2, the frequency of the output voltage of each phase is greater than the carrier frequency fc in section T2.

[0140] Thus, in the case of patterns 2 and 3 shown in Figure 14, where the slope of the modulated wave Dca is negative, the output voltage of each phase has, within one cycle, a section T1 where the frequency is lower than the carrier frequency fc and a section T2 where the frequency is higher than the carrier frequency fc.

[0141] Figure 22 is a schematic diagram showing an example of the relationship between modulated wave Dca, carrier waves CA1 and CA2, and each phase output voltage during a period when the slope of modulated wave Dca is positive. In Figure 22, as in Figures 15 to 18, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the upper row represents the waveform of modulated wave Dca subjected to carrier injection control, the dashed line in the upper row represents the waveform of upper carrier wave CA1, the solid line in the middle represents the waveform of lower carrier wave CA2, and the dashed lines in the lower row represent each phase output voltage pulse. Note that Figure 22 shows a case in which modulated wave Dca crosses both upper carrier wave CA1 and lower carrier wave CA2, so the top of the pulse represented by the dashed line in the lower row is DC voltage, the center of the pulse is 1 / 2 DC voltage, and the bottom of the pulse is 0.

[0142] As shown in Fig. 22, in the case of patterns 1 and 4 shown in Fig. 14, in which the slope of the modulated wave Dca is positive, the center of the peak of the output voltage pulse of each phase shifts to the right from the valley of the carrier. On the other hand, in this case, the center of the valley of the output voltage pulse of each phase shifts to the left from the peak of the carrier. Therefore, the output voltage frequency of each phase in section T3 is higher than the carrier frequency fc. On the other hand, the frequency of the output voltage of each phase in section T4 is lower than the carrier frequency fc.

[0143] 22, when the slope of modulated wave Dca is positive, section T3 from the center of the peak of the left-hand output voltage pulse to the center of the valley of the next output voltage pulse is shorter than the period from the dashed line extending downward from the valley of the left-hand carrier to the dashed line extending downward from the peak of the next carrier. In other words, as shown in FIG. 22, section T3 is shorter than half the period of carrier waves CA1 and CA2, and therefore the frequency of the output voltage of each phase in section T3 is greater than carrier frequency fc.

[0144] On the other hand, in this case, in Fig. 22, the section T4 from the center of the valley of the central output voltage pulse to the center of the peak of the next output voltage pulse is longer than the period from the dashed line extending downward from the central carrier peak to the dashed line extending downward from the valley of the next carrier. In other words, as shown in Fig. 22, since the section T4 is longer than half the period of the carrier waves CA1 and CA2, the frequency of the output voltage of each phase in section T4 is smaller than the carrier frequency fc.

[0145] Thus, in the case of patterns 1 and 4 shown in Figure 14, where the slope of the modulated wave Dca is a positive period, the output voltage of each phase has, within one cycle, a section T3 where the frequency is higher than the carrier frequency fc and a section T4 where the frequency is lower than the carrier frequency fc.

[0146] As can be seen from Figures 21 and 22, there is a 180-degree phase difference between the output voltages of each phase when the slope of the modulated wave Dca is positive and the output voltages of each phase when the slope of the modulated wave Dca is negative. In this case, the sidebands generated when the slope of the modulated wave Dca is positive and the sidebands generated when the slope of the modulated wave Dca is negative cancel each other out. That is, for example, assuming that the period T of the Fourier series expansion is the fundamental frequency fo (e.g., 50 Hz or 60 Hz), high-frequency components with equal amplitudes and a 180-degree phase difference within the period T of the Fourier series expansion cancel each other out through integral calculation. Therefore, these components do not appear in the harmonic spectrum. Therefore, when carrier injection control is performed, the sideband components of the carrier frequency fc can be suppressed.

[0147] <Effects of an embodiment> Figure 23 is a diagram showing an example of a harmonic spectrum of a line output voltage normalized by a DC voltage when carrier injection control is not performed and when carrier injection control is performed. Figure 23(a) shows an example of a harmonic spectrum of a line output voltage normalized by a DC voltage in a power conversion system 120 in which carrier injection control is not performed according to the comparative example shown in Figures 6 to 18. Figure 23(b) shows an example of a harmonic spectrum of a line output voltage normalized by a DC voltage in a power conversion system 20 in which carrier injection control is performed according to an embodiment shown in Figures 1 to 5 and Figures 19 to 22.

[0148] 23(a) and 23(b), the vertical axis represents the magnitude of the harmonic spectrum, the horizontal axis represents frequency, fc represents the frequency component of the carrier frequency, and 2fc to 4fc represent frequency components that are integer multiples of the carrier frequency fc.

[0149] As shown in Figure 23(a), when carrier injection control is not performed, sideband components are spread in the high and low frequencies of each harmonic that is an integer multiple of the carrier frequency fc, and the sideband components are also spread in the relatively low frequency band near the carrier frequency fc. On the other hand, as shown in Figure 23(b), when carrier injection control is performed, sideband components are spread in the high and low frequencies of each harmonic that is an integer multiple of the carrier frequency fc, but the sideband components are not spread in the relatively low frequency band near the carrier frequency fc.

[0150] 23A and 23B, it can be seen that when carrier injection control is used, the sideband components near the carrier frequency fc are smaller and more suppressed than when carrier injection control is not used. As a result, it is thought that by performing the carrier injection control according to one embodiment, the harmonics of the output line voltage are reduced, and therefore the output harmonic current of the power converter (inverter) 30 is reduced.

[0151] 1 to 5 and 19 to 22, in a power converter 30 that uses carrier level shift modulation, harmonics near the carrier frequency fc, which are harmonic components in a relatively low frequency band, can be suppressed more than in the past. As a result, according to one embodiment, as described in FIGS. 23 and 24, the output harmonic current can be suppressed more than in the past.

[0152] Furthermore, according to the embodiment shown in FIGS. 1 to 5 and 19 to 22, it is possible to suppress an increase in the size and cost of the device. That is, as described in FIG. 10, conventionally, in order to attenuate harmonic components in a relatively low frequency band, the filter size had to be increased, resulting in an increase in the size and cost of the device. On the other hand, when carrier injection control according to one embodiment is performed, rather than attenuating harmonics occurring around the carrier frequency fc, which are harmonic components in a relatively low frequency band, the harmonics (occurrence) around the carrier frequency fc themselves can be suppressed more than conventionally. Furthermore, because this can be processed by software, costs can be reduced compared to adding hardware (compared to physically increasing the filter size). Therefore, according to one embodiment, because the processing can be performed by software, there is no need to physically increase the filter size, and it is possible to suppress an increase in the size and cost of the device more than conventionally.

[0153] 1 to 5 and 19 to 22, harmonics in the output voltage are reduced by carrier injection control. Therefore, according to one embodiment, when a filter capacitor is used on the AC side, the AC capacitor current flowing through the filter capacitor can be reduced more than in the past. As a result, the AC capacitor current is reduced, which makes it possible to reduce heat generation in the capacitor more than in the past and extend the life of the capacitor more than in the past.

[0154] Fig. 24 is a diagram showing an example of carrier waves CA1, CA2, and modulated wave D under the condition that the DC voltage is small relative to the AC output voltage. In Fig. 24, as in Fig. 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave D, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2.

[0155] Generally, the effective value of the output line voltage relative to the DC voltage is called the DC voltage utilization factor. The purpose of a power converter (inverter) 30 is to convert DC voltage into power to obtain a desired AC voltage. Therefore, a power converter (inverter) 30 with a high DC voltage utilization factor is required. Assume that the power converter (inverter) 30 is operated under the condition that the DC voltage is small relative to the AC output voltage. In this case, as shown in FIG. 24 , the maximum value of the modulating wave D becomes larger than the maximum values ​​of the carrier waves CA1 and CA2, resulting in overmodulation.

[0156] 25A and 25B are enlarged views of the vicinity of the peak of modulated wave D in Fig. 24 and an example of gate signal G1 at that time. Fig. 25A shows an enlarged view of the vicinity of the peak of modulated wave D in Fig. 24. Fig. 25B shows an example of gate signal G1 of semiconductor element Q1 corresponding to Fig. 25A.

[0157] In Fig. 25(a), as in Fig. 24, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave D, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2. In Fig. 25(b), gate signal G1 of semiconductor element Q1 is generated according to, for example, the predetermined switching pattern shown in Fig. 8.

[0158] For example, in the circuit shown in FIG. 2 , when semiconductor element Q1 or Q4 is conductive, the amplitude of the output voltage of power converter (inverter) 30 becomes a DC voltage, and the output voltage is the same as the DC voltage. On the other hand, when semiconductor element (neutral element) Q2 or Q3 is conductive, DC neutral point C is conductive, and the amplitude of the output voltage of power converter (inverter) 30 is half the DC voltage, resulting in a smaller output voltage than when semiconductor element Q1 or Q4 is conductive. Power converter (inverter) 30 essentially generates an AC output voltage by cutting out a DC voltage. Therefore, when semiconductor element Q1 or Q4 is conductive, the DC voltage itself is cut out, resulting in a large output. However, when semiconductor element (neutral element) Q2 or Q3 is conductive, DC neutral point C is conductive, resulting in a small output voltage. Therefore, the longer the conduction period of semiconductor element Q1 or Q4 within one fundamental wave cycle, the larger the AC output voltage. The larger the amplitude of the modulated wave D, the longer the conduction period of the semiconductor element Q1 or Q4.

[0159] Here, as shown in Figure 25(a), if the maximum value of modulated wave D becomes larger than the maximum value of carrier waves CA1 and CA2, resulting in overmodulation, as shown in Figure 25(b), a section will arise in which switching cannot be performed, and appropriate control will not be performed.

[0160] For example, when the AC voltage is higher than the DC voltage, the power converter (inverter) 30 must output this high AC voltage, so it is necessary to increase the conduction period of the semiconductor elements Q1 and Q4 as much as possible. However, for example, as shown in Figure 25(a), when the modulation wave D is higher than the carrier waves CA1 and CA2 (this is generally called overmodulation), the power converter (inverter) 30 has a section where switching is not possible, and therefore cannot output the desired AC voltage. Therefore, when the DC voltage is lower than the AC output voltage, the power converter (inverter) 30 cannot output the desired AC voltage in the section where switching is not possible, resulting in a poor DC voltage utilization rate.

[0161] 26 is a diagram showing an example of carrier waves CA1 and CA2 and a modulated wave Dca subjected to carrier injection control under conditions where the DC voltage is small relative to the AC output voltage. In FIG. 26, as in FIG. 7, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave Dca, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2.

[0162] 24 and 25, in Fig. 26, the maximum value of modulated wave Dca is greater than the maximum values ​​of carrier waves CA1 and CA2. However, carrier injection control is performed on modulated wave Dca, in which an injection carrier CAin having the same carrier period but opposite phase (i.e., a phase difference of 180 degrees) is injected into carrier waves CA1 and CA2.

[0163] Fig. 27 shows an enlarged view of the vicinity of the peak of modulated wave Dca in Fig. 26 and an example of gate signal G1 at that time. Fig. 27(a) shows an enlarged view of the vicinity of the peak of modulated wave Dca in Fig. 26. Fig. 27(b) shows an example of gate signal G1 of semiconductor element Q1 corresponding to Fig. 27(a).

[0164] In Fig. 27(a), as in Fig. 26, the vertical axis represents voltage and the horizontal axis represents time. The thick solid line in the center represents the waveform of modulated wave Dca, the upper dashed line represents the waveform of upper carrier wave CA1, and the lower solid line represents the waveform of lower carrier wave CA2. In Fig. 27(b), gate signal G1 of semiconductor element Q1 is generated according to, for example, the predetermined switching pattern shown in Fig. 8.

[0165] As explained in FIG. 25 , the longer the conduction period of semiconductor element Q1 or Q4 within one fundamental wave cycle, the larger the AC output voltage. Furthermore, the larger the amplitude of modulated wave Dca, the longer the conduction period of semiconductor element Q1 or Q4. In this regard, as shown in FIG. 27( a), carrier injection control is performed in which carrier CAin, which has a 180-degree phase difference with carriers CA1 and CA2, is injected into modulated wave Dca. This allows modulated wave Dca to have many intersections with carrier waves CA1 and CA2. In this case, as shown in FIG. 27( b), semiconductor element Q1 is switched by gate signal G1 even near the peaks of modulated wave Dca. As a result, when carrier injection control is performed, the interval during which switching is not possible is reduced, allowing power converter (inverter) 30 to output a desired AC voltage even when the DC voltage is small relative to the AC output voltage. Therefore, when carrier injection control is performed, the DC voltage utilization rate can be improved compared to conventional methods.

[0166] 1 to 5 and 19 to 22, the carrier injection control is used, and therefore a desired AC voltage can be output with a smaller DC voltage than when the carrier injection control is not used. As a result, the DC voltage utilization rate of the power converter (inverter) 30 can be improved compared to when the carrier injection control is not used.

[0167] Figure 28 shows an example of the charging and discharging of the voltages of DC capacitors Cp and Cn in the circuit configuration for one phase of the three-level NPP system shown in Figure 2. Figure 28(a) shows an example of the charging and discharging of the voltages of DC capacitors Cp and Cn when the current is positive in the circuit configuration for one phase of the three-level NPP system shown in Figure 2. Figure 28(b) shows an example of the charging and discharging of the voltages of DC capacitors Cp and Cn when the current is negative in the circuit configuration for one phase of the three-level NPP system shown in Figure 2.

[0168] Here, consider the switching pattern in which the semiconductor elements (neutral point elements) Q2 and Q3 are conductive in the case shown in Figure 28. For example, as shown in Figure 28(a), when the current is positive, the DC capacitor Cp is charged and the DC capacitor Cn is discharged. On the other hand, as shown in Figure 28(b), when the current is negative, the DC capacitor Cp is discharged and the DC capacitor Cn is charged. Therefore, in a power converter (inverter) 30 having a DC neutral point C, when the semiconductor elements (neutral point elements) Q2 and Q3 are conductive, pulsation occurs in the DC neutral point voltage.

[0169] That is, in a power converter (inverter) 30 having a DC neutral point C, as shown in FIGS. 28(a) and 28(b), each time the semiconductor elements (neutral elements) Q2 and Q3 conduct, the DC capacitors Cp and Cn are charged or discharged, causing pulsation in the DC capacitor voltage. This results in pulsation at the DC neutral point C according to the switching pattern. When carrier injection control is performed, the period during which the modulated wave Dca is greater than the upper carrier wave CA1 or less than the lower carrier wave CA2 increases, thereby increasing the conduction period of the semiconductor elements Q1 and Q4. In other words, the period during which the modulated wave Dca exists between the upper carrier wave CA1 and the lower carrier wave CA2 decreases, thereby reducing the conduction period of the semiconductor elements (neutral elements) Q2 and Q3. As a result, the number of patterns during which the semiconductor elements (neutral elements) Q2 and Q3, which cause pulsation, conduct is reduced, thereby reducing the pulsation of the capacitor voltage. Therefore, according to one embodiment, the conduction period of the semiconductor elements (neutral point elements) Q2 and Q3 is reduced near the zero crossing, so that pulsation of the DC neutral point voltage can be suppressed more than conventionally.

[0170] 1 to 5 and 19 to 22, carrier injection control is performed, so the flow rate through the semiconductor elements (neutral elements) Q2 and Q3 is reduced compared to when carrier injection control is not performed. As a result, according to the embodiment in which carrier injection control is performed, pulsation of the DC neutral point voltage can be suppressed more effectively than when carrier injection control is not performed.

[0171] 1 to 5 and 19 to 22, carrier injection control is performed, and therefore, as described above, the flow rate through the semiconductor elements (neutral elements) Q2 and Q3 is reduced compared to when carrier injection control is not performed. As a result, according to one embodiment, the conduction loss of the semiconductor elements (neutral elements) Q2 and Q3 is reduced, and heat generation from the semiconductor elements (neutral elements) Q2 and Q3 can be suppressed more than when carrier injection control is not performed.

[0172] 1 to 5 and 19 to 22, an example in which the injected carrier is a triangular wave has been described, but the invention is not limited to this, and the injected carrier may be a signal other than a triangular wave as long as it has the same cycle and opposite phase as the carrier waves CA1 and CA2. Even if the injected carrier is a wave other than a triangular wave, such as a sine wave or a rectangular wave, the same effects as those of the embodiment shown in FIGS. 1 to 5 and 19 to 22 can be achieved.

[0173] <Modification of an embodiment> Fig. 29 is a diagram showing an example of a control configuration in a gate signal generation unit 53A according to a modification of an embodiment. Fig. 29 shows control configuration examples for three phases, namely, U-phase, V-phase, and W-phase, but in the following description, as in Fig. 5, the control common to each phase will be described using the control of the U-phase as an example.

[0174] In the modification of the embodiment shown in FIG. 29 , the gate signal generating unit 53 shown in FIGS. 3 and 5 in the power conversion system 20 according to the embodiment shown in FIGS. 1 to 5 and 19 to 22 is replaced with a gate signal generating unit 53A. Although not shown, in the modification of the embodiment shown in FIG. 29 , the three-level power converter 30 in the power conversion system 20 according to the embodiment is replaced with an n-level power converter 30A. Other configurations in the power conversion system 20A according to the following modification of the embodiment are the same as or similar to the configurations in the power conversion system 20 according to the embodiment shown in FIGS. 1 to 5 and 19 to 22 . Therefore, in the modification of the embodiment shown below, the same reference numerals are used for configurations that are the same as or similar to those in the power conversion system 20 according to the embodiment shown in FIGS. 1 to 5 and 19 to 22 , and detailed description and illustration thereof will be omitted.

[0175] As described with reference to FIGS. 1 to 5 and 19 to 22 , the gate signal generation unit 53 according to one embodiment is the gate signal generation unit 53 in a three-level power converter (inverter) 30. On the other hand, the gate signal generation unit 53A according to a modified embodiment shown in FIG. 29 is the gate signal generation unit 53A in an n-level power converter (inverter) 30A. Therefore, the gate signal generation unit 53A according to the modified embodiment shown in FIG. 29 includes carrier generators 63, 64, ..., 6n-1 in addition to carrier generators 61 and 62. As a result, the gate signal generation unit 53A generates carrier waves CA3, CA4, ..., CAn-1 in addition to carrier waves CA1 and CA2. As a result, the gate signal generation unit 53A generates and outputs gate signals Gu1 to Gu4 as well as gate signals G corresponding to the n-level. In addition, the gate signal generating unit 53A generates and outputs gate signals G according to the n level in addition to gate signals Gv1 to Gv4 and Gw1 to Gw4 for the V and W phases, similar to the U phase.

[0176] As described above, the modified example of the embodiment shown in Fig. 29 achieves the same effects as those of the embodiment shown in Figs. 1 to 5 and 19 to 22. That is, in the embodiment shown in Figs. 1 to 5 and 19 to 22, the three-level power conversion system 20 has been described as an example of the multilevel power conversion system 20. In this respect, the n-level power conversion system 20A is also an example of the multilevel power conversion system 20. Therefore, the n-level power conversion system 20A according to the modified example of the embodiment shown in Fig. 29 also achieves the same effects as those of the three-level power conversion system 20 described in Figs. 23 to 28.

[0177] 29, an example in which the injected carrier is a triangular wave has been described, but the invention is not limited to this, and the injected carrier may be a signal other than a triangular wave as long as it has the same cycle and opposite phase as the carrier waves CA1, CA2, ..., CAn-1. Even if the injected carrier is a wave other than a triangular wave, such as a sine wave or a rectangular wave, the same effects as those of the modified embodiment shown in FIG.

[0178] <Hardware Configuration Example> Fig. 30 is a conceptual diagram showing an example of the hardware configuration of the processing circuitry 90 included in the control device 40 in the embodiment and its modified examples shown in Figs. 1 to 5 and 19 to 29. The functions described above are realized by the processing circuitry 90. In one aspect, the processing circuitry 90 includes at least one processor 91 and at least one memory 92. In another aspect, the processing circuitry 90 includes at least one dedicated hardware 93.

[0179] When the processing circuit 90 includes a processor 91 and a memory 92, each function is realized by software, firmware, or a combination of software and firmware. At least one of the software and firmware is written as a program. At least one of the software and firmware is stored in the memory 92. The processor 91 realizes each function by reading and executing the program stored in the memory 92.

[0180] When the processing circuitry 90 includes dedicated hardware 93, the processing circuitry 90 may be, for example, a single circuit, multiple circuits, a programmed processor, or a combination thereof. Each function is implemented by the processing circuitry 90.

[0181] Each function of the control device 40 may be partially or entirely configured by hardware, or may be configured as a program executed by a processor. That is, the control device 40 can be realized by a computer and a program, and the program can be stored in a storage medium or provided via a network.

[0182] 1 to 5 and 19 to 29, the NPP multilevel power converter 30 has been described as one aspect of the present disclosure, but the present disclosure is not limited thereto. The present disclosure may be applied to other types of multilevel power converters 30, such as an NPC multilevel power converter 30 or an MMC multilevel power converter 30.

[0183] 1 to 5 and 19 to 29, the power conversion system 20, 20A and the control device 40 (control unit 50) included therein have been described as examples of one aspect of the present disclosure, but the present disclosure is not limited to this. The present disclosure can also be realized as a control method in which processing steps are performed in each part of the control device 40 (control unit 50).

[0184] The present disclosure can also be realized as a control program that causes a computer to execute processing steps in each part of the control device 40 (control unit 50).

[0185] The present disclosure can also be realized as a storage medium (non-transitory computer-readable storage medium) on which a control program is stored. The control program can be stored and distributed on removable media such as a CD (Compact Disc), a DVD (Digital Versatile Disc), or a USB (Universal Serial Bus) memory. The control program may be uploaded to a network via a network interface (not shown) of the control device 40, or may be downloaded from the network and stored in the storage unit 43, the memory 92, or the like.

[0186] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized.

[0187] 11...solar cell; 12...DC cable; 13...AC cable; 14...transformer; 15...AC power system (power system, system); 20...multilevel power conversion system (three-level power conversion system, power conversion system); 20A...multilevel power conversion system (n-level power conversion system, power conversion system); 21...DC switch; 22...AC reactor; 23...AC capacitor; 24...AC switch; 25...DC voltage sensor; 26...AC current sensor; 30...multilevel power converter (three-level power converter, power converter, inverter); 30A...multilevel power converter Multilevel power converter (n-level power converter, power converter, inverter); 31... DC input / output unit; 32... AC input / output unit; 40... control device; 41... acquisition unit; 42... output unit; 43... memory unit; 45... system bus; 50... control unit; 51... operation control unit; 52... voltage command generation unit; 53, 53A... gate signal generation unit; 60... injection carrier generator; 61, 62, 63, 64... carrier generator; 90... processing circuit; 91... processor; 92... memory; 93... hardware; 120... multilevel power conversion system (three-level power conversion system, power conversion system); 130A to 130D... (3-level power converter, n-level power converter, power converter, inverter); 153... gate signal generating unit; AC... AC terminal; C... DC neutral point; CA1... triangular wave carrier (upper carrier wave, carrier wave); CA2... triangular wave carrier (lower carrier wave, carrier wave); CA3, CA4... triangular wave carrier (carrier wave); CAin... injected carrier; Cell #1 to Cell #4... chopper cells; Cn, Cp... DC capacitor; D... modulation wave; D1 to D4... freewheeling diode (anti-parallel diode, diode); D5, D6... diode Dca...modulated wave; Du, Dv, Dw...modulated wave; Duca, Dvca, Dwca...modulated wave; fc...carrier frequency; fo...fundamental wave frequency (fundamental frequency, modulated wave frequency); G...gate signal; G1 to G4...gate signal; Gu1 to Gu4, Gv1 to Gv4, Gw1 to Gw4...gate signal; Iu, Iv, Iw...AC current value (AC current, measured current value, current); I_ref, Iu_ref, Iv_ref, Iw_ref...current command value; Kp...proportional control gain; N...negative terminal; NC...non-connection terminal; P...positive terminal; P_ref...output power command value (power command value);Q1, Q4...semiconductor switching elements (semiconductor element, element); Q2, Q3...semiconductor switching elements (neutral point element, semiconductor element, element); T...period; T1 to T4...interval; V_ref, Vu_ref, Vv_ref, Vw_ref...voltage command values; Vdc...DC voltage value (DC voltage, voltage measurement value, voltage);

Claims

1. A control device in a multilevel power conversion system using a carrier level shift modulation method, comprising a multilevel power converter having a plurality of semiconductor switching elements and a plurality of neutral point elements, and a control device, the control device performing the following processes: generating a modulated wave based on a voltage command value for each phase; generating a carrier wave which is a triangular wave signal having a predetermined carrier period; generating an injected carrier which changes within a predetermined amplitude range and is a signal with the same carrier period and opposite phase as the carrier wave; generating a modulated wave for which carrier injection control has been performed that superimposes the modulated wave and the injected carrier; and generating a gate signal that controls the operation of the plurality of semiconductor switching elements and the plurality of neutral point elements in the multilevel power converter based on a result of comparing the modulated wave for which carrier injection control has been performed with the plurality of carrier waves.

2. A control device according to claim 1, characterized in that the range of the predetermined amplitude of the injected carrier is smaller than the amplitude of the carrier wave.

3. A control device according to claim 2, characterized in that the predetermined amplitude range of the injected carrier is between 20% and 30% of the amplitude of the carrier wave.

4. A control device according to claim 1, characterized in that the range of the predetermined amplitude of the injected carriers is dynamically changed according to the state of the DC voltage and the modulation rate.

5. A control device according to claim 4, characterized in that the range of the predetermined amplitude of the injected carriers is made smaller when the DC voltage is low and made larger when the DC voltage is high.

6. A control device according to claim 1, wherein the injected carrier changes within a predetermined amplitude range and is a triangular wave signal having the same carrier cycle as the carrier wave but in the opposite phase.

7. A multilevel power conversion system using a carrier level shift modulation method, comprising: a multilevel power converter having: a plurality of DC capacitors connected in series via a DC neutral point between a positive terminal connected to a DC power supply or a DC load and a negative terminal; a plurality of semiconductor switching elements connected between the positive terminal, the negative terminal, and an AC terminal connected to an AC power supply or an AC load; and a plurality of neutral point elements connected between the DC neutral point and the AC terminal; and a control device that performs the following processes: generating a modulated wave based on a voltage command value of each phase; generating a carrier wave that is a triangular wave signal having a predetermined carrier period; generating an injected carrier that changes within a predetermined amplitude range and is a signal of the opposite phase to the carrier wave and the same carrier period; generating a modulated wave that has been subjected to carrier injection control in which the modulated wave and the injected carrier are superimposed; and generating a gate signal that controls the operation of the plurality of semiconductor switching elements and the plurality of neutral point elements in the multilevel power converter based on a result of comparing the modulated wave that has been subjected to carrier injection control with the plurality of carrier waves. A multilevel power conversion system comprising:

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