Semiconductor device

Abstract

This semiconductor device comprises: a first chip mounted on a first die pad; a second chip mounted on a second die pad; an insulating chip mounted on the first die pad; a first bonding material for bonding the first die pad and the first chip; a second bonding material for bonding the second die pad and the second chip; and a third bonding material for bonding the first die pad and the insulating chip. The insulating chip includes: a third semiconductor substrate; a third insulating layer that is provided on the third semiconductor substrate; and a transformer that is disposed inside of the third insulating layer, and that includes a first coil and a second coil which are insulated from each other. The third semiconductor substrate is bonded to the first die pad by the third bonding material. The third bonding material is an insulating bonding material.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a module including a controller chip and a transformer chip arranged on a first die pad and a driver chip arranged on a second die pad. The transformer chip includes a substrate, an insulating layer stack structure formed on a main surface of the substrate, and an upper coil and a lower coil formed on different insulating layers in the insulating layer stack structure.

[0003] JP 2018-78169 A

[0004] [Summary] In the above-mentioned modules, there are cases where improvement in surge resistance is required.

[0005] A semiconductor device according to one aspect of the present disclosure includes a first die pad and a second die pad insulated from each other, a first chip mounted on the first die pad, a second chip mounted on the second die pad, an insulating chip mounted on the first die pad or the second die pad and connected between the first chip and the second chip, a first bonding material interposed between the first die pad and the first chip and bonding the first die pad to the first chip, and a bonding material interposed between the second die pad and the second chip and bonding the second die pad to the and a third bonding material interposed between the first die pad or the second die pad and the insulating chip and bonding the first die pad or the second die pad to the insulating chip, wherein the insulating chip includes a semiconductor substrate, an insulator provided on the semiconductor substrate, and an insulating element disposed within the insulator and including a first conductive layer and a second conductive layer insulated from each other, and the semiconductor substrate is bonded to the first die pad or the second die pad by the third bonding material, and the third bonding material is an insulating bonding material.

[0006] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view showing the internal structure of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 2. FIG. 4 is a perspective view of an insulating chip in the semiconductor device according to FIG. 2. FIG. 5 is a schematic plan view of the insulating chip according to FIG. 4. FIG. 6 is a schematic plan view of a first coil and an electrode structure in the internal structure of the insulating chip. FIG. 7 is a schematic plan view of a second coil and an electrode structure in the internal structure of the insulating chip. FIG. 8 is a schematic cross-sectional view of the insulating chip taken along line F8-F8 in FIG. 5. FIG. 9 is a graph showing the transition of the voltage of the first coil in a surge withstand voltage test of a semiconductor device according to a comparative example. FIG. 10 is a graph showing the transition of the voltage of the first coil in a surge withstand voltage test of the semiconductor device according to the first embodiment. FIG. 11 is a circuit diagram of a semiconductor device according to a second embodiment. FIG. 12 is a schematic plan view showing the internal structure of the semiconductor device according to the second embodiment. 13 is a schematic cross-sectional view of the semiconductor device taken along line F13-F13 in FIG. 12. FIG. 14 is a circuit diagram of a semiconductor device according to a third embodiment. FIG. 15 is a schematic cross-sectional view showing the internal structure of the semiconductor device according to the third embodiment. FIG. 16 is a schematic cross-sectional view of an insulating chip. FIG. 17 is a schematic cross-sectional view of a semiconductor device according to a modified example. FIG. 18 is a schematic cross-sectional view of a semiconductor device according to a modified example. FIG. 19 is a schematic cross-sectional view of a semiconductor device according to a modified example. FIG. 20 is a schematic plan view of an insulating chip in a semiconductor device according to a modified example. FIG. 21 is a schematic cross-sectional view of the insulating chip taken along line F21-F21 in FIG. 20. FIG. 22 is a schematic cross-sectional view of a semiconductor device according to a modified example. FIG. 23 is a schematic plan view showing the internal structure of a semiconductor device according to a modified example.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this specification, "the dimension (thickness) of A is equal to the dimension (thickness) of B" or "the dimension (thickness) of A and the dimension (thickness) of B are equal to each other" also includes a relationship in which the difference between the dimension (thickness) of A and the dimension (thickness) of B is, for example, within 10% of the dimension (thickness) of A.

[0011] First Embodiment [Schematic Configuration of Semiconductor Device] A schematic configuration of a semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 to 3. Figure 1 schematically shows the circuit configuration of the semiconductor device 10 according to the first embodiment. Figure 2 schematically shows an example of the internal planar structure of the semiconductor device 10. In Figure 2, a sealing resin 100 (described later) is indicated by a two-dot chain line to show the internal structure of the semiconductor device 10. Figure 3 schematically shows the cross-sectional structure of the semiconductor device 10 of Figure 2 taken along line F3-F3.

[0012] 1 shows a simplified circuit configuration of the semiconductor device 10, the number of external terminals of the semiconductor device 10 in Fig. 2 is greater than the number of external terminals of the semiconductor device 10 in Fig. 1. Here, the number of external terminals of the semiconductor device 10 refers to the number of external electrodes that can connect the semiconductor device 10 to electronic components external to the semiconductor device 10.

[0013] 1, the semiconductor device 10 includes a first circuit 20, a second circuit 30, and transformers 40A and 40B. The transformers 40A and 40B electrically insulate the first circuit 20 from the second circuit 30. Here, the transformers 40A and 40B are examples of "isolation elements."

[0014] The first circuit 20 is configured to operate using a first voltage V1. In one example, the first circuit 20 includes a transmitting circuit or a receiving circuit. In the first embodiment, the first circuit 20 includes a transmitting circuit 21. The transmitting circuit 21 includes at least one transistor. The second circuit 30 is configured to operate using a second voltage V2. In one example, the second circuit 30 includes a transmitting circuit or a receiving circuit. In the first embodiment, the second circuit 30 includes a receiving circuit 31. The receiving circuit 31 includes at least one transistor. The first voltage V1 and the second voltage V2 may be the same as or different from each other. In one example, the second voltage V2 is equal to the first voltage V1. The semiconductor device 10 may be referred to as a digital isolator. Therefore, the semiconductor device 10 can also be referred to as a signal transmission device that transmits a signal from the first circuit 20 to the second circuit 30. In the first embodiment, a ground GND1 of the first circuit 20 and a ground GND2 of the second circuit 30 are provided independently.

[0015] The transformers 40A and 40B are provided corresponding to two signals transmitted from the first circuit 20 to the second circuit 30. These signals are, for example, signals for driving switching elements, and examples thereof include a set signal (SET) and a reset signal (RESET). The set signal is a signal that transmits the rising edge of a control signal from a control circuit (not shown), and the reset signal is a signal that transmits the falling edge of a control signal from the control circuit. In one example, the transformer 40A is used to transmit the set signal, and the transformer 40B is used to transmit the reset signal.

[0016] The transformers 40A and 40B include a first coil 41 and a second coil 42. The first coil 41 and the second coil 42 are electrically insulated from each other and configured to be magnetically coupled. The first coil 41 is electrically connected to the transmitting circuit 21 of the first circuit 20. The second coil 42 is electrically connected to the receiving circuit 31 of the second circuit 30.

[0017] A first end of the first coil 41 of the transformers 40A, 40B is electrically connected to the first circuit 20. A second end of the first coil 41 of the transformers 40A, 40B is electrically connected to the ground GND1. A first end of the second coil 42 of the transformers 40A, 40B is electrically connected to the second circuit 30. A second end of the second coil 42 of the transformers 40A, 40B is electrically connected to the ground GND2.

[0018] The transmitting circuit 21 of the first circuit 20 receives an input signal and pulse-drives, for example, a transformer 40A. The pulse signal excited in the first coil 41 of the transformer 40A is transmitted through the second coil 42 of the transformer 40A and input to the receiving circuit 31 of the second circuit 30. The receiving circuit 31 outputs an output signal based on the input pulse signal. The transmitting circuit 21 may pulse-drive the transformer 40B.

[0019] 2, the semiconductor device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged together. The semiconductor device 10 includes a first chip 50, a second chip 60, and an insulating chip 70 as the semiconductor chips.

[0020] The package format of the semiconductor device 10 is an SO (Small Outline) type, and in the first embodiment is an SOP (Small Outline Package). The package format of the semiconductor device 10 can be changed as desired. The package format is not limited to an SOP, and may be a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), an SOJ (Small Outline J-leaded Package), or various similar package structures.

[0021] The semiconductor device 10 further includes a first lead frame 80, a second lead frame 90, and a sealing resin 100. The sealing resin 100 is configured to seal the first chip 50, the second chip 60, and the insulating chip 70, and also to partially seal the first lead frame 80 and the second lead frame 90. The sealing resin 100 is configured to seal a first die pad 81 (described later) of the first lead frame 80 and a second die pad 91 (described later) of the second lead frame 90. The sealing resin 100 is formed from an electrically insulating resin material. This resin material includes, for example, a black epoxy resin. The sealing resin 100 is formed in the shape of a rectangular plate with its thickness direction in the Z direction. The sealing resin 100 has four sealing side surfaces 101 to 104. More specifically, the sealing resin 100 has sealing side surfaces 101 and 102 as both end surfaces in the X direction and sealing side surfaces 103 and 104 as both end surfaces in the Y direction. The X direction and the Y direction are directions orthogonal to the Z direction. The X direction and the Y direction are orthogonal to each other when viewed from the Z direction. When viewed from the Z direction, the sealing resin 100 has a rectangular shape with the X direction as the long side direction and the Y direction as the short side direction. Here, the Y direction corresponds to the "first direction." In the following description, "planar view" means viewed from the Z direction. The shape of the sealing resin 100 when viewed from a plan can be changed as desired. In one example, the sealing resin 100 may have a rectangular shape with the Y direction as the long side direction and the X direction as the short side direction when viewed from a plan.

[0022] Each of the first lead frame 80 and the second lead frame 90 is a conductor and is formed of a material containing, for example, copper (Cu), iron (Fe), aluminum (Al), etc. Each of the lead frames 80, 90 is provided across the inside and outside of the sealing resin 100.

[0023] The first lead frame 80 has a first die pad 81 disposed within the sealing resin 100, and a plurality of first leads 82 disposed across the inside and outside of the sealing resin 100. Each of the first leads 82 constitutes an external terminal that electrically connects to an electronic device external to the semiconductor device 10. The plurality of first leads 82 includes a pair of first leads 82A connected to the first die pad 81. The pair of first leads 82A are integrated with the first die pad 81.

[0024] The first chip 50 is mounted on the first die pad 81. In plan view, the first die pad 81 is disposed so that the center in the Y direction is closer to the sealing side surface 103 than the center in the Y direction of the sealing resin 100. In the first embodiment, the first die pad 81 is not exposed from the sealing resin 100. In one example, the shape of the first die pad 81 in plan view is rectangular with the long side direction in the X direction and the short side direction in the Y direction.

[0025] The multiple first leads 82 are arranged spaced apart from one another in the X direction. Of the multiple first leads 82, the first leads 82 located at both ends in the X direction are integrated with the first die pad 81. The remaining first leads 82 are arranged spaced apart from the first die pad 81 in the Y direction. A portion of each first lead 82 protrudes from the sealing side surface 103 toward the outside of the sealing resin 100.

[0026] The second lead frame 90 has a second die pad 91 disposed within the sealing resin 100, and a plurality of second leads 92 disposed across the inside and outside of the sealing resin 100. Each second lead 92 constitutes an external terminal that electrically connects to an electronic device external to the semiconductor device 10. The plurality of second leads 92 includes a pair of second leads 92A connected to the second die pad 91. The pair of second leads 92A are integrated with the second die pad 91.

[0027] The second chip 60 is mounted on the second die pad 91. In plan view, the second die pad 91 is disposed closer to the encapsulation side surface 104 in the Y direction than the first die pad 81. That is, the first die pad 81 and the second die pad 91 are arranged at a distance from each other in the Y direction. Therefore, the Y direction can also be said to be the arrangement direction of the two die pads 81, 91. The first chip 50 and the second die pad 60 are arranged at a distance from each other in the Y direction. The first die pad 81 and the second die pad 91 are insulated from each other. In the first embodiment, the second die pad 91 is not exposed from the encapsulation resin 100. In one example, the shape of the second die pad 91 in plan view is rectangular with the long side direction in the X direction and the short side direction in the Y direction.

[0028] The multiple second leads 92 are arranged spaced apart from one another in the X direction. Of the multiple second leads 92, the second leads 92 adjacent to the second leads 92 at both ends in the X direction are integrated with the second die pad 91. The remaining second leads 92 are arranged spaced apart from the second die pad 91 in the X direction or the Y direction. A portion of each second lead 92 protrudes from the sealing side surface 104 toward the outside of the sealing resin 100.

[0029] In the first embodiment, the number of second leads 92 is the same as the number of first leads 82. As can be seen from FIG. 2 , the multiple first leads 82 and the multiple second leads 92 are arranged in a direction (X direction) perpendicular to the arrangement direction (Y direction) of the first die pads 81 and the second die pads 91 in a plan view. Note that the number of second leads 92 and the number of first leads 82 can each be changed arbitrarily. In one example, the number of first leads 82 and the number of second leads 92 may be different from each other.

[0030] In the first embodiment, the first die pad 81 is supported by a pair of first leads 82 that are integrated with the first die pad 81. The second die pad 91 is supported by a pair of second leads 92 that are integrated with the second die pad 91. Therefore, each die pad 81, 91 does not have a suspension lead that is exposed from the sealing side surfaces 101, 102. This allows a large insulation distance (creepage distance) to be secured between the first lead frame 80 and the second lead frame 90.

[0031] The first chip 50 mounted on the first die pad 81 is a semiconductor chip including the first circuit 20 of FIG. 1. The first chip 50 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the first chip 50 is mounted on the first die pad 81 so that the long sides are aligned in the X direction and the short sides are aligned in the Y direction.

[0032] 3, the first chip 50 includes a first semiconductor substrate 51, a first insulating layer 52, and a plurality of electrode pads 53. The first semiconductor substrate 51 is made of a material containing, for example, silicon (Si). In one example, the first semiconductor substrate 51 is a Si substrate. The first insulating layer 52 is formed on the first semiconductor substrate 51. The first insulating layer 52 is made of, for example, a silicon oxide film (SiO ２ The first insulating layer 52 includes at least one of a silicon nitride film (SiN) and a silicon nitride film (SiN). The first insulating layer 52 is provided with connection wiring that electrically connects the first semiconductor substrate 51 and a plurality of electrode pads 53. The plurality of electrode pads 53 are provided on the first insulating layer 52.

[0033] The first chip 50 is bonded to the first die pad 81 by a first bonding material 111. The first bonding material 111 is interposed between the first die pad 81 and the first chip 50. The first bonding material 111 bonds the first semiconductor substrate 51 to the first die pad 81. In the first embodiment, a conductive bonding material is used as the first bonding material 111. Examples of the conductive bonding material that can be used include solder paste and silver (Ag) paste.

[0034] 2, the second chip 60 mounted on the second die pad 91 is a semiconductor chip including the second circuit 30 of FIG. 1. The second chip 60 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the second chip 60 is mounted on the second die pad 91 so that the long sides extend along the X direction and the short sides extend along the Y direction.

[0035] As shown in FIG. 3 , the second chip 60 includes a second semiconductor substrate 61, a second insulating layer 62, and a plurality of electrode pads 63. The second semiconductor substrate 61 is made of, for example, a material containing Si. In one example, the second semiconductor substrate 61 is a Si substrate. The second insulating layer 62 is formed on the second semiconductor substrate 61. The second insulating layer 62 includes, for example, at least one of a silicon oxide film and a silicon nitride film. The second insulating layer 62 is provided with connection wiring that electrically connects the second semiconductor substrate 61 and the plurality of electrode pads 63. The plurality of electrode pads 63 are provided on the second insulating layer 62.

[0036] The second chip 60 is bonded to the second die pad 91 by a second bonding material 112. The second bonding material 112 is interposed between the second die pad 91 and the second chip 60. The second bonding material 112 bonds the second semiconductor substrate 61 to the second die pad 91. In the first embodiment, a conductive bonding material is used for the second bonding material 112. Examples of the conductive bonding material that can be used include solder paste and Ag paste.

[0037] 2 , in the first embodiment, the insulating chip 70 is mounted on the first die pad 81. The insulating chip 70 is disposed closer to the second chip 60 than the first chip 50 on the first die pad 81. In other words, the insulating chip 70 is disposed between the first chip 50 and the second chip 60 in the Y direction. The distance between the second chip 60 and the insulating chip 70 in the Y direction is greater than the distance between the first chip 50 and the insulating chip 70 in the Y direction. The insulating chip 70 is connected between the first chip 50 and the second chip 60.

[0038] The insulating chip 70 is a semiconductor chip including the transformers 40A and 40B. The insulating chip 70 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the insulating chip 70 is mounted on the first die pad 81 so that the long sides are aligned in the X direction and the short sides are aligned in the Y direction.

[0039] As shown in FIG. 3 , the insulating chip 70 includes a third semiconductor substrate 71, a third insulating layer 72, and a plurality of electrode pads 73 and 74. The third insulating layer 72 is an example of an "insulator." The third semiconductor substrate 71 is made of a material containing Si, for example. In one example, the third semiconductor substrate 71 is a Si substrate. The third insulating layer 72 is provided on the third semiconductor substrate 71. The first coil 41 and the second coil 42 of the transformers 40A and 40B in FIG. 1 are provided on the third insulating layer 72. The plurality of electrode pads 73 and 74 are provided on the third insulating layer 72.

[0040] The insulating chip 70 is bonded to the first die pad 81 by a third bonding material 113. The third bonding material 113 is interposed between the first die pad 81 and the insulating chip 70. The third bonding material 113 bonds the third semiconductor substrate 71 to the first die pad 81. An insulating bonding material is used as the third bonding material 113. For example, an insulating material containing epoxy resin is used as the insulating bonding material.

[0041] In the first embodiment, the thickness relationships among the first chip 50, the second chip 60, and the insulating chip 70 are as follows: That is, the thickness TA3 of the third semiconductor substrate 71 is equal to the thickness TA1 of the first semiconductor substrate 51. The thickness TA3 of the third semiconductor substrate 71 is equal to the thickness TA2 of the second semiconductor substrate 61. The thickness TB3 of the third insulating layer 72 is equal to the thickness TB1 of the first insulating layer 52. The thickness TB3 of the third insulating layer 72 is equal to the thickness TB2 of the second insulating layer 62. The thickness TC3 of the third bonding material 113 is equal to the thickness TC1 of the first bonding material 111. The thickness TC3 of the third bonding material 113 is equal to the thickness TC2 of the second bonding material 112.

[0042] In this way, in the first embodiment, the heights of the first chip 50, the second chip 60, and the insulating chip 70 are all equal to one another. Therefore, the positions in the Z direction of the multiple electrode pads 53 of the first chip 50, the multiple electrode pads 63 of the second chip 60, and the multiple electrode pads 73 and 74 of the insulating chip 70 are all the same.

[0043] 2 and 3, a plurality of wires W1 to W4 are connected to each of the first chip 50, the insulating chip 70, and the second chip 60. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor containing, for example, gold (Au), Al, Cu, or the like.

[0044] 2, the first chip 50 is electrically connected to the first lead frame 80 by wires W1. More specifically, the electrode pads 53 of the first chip 50 are individually connected to the first leads 82 by the wires W1. Some of the wires W1 are individually connected to a pair of first leads 82 integrated with the first die pad 81. In the first embodiment, the pair of first leads 82A integrated with the first die pad 81 constitutes ground terminals. Therefore, the first die pad 81 has the same potential as the ground GND1 of the first circuit 20 (see FIG. 1).

[0045] The second chip 60 is electrically connected to the second lead frame 90 by wires W4. More specifically, the electrode pads 63 of the second chip 60 are individually connected to the second leads 92 by the wires W4. Some of the wires W4 are individually connected to a pair of second leads 92A integrated with the second die pad 91. In the first embodiment, the pair of second leads 92A integrated with the second die pad 91 constitute ground terminals. Therefore, the second die pad 91 has the same potential as the ground GND2 of the second circuit 30 (see FIG. 1 ).

[0046] The insulating chip 70 is electrically connected to the first chip 50 by wires W2. The insulating chip 70 is electrically connected to the second chip 60 by wires W3. More specifically, the plurality of electrode pads 73 of the insulating chip 70 and the plurality of electrode pads 53 of the first chip 50 are individually connected by the plurality of wires W2. The plurality of electrode pads 74 of the insulating chip 70 and the plurality of electrode pads 63 of the second chip 60 are individually connected by the plurality of wires W3.

[0047] Both of the first coils 41 of the transformers 40A and 40B are electrically connected to the ground GND1 of the first circuit 20 via the wire W2, the first chip 50, etc. Both of the second coils 42 of the transformers 40A and 40B are electrically connected to the ground GND2 of the second circuit 30 via the wire W3, the second chip 60, etc.

[0048] 3 may be made of a wide bandgap semiconductor or a compound semiconductor instead of a Si substrate. A wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO). ２ O ３ The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of aluminum nitride (AlN), indium nitride (InN), GaN, and gallium arsenide (GaAs).

[0049] 4 to 8, an example of the configuration of the insulating chip 70 will be described. In the following description, the direction from the third semiconductor substrate 71 toward the third insulating layer 72 of the insulating chip 70 shown in Fig. 8 will be referred to as "upward," and the direction from the third insulating layer 72 toward the third semiconductor substrate 71 will be referred to as "downward."

[0050] 4 and 5 show the external appearance of the insulating chip 70. FIG. 4 shows a perspective view of the insulating chip 70, and FIG. 5 shows a plan view of the insulating chip 70. For ease of explanation, FIG. 5 shows a passivation film 78 (described later) with a two-dot chain line, and transformers 40A and 40B and floating dummy wiring 48 (described later) with dashed lines. Also, separation grooves 79A, first resin openings 79B, and second resin openings 79C (described later) in a resin layer 79 (all see FIG. 4) are omitted. FIG. 6 shows a cross-sectional structure of the insulating chip 70 taken along the XY plane at a position in the Z direction of the first coil 41. FIG. 6 illustrates the connections of the first coil 41. FIG. 7 shows a cross-sectional structure of the insulating chip 70 taken along the XY plane at a position in the Z direction of the second coil 42. FIG. 7 illustrates the connections of the second coil 42. FIG. 8 shows a cross-sectional structure of the insulating chip 70, the third bonding material 113, and the first die pad 81 taken along line F8-F8 in FIG.

[0051] As shown in FIG. 4 , the insulating chip 70 includes a chip top surface 70S and a chip bottom surface 70R facing opposite directions in the Z direction, and first to fourth chip side surfaces 70A to 70D connecting the chip top surface 70S and the chip bottom surface 70R. The chip bottom surface 70R is formed by a third semiconductor substrate 71. A plurality of electrode pads 73, 74 are exposed from the chip top surface 70S. The first chip side surface 70A and the second chip side surface 70B form both end surfaces of the insulating chip 70 in the X direction. The third chip side surface 70C and the fourth chip side surface 70D form both end surfaces of the insulating chip 70 in the Y direction.

[0052] As shown in FIG. 5, the insulating chip 70 includes two pairs of transformers 40A, 40B. More specifically, the insulating chip 70 is a semiconductor chip that integrates the two pairs of transformers 40A, 40B into a single chip. In other words, the insulating chip 70 is provided separately from the first chip 50 and the second chip 60 (both of which are shown in FIG. 3). The two pairs of transformers 40A, 40B are arranged at the same positions in the Y direction and spaced apart from each other in the X direction. The two pairs of transformers 40A, 40B are arranged alternately in the X direction, with the transformers 40A and the transformers 40B arranged one after the other.

[0053] The transformers 40A and 40B are disposed near the center of the insulating chip 70 in the Y direction in a plan view. In one example, the electrode pads 73 and 74 and the transformers 40A and 40B are disposed in positions that do not overlap each other in a plan view. The electrode pads 73 and 74 are electrically connected to the transformers 40A and 40B. The electrode pads 73 and 74 are made of a material containing one or more of titanium (Ti), titanium nitride (TiN), Au, Ag, Cu, Al, and tungsten (W). The electrode pads 73 and 74 are made of a material containing, for example, Al.

[0054] The electrode pads 73 are arranged closer to the third chip side surface 70C than the transformers 40A and 40B in a plan view. In other words, the electrode pads 73 are arranged between the transformers 40A and 40B and the third chip side surface 70C in the Y direction in a plan view. The electrode pads 73 are arranged at the same positions in the X direction as the two transformers 40A and the two transformers 40B, and between the transformers 40A and 40B in the X direction.

[0055] Each electrode pad 73 has a shape that is long in the X direction in a plan view, with the plurality of electrode pads 73 arranged in the array. In one example, each electrode pad 73 has a rectangular shape with its long side extending in the X direction and its short side extending in the Y direction.

[0056] The multiple electrode pads 73 include multiple first pads 73A electrically connected to the transformer 40A or 40B and multiple second pads 73B electrically connected to both the transformer 40A and the transformer 40B. The second pads 73B are provided as common pads for the transformers 40A and 40B. The multiple first pads 73A and the multiple second pads 73B are arranged at the same positions in the Y direction and spaced apart from each other in the X direction. The first pads 73A are arranged in a position overlapping with the transformers 40A and 40B when viewed from the Y direction. The second pads 73B are arranged in a position overlapping with the portion between the transformers 40A and 40B in the X direction when viewed from the Y direction. In this way, the second pads 73B are arranged between the two first pads 73A in the X direction.

[0057] The electrode pads 74 are arranged at positions overlapping the transformers 40A and 40B when viewed from the X direction. Each electrode pad 74 has a shape that is elongated in the Y direction, which is a direction perpendicular to the direction in which the electrode pads 74 are arranged in a plan view. In one example, each electrode pad 74 has a rectangular shape with its long side extending in the Y direction and its short side extending in the X direction.

[0058] The multiple electrode pads 74 include multiple first pads 74A electrically connected to the transformer 40A or 40B and multiple second pads 74B electrically connected to both the transformer 40A and the transformer 40B. The second pads 74B are provided as pads common to the transformers 40A and 40B. The multiple first pads 74A and the multiple second pads 74B are arranged at the same positions in the Y direction and spaced apart from each other in the X direction. The first pads 74A are arranged in the inner region 43 of the transformers 40A and 40B in a plan view. The second pads 74B are arranged outside the transformers 40A and 40B. The second pads 74B are arranged between the transformers 40A and 40B in the X direction.

[0059] Each pair of transformers 40A and 40B has the same configuration. Furthermore, the transformer 40B has the same configuration as the transformer 40A. Therefore, the detailed structure of the transformer 40A will be described, and a description of the transformer 40B will be omitted.

[0060] As shown in Figure 8, the transformer 40A is provided in the third insulating layer 72. The transformer 40A is disposed within the third insulating layer 72. It can also be said that the transformer 40A is embedded in the third insulating layer 72. The third insulating layer 72 includes a plurality of insulating films 75 stacked in the Z direction from the third semiconductor substrate 71. In other words, it can be said that the Z direction is the thickness direction of the third insulating layer 72. It can also be said that the Z direction is the stacking direction of the insulating films 75.

[0061] The insulating film 75 includes a first insulating film 75A and a second insulating film 75B formed on the first insulating film 75A. The first insulating film 75A is a thin film, and is, for example, an etching stopper layer. The first insulating film 75A is made of a material containing SiN, SiC, SiCN (nitrogen-doped silicon carbide), etc. In the first embodiment, the first insulating film 75A is made of a material containing SiN. The second insulating film 75B is, for example, an interlayer insulating film. The second insulating film 75B is made of SiO ２ The second insulating film 75B is made of a material containing the above-mentioned compound. The thickness of the second insulating film 75B is thicker than the thickness of the first insulating film 75A. The thickness of the first insulating film 75A may be equal to or greater than 100 nm and less than 1000 nm. The thickness of the second insulating film 75B may be equal to or greater than 1000 nm and less than 3000 nm. In one example, the thickness of the first insulating film 75A is about 300 nm, and the thickness of the second insulating film 75B is about 2000 nm.

[0062] Of the third insulating layer 72, both the bottom insulating film 75L in contact with the third semiconductor substrate 71 and the top insulating film 75U are composed of the second insulating film 75B. In one example, the thicknesses of both the bottom insulating film 75L and the top insulating film 75U are thinner than the thicknesses of the other second insulating films 75B. The thicknesses of both the bottom insulating film 75L and the top insulating film 75U are equal to or greater than the thickness of the first insulating film 75A.

[0063] The thicknesses of both the bottom insulating film 75L and the top insulating film 75U can be changed as desired. For example, the thicknesses of both the bottom insulating film 75L and the top insulating film 75U may be equal to or greater than the thickness of the second insulating film 75B. The thicknesses of both the bottom insulating film 75L and the top insulating film 75U may be equal to or greater than the thickness of the insulating film 75 formed by the first insulating film 75A and the second insulating film 75B.

[0064] As shown in Figure 6, the first coil 41 of the transformers 40A, 40B is composed of first coil wiring 44. The first coil wiring 44 has an elliptical spiral shape in a plan view. The first coil wiring 44 is composed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the first coil wiring 44 is composed of a material containing Cu. Here, the first coil 41 is an example of a "first conductive layer."

[0065] An inner end wiring 46A is arranged inside the first coil wiring 44. An outer end wiring 46B is arranged outside the first coil wiring 44. The inner end of the first coil wiring 44 is electrically connected to the inner end wiring 46A. The outer end of the first coil wiring 44 is electrically connected to the outer end wiring 46B. In one example, the inner end wiring 46A is arranged offset in the X direction with respect to the center of the first coil 41 in the X direction. In one example, the outer end wiring 46B is arranged offset toward the transformer 40B with respect to the center in the X direction between the first coil 41 of the transformer 40A and the first coil 41 of the transformer 40B.

[0066] The inner end wiring 46A and the outer end wiring 46B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the inner end wiring 46A and the outer end wiring 46B are made of a material containing Cu. That is, the inner end wiring 46A and the outer end wiring 46B may be made of the same material as the first coil wiring 44. The outer end wiring 46B is configured as a common end wiring for the first coils 41 of the transformers 40A and 40B. Note that an outer end wiring may be provided for each of the first coils 41 of the transformers 40A and 40B.

[0067] 6 and 8, the inner end wiring 46A is connected to the first pad 73A by a connection wiring 121A. The connection wiring 121A is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the connection wiring 121A is made of a material containing Cu.

[0068] As shown in FIG. 8 , the connection wiring 121A includes a first wiring portion 122A extending in the Z direction so as to penetrate the multiple insulating films 75, and a second wiring portion 123A extending in the Y direction. The first wiring portion 122A is positioned so as to overlap the first pad 73A in a plan view. The first wiring portion 122A is connected to the first pad 73A. In one example, the first wiring portion 122A penetrates from the topmost insulating film 75U of the multiple insulating films 75 to the insulating film 75 two layers above the bottommost insulating film 75L. The first wiring portion 122A includes a flat wiring portion and multiple vias. The wiring portions are provided at the same positions as the insulating films 75P and 75Q where the coils 41 and 42 are provided. Vias are provided between the two wiring portions in the Z direction, between the upper wiring portion and the first pad 73A in the Z direction, and between the lower wiring portion and the second wiring portion 123A in the Z direction.

[0069] The second wiring portion 123A is provided closer to the third semiconductor substrate 71 than the first wiring portion 122A. The second wiring portion 123A is provided closer to the third semiconductor substrate 71 than the first coil 41. In the first embodiment, the second wiring portion 123A is provided in an insulating film 75 one layer above the lowest insulating film 75L among the multiple insulating films 75. The second wiring portion 123A is connected to the first wiring portion 122A. The end of the second wiring portion 123A opposite the first wiring portion 122A in the Y direction is provided at a position overlapping the inner end wiring 46A to which the first coil 41 of the transformer 40A is connected in a plan view. The second wiring portion 123A is connected to the inner end wiring 46A by multiple vias 124A.

[0070] As shown in FIG. 6 , the outer edge wiring 46B is electrically connected to the second pad 73B (see FIG. 5 ) by a connection wiring 121B. The connection wiring 121B is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the connection wiring 121B is made of a material containing Cu. That is, the connection wiring 121B may be made of the same material as the connection wiring 121A. Similarly to the connection wiring 121A, the connection wiring 121B includes a first wiring portion 122B, a second wiring portion 123B, and multiple vias (not shown). The first wiring portion 122B, the second wiring portion 123B, and the multiple vias have the same configuration as the first wiring portion 122A, the second wiring portion 123A, and the multiple vias 124A of the connection wiring 121A (see FIG. 8 ).

[0071] 7, the second coil 42 of the transformers 40A, 40B includes second coil wiring 45. The second coil wiring 45 has an elliptical spiral shape in a plan view. The second coil wiring 45 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. Here, the second coil 42 is an example of a "second conductive layer."

[0072] In the first embodiment, the second coil wiring 45 is formed in the same winding direction as the first coil wiring 44 shown in Fig. 6 in a plan view. The number of turns of the second coil wiring 45 is equal to the number of turns of the first coil wiring 44. The relationship between the number of turns and the winding direction of the first coil wiring 44 and the second coil wiring 45 can be changed as desired.

[0073] The inner end of the second coil wiring 45 is electrically connected to the first pad 74A by a connection wiring 125A, and the outer end of the second coil wiring 45 is electrically connected to the second pad 74B by a connection wiring 125B.

[0074] The connection wiring 125A includes an inner end wiring 126A and a plurality of vias 127A (see FIG. 8). In one example, the inner end wiring 126A is disposed offset in the X direction from the center of the second coil 42 in the X direction. The inner end wiring 126A is disposed at a position offset in the X direction from the inner end wiring 46A (see FIG. 8) in a plan view. The inner end wiring 126A is disposed at a position overlapping the first pad 74A in a plan view. The plurality of vias 127A connect the inner end wiring 126A and the first pad 74A.

[0075] The connection wiring 125B includes an outer end wiring 126B and a plurality of vias (not shown). In one example, the outer end wiring 126B is arranged biased toward the transformer 40A with respect to the center in the X direction between the second coil 42 of the transformer 40A and the second coil 42 of the transformer 40B. The outer end wiring 126B is arranged at a position offset in the X direction from the outer end wiring 46B (see FIG. 6) in a plan view. The outer end wiring 126B is arranged at a position overlapping the second pad 74B in a plan view. The plurality of vias connect the outer end wiring 126B and the second pad 74B.

[0076] 8, the first coil 41 and the second coil 42 of the transformer 40A are arranged to face each other in the Z direction via an insulating film 75. In the first embodiment, the first coil 41 and the second coil 42 are arranged to face each other in the Z direction via a plurality of insulating films 75. The first coil 41 and the second coil 42 of the transformer 40B (see FIG. 7) have the same configuration as the transformer 40A.

[0077] The first coil 41 is configured as a conductive layer embedded in one insulating film 75P. More specifically, a first coil groove is formed in the insulating film 75P, penetrating both the first insulating film 75A and the second insulating film 75B in the Z direction. The conductive layer that constitutes the first coil 41 is embedded in the first coil groove of the insulating film 75P. The first coil 41 is covered by the insulating film 75P and the insulating film 75 adjacent to the insulating film 75P in the Z direction. As a result, the first coil 41 can be said to be embedded in the third insulating layer 72. Furthermore, the first coil wiring 44 can be said to be configured by embedding the conductive layer in the first coil groove.

[0078] The second coil 42 is configured as a conductive layer embedded in one insulating film 75Q. More specifically, a second coil groove is formed in the insulating film 75Q, penetrating both the first insulating film 75A and the second insulating film 75B in the Z direction. The conductive layer constituting the second coil 42 is embedded in the second coil groove of the insulating film 75Q. The second coil 42 is covered by the insulating film 75Q and the insulating film 75 adjacent to the insulating film 75Q in the Z direction. As a result, the second coil 42 can be said to be embedded in the third insulating layer 72. Furthermore, the second coil wiring 45 can be said to be configured by embedding a conductive layer in the second coil groove.

[0079] The second coil 42 is disposed at a position farther from the third semiconductor substrate 71 in the Z direction than the first coil 41. In other words, the second coil 42 is disposed higher than the first coil 41. In the first embodiment, the distance between the second coil 42 and the first coil 41 in the Z direction is greater than the distance between the first coil 41 and the third semiconductor substrate 71 in the Z direction.

[0080] 5 and 7 , the insulating chip 70 includes outer dummy wiring 47. The outer dummy wiring 47 is a wiring pattern formed so as to prevent current from flowing through the second coil wiring 45 of the second coil 42. The outer dummy wiring 47 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the outer dummy wiring 47 is made of a material containing Cu. In other words, the outer dummy wiring 47 may be made of the same material as the second coil wiring 45.

[0081] In the first embodiment, the outer dummy wiring 47 includes a first dummy wiring 47A, a second dummy wiring 47B, and a third dummy wiring 47C. In plan view, the first dummy wiring 47A is formed between the second coil wiring 45 of the transformer 40A and the second coil wiring 45 of the transformer 40B in the X direction, and two dummy wirings 47A are formed spaced apart in the Y direction. In plan view, the first dummy wiring 47A is formed to avoid the second pad 74B. In plan view, the third dummy wiring 47C is provided between the pair of transformers 40A, 40B and the pair of transformers 40A, 40B in the X direction.

[0082] The first dummy wiring 47A and the third dummy wiring 47C are formed in a pattern different from that of the second coil wiring 45. The first dummy wiring 47A and the third dummy wiring 47C are composed of a plurality of wirings. The wiring width and wiring spacing of the first dummy wiring 47A and the third dummy wiring 47C, which are composed of a plurality of wirings, are equal to, for example, the wiring width and wiring spacing of the second coil wiring 45. In other words, the density (wiring density) of the first dummy wiring 47A and the third dummy wiring 47C is equal to the density (wiring density) of the second coil wiring 45. Note that the density of the first dummy wiring 47A and the third dummy wiring 47C may be different from the density of the second coil wiring 45. Furthermore, the density of the first dummy wiring 47A may be different from the density of the third dummy wiring 47C.

[0083] 7, the first dummy wiring 47A and the third dummy wiring 47C have first slits formed along the Y direction. The first slits form the first dummy wiring 47A in an open ring shape. The first slits suppress the formation of a current loop in the first dummy wiring 47A.

[0084] The first dummy wiring 47A and the third dummy wiring 47C are electrically connected to the second pad 74B. This causes the first dummy wiring 47A and the third dummy wiring 47C to have the same potential as the second coil 42. Therefore, as with the second reference potential of the second coil 42, the voltages of the first dummy wiring 47A and the third dummy wiring 47C may become higher than the voltage of the first coil 41, similar to the second coil 42.

[0085] The second dummy wiring 47B is formed so as to surround the second coil 42, the first dummy wiring 47A, and the third dummy wiring 47C in a plan view. The second dummy wiring 47B is electrically connected to the first dummy wiring 47A.

[0086] The second dummy wiring 47B is configured with a plurality of wirings surrounding the second coil 42, the first dummy wiring 47A, and the third dummy wiring 47C in a plan view. The wiring width and wiring spacing of the second dummy wiring 47B configured with a plurality of wirings are equal to, for example, the wiring width and wiring spacing of the second coil wiring 45. In other words, the density (wiring density) of the second dummy wiring 47B is equal to the density (wiring density) of the second coil wiring 45. Note that the density of the second dummy wiring 47B may be different from the density of the second coil wiring 45.

[0087] The second dummy wiring 47B has a second slit formed along the Y direction. The second slit causes the second dummy wiring 47B to be formed in an open loop shape. The second slit suppresses the formation of a current loop in the second dummy wiring 47B.

[0088] The insulating chip 70 includes floating dummy wiring 48. The floating dummy wiring 48 includes a first dummy pattern 48A and a second dummy pattern 48B. The first dummy pattern 48A and the second dummy pattern 48B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0089] The first dummy pattern 48A is formed to surround the second dummy wiring 47B in a plan view. The first dummy pattern 48A is electrically independent from the second coil 42. In other words, the first dummy pattern 48A is not electrically connected to the second coil 42.

[0090] The first dummy pattern 48A is composed of a plurality of wires. In one example, each of the plurality of wires is formed in a closed loop. The wire width of the first dummy pattern 48A composed of a plurality of wires is equal to the wire width of the second coil wiring 45. The wire spacing of the first dummy pattern 48A is greater than the wire spacing of the second coil wiring 45. In other words, the density (wire density) of the first dummy pattern 48A is lower than the density (wire density) of the second coil wiring 45. Note that the density of the first dummy pattern 48A may be equal to or higher than the density of the second coil wiring 45.

[0091] 8 , the first dummy pattern 48A and the outer dummy wiring 47 are disposed in the same position in the Z direction as the second coil 42. In other words, the first dummy pattern 48A and the outer dummy wiring 47 are disposed in a position in the Z direction farther from the third semiconductor substrate 71 than the first coil 41. The first dummy pattern 48A and the outer dummy wiring 47 suppress an increase in the electric field strength around the second coil 42 while suppressing electric field concentration around the second coil 42.

[0092] As shown in FIG. 7 , the second dummy pattern 48B is disposed between the second coil 42 and the electrode pad 73 (see FIG. 5 ) in a plan view. The second dummy pattern 48B extends along the X direction. In the example shown in FIG. 7 , the second dummy pattern 48B is configured with a single wire extending along the X direction. Note that the second dummy pattern 48B may also be configured with multiple wires extending along the X direction. In this case, the multiple wires are arranged at a distance in the Y direction. The second dummy pattern 48B is electrically independent from the second coil 42. In other words, the second dummy pattern 48B is not electrically connected to the second coil 42.

[0093] 8, the insulating chip 70 includes a passivation film 78 that protects the third insulating layer 72, and a resin layer 79 formed on the passivation film 78. Here, the third insulating layer 72 and the passivation film 78 are an example of an "insulator." Also, the third insulating layer 72, the passivation film 78, and the resin layer 79 are an example of an "insulator."

[0094] The passivation film 78 can be considered a surface protection film for the insulating chip 70. The passivation film 78 is formed on the upper surface of the third insulating layer 72. The passivation film 78 is made of a material containing at least one of a silicon oxide film and a silicon nitride film, for example. Examples of materials containing a silicon nitride film include SiN and SiCN.

[0095] The electrode pads 73 and 74 are covered with a passivation film 78. The passivation film 78 has openings that expose portions of the electrode pads 73 and 74. As a result, the electrode pad 73 has an exposed surface for connecting the wire W2 (see FIG. 3 ), and the electrode pad 74 has an exposed surface for connecting the wire W3 (see FIG. 3 ).

[0096] The resin layer 79 is made of a material containing, for example, polyimide (PI). As shown in FIG. 4, the resin layer 79 is separated into an inner resin layer and an outer resin layer by a separation groove 79A. The separation groove 79A is formed so as to surround the transformers 40A and 40B (see FIG. 5) in a plan view. The resin layer 79 includes a first resin opening 79B exposing the electrode pad 73 and a second resin opening 79C exposing the electrode pad 74.

[0097] 8 , in the first embodiment, the third bonding material 113 is in contact with the entire lower surface of the third semiconductor substrate 71. The third bonding material 113 is formed so as to widen as it moves from the third semiconductor substrate 71 toward the first die pad 81. For example, an insulating bonding material having a smaller dielectric constant than that of the third semiconductor substrate 71 may be used for the third bonding material 113. When the third semiconductor substrate 71 is a Si substrate, the third semiconductor substrate 71 has a dielectric constant of about 12. Therefore, an insulating bonding material having a dielectric constant of less than 12 may be used for the third bonding material 113.

[0098] In one example, the third bonding material 113 may be an insulating bonding material having a relative dielectric constant that is ½ or less of the third semiconductor substrate 71. In one example, the third bonding material 113 may be an insulating bonding material having a relative dielectric constant that is ⅓ or less of the third semiconductor substrate 71. In one example, the third bonding material 113 is made of an insulating material having a relative dielectric constant of less than 4. In one example, the relative dielectric constant of the third bonding material 113 may be equal to the relative dielectric constant of the sealing resin 100. In one example, the relative dielectric constant of the third bonding material 113 may be less than the relative dielectric constant of the sealing resin 100. In the first embodiment, the relative dielectric constant of the third bonding material 113 is 3.5.

[0099] (Method for Manufacturing Semiconductor Device) Next, an example of a method for manufacturing the semiconductor device 10 of this embodiment will be described. In the following description, for components related to the semiconductor device 10, please refer to the reference numerals assigned to the components of the semiconductor device 10 shown in FIGS. 1 to 8.

[0100] The manufacturing method of the semiconductor device 10 mainly includes a step of preparing a lead frame, a step of mounting a chip, a step of forming wires, a step of forming a sealing resin, and a step of singulating.

[0101] In the step of preparing the lead frames, a first lead frame 80 and a second lead frame 90 are prepared. The die pads 81, 91 and the leads 82, 92 of the first lead frame 80 and the second lead frame 90 are formed by etching a metal plate made of, for example, a material containing Cu. The first lead frame 80 and the second lead frame 90 may also be formed by press working.

[0102] The next step of mounting the chips includes a step of mounting the first chip 50 and the second chip 60, and a step of mounting the insulating chip 70. In the step of mounting the first chip 50 and the second chip 60, first, a first bonding material 111 is applied to the first die pad 81, and a second bonding material 112 is applied to the second die pad 91. A conductive bonding material is used for both the first bonding material 111 and the second bonding material 112. In one example, a solder paste is used for the first bonding material 111 and the second bonding material 112. Next, the first chip 50 is placed on the first bonding material 111, and the second chip 60 is placed on the second bonding material 112. Next, a reflow process is performed, which melts the first bonding material 111 and the second bonding material 112. Next, the first bonding material 111 and the second bonding material 112 are cooled to solidify the first bonding material 111 and the second bonding material 112. Through the above steps, the first chip 50 is mounted on the first die pad 81, and the second chip 60 is mounted on the second die pad 91.

[0103] In the process of mounting the insulating chip 70, first, a third bonding material 113 is applied to the first die pad 81. An insulating bonding material is used as the third bonding material 113. In one example, a paste-like bonding material containing epoxy resin is used as the third bonding material 113. Next, the insulating chip 70 is placed on the third bonding material 113. When the third bonding material 113 hardens, the insulating chip 70 is bonded to the first die pad 81. In this manner, the insulating chip 70 is mounted on the first die pad 81.

[0104] In the wire forming step, wires W1 to W4 are formed using, for example, a wire bonding apparatus. In one example, the wire bonding apparatus forms wires W1 individually from the plurality of electrode pads 53 of the first chip 50 to the plurality of first leads 82. In one example, the wire bonding apparatus forms wires W2 individually from the plurality of electrode pads 63 of the second chip 60 to the plurality of second leads 92. In one example, the wire bonding apparatus forms wires W3 from the plurality of electrode pads 73 of the insulating chip 70 to the plurality of electrode pads 53 of the first chip 50. In one example, the wire bonding apparatus forms wires W4 from the plurality of electrode pads 74 of the insulating chip 70 to the plurality of electrode pads 63 of the second chip 60.

[0105] In the process of forming the sealing resin, for example, transfer molding is used to form sealing resin 100. Sealing resin 100 seals first chip 50, second chip 60, insulating chip 70, first die pad 81, second die pad 91, and wires W1 to W4, and also partially seals each of the plurality of leads 82, 92.

[0106] In the singulation step, a dicing blade or a mold is used to cut off the leads 82, 92 protruding from the sealing resin 100. Through the above steps, the semiconductor device 10 is manufactured.

[0107] [Operation of First Embodiment] The operation of the semiconductor device 10 of the first embodiment will be described with reference to Figures 9 and 10. Figure 9 shows the transition of voltage applied to the coil of the insulating chip during a surge withstand voltage test on a semiconductor device of a comparative example. Figure 10 shows the transition of voltage in the first coil 41 of the insulating chip 70 during a surge withstand voltage test on the semiconductor device 10 of the first embodiment. The semiconductor device of the comparative example differs from the semiconductor device 10 of the first embodiment mainly in the configuration in which the insulating chip 70 and the first die pad 81 are joined with a conductive bonding material.

[0108] In the surge withstand voltage test, the semiconductor device has the first leads 82 shorted to one another and the second leads 92 shorted to one another. In the surge withstand voltage test, the second leads 92 are grounded. Then, in the surge withstand voltage test, a predetermined surge voltage VT (e.g., a surge voltage of 10,000 V and 1 nS) is applied to the first leads 82.

[0109] In a surge withstand voltage test, a surge voltage is applied to the first coil 41 of the insulating chip 70 mainly via two paths. These paths will be described with reference to FIGS. 2 and 3 . The first path runs from the first lead 82 (82A) through the first die pad 81, the third bonding material 113 (a conductive bonding material in the semiconductor device of the comparative example), and the third semiconductor substrate 71 to the first coil 41. The second path runs from the first lead 82 (82A) through the wire W1, the first chip 50, and the wire W2 to the first coil 41. The voltage at the second coil 42 of the insulating chip 70 is ground potential (0 V) because the second lead 92 (92A) is grounded.

[0110] Graph GX1 in Fig. 9 and graph G1 in Fig. 10 show the transition of the voltage of the first coil 41 (the voltage between the second coil 42 and the first coil 41) to which the surge voltage is applied via the first path. Graph GX2 in Fig. 9 and graph G2 in Fig. 10 show the transition of the voltage of the first coil 41 to which the surge voltage is applied via the second path. Graph GX3 in Fig. 9 and graph G3 in Fig. 10 show the transition of the voltage of the first coil 41 during the surge withstand voltage test. The surge voltage is applied to the first coil 41 via the first path and the second path. Therefore, graph G3 (GX3) showing the voltage of the first coil 41 during the surge withstand voltage test has a waveform that combines the above-described graph G1 (GX1) and graph G2 (GX2).

[0111] 9 , while the voltage trends are similar in both graphs GX1 and GX2, the voltage applied to the first coil 41 in graph GX2 lags behind that in graph GX1. As a result, as shown in graph GX3, in the semiconductor device of the comparative example, the peak value Gx1 of the voltage applied to the first coil 41 becomes significantly higher than the predetermined surge voltage VT. This increases the peak value Gx3 of the voltage applied to the third insulating layer 72, as shown in graph GX3. This may hasten the breakdown of the third insulating layer 72 between the first coil 41 and the second coil 42.

[0112] In the semiconductor device of the comparative example, the insulating chip 70 and the first die pad 81 are bonded together with a conductive bonding material. Therefore, in the first path, the surge voltage is transmitted to the first coil 41 through capacitive coupling (AC coupling) between the conductive bonding material and the first coil 41, which are opposed across the third semiconductor substrate 71. The capacitance value between the conductive bonding material and the first coil 41 is determined by the opposing area, distance, and dielectric constant between the conductive bonding material and the first coil 41. The opposing area is determined primarily by the area of ​​the first coil 41 in a planar view. The distance and dielectric constant are determined primarily by the thickness of the third semiconductor substrate 71. In other words, in the first path in the semiconductor device of the comparative example, the surge voltage is applied to the first coil 41 through coupling due to capacitance Cs in the third semiconductor substrate 71.

[0113] In contrast, in the semiconductor device 10 of the first embodiment, the third bonding material 113 that bonds the insulating chip 70 and the first die pad 81 is made of an insulating bonding material. Therefore, the first coil 41 faces the first die pad 81 mainly with the third semiconductor substrate 71 and the third bonding material 113 sandwiched between them. Therefore, the surge voltage in the first path is applied to the first coil 41 via the capacitance Cp of the third bonding material 113 in addition to the capacitance Cs of the third semiconductor substrate 71. The capacitance Cp of the third bonding material 113 and the capacitance Cs of the third semiconductor substrate 71 are connected in series between the first die pad 81 and the first coil 41. The capacitance value of the third bonding material 113 is determined by the thickness (distance) of the third bonding material 113, the relative dielectric constant of the third bonding material 113, and the opposing area of ​​the first die pad 81 and the third semiconductor substrate 71 that face each other via the third bonding material 113. As a result, the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71 in the first path is smaller than the capacitance Cs of the third semiconductor substrate 71. Therefore, in the semiconductor device 10 of the first embodiment, the surge voltage applied to the first coil 41 via the first path is lower than the surge voltage applied to the first coil 41 in the semiconductor device of the comparative example.

[0114] As shown in FIG. 10 , although the voltage is applied to the third insulating layer 72 with a delay in graph G2 relative to graph G1, the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71 in the first path is small, so the peak voltage value Gp1 of graph G1 is smaller than the peak voltage value Gx1 of graph GX1. On the other hand, in the second path, the semiconductor device of the comparative example and the semiconductor device 10 of the first embodiment have the same configuration, so the peak voltage value Gx2 of graph GX2 shown in FIG. 9 is equal to the peak voltage value Gp2 of graph G2. As a result, the peak voltage value Gp3 of graph G3 is smaller than the peak voltage value Gx3 of graph GX3 shown in FIG. 9 . In this way, in the semiconductor device 10 of the first embodiment, the surge voltage applied to the first coil 41 can be made lower than the surge voltage applied to the first coil 41 in the semiconductor device of the comparative example. Therefore, the early occurrence of dielectric breakdown of the third insulating layer 72 between the first coil 41 and the second coil 42 can be suppressed.

[0115] [Effects of First Embodiment] The semiconductor device 10 of the first embodiment provides the following effects: (1-1) The semiconductor device 10 includes a first die pad 81 and a second die pad 91 that are insulated from each other, a first chip 50 mounted on the first die pad 81, a second chip 60 mounted on the second die pad 91, an insulating chip 70 that is mounted on the first die pad 81 and connected between the first chip 50 and the second chip 60, a first bonding material 111 that is interposed between the first die pad 81 and the first chip 50 and bonds the first die pad 81 to the first chip 50, a second bonding material 112 that is interposed between the second die pad 91 and the second chip 60 and bonds the second die pad 91 to the second chip 60, and a third bonding material 113 that is interposed between the first die pad 81 and the insulating chip 70 and bonds the first die pad 81 to the insulating chip 70. The insulating chip 70 includes a third semiconductor substrate 71, a third insulating layer 72 provided on the third semiconductor substrate 71, and transformers 40A, 40B disposed within the third insulating layer 72 and including a first coil 41 and a second coil 42 that are insulated from each other. The third semiconductor substrate 71 is bonded to the first die pad 81 by a third bonding material 113. The third bonding material 113 is an insulating bonding material.

[0116] This configuration reduces the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71 compared to when a conductive bonding material is used as the third bonding material 113. Therefore, the surge voltage applied to the first coil 41 of the insulating chip 70 can be reduced, thereby improving the surge withstand voltage of the semiconductor device 10.

[0117] (1-2) The third bonding material 113 is made of an insulating material having a dielectric constant smaller than that of the semiconductor material making up the third semiconductor substrate 71. With this configuration, the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71 can be reduced compared to when a third bonding material 113 having a dielectric constant equal to or greater than that of the semiconductor material making up the third semiconductor substrate 71 is used. Therefore, the surge voltage applied to the first coil 41 of the insulating chip 70 can be reduced, thereby improving the surge withstand voltage of the semiconductor device 10.

[0118] (1-3) The third bonding material 113 is made of an insulating material with a relative dielectric constant of less than 12. With this configuration, the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71 can be reduced compared to when the third bonding material 113 is made of an insulating material with a relative dielectric constant of 12 or more. Therefore, the surge voltage applied to the first coil 41 of the insulating chip 70 can be reduced, thereby improving the surge withstand voltage of the semiconductor device 10.

[0119] (1-4) The multiple electrode pads 53 of the first chip 50, the multiple electrode pads 63 of the second chip 60, and the multiple electrode pads 73, 74 of the insulating chip 70 are arranged at the same positions relative to one another in the Z direction. The multiple electrode pads 53 of the first chip 50 and the multiple electrode pads 73 of the insulating chip 70 are individually electrically connected by wires W2. The multiple electrode pads 74 of the insulating chip 70 and the multiple electrode pads 63 of the second chip 60 are individually electrically connected by wires W3.

[0120] With this configuration, the wires W2 and W3 can be easily formed compared to a configuration in which the multiple electrode pads 53 of the first chip 50, the multiple electrode pads 63 of the second chip 60, and the multiple electrode pads 73 and 74 of the insulating chip 70 are arranged at different positions in the Z direction.

[0121] (1-5) The third bonding material 113 is made of an insulating material with a relative dielectric constant of less than 4. With this configuration, the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71 can be reduced compared to when the third bonding material 113 is made of an insulating material with a relative dielectric constant of 4 or more. Therefore, the surge voltage applied to the first coil 41 of the insulating chip 70 can be reduced, thereby improving the surge withstand voltage of the semiconductor device 10.

[0122] 11 to 13, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment differs from the first embodiment in that it includes a double insulation structure using a transformer. Below, differences from the first embodiment will be described in detail, and components common to the semiconductor device 10 according to the first embodiment will be designated by the same reference numerals and will not be described again.

[0123] Fig. 11 schematically shows the electrical configuration of the semiconductor device 10 of the second embodiment. Fig. 12 schematically shows the internal planar structure of the semiconductor device 10 of the second embodiment. Fig. 13 schematically shows the cross-sectional structure of the semiconductor device 10 of the second embodiment taken along line F13-F13 in Fig. 12.

[0124] 11, the semiconductor device 10 includes transformers 130A and 130B that electrically isolate the first circuit 20 from the second circuit 30. In one example, similar to the first embodiment, the transformer 130A is used to transmit a set signal, and the transformer 130B is used to transmit a reset signal.

[0125] Transformer 130A includes first transformer 131A and second transformer 132A connected in series. First transformer 131A includes first coil 141A and second coil 142A that is electrically insulated from first coil 141A and configured to be magnetically coupleable. Second transformer 132A includes third coil 143A and fourth coil 144A that is electrically insulated from third coil 143A and configured to be magnetically coupleable.

[0126] The first coil 141A is electrically connected to the first circuit 20. The fourth coil 144A is electrically connected to the second circuit 30. The second coil 142A and the third coil 143A are in an electrically floating state and are electrically connected to each other.

[0127] Transformer 130B includes first transformer 131B and second transformer 132B connected in series. First transformer 131B includes first coil 141B and second coil 142B that is electrically insulated from first coil 141B and configured to be magnetically coupleable. Second transformer 132B includes third coil 143B and fourth coil 144B that is electrically insulated from third coil 143B and configured to be magnetically coupleable.

[0128] The first coil 141B is electrically connected to the first circuit 20. The fourth coil 144B is electrically connected to the second circuit 30. The second coil 142B and the third coil 143B are in an electrically floating state and are electrically connected to each other.

[0129] 12, the semiconductor device 10 includes a first insulating chip 70P and a second insulating chip 70Q. Both the first insulating chip 70P and the second insulating chip 70Q are disposed between the first chip 50 and the second chip 60 in the Y direction. The first insulating chip 70P is disposed closer to the first chip 50 than the second insulating chip 70Q.

[0130] The first insulating chip 70P has the same configuration as the insulating chip 70 of the first embodiment (see FIG. 2). The first insulating chip 70P includes first transformers 131A and 131B of the transformers 130A and 130B instead of the first coil 41 and second coil 42 of the transformers 40A and 40B (both see FIG. 3) of the insulating chip 70 of the first embodiment. The first coil 141A and second coil 142A of the first transformer 131A and the first coil 141B and second coil 142B of the first transformer 131B are each provided within the third insulating layer 72. The configuration and arrangement of the first coils 141A and 141B and the second coils 142A and 142B are similar to those of the first coil 41 and second coil 42 of the first embodiment.

[0131] 13 , the first coil 141A of the first transformer 131A in the first insulating chip 70P is electrically connected to the electrode pad 73. The second coil 142A is electrically connected to the electrode pad 74. Although not shown, the first coil 141B of the first transformer 131B in the first insulating chip 70P is electrically connected to the electrode pad 73. The second coil 142B is electrically connected to the electrode pad 74.

[0132] The first insulating chip 70P is mounted on the first die pad 81. The first insulating chip 70P is bonded to the first die pad 81 by a third bonding material 113. Here, an insulating bonding material is used for the third bonding material 113, as in the first embodiment. As the insulating bonding material, for example, a material containing epoxy resin is used. The third bonding material 113 of the second embodiment may have the same relative dielectric constant as the third bonding material 113 of the first embodiment, for example.

[0133] In the second embodiment, the third bonding material 113 is in contact with the entire lower surface of the third semiconductor substrate 71 of the first insulating chip 70P. The third bonding material 113 is formed so as to widen from the third semiconductor substrate 71 toward the first die pad 81.

[0134] The second insulating chip 70Q has the same configuration as the first insulating chip 70P. Instead of the first coils 141A, 141B and second coils 142A, 142B of the first transformers 131A, 131B of the first insulating chip 70P, the second insulating chip 70Q includes third coils 143A, 143B and fourth coils 144A, 144B of the second transformers 132A, 132B. The configuration and arrangement of the third coils 143A, 143B are the same as those of the second coils 142A, 142B of the first insulating chip 70P. The configuration and arrangement of the fourth coils 144A, 144B are the same as those of the first coils 141A, 141B of the first insulating chip 70P. The fourth coil 144A is electrically connected to the electrode pad 73. The third coil 143A is electrically connected to the electrode pad 74.

[0135] The third coil 143A of the second transformer 132A in the second insulating chip 70Q is electrically connected to the electrode pad 74. The fourth coil 144A of the second transformer 132A is electrically connected to the electrode pad 73. Although not shown, the third coil 143B of the second transformer 132B in the second insulating chip 70Q is electrically connected to the electrode pad 74. The fourth coil 144B of the second transformer 132B is electrically connected to the electrode pad 73.

[0136] The second insulating chip 70Q is mounted on the second die pad 91. The second insulating chip 70Q is bonded to the second die pad 91 by a fourth bonding material 114. The fourth bonding material 114 is interposed between the second die pad 91 and the second insulating chip 70Q. In the second embodiment, a conductive bonding material is used as the fourth bonding material 114. The conductive bonding material may be, for example, a solder paste or an Ag paste.

[0137] In the second embodiment, the thickness relationships among the first chip 50, the second chip 60, the first insulating chip 70P, and the second insulating chip 70Q are as follows: The thickness TA3 of the third semiconductor substrate 71 of the first insulating chip 70P is equal to the thickness TA4 of the third semiconductor substrate 71 of the second insulating chip 70Q. The thicknesses TA3 and TA4 of the third semiconductor substrate 71 of each insulating chip 70P and 70Q are equal to the thickness TA1 of the first semiconductor substrate 51. The thicknesses TA3 and TA4 of the third semiconductor substrate 71 of each insulating chip 70P and 70Q are equal to the thickness TA2 of the second semiconductor substrate 61. The thickness TB3 of the third insulating layer 72 of the first insulating chip 70P is equal to the thickness TB4 of the third insulating layer 72 of the second insulating chip 70Q. The thicknesses TB3 and TB4 of the third insulating layer 72 of each insulating chip 70P and 70Q are equal to the thickness TB1 of the first insulating layer 52. The thicknesses TB3 and TB4 of the third insulating layer 72 of each insulating chip 70P and 70Q are equal to the thickness TB2 of the second insulating layer 62. The thickness TC3 of the third bonding material 113 is equal to the thickness TC1 of the first bonding material 111. The thickness TC3 of the third bonding material 113 is equal to the thickness TC2 of the second bonding material 112. The thickness TC3 of the third bonding material 113 is equal to the thickness TC4 of the fourth bonding material 114.

[0138] The semiconductor device 10 of the second embodiment includes multiple wires W5 to W7 instead of the wires W2 and W3 of the first embodiment. The multiple wires W5 individually connect the multiple electrode pads 53 of the first chip 50 to the multiple electrode pads 73 of the first insulating chip 70P. The multiple wires W6 individually connect the multiple electrode pads 74 of the first insulating chip 70P to the multiple electrode pads 74 of the second insulating chip 70Q. The multiple wires W7 individually connect the multiple electrode pads 63 of the second chip 60 to the multiple electrode pads 73 of the second insulating chip 70Q.

[0139] The sealing resin 100 seals the first chip 50, the second chip 60, the first insulating chip 70P, the second insulating chip 70Q, the first die pad 81, the second die pad 91, and the wires W1, W4, W5 to W7. The sealing resin 100 also partially seals each of the multiple leads 82 and 92.

[0140] Effects of the Second Embodiment The semiconductor device 10 of the second embodiment provides the following effects: (2-1) The semiconductor device 10 includes a first insulating chip 70P mounted on the first die pad 81, a second insulating chip 70Q mounted on the second die pad 91, and a fourth bonding material 114 interposed between the second die pad 91 and the second insulating chip 70Q and bonding the second die pad 91 and the second insulating chip 70Q together. With this configuration, a double insulation structure is formed by the first insulating chip 70P and the second insulating chip 70Q, thereby improving the dielectric strength of the semiconductor device 10.

[0141] (2-2) The first insulating chip 70P and the second insulating chip 70Q have the same configuration. This configuration reduces the manufacturing costs of the first insulating chip 70P and the second insulating chip 70Q compared to when the first insulating chip 70P and the second insulating chip 70Q have different configurations.

[0142] (2-3) The multiple electrode pads 53 of the first chip 50, the multiple electrode pads 63 of the second chip 60, the multiple electrode pads 73, 74 of the first insulating chip 70P, and the multiple electrode pads 73, 74 of the second insulating chip 70Q are arranged at the same positions relative to one another in the Z direction. The multiple electrode pads 53 of the first chip 50 and the multiple electrode pads 73 of the first insulating chip 70P are individually electrically connected by wires W5. The multiple electrode pads 74 of the first insulating chip 70P and the multiple electrode pads 74 of the second insulating chip 70Q are individually electrically connected by wires W6. The multiple electrode pads 73 of the second insulating chip 70Q and the multiple electrode pads 63 of the second chip 60 are individually electrically connected by wires W7.

[0143] With this configuration, wires W5 to W7 can be formed more easily than when the multiple electrode pads 53 of the first chip 50, the multiple electrode pads 63 of the second chip 60, the multiple electrode pads 73, 74 of the first insulating chip 70P, and the multiple electrode pads 73, 74 of the second insulating chip 70Q are positioned at different positions in the Z direction.

[0144] 14 to 16, a semiconductor device 10 according to a third embodiment will be described. The semiconductor device 10 according to the third embodiment differs from the first embodiment in that the insulating structure using a transformer is changed to an insulating structure using a capacitor. Below, differences from the first embodiment will be described in detail, and components common to the components of the semiconductor device 10 according to the first embodiment will be assigned the same reference numerals and will not be described again.

[0145] FIG. 14 schematically shows the electrical configuration of the semiconductor device 10 of the third embodiment. FIG. 15 schematically shows the cross-sectional structure of the semiconductor device 10 of the third embodiment. The cross-sectional position of the cross-sectional structure of FIG. 15 is the same as the cross-sectional position of the cross-sectional structure of FIG. 3, for example. FIG. 16 schematically shows the cross-sectional structure of an insulating chip 70T, which will be described later. The cross-sectional position of the cross-sectional structure of FIG. 16 is the same as the cross-sectional position of the cross-sectional structure of FIG. 8, for example.

[0146] 14, the semiconductor device 10 includes capacitors 150A and 150B instead of the transformers 40A and 40B. The capacitors 150A and 150B are configured to electrically insulate the first circuit 20 from the second circuit 30. In one example, similar to the first embodiment, the capacitor 150A is used to transmit a set signal, and the capacitor 150B is used to transmit a reset signal. Here, the capacitors 150A and 150B are examples of "insulating elements."

[0147] The capacitors 150A and 150B include a first electrode 151 and a second electrode 152. The first electrode 151 of the capacitors 150A and 150B is electrically connected to the first circuit 20. The second electrode 152 of the capacitors 150A and 150B is electrically connected to the second circuit 30.

[0148] 15, the semiconductor device 10 includes an insulating chip 70T instead of the insulating chip 70. The insulating chip 70T includes capacitors 150A and 150B. Therefore, the insulating chip 70T can also be called a capacitor chip.

[0149] The insulating chip 70T is disposed between the first chip 50 and the second chip 60 in the Y direction. The insulating chip 70T is mounted on the first die pad 81. The insulating chip 70T is bonded to the first die pad 81 by a third bonding material 113. The third bonding material 113 is the same as the third bonding material 113 in the first embodiment.

[0150] As shown in FIG. 16 , capacitors 150A and 150B are provided in the third insulating layer 72. The first electrode 151 and the second electrode 152 of capacitors 150A and 150B are arranged opposite each other in the Z direction. The first electrode 151 is arranged closer to the third semiconductor substrate 71 than the second electrode 152. Both the first electrode 151 and the second electrode 152 are formed in a rectangular flat plate shape with the thickness direction aligned with the Z direction. Here, the first electrode 151 and the second electrode 152 are an example of an "electrode plate." The first electrode 151 is also an example of a "first conductive layer." The second electrode 152 is also an example of a "second conductive layer."

[0151] The first electrode 151 is provided in the insulating film 75P of the third insulating layer 72. More specifically, the insulating film 75P has a first capacitor groove that penetrates both the first insulating film 75A and the second insulating film 75B in the Z direction. The first electrode 151 is formed by filling the first capacitor groove with a conductive layer. The first electrode 151 is covered with the insulating film 75P and the insulating film 75 adjacent to the insulating film 75P in the Z direction. For this reason, it can be said that the first electrode 151 is embedded in the third insulating layer 72.

[0152] The second electrode 152 is provided in the insulating film 75Q of the third insulating layer 72. More specifically, the insulating film 75Q has a second capacitor groove that penetrates both the first insulating film 75A and the second insulating film 75B in the Z direction. The second electrode 152 is formed by filling a conductive layer in the second capacitor groove. The second electrode 152 is covered by the insulating film 75Q and the insulating film 75 adjacent to the insulating film 75Q in the Z direction. For this reason, it can be said that the second electrode 152 is embedded in the third insulating layer 72.

[0153] The first electrode 151 is electrically connected to the electrode pad 73 by a connection wiring 161A. The connection wiring 161A includes a first wiring portion 162 extending in the Z direction so as to penetrate the multiple insulating films 75, and a second wiring portion 163 extending in a direction perpendicular to the Z direction (the Y direction in FIG. 16 ).

[0154] The first wiring portion 162 is disposed at a position overlapping the first pad 73A in a plan view. The first wiring portion 162 is connected to the first pad 73A. In one example, the first wiring portion 162 penetrates from the uppermost insulating film 75U of the multiple insulating films 75 to the insulating film 75 that is two layers above the lowermost insulating film 75L. The first wiring portion 162 includes a flat wiring portion and multiple vias. The wiring portions are provided at the same positions as the insulating films 75Q on which the electrodes 151 and 152 are provided. The vias are provided between the upper wiring portion and the first pad 73A in the Z direction, and between the upper wiring portion and the second wiring portion 163 in the Z direction.

[0155] The second wiring portion 163 is provided closer to the third semiconductor substrate 71 than the first wiring portion 162. The second wiring portion 163 is provided on the insulating film 75P. That is, the second wiring portion 163 is provided at the same position as the first electrode 151 in the Z direction. The second wiring portion 163 is connected to the first wiring portion 162. The end of the second wiring portion 163 opposite to the first wiring portion 162 in the Y direction is connected to the first electrode 151.

[0156] The second electrode 152 is electrically connected to the electrode pad 74 by a connection wiring 161B. The connection wiring 161B is composed of, for example, a plurality of vias. The plurality of vias penetrate, for example, the insulating film 75U, which is the top layer of the third insulating layer 72, in the Z direction. The connection wirings 161A and 161B are composed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0157] [Effects of the Third Embodiment] According to the semiconductor device 10 of the third embodiment, in addition to the same effects as those of the semiconductor device 10 of the first embodiment, the following effects can be obtained.

[0158] (3-1) The connection wiring 161A includes a first wiring portion 162 connected to the first pad 73A, and a second wiring portion 163 connected to the first wiring portion 162, extending in a direction perpendicular to the Z direction, and connected to the first electrode 151. The second wiring portion 163 is disposed in the same position as the first electrode 151 in the Z direction.

[0159] With this configuration, the number of layers of the third insulating layer 72 can be reduced compared to a configuration in which the second wiring portion 163 is arranged closer to the third semiconductor substrate 71 than the first electrode 151. Therefore, the height of the insulating chip 70 can be reduced. Furthermore, if the number of layers of the third insulating layer 72 is not reduced, the number of layers of the third insulating layer 72 interposed between the first electrode 151 and the second electrode 152 can be increased compared to a configuration in which the second wiring portion 163 is arranged closer to the third semiconductor substrate 71 than the first electrode 151. Therefore, the dielectric strength of the insulating chip 70 can be improved.

[0160] <Modifications> The above-described embodiments can be modified as follows: The following modifications can be combined with each other to the extent that they are not technically inconsistent.

[0161] In the first and third embodiments, the relationship between the thicknesses TC1 to TC3 of the first to third bonding materials 111 to 113 can be changed as desired. Fig. 17 schematically shows a cross-sectional structure of a modified example of the semiconductor device 10 of the first embodiment. As shown in Fig. 17, the thickness TC3 of the third bonding material 113 may be thicker than the thickness TC1 of the first bonding material 111. The thickness TC3 of the third bonding material 113 may be thicker than the thickness TC2 of the second bonding material 112.

[0162] 17 , the thickness TA3 of the third semiconductor substrate 71 is equal to the thickness TA1 of the first semiconductor substrate 51 and the thickness TA2 of the second semiconductor substrate 61. The thickness TB3 of the third insulating layer 72 is equal to the thickness TB1 of the first insulating layer 52 and the thickness TB2 of the second insulating layer 62. Therefore, the height of the insulating chip 70 is greater than the heights of the first chip 50 and the second chip 60. In other words, the positions of the electrode pads 73 and 74 of the insulating chip 70 in the Z direction are higher than the electrode pads 53 of the first chip 50 and the electrode pads 63 of the second chip 60.

[0163] According to this configuration, the thickness TC3 of the third bonding material 113 is increased, thereby reducing the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71. Therefore, the surge voltage applied to the first coil 41 of the insulating chip 70 can be reduced, thereby improving the surge withstand voltage of the semiconductor device 10.

[0164] In the second embodiment, the relationship between the thicknesses TC1 to TC4 of the first to fourth bonding materials 111 to 114 can be changed as desired. For example, similar to the semiconductor device 10 of the modified example shown in FIG. 17 , the thickness TC3 of the third bonding material 113 may be thicker than the thickness TC1 of the first bonding material 111. The thickness TC3 of the third bonding material 113 may be thicker than the thickness TC2 of the second bonding material 112. The thickness TC3 of the third bonding material 113 may be thicker than the thickness TC4 of the fourth bonding material 114.

[0165] According to this configuration, the thickness TC3 of the third bonding material 113 is increased, thereby reducing the combined capacitance of the third bonding material 113 and the third semiconductor substrate 71. Therefore, the surge voltage applied to the first coil 41 of the insulating chip 70 can be reduced, thereby improving the surge withstand voltage of the semiconductor device 10.

[0166] Furthermore, the thickness TC3 of the third bonding material 113 may be equal to the thickness TC4 of the fourth bonding material 114. In other words, both the thickness TC3 of the third bonding material 113 and the thickness TC4 of the fourth bonding material 114 may be thicker than the thickness TC1 of the first bonding material 111 and the thickness TC2 of the second bonding material 112.

[0167] With this configuration, the electrode pads 73, 74 of the first insulating chip 70P and the electrode pads 73, 74 of the second insulating chip 70Q are arranged at the same positions in the Z direction, which makes it easier to form the wires W6 compared to when the electrode pads 73, 74 of the first insulating chip 70P and the electrode pads 73, 74 of the second insulating chip 70Q are arranged at different positions in the Z direction.

[0168] In each embodiment, the thickness TA1 of the first semiconductor substrate 51, the thickness TA2 of the second semiconductor substrate 61, and the thickness TA3 of the third semiconductor substrate 71 can be changed as desired. Figure 18 schematically shows a cross-sectional structure of a first modified example of the semiconductor device 10 of the first embodiment. As shown in Figure 18, the thickness TA1 of the first semiconductor substrate 51, the thickness TA2 of the second semiconductor substrate 61, and the thickness TA3 of the third semiconductor substrate 71 are each thicker than the thickness TA1 of the first semiconductor substrate 51, the thickness TA2 of the second semiconductor substrate 61, and the thickness TA3 of the third semiconductor substrate 71, respectively, of the first embodiment. In the first modified example, the thickness TA1 of the first semiconductor substrate 51, the thickness TA2 of the second semiconductor substrate 61, and the thickness TA3 of the third semiconductor substrate 71 are each, for example, thicker than 180 μm and not greater than 400 μm.

[0169] According to this configuration, the thickness TA3 of the third semiconductor substrate 71 is increased, thereby reducing the combined capacitance of the third semiconductor substrate 71 and the third bonding material 113. Therefore, the surge voltage applied to the first coil 41 of the insulating chip 70 can be reduced, thereby improving the surge withstand voltage of the semiconductor device 10.

[0170] FIG. 19 schematically illustrates a cross-sectional structure of a second modified example of the semiconductor device 10 of the first embodiment. As illustrated in FIG. 19 , the thickness TA3 of the third semiconductor substrate 71 may be thicker than the thickness TA1 of the first semiconductor substrate 51. The thickness TA3 of the third semiconductor substrate 71 may be thicker than the thickness TA2 of the second semiconductor substrate 61. The thickness TA3 of the third semiconductor substrate 71 may be thicker than both the thickness TA1 of the first semiconductor substrate 51 and the thickness TA2 of the second semiconductor substrate 61. In the second modified example, the thickness TA3 of the third semiconductor substrate 71 is, for example, thicker than 180 μm and not more than 400 μm. In the second modified example, the thickness TA1 of the first semiconductor substrate 51 and the thickness TA2 of the second semiconductor substrate 61 are each approximately 180 μm.

[0171] In each embodiment, the contact range of the third bonding material 113 with the insulating chips 70, 70T, and the first insulating chip 70P can be changed as desired. Fig. 20 schematically shows the planar structure of a modified insulating chip 70. Fig. 21 schematically shows a cross-sectional structure of the first die pad 81, the insulating chip 70, and the third bonding material 113 taken along line F21-F21 in Fig. 20 with the insulating chip 70 bonded to the first die pad 81.

[0172] 20 , the third bonding materials 113 are arranged spaced apart from one another in the X direction. That is, the third bonding materials 113 are in partial contact with the lower surface of the third semiconductor substrate 71.

[0173] 21 , each third bonding material 113 is formed so as to widen from the third semiconductor substrate 71 toward the first die pad 81. Each third bonding material 113 is made of an insulating bonding material, similar to the third bonding material 113 of the first embodiment.

[0174] The chip underside 70R of the insulating chip 70 includes a first region R1 that is in contact with the third bonding material 113 and a second region R2 that is not in contact with the third bonding material 113. The second region R2 is in contact with the sealing resin 100 (see FIG. 20 ). That is, the sealing resin 100 is filled between the second region R2 and the die pad 81 in the Z direction.

[0175] This configuration reduces the contact area between the third bonding material 113 and the third semiconductor substrate 71, thereby reducing the combined capacitance of the third semiconductor substrate 71 and the third bonding material 113. This reduces the surge voltage applied to the first coil 41 of the insulating chip 70, thereby improving the surge withstand voltage of the semiconductor device 10.

[0176] Although the third bonding material 113 in the modified example is in contact with the lower surface of the third semiconductor substrate 71 at two locations, this is not limitative. The third bonding material 113 may be in contact with the lower surface of the third semiconductor substrate 71 at three or more locations.

[0177] In the first and third embodiments, the positions of the insulating chips 70 and 70T can be changed as desired. Fig. 22 schematically shows a cross-sectional structure of a semiconductor device 10 according to a modification of the first embodiment.

[0178] 22 , the insulating chip 70 may be mounted on the second die pad 91. The insulating chip 70 is bonded to the second die pad 91 by a third bonding material 113. The third bonding material 113 is interposed between the second die pad 91 and the insulating chip 70. The third bonding material 113 may be, for example, an insulating bonding material. Note that the insulating chip 70T may also be mounted on the second die pad 91 in a similar manner.

[0179] In the first and third embodiments, the semiconductor device 10 may be configured to transmit signals bidirectionally between the first circuit 20 and the second circuit 30. In one example, as shown in FIG. 23 , the semiconductor device 10 includes a first insulating chip 70U that transmits a first signal from the first circuit 20 to the second circuit 30 shown in FIG. 1 , and a second insulating chip 70V that transmits a second signal from the second circuit 30 to the first circuit 20. The first insulating chip 70U and the second insulating chip 70V have, for example, the same configuration as each other. In one example, the first insulating chip 70U and the second insulating chip 70V have the same configuration as the insulating chip 70.

[0180] The first insulating chip 70U includes a transformer 40U. The transformer 40U includes a first coil 41 and a second coil 42 (see FIG. 1 for both). The first coil 41 is electrically connected to the first circuit 20. The second coil 42 is electrically connected to the second circuit 30. The first insulating chip 70U is formed in a rectangular shape with its longer sides in the X direction and its shorter sides in the Y direction in a plan view. Here, the transformer 40U is an example of a "first insulating element." The first coil 41 of the transformer 40U is an example of a "first conductive layer." The second coil 42 of the transformer 40U is an example of a "second conductive layer."

[0181] Similar to the insulating chip 70, the first insulating chip 70U includes a plurality of electrode pads 73 and 74. The plurality of electrode pads 73 are electrically connected to the first coil 41. The plurality of electrode pads 74 are electrically connected to the second coil 42.

[0182] The first insulating chip 70U is mounted on the first die pad 81. The first insulating chip 70U is disposed between the first chip 50 and the second chip 60 in the Y direction. In a plan view, the distance between the first insulating chip 70U and the second chip 60 in the Y direction is greater than the distance between the first insulating chip 70U and the first chip 50 in the Y direction. The first insulating chip 70U is connected to the first chip 50 and the second chip 60. The first insulating chip 70U is disposed offset from the center of the first die pad 81 in the X direction. In the example shown in FIG. 23 , the first insulating chip 70U is disposed closer to the sealing side surface 101 than the center of the first die pad 81 in the X direction.

[0183] The first insulating chip 70U is bonded to the first die pad 81 by a third bonding material 113 (see FIG. 3 ). The bonding mode between the first insulating chip 70U and the first die pad 81 by the third bonding material 113 is the same as the bonding mode between the insulating chip 70 and the first die pad 81 in the first embodiment. An insulating bonding material is used as the third bonding material 113 that bonds the first insulating chip 70U and the first die pad 81. This insulating bonding material is, for example, the same as the third bonding material 113 in the first embodiment.

[0184] The second insulating chip 70V includes a transformer 40V. The transformer 40V includes a first coil 41 and a second coil 42. The first coil 41 is electrically connected to the second circuit 30. The second coil 42 is electrically connected to the first circuit 20. The second insulating chip 70V is formed in a rectangular shape with its long side oriented in the X direction and its short side oriented in the Y direction in a planar view. In one example, the size of the second insulating chip 70V in a planar view is equal to the size of the first insulating chip 70U in a planar view. Here, the transformer 40V is an example of a "second insulating element." The first coil 41 of the transformer 40V is an example of a "third conductive layer." The second coil 42 of the transformer 40V is an example of a "fourth conductive layer."

[0185] Similar to the insulating chip 70, the second insulating chip 70V includes a plurality of electrode pads 73 and 74. The plurality of electrode pads 73 are electrically connected to the first coil 41. The plurality of electrode pads 74 are electrically connected to the second coil 42.

[0186] The second insulating chip 70V is mounted on the second die pad 91. In a plan view, the distance between the second insulating chip 70V and the first chip 50 in the Y direction is greater than the distance between the second insulating chip 70V and the second chip 60 in the Y direction. The second insulating chip 70V is connected to the first chip 50 and the second chip 60. The second insulating chip 70V is disposed offset from the center of the second die pad 91 in the X direction. In the example shown in FIG. 23 , the second insulating chip 70V is disposed closer to the sealing side surface 102 than the center of the second die pad 91 in the X direction. Thus, in a plan view, the first insulating chip 70U and the second insulating chip 70V are disposed offset from each other in the X direction.

[0187] The second insulating chip 70V is bonded to the second die pad 91 by a fourth bonding material 114 (see FIG. 13 ). The bonding mode between the second insulating chip 70V and the second die pad 91 by the fourth bonding material 114 is the same as the bonding mode between the second insulating chip 70Q (see FIG. 13 ) and the second die pad 91 of the second embodiment. The fourth bonding material 114 that bonds the second insulating chip 70V and the second die pad 91 is, for example, a conductive bonding material.

[0188] Note that an insulating bonding material may be used for the fourth bonding material 114. In this case, the insulating bonding material used for the fourth bonding material 114 may be the same insulating bonding material as the third bonding material 113. In other words, the relative dielectric constant of the third bonding material 113 may be equal to the relative dielectric constant of the fourth bonding material 114. Furthermore, the insulating bonding material used for the fourth bonding material 114 may be a different type of insulating bonding material from that of the third bonding material 113. In one example, the insulating bonding material used for the fourth bonding material 114 may be an insulating bonding material having a higher relative dielectric constant than that of the third bonding material 113. In other words, the third bonding material 113 may be an insulating bonding material having a lower relative dielectric constant than that of the insulating bonding material used for the fourth bonding material 114. In other words, the relative dielectric constant of the third bonding material 113 may be lower than that of the fourth bonding material 114.

[0189] The electrode pads 73 of the first insulating chip 70U and the electrode pads 53 of the first chip 50 are individually electrically connected by wires W8. The electrode pads 74 of the first insulating chip 70U and the electrode pads 63 of the second chip 60 are individually electrically connected by wires W9.

[0190] The electrode pads 73 of the second insulating chip 70V and the electrode pads 63 of the second chip 60 are individually electrically connected by wires W10. The electrode pads 74 of the second insulating chip 70V and the electrode pads 53 of the first chip 50 are individually electrically connected by wires W11.

[0191] 23 , for example, a first signal input to a first lead 82 of a first lead frame 80 is input to a first circuit 20 of a first chip 50. Then, the first signal output from the first circuit 20 is input to a second circuit 30 of a second chip 60 via a first coil 41 and a second coil 42 of a transformer 40U of a first insulating chip 70U. Then, the first signal output from the second circuit 30 is output to the outside of the semiconductor device 10 via a second lead 92 of a second lead frame 90.

[0192] 23 , for example, a second signal input to the second lead 92 of the second lead frame 90 is input to the second circuit 30 of the second chip 60. The second signal output from the second circuit 30 is input to the first circuit 20 of the first chip 50 via the first coil 41 and the second coil 42 of the transformer 40V of the second insulating chip 70V. The second signal output from the first circuit 20 is output to the outside of the semiconductor device 10 via the first lead 82 of the first lead frame 80.

[0193] In each embodiment, the types of the first bonding material 111 and the second bonding material 112 can be changed as desired. For example, the first bonding material 111 may be an insulating bonding material, similar to the third bonding material 113. In this case, the insulating bonding material used for the first bonding material 111 may be the same insulating bonding material as the third bonding material 113. In other words, the relative dielectric constant of the third bonding material 113 may be equal to the relative dielectric constant of the first bonding material 111. Furthermore, the insulating bonding material used for the first bonding material 111 may be a different type of insulating bonding material from the third bonding material 113. For example, the insulating bonding material used for the first bonding material 111 may be an insulating bonding material having a higher relative dielectric constant than the third bonding material 113. In other words, the third bonding material 113 may be an insulating bonding material having a lower relative dielectric constant than the insulating bonding material used for the first bonding material 111. That is, the relative dielectric constant of the third bonding material 113 may be less than the relative dielectric constant of the first bonding material 111 .

[0194] In one example, the second bonding material 112 may be an insulating bonding material, similar to the third bonding material 113. In this case, the insulating bonding material used for the second bonding material 112 may be the same insulating bonding material as the third bonding material 113. In other words, the relative dielectric constant of the third bonding material 113 may be equal to the relative dielectric constant of the second bonding material 112. Furthermore, the insulating bonding material used for the second bonding material 112 may be a different type of insulating bonding material from the third bonding material 113. In one example, the insulating bonding material used for the second bonding material 112 may be an insulating bonding material having a higher relative dielectric constant than the third bonding material 113. In other words, the third bonding material 113 may be an insulating bonding material having a lower relative dielectric constant than the insulating bonding material of the second bonding material 112. In other words, the relative dielectric constant of the third bonding material 113 may be lower than the relative dielectric constant of the second bonding material 112.

[0195] In the second embodiment, the type of the fourth bonding material 114 can be changed arbitrarily. For example, the fourth bonding material 114 may be an insulating bonding material, similar to the third bonding material 113. In this case, the insulating bonding material used for the fourth bonding material 114 may be the same insulating bonding material as the third bonding material 113. In other words, the relative dielectric constant of the third bonding material 113 may be equal to the relative dielectric constant of the fourth bonding material 114. Furthermore, the insulating bonding material used for the fourth bonding material 114 may be a different type of insulating bonding material from the third bonding material 113. For example, the insulating bonding material used for the fourth bonding material 114 may be an insulating bonding material having a higher relative dielectric constant than the third bonding material 113. In other words, the third bonding material 113 may be an insulating bonding material having a lower relative dielectric constant than the insulating bonding material used for the fourth bonding material 114. In other words, the relative dielectric constant of the third bonding material 113 may be lower than the relative dielectric constant of the fourth bonding material 114.

[0196] In each embodiment, the configuration of the insulating chip 70 can be changed as desired. In one example, at least one of the passivation film 78 and the resin layer 79 may be omitted from the insulating chip 70. When the passivation film 78 is omitted from the insulating chip 70, the third insulating layer 72 and the resin layer 79 are an example of an "insulator." When the resin layer 79 is omitted from the insulating chip 70, the third insulating layer 72 and the passivation film 78 are an example of an "insulator." When both the passivation film 78 and the resin layer 79 are omitted from the insulating chip 70, the third insulating layer 72 is an example of an "insulator."

[0197] The semiconductor device 10 of each embodiment is not limited to a digital isolator, and may be applied to, for example, an isolated gate driver, an isolated analog-to-digital converter (ADC), an isolated amplifier, or the like.

[0198] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed (mounted) on a second element" means that in some embodiments, the first element may be disposed (mounted) directly on the second element in contact with the second element, but in other embodiments, the first element may be disposed (mounted) above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0199] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described herein being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0200] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0201] [Supplementary Note 1] A first die pad (81) and a second die pad (91) insulated from each other; a first chip (50) mounted on the first die pad (81); a second chip (60) mounted on the second die pad (91); an insulating chip (70) mounted on the first die pad (81) or the second die pad (91) and connected between the first chip (50) and the second chip (60); a first bonding material (111) interposed between the first die pad (81) and the first chip (50) and bonding the first die pad (81) and the first chip (50); a second bonding material (112) interposed between the second die pad (91) and the second chip (60) and bonding the second die pad (91) and the second chip (60); and a third bonding material (113) interposed between the first die pad (81) or the second die pad (91) and the insulating chip (70) and bonding the first die pad (81) or the second die pad (91) to the insulating chip (70), wherein the insulating chip (70) includes: a semiconductor substrate (71); an insulator (72) provided on the semiconductor substrate (71); and insulating elements (40A, 40B) disposed within the insulator (72) and including a first conductive layer (41) and a second conductive layer (42) insulated from each other, wherein the semiconductor substrate (71) is bonded to the first die pad (81) or the second die pad (91) by the third bonding material (113), and the third bonding material (113) is an insulating bonding material.

[0202] [Supplementary Note 2] The semiconductor device according to Supplementary Note 1, wherein the third bonding material (113) is made of an insulating material having a lower dielectric constant than a semiconductor material that constitutes the semiconductor substrate (71).

[0203] [Supplementary Note 3] The semiconductor device according to Supplementary Note 2, wherein the semiconductor substrate (71) of the insulating chip (70) is a Si substrate.

[0204] [Supplementary Note 4] The semiconductor device according to Supplementary Note 2 or 3, wherein the third bonding material (113) is made of an insulating material containing epoxy resin.

[0205] [Supplementary Note 5] The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the third bonding material (113) is made of an insulating material having a relative dielectric constant of less than 12.

[0206] [Appendix 6] The semiconductor device according to any one of appendices 1 to 5, wherein a thickness (TC3) of the third bonding material (113) is greater than thicknesses (TC1, TC2) of the first bonding material (111) and the second bonding material (112).

[0207] [Supplementary Note 7] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the third bonding material (113) is in contact with the semiconductor substrate (71).

[0208] [Appendix 8] The semiconductor device according to any one of Appendices 1 to 7, wherein the third bonding material (113) includes a plurality of third bonding materials (113) spaced apart from each other and bonding the semiconductor substrate (71) to the first die pad (81) or the second die pad (91).

[0209] [Supplementary Note 9] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the first chip (50) includes a first semiconductor substrate (51), the second chip (60) includes a second semiconductor substrate (61), the first semiconductor substrate (51) is bonded to the first die pad (81) by the first bonding material (111), the second semiconductor substrate (61) is bonded to the second die pad (91) by the second bonding material (112), and a thickness (TA3) of the semiconductor substrate (71) of the insulating chip (70) is greater than a thickness (TA1) of the first semiconductor substrate (51) and a thickness (TA2) of the second semiconductor substrate (61).

[0210] [Supplementary Note 10] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the first chip (50) includes a first semiconductor substrate (51), the second chip (60) includes a second semiconductor substrate (61), and a thickness (TA1) of the first semiconductor substrate (51), a thickness (TA2) of the second semiconductor substrate (61), and a thickness (TA3) of the semiconductor substrate (71) of the insulating chip (70) are equal to each other.

[0211] [Appendix 11] The semiconductor device according to any one of claims 1 to 10, wherein the thickness (TA3) of the semiconductor substrate (71) is greater than 180 µm and equal to or less than 400 µm.

[0212] [Appendix 12] The semiconductor device according to any one of Appendices 1 to 11, including: a first insulating chip (70P) as the insulating chip mounted on the first die pad (81); a second insulating chip (70Q) mounted on the second die pad (91); and a fourth bonding material (114) interposed between the second die pad (91) and the second insulating chip (70Q) and bonding the second die pad (91) and the second insulating chip (70Q).

[0213] [Supplementary Note 13] The semiconductor device according to Supplementary Note 12, wherein a thickness (TC3) of the third bonding material (113) is greater than a thickness (TC4) of the fourth bonding material (114).

[0214] [Supplementary Note 14] The semiconductor device according to Supplementary Note 12, wherein a thickness (TC3) of the third bonding material (113) is equal to a thickness (TC4) of the fourth bonding material (114).

[0215] [Supplementary Note 15] The semiconductor device according to any one of Supplementary Notes 12 to 14, wherein the fourth bonding material (114) is a conductive bonding material.

[0216] [Supplementary Note 16] The semiconductor device according to any one of Supplementary Notes 1 to 15, wherein the first bonding material (111) is a conductive bonding material.

[0217] [Supplementary Note 17] The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the second bonding material (112) is a conductive bonding material.

[0218] [Supplementary Note 18] The semiconductor device according to any one of Supplementary Notes 1 to 17, wherein the first conductive layer (41) and the second conductive layer (42) include a coil.

[0219] [Supplementary Note 19] The semiconductor device according to any one of Supplementary Notes 1 to 17, wherein the first conductive layer (151) and the second conductive layer (152) include electrode plates.

[0220] [Supplementary Note 20] The semiconductor device according to any one of Supplementary Notes 1 to 15, wherein the first bonding material (111) is an insulating bonding material.

[0221] [Supplementary Note 21] The semiconductor device according to Supplementary Note 20, wherein the third bonding material (113) has a relative dielectric constant lower than the relative dielectric constant of the first bonding material (111).

[0222] [Supplementary Note 22] The semiconductor device according to Supplementary Note 20, wherein the third bonding material (113) has a relative dielectric constant equal to that of the first bonding material (111).

[0223] [Supplementary Note 23] The semiconductor device according to any one of Supplementary Notes 1 to 22, wherein the second bonding material (112) is an insulating bonding material.

[0224] [Supplementary Note 24] The semiconductor device according to Supplementary Note 23, wherein the third bonding material (113) has a relative dielectric constant lower than the relative dielectric constant of the second bonding material (112).

[0225] [Supplementary Note 25] The semiconductor device according to Supplementary Note 23, wherein the third bonding material (113) has a relative dielectric constant equal to the relative dielectric constant of the second bonding material (112).

[0226] [Appendix 26] The semiconductor device according to any one of Appendices 1 to 25, further comprising a sealing resin (100) that seals the first chip (50), the second chip (60), the first die pad (81), the second die pad (91), the first bonding material (111), the second bonding material (112), and the third bonding material (113).

[0227] [Supplementary Note 27] The semiconductor device according to Supplementary Note 26, wherein the third bonding material (113) has a relative dielectric constant lower than the relative dielectric constant of the sealing resin (100).

[0228] [Supplementary Note 28] The semiconductor device according to Supplementary Note 26, wherein the third bonding material (113) has a relative dielectric constant equal to the relative dielectric constant of the sealing resin (100).

[0229] [Supplementary Note 29] The semiconductor device according to any one of Supplementary Notes 12 to 14, wherein the fourth bonding material (114) is an insulating bonding material.

[0230] [Supplementary Note 30] The semiconductor device according to Supplementary Note 29, wherein the third bonding material (113) has a relative dielectric constant lower than the relative dielectric constant of the fourth bonding material (114).

[0231] [Supplementary Note 31] The semiconductor device according to Supplementary Note 29, wherein the third bonding material (113) has a relative dielectric constant equal to the relative dielectric constant of the fourth bonding material (114).

[0232] [Appendix 32] The semiconductor device according to any one of Appendices 1 to 11, wherein the insulating chip (70) is bonded to the first die pad (81) by the third bonding material (113).

[0233] [Appendix 33] The semiconductor device according to any one of Appendices 1 to 11, wherein the insulating chip (70) is bonded to the second die pad (91) by the third bonding material (113).

[0234] [Supplementary Note 34] The semiconductor device according to any one of Supplementary Notes 1 to 11, comprising: a first insulating chip (70U) as the insulating chip mounted on the first die pad (81); and a second insulating chip (70V) mounted on the second die pad (91), wherein the first chip (50) includes a first circuit (20), and the second chip (60) includes a second circuit (30), the first insulating chip (70U) is connected to the first chip (50) and the second chip (60) and is configured to transmit a first signal output from the first circuit (20) to the second circuit (30), and the second insulating chip (70V) is connected to the first chip (50) and the second chip (60) and is configured to transmit a second signal output from the second circuit (30) to the first circuit (20).

[0235] [Appendix 35] The semiconductor device according to Appendix 34, further comprising a fourth bonding material (114) interposed between the second insulating chip (70V) and the second die pad (91) and bonding the second insulating chip (70V) and the second die pad (91).

[0236] [Supplementary Note 36] The semiconductor device according to Supplementary Note 35, wherein the fourth bonding material (114) is a conductive bonding material.

[0237] [Supplementary Note 37] The semiconductor device according to Supplementary Note 35, wherein the fourth bonding material (114) is an insulating bonding material.

[0238] [Supplementary Note 38] The semiconductor device according to Supplementary Note 37, wherein the third bonding material (113) has a relative dielectric constant lower than the relative dielectric constant of the fourth bonding material (114).

[0239] [Supplementary Note 39] The semiconductor device according to Supplementary Note 37, wherein the third bonding material (113) has a relative dielectric constant equal to the relative dielectric constant of the fourth bonding material (114).

[0240] [Appendix 40] The semiconductor device described in any one of Appendices 34 to 39, wherein, when viewed from the thickness direction (Z) of the first die pad (81), the first insulating chip (70U) and the second insulating chip (70V) are arranged so as to be shifted from each other in a direction (X) perpendicular to the arrangement direction (Y) of the first die pad (81) and the second die pad (91).

[0241] [Appendix 41] The semiconductor device according to any one of Appendices 34 to 40, wherein the first insulating chip (70U) includes a first insulating element (40U) including a first conductive layer (41) and a second conductive layer (42) insulated from each other, and the second insulating chip (70V) includes a second insulating element including a third conductive layer and a fourth conductive layer insulated from each other.

[0242] [Supplementary Note 42] The semiconductor device according to any one of Supplementary Notes 1 to 41, wherein the third bonding material (113) is made of an insulating material having a relative dielectric constant of less than 4.

[0243] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0244] DESCRIPTION OF SYMBOLS 10...Semiconductor device 20...First circuit 21...Transmitting circuit 30...Second circuit 31...Receiving circuit 40A, 40B...Transformer 40U...Transformer 40V...Transformer 41...First coil 42...Second coil 43...Inner region 44...First coil wiring 45...Second coil wiring 46A...Inner end wiring 46B...Outer end wiring 47...Outer dummy wiring 47A...First dummy wiring 47B...Second dummy wiring 47C...Third dummy wiring 48...Floating dummy wiring 48A...First dummy pattern 48B...Second dummy pattern 50...First chip 51...First semiconductor substrate 52...First insulating layer 53...Electrode pad 60...Second chip 61...Second semiconductor substrate 62...Second insulating layer 63...Electrode pad 70...Insulating chip 70A to 70D...First to fourth chip side surfaces 70S...Chip upper surface 70R...Chip lower surface 70P...First insulating chip 70Q...Second insulating chip 70T...Insulating chip 70U...First insulating chip 70V...Second insulating chip 71...Third semiconductor substrate 72...Third insulating layer 73, 74...Electrode pads 73A...First pad 73B...Second pad 75...Insulating film 75A...First insulating film 75B...Second insulating film 75L...Lowermost insulating film 75U...Uppermost insulating film 75P...Insulating film provided with first coil 75Q...Insulating film provided with second coil 78...Passivation film 79...Resin layer 79A...Separation groove 79B...First resin opening 79C...Second resin opening 80...First lead frame 81...First die pad 82...First lead 90... Second lead frame 91... Second die pad 92... Second lead 100... Sealing resin 101-104... Sealing side surface 111... First bonding material 112... Second bonding material 113... Third bonding material 114... Fourth bonding material 121A, 121B... Connection wiring 122A, 122B... First wiring portion 123A, 123B... Second wiring portion 124A... Via 125A, 125B... Connection wiring 126A... Inner end wiring 126B... Outer end wiring 127A... Via 130A, 130B... Transformer 131A, 131B... First transformer 132A, 132B... Second transformer 141A-144A, 141B-144B... First to fourth coils 150A,150B...capacitor 151...first electrode 152...second electrode 161A, 161B...connection wiring 162...first wiring portion 163...second wiring portion W1 to W11...wires TA1...thickness of first semiconductor substrate TA2...thickness of second semiconductor substrate TA3, TA4...thickness of third semiconductor substrate TB1...thickness of first insulating layer TB2...thickness of second insulating layer TB3, TB4...thickness of third insulating layer TC1...thickness of first bonding material TC2...thickness of second bonding material TC3...thickness of third bonding material TC4...thickness of fourth bonding material R1...first region R2...second region,

Claims

1. A semiconductor device comprising a first die pad and a second die pad insulated from each other, a first chip mounted on the first die pad, a second chip mounted on the second die pad, an insulating chip mounted on the first die pad or the second die pad and connected between the first chip and the second chip, a first bonding material interposed between the first die pad and the first chip and bonding the first die pad to the first chip, a second bonding material interposed between the second die pad and the second chip and bonding the second die pad to the second chip, and a third bonding material interposed between the first die pad or the second die pad and the insulating chip and bonding the first die pad or the second die pad to the insulating chip, wherein the insulating chip comprises: a semiconductor substrate; an insulator provided on the semiconductor substrate; and an insulating element disposed within the insulator, the insulating chip including a first conductive layer and a second conductive layer insulated from each other, the semiconductor substrate is bonded to the first die pad or the second die pad by the third bonding material, the third bonding material being an insulating bonding material.

2. The semiconductor device according to claim 1, wherein the third bonding material is made of an insulating material having a lower dielectric constant than a semiconductor material constituting the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein the semiconductor substrate of the insulating chip is a Si substrate.

4. The semiconductor device according to claim 2 or 3, wherein the third bonding material is made of an insulating material containing an epoxy resin.

5. The semiconductor device according to any one of claims 1 to 4, wherein the third bonding material is made of an insulating material having a relative dielectric constant of less than 12.

6. The semiconductor device according to any one of claims 1 to 5, wherein the third bonding material is thicker than the first bonding material and the second bonding material.

7. The semiconductor device according to any one of claims 1 to 6, wherein the third bonding material is in contact with the semiconductor substrate.

8. The semiconductor device according to any one of claims 1 to 7, wherein the third bonding material includes a plurality of third bonding materials spaced apart from each other and bonding the semiconductor substrate to the first die pad or the second die pad.

9. The semiconductor device according to any one of claims 1 to 8, wherein the first chip includes a first semiconductor substrate, the second chip includes a second semiconductor substrate, the first semiconductor substrate is bonded to the first die pad by the first bonding material, and the second semiconductor substrate is bonded to the second die pad by the second bonding material, and a thickness of the semiconductor substrate of the insulating chip is thicker than a thickness of the first semiconductor substrate and a thickness of the second semiconductor substrate.

10. The semiconductor device according to any one of claims 1 to 8, wherein the first chip includes a first semiconductor substrate, the second chip includes a second semiconductor substrate, and the thickness of the first semiconductor substrate, the thickness of the second semiconductor substrate, and the thickness of the semiconductor substrate of the insulating chip are equal to each other.

11. The semiconductor device according to any one of claims 1 to 10, wherein the thickness of the semiconductor substrate is greater than 180 µm and equal to or less than 400 µm.

12. A semiconductor device as claimed in any one of claims 1 to 11, comprising: a first insulating chip as the insulating chip mounted on the first die pad; a second insulating chip mounted on the second die pad; and a fourth bonding material interposed between the second die pad and the second insulating chip, bonding the second die pad and the second insulating chip.

13. The semiconductor device according to claim 12, wherein the third bonding material is thicker than the fourth bonding material.

14. The semiconductor device according to claim 12, wherein the thickness of the third bonding material is equal to the thickness of the fourth bonding material.

15. The semiconductor device according to any one of claims 12 to 14, wherein the fourth bonding material is a conductive bonding material.

16. The semiconductor device according to any one of claims 1 to 15, wherein the first bonding material is a conductive bonding material.

17. The semiconductor device according to any one of claims 1 to 16, wherein the second bonding material is a conductive bonding material.

18. The semiconductor device according to any one of claims 1 to 17, wherein the first conductive layer and the second conductive layer include a coil.

19. The semiconductor device according to any one of claims 1 to 17, wherein the first conductive layer and the second conductive layer include electrode plates.

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