Program compatible with all algorithms

Abstract

[Problem] To enable any algorithm to be executed by a single program without changing the structure of a program, or without adding or deleting a program itself. [Solution] An algorithm is divided into a plurality of processes, each process executes, on the basis of each process data, one structured program on a row-by-row basis of process data for each process, and the first address of a row to be executed is added as data to each process data, thereby continuously constructing a variable data structure.

Description

All algorithm compatible programs

[0001] The present invention relates to a system that uses a programmable logic controller (PLC) that can be programmed to support various algorithms, and a personal computer (PC) that can be programmed to support various algorithms.

[0002] Conventionally, production factories have used devices and equipment to automate production processes. Programmable logic controllers (PLCs) have been used as control devices to electrically control such devices and equipment. In recent years, programmable logic controller (PLC) systems have been constructed and used in which the devices and equipment are interconnected by various cables and complemented by interfaces such as touch panels (TPs), external link I / Os (I / O, Input / Output), various network devices, and personal computers (PCs).

[0003] Among these, for example, Patent Document 1 (Japanese Patent No. 5335128) has been devised, which aims to easily change a control program when changing the order of processes or setting values ​​in equipment that constitutes a plant. Other examples include Patent Document 2 (Japanese Patent No. 5155228), which aims to simplify and shorten engineering work, Patent Document 3 (Japanese Patent No. 6023266), which aims to provide a programmable logic controller (PLC) program management device that variably configures the size of memory blocks allocated to each user program, improves the utilization of unused space, and enables flexible program modification and addition, Patent Document 4 (Japanese Patent Application No. 7-78376), which aims to enable the rapid creation of programs suited to applications and their modification as needed in a robot control system, and Patent Document 5 (Japanese Patent Application No. 14-41125), which aims to reduce the design and creation costs of an operation scheduler that executes unit sequences. Furthermore, in relation to data structures, Patent Document 6 (Patent 4,770,694) has been devised, which aims to efficiently search within data having a data structure consisting of identification information made up of multiple components and information main body associated with the identification information, and Patent Document 7 (Patent 4,884,438) has been devised, which aims to efficiently compress XML (Extensible Markup Language) based documents using a data structure representing a hierarchical tree, the data structure being a content type that can be associated with compression coding technology.

[0004] The idea in Patent Document 1 (Patent 5335128) is divided into an operation control circuit, a process control circuit, a main control circuit, and a process control circuit, but the operation circuit is a general automatic circuit, the process control circuit is a recipe selection circuit and a changeover circuit, the main control circuit is an initial setting circuit, and the process control circuit is a data setting screen control circuit, so there is not much difference from traditional design methods. In other words, it is nothing more than a plant version of the recipe control used in LCD and semiconductor manufacturing. In other words, it is nothing more than a changeover of an automatic process and does not support free process dispersion or convergence.

[0005] In the idea of ​​Patent Document 2 (Patent 5155228), a template is created by pre-determining the form, but for forms that are not pre-determined, a template must be created as before. This difference is merely an attempt to shorten the work. It is the same as a subroutine or function block, except that it is called a template. This idea also does not support the free dispersion or convergence of processes.

[0006] In the invention of Patent Document 3 (Patent 6023266), contiguous memory is divided into blocks of the desired size, such as N, 2N, or 4N, thereby reducing waste. However, the blocks between N and 2N, or between 2N and 4N, are still the same as before, and when a large amount of data is added, they span across the block, making it necessary to define new blocks of N, 2N, or 4N. Furthermore, this does not support cases where the contiguous rows themselves are variable.

[0007] The invention of Patent Document 4 (Japanese Patent Application No. 7-78366) is a robot control system that uses a hierarchical structure rather than plant control, but even if a program can be selected using a hierarchical structure, it is only a partial advantage because robot control requires time and effort to make fine adjustments to match the actual movement, and these adjustments are important. Furthermore, like Patent Documents 1 and 2, this invention does not address the dispersion or convergence of free processes.

[0008] The idea in Patent Document 5 (Japanese Patent Application No. 14-41125) is mostly about plant control, but it attempts to keep development costs low by dividing the program into a unit sequence section that uses current programmable logic controller (PLC) units as units, and an operation scheduler section that uses current stepping circuits and sequential circuits as units, and a parameter buffer that describes the state of the units and operation scheduler, but it has drawbacks such as complicated processing when the unit is constantly monitoring the process or when multiple units are involved at one point.

[0009] The idea in Patent Document 6 (Patent 4770694) is to efficiently search by matching identification information and indexes on a component-by-component basis, and the focus is on the speed of searching data structures, not on data structures for the extensibility of the program itself.

[0010] The invention of Patent Document 7 (Patent 4,884,438) compensates for the shortcomings of conventional techniques, and provides an efficient compression technique for XML-based documents, document skipping capabilities, and a progressive structure, but is not a data structure for the extensibility of the program itself.

[0011] Conventionally, even in the case of plant or robot control, it has been customary to make the control dedicated to that device, i.e., to manufacture it as a one-off, except for a perfect replica device. For this reason, Patent Documents 1 to 5 focus on the field of control and are devised with consideration for versatility in that field, rather than general algorithms. Patent Documents 6 and 7 are devised for efficient search and compression using data structures.

[0012] Patent No. 5335128, Patent No. 5155228, Patent No. 6023266, Patent Application No. 7-78366, Patent Application No. 14-41125, Patent No. 4770694, Patent No. 4884438

[0013] The problem we are trying to solve is that there is a contradiction between being able to support all algorithms without changing the program by simply changing the processing data of each processing program, and setting up a storage area for each processing data. In other words, if an area is set up, an increase in processing data may cause it to span another processing area, making it impossible to support all algorithms. Furthermore, setting up a large area results in wasted memory space.

[0014] Furthermore, the problem to be solved is that when processing data consisting of an arbitrary number of rows and an arbitrary number of columns is executed row by row by a processing program, and if the processing content to be executed requires repetition or branching, the rows of processing data must be created in advance, taking into account the maximum number of repetitions.In other words, once the algorithm is determined, the maximum number of repetitions can be determined, but it is not possible to determine a maximum number of repetitions that can accommodate all algorithms.Similarly, it is not possible to determine the maximum number of maximums for processing in which the number of processing data changes row by row.In addition, memory that does not meet the maximum value becomes wasted memory area.

[0015] Another problem to be solved is that the programmable logic controller (PLC), which writes programs to various algorithms and supports them, and the engineering tool that writes the programs to and controls the PLC are separate. Furthermore, even the connection cables connecting the PLC to the engineering tool vary depending on the manufacturer of the programmable logic controller (PLC), making it difficult to respond quickly on the spot. However, in recent years, while attempts have been made to resolve this issue by standardizing the connection cables and incorporating a single software package for personal computers (PCs), this has also resulted in incompatible versions and other issues. Furthermore, while some external touch panels (TPs) have added features such as add-on memory that allow programs to be added, changed, and deleted, this is merely an auxiliary function.

[0016] Furthermore, the problem to be solved is that in order to support various algorithms, programs tailored to individual algorithms must be created, and sometimes, as necessary, data and constants must be written into a programmable logic controller (PLC) to make the created program executable, which requires program files, data files, comment files, etc., and all of these must be managed every time an individual algorithm is created.

[0017] Furthermore, the problem to be solved is that even if the algorithm is the same, the command words and description methods differ depending on the manufacturer of the programmable logic controller (PLC), so it is necessary to understand the differences in the command words and description methods between manufacturers.

[0018] Furthermore, the problem to be solved is that when a program is added or deleted while it is being executed, the program automatically becomes larger or smaller when it is converted into a format that can be directly executed by the microprocessor (MPU, Micro Processing Unit), so the program may not run reliably depending on where the currently executing program is being executed.In addition, even if the program is executed by watching the monitor, there is a time lag in the monitor itself, and the program may not run reliably, in other words, the size of the program is changed.

[0019] Furthermore, the problem to be solved is that the number of characters in a comment managed in a comment file is generally fixed, and it is not easy to increase the number of characters in a comment. Furthermore, although it is possible to write comments in the microprocessor (MPU) of a programmable logic controller (PLC), there are limitations, and since comments must be written each time, they can be forgotten, which is cumbersome.

[0020] Furthermore, the problem to be solved is that the programs, which differ for each manufacturer of programmable logic controllers (PLCs), are designed with program instructions based on microprocessor (MPU) assembly language, which is the closest to machine language among the programming languages ​​that humans can use in practice. This makes it difficult for people to understand the program instructions based on numerical values ​​such as addresses and instructions. As a result, various notes and comments are set at the expense of the format of separate files and the program capacity, but there is no common way of writing them, and the freedom of the program can actually hinder understanding.

[0021] Another problem we aim to solve is that program creators have too much freedom, making it difficult to understand whether a coil or contact is physically determined, a replacement coil or contact, or a contact or coil that is only necessary for the program's internal connections. Furthermore, because all devices can be freely selected, program creators can use replacement coils or contacts, or choose different coils or contacts depending on the application, further complicating understanding. Furthermore, when a program is constructed hierarchically, the definition of the hierarchy becomes unclear, further complicating understanding. For example, interlock processing is sometimes not placed in the same hierarchy, and conversely, the same interlock processing is used in all hierarchies, resulting in complex programs that are difficult to understand. In other words, program creators can freely incorporate information into programs based on their own mood and thinking, which is one of the reasons why programs vary from program creator to program creator. This problem further develops, preventing complete modifications and changes when someone other than the program creator modifies or changes the program. Furthermore, because complete modifications and changes are not possible, forced additions are made, further complicating the program.

[0022] Furthermore, the problem to be solved is that in recent years, technological innovation has progressed and the role of electrical control has become greater, which has led to larger and more complex programs. As a result, machine designers and plant designers must communicate the intentions, key points, and ingenuity of the design to program designers, which takes a lot of time to get them to understand.

[0023] Furthermore, the problem to be solved is that in recent years, as programs have become larger and more complex, program designers often work together to design programs, spending a lot of time communicating the intentions, key points, and innovations of the design, which increases the probability that confidential information contained in the intentions, key points, and innovations will be leaked.

[0024] Furthermore, the problem to be solved is that the display devices controlled by touch panels (TP) or personal computers (PC) as interfaces have various screen sizes, resolutions, specifications, and character sizes. Therefore, depending on the type of display device used, the character size, and the data control specifications, it is necessary to create many screens when creating a lot of data.

[0025] Another problem we are trying to solve is the inherent nature of digital structures, which makes programs easily duplicable. In recent years, many programs have been distributed across multiple files, each with its own function. While changing only addresses and increasing the number of times a file is used improves the reliability of the program's file structure, from the perspective of machine and plant designers, the labor hours required to design a program differ from the labor hours required to actually design the program. This means that labor hours vary significantly depending on whether the program is constructed by reading the controlled device's manual or whether the program is created once, resulting in higher costs. Furthermore, from the perspective of programmable logic controller (PLC) manufacturers, even if a reference program is modified or changed, it is difficult for those modifications or changes to be reflected. This means that accurate design costs cannot be determined. Another problem is that reference programs are not easily modified or changed.

[0026] Furthermore, the problem to be solved is that the manufacturing equipment that controls the connected devices and equipment is highly confidential, and in general factories, outsiders are prohibited from entering and the manufacturing equipment is not shown, so a manufacturing equipment manufacturer other than the one used for the original machine is used, and the design intent, key points, and ingenious parts are copied cheaply. Therefore, although a process to prohibit copying is carried out using a password, in general factories, because outsiders are prohibited from entering, the analysis process takes time and illegal copying is made.

[0027] The first aspect of the present invention is a data structure characterized in that a microprocessor (MPU) or CPU executes processing according to a purpose based on a plurality of pieces of processing data, each consisting of an arbitrary number of rows and an arbitrary number of columns, of one row of one of the plurality of pieces of processing data, then moves on to the next row and executes processing, and when the rows run out, returns to the first row and continues executing processing, in which, in addition to the processing data of that row, the starting address of the next row and the starting address of the previous row are added to the processing data of that row, and further, if the number of pieces of data in one row of processing data is variable, a variable number of pieces of data are added to the processing data of that row, and further, if the processing content of one row requires repetition or branching, repeat data and processing data for the amount of processing data that is repeated or branched are added to the processing data of that row.

[0028] The first aspect of the present invention is illustrated in Figures 4, 8 to 13, 16 to 20, 38 to 47, 57 and 58 as processing data, migration data, repetition data and number data, and further shows the relationship between data structures.

[0029] A second aspect of the present invention is a program for making a microprocessor (MPU) or CPU execute processing according to a purpose based on the data structure according to the first aspect of the present invention, wherein the plurality of processing data comprises: processing data for input device data processing, which, for each row, compares device data and executes the results by changing the ON / OFF state of a general-purpose bit; processing data for input processing, which, for each row, executes a state of physically arranged input bits by changing the ON / OFF state of a general-purpose bit; processing data for logical processing, which, for each row, replaces the ON / OFF state of a general-purpose bit with a general-purpose bit when a logical product or logical sum of a plurality of general-purpose bits output from another processing becomes true; processing data for sequential step processing, which, for each row, transitions the ON state of a general-purpose bit based on the general-purpose bits output from the other processing, thereby passing and transmitting the execution state of the processing to another row or row of another processing, and executing it; processing data for device data calculation processing, which, for each row, calculates and executes a calculation function provided in the microprocessor (MPU) or CPU using device data or device bits as specified; The program includes at least one of the following processing data: processing data for output processing, which executes, for each row, general-purpose bits output from other processing by changing the ON / OFF state of physically arranged output bits; and processing data for timing processing, which executes, for each row, by changing the ON / OFF state of general-purpose bits over time; and to execute the above processing, the program replaces the selection required for the processing with the numerical value of the processing data, treats the address of the general-purpose bit as processing data, and writes and uses the processing data in multiple modifier registers to execute the processing of that row, then moves on to the next row and executes the processing, and when the row runs out, returns to the first row and continues executing the processing.

[0030] The second aspect of the present invention is illustrated as ladder programs in FIGS. 23 to 34 and 48 to 54, as the overall configuration in FIGS. 55 and 56, and as all the flowcharts in FIGS. 64 to 84.

[0031] The third aspect of the present invention is an interface processing program that uses a touch panel (TP) or a PC as an interface for operating each processing data of the program described in the second aspect of the present invention, and when a display memory area for the part that displays each processing data described in the second aspect of the present invention is reserved in a microprocessor (MPU) or CPU, creates, deletes, adds, and modifies the processing data using the display memory area, and is characterized in that it is further included in the program on the touch panel (TP) or the PC side, or in the program described in the second aspect of the present invention.

[0032] A third aspect of the present invention is illustrated in FIG.

[0033] The fourth aspect of the present invention is an identification and initial processing program that performs identification processing when the power supply is turned on or reset, and controls and stabilizes the processing state to an initial state, wherein unique physical specific data is written into the identification and initial processing program before the identification and initial processing program is written into a microprocessor (MPU) or CPU, and during the identification processing, the written data is compared with the unique physical specific data held by the microprocessor (MPU) or CPU that has been read, and if they do not match, the identification and initial processing program changes the ON / OFF state of a general-purpose bit and transmits a prohibition instruction to each processing program described in the second aspect of the present invention, and is the program described in the second aspect of the present invention, characterized in that a program that does not execute each processing program described in the second aspect of the present invention based on the prohibition instruction from the identification and initial processing program is incorporated into each processing program.

[0034] A fourth aspect of the present invention is illustrated in FIG.

[0035] The effect of the present invention is that processing is performed on processing data in row units, and for multiple processing data consisting of any number of rows and columns, each processing adds or deletes processing data in row units, and since the starting address of the next row and the starting address of the previous row are added to the processing data of that row in addition to the processing data of that row, multiple processing data can be mixed in row units, and even if processing data is added, it will not overlap with other processing.In other words, algorithms can be easily added or deleted without worrying about the area that can be added.

[0036] Furthermore, in order to execute processing on a row-by-row basis and add or delete processing data on a row-by-row basis, the start address of the next row and the start address of the previous row are added to the processing data of that row. By adding a number of items to the processing data, it is no longer necessary to fix the size of the processing unit row, and a variable number of data items can be incorporated. Similarly, by adding repetitive data and the repetitive processing data to the processing data, a repetitive structure can be incorporated within the row. In other words, it is possible to accommodate further changes to the algorithm.

[0037] Furthermore, when building a program that reflects an algorithm, which is a procedure or calculation method for solving a problem, in a programmable logic controller (PLC), the program can be built or changed by changing the processing data without converting it into a program that the programmable logic controller's (PLC's) microprocessor (MPU) can directly execute. Therefore, if the programmable logic controller (PLC) is connected to an input / display device such as an external touch panel (TP) or personal computer (PC) with a standard input screen via a connection cable, the program can be built or changed simply by changing the data on the standard input screen, eliminating the need for an engineering tool. Also, even if the device does not have a standard input screen, some manufacturers have a function that allows device data to be changed from the touch panel (TP), so changes can be made without the need for an engineering tool.

[0038] Furthermore, since the method of constructing or changing a program involves adding, deleting, or changing only the processing data, program files are no longer necessary, making file management easier. However, depending on the manufacturer, some touch panels (TPs) that are not engineering tools but are connected to input / display devices such as external touch panels (TPs) or personal computers (PCs) via a connection cable have the function of reading and writing programs, but these have limitations such as the need for external memory, which can create new problems.

[0039] Furthermore, because each manufacturer of the programmable logic controller (PLC) that creates the program uses different command words and wording such as the format of the values ​​used, the differences between each manufacturer can be absorbed. In other words, even if the equipment is made by different manufacturers in the same factory, when it is connected to an input / display device such as an external touch panel (TP) or personal computer (PC) via a connection cable, the screen has the same structure, so the differences between each manufacturer are reduced.

[0040] Furthermore, even if a program is changed, added, or deleted while it is running, the microprocessor (MPU) of the programmable logic controller (PLC) converts it into a directly executable program format and does not write it. This prevents the program from stopping due to the mistaken deletion of initial settings for loop structures (For-Next syntax) or the mistaken address or label of a jump structure (subroutine call, unconditional jump, conditional jump, etc.). In other words, the program structure is not changed. However, depending on the manufacturer, syntax checks are also performed when the microprocessor (MPU) of the programmable logic controller (PLC) converts it into a directly executable program format. However, even this process can slip through, and depending on the usage method, it is necessary to uncheck this process, which can occasionally cause the program to stop.

[0041] Furthermore, since comments are not managed in maximum number units, memory capacity for comments is not wasted. However, since many manufacturers currently have comment files separate from program files, the manufacturer must change the comment structure. Furthermore, although it depends on the touch panel (TP) manufacturer, it is best to use the comments on the touch panel (TP). However, since comments on the touch panel (TP) cannot be written from the screen, the structure must also be changed.

[0042] Furthermore, by making comments device data, this method alone consumes a lot of data memory, which is its biggest drawback. However, although comments can be written to the microprocessor (MPU) of a programmable logic controller (PLC), there are limitations, and it eliminates the need to write them each time, which is a hassle.

[0043] Furthermore, as a method of constructing or modifying a program, it uses only processing data, and when connected to an input / display device such as an external touch panel (TP) or personal computer (PC) via a connection cable, tables are used on the screen, making it easy to understand visually.

[0044] Furthermore, by using only the processing data as a method for constructing a program, a hierarchical structure is generally constructed when designing a program for a large device, and the hierarchical structure can be divided at the discretion of the program designer, preventing differences in the hierarchical structure depending on the person. Also, even if someone other than the program designer changes the program, the changes can be seen at a glance because the screen is in a table format.

[0045] Furthermore, with the advancement of technological innovation in recent years and the growing role of electrical control, programs have become larger, and mechanical and plant designers can no longer design them on the side. Instead, they have had to communicate the intent, key points, and ingenuity of the design to program designers with programming knowledge. However, if new employees with no programming knowledge within the same company as the mechanical and plant designers can input the data based on design flowcharts, time can be saved, the new employees can understand the equipment and devices, and confidential information will no longer be leaked.

[0046] Furthermore, by creating a display memory, it is possible to provide versatility, since display devices controlled by touch panels (TP) or personal computers (PC) have a variety of screen sizes, resolutions, specifications, and character sizes, and these vary depending on the type of display device used, the character size, and the specifications of the equipment and factory.

[0047] Furthermore, by having the unique physical specific data that a programmable logic controller (PLC) possesses and controlling from the program side whether or not the program will be executed by the programmable logic controller (PLC), it is possible to prevent the program from being executed without changing it. When combined with the ability to control programs by data input, security permissions such as passwords regain their true meaning, and it is possible to protect the rights of programs even in spaces where manufacturing equipment is located and where outsiders can enter.

[0048] In other words, although it is a programmable logic controller (PLC), it is possible to construct and change algorithms simply by changing the data without changing the program, so in simple terms it can be said to be a datable logic controller (DLC) or a datable controller (DC).

[0049] (Explanation of Drawing Classification) Before briefly explaining the drawings, the classification will be described, as the figures span multiple drawings, including Figures 1 to 15. Figures 1 to 3 are basic diagrams of a general embodiment of the present invention. Figure 4 is a memory tree diagram of an embodiment of the present invention. Figures 5 to 54 are related diagrams for operating two motors in an embodiment of the present invention. The detailed classification is further described below, separated by two spaces. Figures 5 to 6 are basic diagrams for operating two motors in an embodiment of the present invention. Figures 7 to 13 are data diagrams related to initial settings in an embodiment of the present invention. Figures 14 to 20 are data diagrams related to various processes for operating two motors in an embodiment of the present invention. Figures 21 to 23 are ladder program circuit diagrams for input processing in a general embodiment of the present invention. Figures 24 to 27 are circuit diagrams of a ladder program for logic processing in a general embodiment according to the present invention. Figures 28 to 30 are circuit diagrams of a ladder program for output processing in a general embodiment according to the present invention. Figures 31 to 34 are circuit diagrams of a ladder program for timing processing in a general embodiment according to the present invention. Figure 35 is a circuit diagram of a ladder program for operating two motors in a general embodiment according to the present invention, with modifications. Figures 36 to 47 are data diagrams related to each process in a general embodiment according to the present invention, with modifications, for operating two motors. Figures 48 to 54 are circuit diagrams of a ladder program for sequential stepping operations in a general embodiment according to the present invention. Figures 55 to 62 are basic conceptual diagrams of an embodiment according to the present invention. Figures 63 to 84 are program flow charts of each process, etc., in an embodiment according to the present invention. The detailed classification is further described below with two spaces inserted at the beginning. Figures 63 to 66 are program flow charts of an embodiment of the present invention, including the initial setting, differential reset of the timing process, start of each process of the same structure, and differential reset of each of the same structure.Figures 67 to 69 are program flowcharts showing the start of execution of the first three processes for each number in one embodiment of the present invention. Figures 70 to 73 are program flowcharts showing interface processing in one embodiment. Figures 74 to 76 are program flowcharts showing logical processing in one embodiment. Figures 77 to 79 are program flowcharts showing sequential step processing in one embodiment. Figure 80 is a program flowchart showing output processing in one embodiment. Figures 81 to 84 are program flowcharts showing timing processing in one embodiment. Figures 85 to 115 are data setting diagrams for all processes set up for a specific servo press device in one embodiment of the present invention. The detailed classifications are further described below, separated by two spaces. Figures 85 and 86 are data setting diagrams for input device data processing and device data calculation processing (input criteria) in one embodiment. 87 and 88 are data setting diagrams for input processing according to one embodiment. FIGS. 89 to 100 are data setting diagrams for logic processing according to one embodiment. FIG. 101 is a data setting diagram for sequential stepping work according to one embodiment. FIGS. 102 to 105 are data setting diagrams for sequential stepping processing in origin return work according to one embodiment. FIGS. 106 and 107 are data setting diagrams for sequential stepping processing in press work according to one embodiment. FIGS. 108 to 113 are data setting diagrams for device data calculation processing (output standard) according to one embodiment. FIGS. 115 and 116 are data setting diagrams for output processing and timing processing according to one embodiment.

[0050] FIG. 1 is a diagram of an electrical control system according to a general embodiment of the present invention; FIG. 2 is a flowchart of a programmable logic controller (PLC) according to a general embodiment of the present invention, including each program and associated processes; FIG. 3 is a relationship diagram of each program according to a general embodiment of the present invention; FIG. 4 is a memory tree diagram according to an embodiment of the present invention; FIG. 5 is a ladder program circuit diagram for operating two motors according to a general embodiment of the present invention; FIG. 6 is a general device memory map for operating two motors according to an embodiment of the present invention; FIG. 7 is an image data diagram displayed on an interface in the initial setting according to an embodiment of the present invention; FIG. 8 is a detailed data diagram of the initial setting of input processing according to an embodiment of the present invention; FIG. 9 is a detailed data diagram of the initial setting of logic processing according to an embodiment of the present invention; FIG. 10 is a detailed data diagram of the initial setting of output processing according to an embodiment of the present invention; FIG. 11 is a detailed data diagram of the initial setting of timing processing according to an embodiment of the present invention; FIG. 12 is a detailed data diagram of the initial setting of sequential stepping work according to an embodiment of the present invention. FIG. 1 is a detailed data diagram of the initial setting of the sequential step processing in one embodiment according to the present invention. FIG. 2 is a diagram of image generic device data displayed on the interface for each process for operating two motors in one embodiment according to the present invention. FIG. 3 is a detailed data diagram of the output processing for operating two motors in one embodiment according to the present invention. FIG. 4 is a detailed data diagram 1 / 2 of the logic processing for operating two motors in one embodiment according to the present invention. FIG. 5 is a detailed data diagram 2 / 2 of the logic processing for operating two motors in one embodiment according to the present invention. FIG. 6 is a detailed data diagram of the output processing for operating two motors in one embodiment according to the present invention. FIG. 7 is a detailed data diagram 1 / 2 of the timing processing for operating two motors in one embodiment according to the present invention. FIG. 8 is a detailed data diagram 2 / 2 of the timing processing for operating two motors in one embodiment according to the present invention. FIG. 9 is a ladder program circuit diagram 1 / 3 of the input processing in one embodiment according to the present invention. FIG. 10 is a ladder program circuit diagram 2 / 3 of the input processing in one embodiment according to the present invention. 3 / 3 is a ladder program circuit diagram for input processing according to one embodiment of the present invention.FIG. 1 is a circuit diagram 1 / 4 of a ladder program for logic processing according to an embodiment of the present invention. FIG. 2 is a circuit diagram 2 / 4 of a ladder program for logic processing according to an embodiment of the present invention. FIG. 3 is a circuit diagram 3 / 4 of a ladder program for logic processing according to an embodiment of the present invention. FIG. 4 / 4 of a ladder program for logic processing according to an embodiment of the present invention. FIG. 1 / 3 of a ladder program for output processing according to an embodiment of the present invention. FIG. 2 / 3 of a ladder program for output processing according to an embodiment of the present invention. FIG. 3 / 3 of a ladder program for output processing according to an embodiment of the present invention. FIG. 1 / 4 of a ladder program for timing processing according to an embodiment of the present invention. FIG. 2 / 4 of a ladder program for timing processing according to an embodiment of the present invention. FIG. 3 / 4 of a ladder program for timing processing according to an embodiment of the present invention. FIG. 4 / 4 of a ladder program for timing processing according to an embodiment of the present invention. FIG. 1 is a general ladder program circuit diagram for one embodiment of the present invention, with modified specifications for operating two motors. FIG. 2 is a diagram of image data 1 / 2 displayed on the interface for each process for one embodiment of the present invention, with modified specifications for operating two motors. FIG. 3 is a diagram of image data 2 / 2 displayed on the interface for each process for one embodiment of the present invention, with modified specifications for operating two motors. FIG. 4 is a diagram of detailed data for logic processing for one embodiment of the present invention, with modified specifications for operating two motors. FIG. 5 is a diagram of detailed data for sequential stepping operations for one embodiment of the present invention, with modified specifications for operating two motors. FIG. 6 is a diagram of detailed data for motor 1 operation for sequential stepping operations for one embodiment of the present invention, with modified specifications for operating two motors. 1 shows a detailed data diagram 2 / 2 of motor 1 operation in a sequential step process with specification modifications for operating two motors in one embodiment according to the present invention. 2 shows a detailed data diagram 1 / 2 of motor 2 operation in a sequential step process with specification modifications for operating two motors in one embodiment according to the present invention.FIG. 2 / 2 is a detailed data diagram of motor 2 operation in sequential step processing with modified specifications for operating two motors in one embodiment according to the present invention. FIG. 3 is a detailed data diagram of output processing with modified specifications for operating two motors in one embodiment according to the present invention. FIG. 1 / 2 is a detailed data diagram of timing processing with modified specifications for operating two motors in one embodiment according to the present invention. FIG. 2 / 2 is a detailed data diagram of timing processing with modified specifications for operating two motors in one embodiment according to the present invention. FIG. 1 / 7 is a ladder program circuit diagram of sequential step processing / processing in one embodiment according to the present invention. FIG. 2 / 7 is a ladder program circuit diagram of sequential step processing / processing in one embodiment according to the present invention. FIG. 3 / 7 is a ladder program circuit diagram of sequential step processing / processing in one embodiment according to the present invention. FIG. 4 / 7 is a ladder program circuit diagram of sequential step processing / processing in one embodiment according to the present invention. FIG. 5 is a ladder program circuit diagram 5 / 7 of sequential stepwise operations and processing according to an embodiment of the present invention. FIG. 6 is a ladder program circuit diagram 6 / 7 of sequential stepwise operations and processing according to an embodiment of the present invention. FIG. 7 is a ladder program circuit diagram 7 / 7 of sequential stepwise operations and processing according to an embodiment of the present invention. FIG. 8 is a flowchart including each program of a programmable logic controller (PLC) and processes associated with the programs according to an embodiment of the present invention. FIG. 9 is a relationship diagram of general-purpose devices and general-purpose device bits in main programs according to an embodiment of the present invention. FIG. 10 is a general-purpose device memory layout diagram used in each program according to an embodiment of the present invention. FIG. 11 is a general-purpose device memory layout diagram in which the general-purpose device memory is rearranged for each process according to an embodiment of the present invention. FIG. 12 is a relationship diagram between the general-purpose device memory for a certain process and the general-purpose device memory for display when a touch panel (TP) is used and the touch panel (TP) has a function for changing the general-purpose device memory for each process according to an embodiment of the present invention.1 is a system relationship diagram between a programmable logic controller (PLC) and an engineering tool for identifying executable programmable logic controllers (PLCs) and allowing execution only on those programmable logic controllers (PLCs) according to one embodiment of the present invention; 2 is a device data setting diagram showing common initial settings according to one embodiment of the present invention; 3 is a device data setting diagram showing initial settings for each program according to one embodiment of the present invention; 4 is a program flowchart diagram showing identification of an initial execution type and start of initial processing according to one embodiment of the present invention; 5 is a program flowchart diagram showing the start of scan execution type processing other than interface processing, sequential stepping processing, and timing processing (each processing has the same structure); 6 is a program flowchart diagram showing the start of differentiation reset (OFF) processing other than timing processing (each processing has the same structure) according to one embodiment of the present invention; 7 is a program flowchart diagram showing the start of execution of processing for each number in input device data processing according to one embodiment of the present invention; FIG. 1 is a program flowchart showing the start of number-specific processing in device data calculation processing (both input and output criteria have the same structure) according to one embodiment of the present invention; FIG. 2 is a program flowchart showing the start of number-specific processing in input processing according to one embodiment of the present invention; FIG. 3 is a program flowchart showing the start of scan execution type interface processing according to one embodiment of the present invention; FIG. 4 is a program flowchart showing the start of number insertion processing in interface processing according to one embodiment of the present invention; FIG. 5 is a program flowchart showing the start of number deletion processing in interface processing according to one embodiment of the present invention; FIG. 6 is a program flowchart showing the start of element count / size increase processing in interface processing according to one embodiment of the present invention; FIG. 7 is a program flowchart showing the start of number-specific processing in logical processing according to one embodiment of the present invention; and FIG. 8 is a program flowchart showing the start of number-specific general-purpose bit output processing in logical processing according to one embodiment of the present invention.FIG. 1 is a program flowchart showing the initiation of a general-purpose bit non-output process for each number in a logic process according to an embodiment of the present invention; FIG. 2 is a program flowchart showing the initiation of a scan execution type sequential step process for each number in a currently running task in a sequential step process according to an embodiment of the present invention; FIG. 3 is a program flowchart showing the initiation of a branch number in a sequential step process for each number in an output process according to an embodiment of the present invention; FIG. 4 is a program flowchart showing the initiation of a periodic cycle type timing process for each number in a timing process according to an embodiment of the present invention; FIG. 5 is a program flowchart showing the initiation of a flashing process for each number in a timing process according to an embodiment of the present invention; FIG. 6 is a program flowchart showing the initiation of an ON delay process for each number in a timing process according to an embodiment of the present invention;

[0051] (Summary Supplement 1) Typically, when a program is created according to an algorithm, it is executed. If the execution result is not good, the program is corrected; if the execution result is good, the program is no longer corrected, and finally, a program that continues to execute is completed. In this invention, an algorithm is realized by starting with an already created program, setting data according to the algorithm into the program, completing the program, executing it, and if the execution result is not good, changing the data; if the execution result is good, the data is no longer changed, and finally, data that continues to execute is completed. The algorithm itself comes in a variety of compound algorithms, such as parallel algorithms, sequential algorithms, parallel and sequential algorithms, and sequential and parallel algorithms, and a data structure corresponding to all of these was required, but this is realized in the first aspect of the present invention. The first aspect of the present invention is a data system in which data consists of rows and columns, and a program is executed based on one row of data. After the last row is executed, the program execution loops back to the beginning and repeats. To allow data with different execution purposes to be mixed row by row, the first address of the next execution row and the first address of the previously executed execution row (to delete the next row) are added to the data, allowing data with the same execution purpose to be searched and executed in the order in which they were arranged in rows. Furthermore, even when the number of data in a row is variable or when repeated processing is performed within a row, this is achieved by adding the first address of the next execution row and the first address of the previously executed execution row (to delete the next row). However, when changing the number of data in a row, a simple change is sufficient; however, when the number of data increases, new space is required, and the first address of the previous row specifying the row must also be rewritten. Address rewriting can be performed automatically by a program or manually. Furthermore, unused and wasted space will inevitably be generated, but this can be dealt with by adding a memory cleaning program, etc. Based on my many years of experience in building program software for programmable logic controllers (PLCs), as long as there is no need to rewrite it in a complicated manner, there should not be any significant waste.This allows us to extend any of the multiple processes on a row-by-row basis, which means we have gained new extensibility. In other words, this data structure is compatible with all algorithms.

[0052] (Supplementary Summary 2) Furthermore, when creating a program, the initial setup program is typically written at the beginning of the program area, followed by the algorithm-based processing program. Subroutine processing is excluded, and finally, the output processing program is written, declaring the program's end. Algorithm-based processing programs are realized in the second aspect of the present invention. Generally, programs are divided into work items (e.g., manual, automatic, return to origin, etc.), and bits and devices are created within the program while providing connections and meaning for each process (e.g., step). In other words, this is comparable to the structured sequential step processing of the second aspect of the present invention. The reason for not generally structuring is that it is difficult to recognize the situation at a glance, making debugging difficult, and programs are not frequently changed. The second aspect of the present invention further includes input device data processing, input processing, logic processing, device data calculation processing, output processing, and timing processing, but these are generally not structured, and are only partially structured, with results written directly where needed without converting them to unified bits. Because the results are not replaced with uniform bits, it may seem like there is no waste, but because it is not a simple replacement, it is also the biggest factor that makes programs complicated. Furthermore, for programmers, addresses are an important element that allows them to assign their own unique meaning to the address, such as odd or even numbers, multiples of a sequence, or multiples of 10, and to play a supplementary role to restricted comments, but since the numbers themselves normally have no meaning, when handling them in an interface, displaying unrestricted comments on the numbers can help to better understand whether they are in line with the algorithm.

[0053] (Supplementary Summary 3) In recent systems using programmable logic controllers (PLCs), touch panels (TPs) or personal computers (PCs) (including engineering tools) are used as interfaces for humans to interact with the equipment, allowing various data settings and changes to the actual addresses of the programmable logic controllers (PLCs). Typically, programmable logic controllers (PLCs), touch panels (TPs), or personal computers (PCs) (including engineering tools) are designed to be dedicated devices, eliminating the need for display memory. However, as in the present invention, which supports various algorithms and comes in various sizes for touch panels (TPs) and personal computers (PCs), the third aspect of the present invention is realized by using a memory buffer function and by modifying only a portion of a row to make the row into complete processing data. Furthermore, providing a basic screen corresponding to the screen size for touch panels (TPs) together with the program of the present invention, or providing the program itself for personal computers (PCs) together with the program of the present invention, would further promote its widespread use.

[0054] (Summary Supplement 4) Once you have this all-algorithm compatible program, there is no longer any need to create a new program. Therefore, if you copy it and transplant it into a different CPU, due to the nature of the factory, it is not possible to tell whether the CPU is running on the copy, so the fourth aspect of this invention is a device to prevent it from starting up from the program side. This requires that the programmable logic controller (PLC) system has at least a general password system built in that prevents the program from being changed, and this ensures that the fourth aspect of this invention can function reliably.

[0055] The following describes embodiments of the present invention with reference to the accompanying drawings. (Preliminary Concept) Figure 1 is a diagram of a typical electrical control system according to one embodiment. It can be said that all facilities or devices are electrically controlled, except for those that utilize traditional wind or water power. Among these, control using rewritable computers is widespread. These computers include microcomputers, personal computers (PCs), and programmable logic controllers (PLCs), and utilize their unique features to control equipment. However, with the rapid advances in technology, the emergence of optical fiber, the increasing speed of CPUs, microprocessors (MPUs), and graphics processing units (GPUs), the exponential increase in memory capacity, the miniaturization of electronic components, the multi-layering of substrates, and fine-machining technology for linewidths are all contributing to the flattening of these features, making the boundaries between them increasingly blurred. Based on the above, Figure 1 shows a typical electrical control equipment diagram for one embodiment. The areas surrounded by dashed lines represent equipment or devices. A represents equipment or devices belonging to Company A, B represents equipment or devices belonging to Company B, C represents equipment or devices belonging to Company C, D represents equipment or devices belonging to Company D, and E represents equipment or devices belonging to Company E. Each company is connected by a network indicated by a thick line (5). In large factories, the core network uses optical fiber, supporting high-speed, high-capacity communications. However, some networks are closed within the facility or equipment, and communication cables are not optical fiber but still use coaxial cables or multi-core cables. 1 represents a programmable logic controller (PLC), 2 represents a touch panel (TP), 3 represents a personal computer (PC), and 4 represents an engineering tool. While it would be easier to manage the programmable logic controller (PLC) (1) and the touch panel (TP) (2) if they were made by the same manufacturer and model, this is not often the case. The personal computer (PC) 3, the engineering tool 4, and the touch panel (TP) 2 are also interfaces (Man Interfaces).

[0056] (Preliminary Concept) Figure 2 is a flowchart showing each program and the associated processes of a programmable logic controller (PLC) according to a typical embodiment of the present invention. Programmable logic controllers (PLCs) from various manufacturers do not differ significantly in specifications and operation. The flowcharts showing each program and the associated processes are also similar. When the power is turned from OFF to ON or from STOP to RUN at 20 in Figure 2, the programmable logic controller (PLC) starts up. First, a program check process is performed at 21. Next, an I / O refresh is performed at 22, and the process proceeds to END process 1 at 23. Then, a group of initial execution-type programs created by the user at 25 are executed in the specified order, and the process proceeds to END process 2 at 24. Next, an I / O refresh is performed (22), followed by END processing 1 (23). The user-created scan execution type programs (26) are executed in the specified order, followed by END processing 2 (24). The process returns to the I / O refresh (22) and is repeated until the power is turned from ON to OFF or from RUN to STOP. The END processing is divided into END processing 1 (23) and END processing 2 (24) because some commands written in the program require processing to be performed before the program. If no such commands are present, only END processing 2 (24) is sufficient. The fixed-cycle execution type programs (27) and the standby type programs (28) are independent programs that are not executed sequentially. Fixed-cycle execution type programs are executed at regular intervals. Standby programs are executed whenever called by each program. Note that some models also offer event execution type programs, which are similar to standby programs and have a wider range of trigger elements. The dashed lines indicate that an interrupt or call is inserted within a normal loop.

[0057] (Preliminary Concept) Figure 3 is a diagram illustrating the relationships between programs in a programmable logic controller (PLC) according to a typical embodiment of the present invention. Although the initial execution type programs 30 and the scan execution type programs 31 in Figure 3 are separated by [END / FEND], they are contiguous and can be considered a single program. Some programmable logic controllers (PLCs) have only one program, rather than being differentiated into the initial execution type program 30, the scan execution type program 31, the periodic execution type program 32, and the standby program 33. Early programmable logic controllers (PLCs) only had a few types of periodic execution type programs, which were handled using a periodic interrupt pointer. Specifically, an interrupt pointer was created, and the circuitry of the pointer was periodically activated, and an [IRET] (interrupt return command) was used to return to normal processing. A similar technique is also used to use a standby program as a subroutine with the pointer as its destination. Furthermore, initial execution type programs that are executed only the first time the power is turned on or from STOP to RUN can achieve the same functionality by simply using a system flag that turns on only the first scan, a conditional jump that combines a system flag that turns off only the first scan, and a pointer that is the destination of the unconditional jump. So why? The reason for grouping programs is to allow programs to be used multiple times as assets, increase reliability, reduce design man-hours, and make them easier for program creators and maintainers to understand. Even in this invention, programs are classified by processing unit, but this does not mean much to anyone who uses the program other than program creators, maintainers, and evaluators.

[0058] Figure 4 is a memory tree diagram of one embodiment of the present invention. The memory tree diagram is subdivided from left to right. The names of memories change depending on the perspective from which the memory is viewed. Figure 4 shows the names of memories as viewed from a programmable logic controller (PLC) incorporating the program of the present invention. The memory is divided into memory within the PLC and memory outside the PLC (external memory). The memory within the PLC is divided into memory within the CPU and memory outside the CPU (buffer memory for each unit), both of which are divided into ROM (Read Only Memory) and RAM (Random Access Memory). The memory outside the CPU varies depending on the specifications of each unit, but both ROM and RAM serve as buffer memory for each unit. The ROM within the CPU is divided into program memory, which stores programs, and data memory. The RAM within the CPU is divided into seven sections: program cache memory, device memory, label memory, function memory, refresh memory, CPU buffer memory, and signal flow memory. The above is a general configuration, and in Figure 4, the device memory is divided into 12 parts (device file memory, device link-related memory, device system-related memory, device timer / counter memory, device general-purpose memory, device latch bit memory, device link-related bit memory, device system-related bit memory, device timer / counter bit memory, device input bit memory, device output bit memory, and device general-purpose bit memory), but this varies depending on the specifications of each company. Note that part of the general-purpose device memory is allocated to the processing data, transfer data, repeat data, and number data of this invention. Note that the memories that can be addressed by a program are generally the buffer memory of each unit, the CPU buffer memory, and the device memory, and the other memories cannot be accessed from the program side.

[0059] Figure 5 is a circuit diagram of a typical ladder program for operating two motors according to one embodiment of the present invention. The input and output bits are the device input bit memory and device output bit memory shown in Figure 4, with addresses determined by hardware. The system bits are device system-related bit memories assigned by the manufacturer. The timer bits are device timer / counter bit memories, with addresses freely selectable by the user. The device timer / counter memory corresponds to the device timer / counter bit memory and stores a set value. This program is intended to help understand the programmable logic controller (PLC) program itself and the purpose of the present invention. This program is for operating two star-delta-started motors. Star-delta starting is a method for starting large-capacity three-phase motors slowly using a star connection, since the starting current is large. After a certain period of time, the motors are switched to a low-current delta connection. Since two motors cannot be operated simultaneously in a star connection, the start switch is disabled while one motor is star-started, preventing the other motor from star-starting. Each motor also has a startup lamp that flashes every 0.5 seconds when it's running in star connection and lights up when it switches to delta connection. For small-scale control like the one above, it's not common to use a programmable logic controller (PLC) that can be configured with input / output units one after another. Instead, it's common to create a relay sequence circuit with three relays and two timer relays for one motor, or to use a small programmable logic controller (PLC) with integrated input / output circuits. However, this configuration was chosen because it's assumed that another device will be added later and a general programmable logic controller (PLC) will be used to control that device.The ladder program circuit diagram in Figure 5 consists of only A contacts, B contacts, and coils, with the signal from the input unit being the input bit, the coil output by the output unit being the output bit, the timer built into the programmable logic controller (PLC) being the timer bit, and the one-second clock built into the programmable logic controller (PLC) being the one-second clock system bit. The PB1 input bit is the start switch for motor 1, the PB2 input bit is the stop switch for motor 1, the TH1 input bit is the thermal trip signal for motor 1, the PB3 input bit is the start switch for motor 2, the PB4 input bit is the stop switch for motor 2, the TH2 input bit is the thermal trip signal for motor 2, the EMS input bit is the emergency stop switch, the MC1 output bit coil is the coil that drives the star start of motor 1, the MC2 output bit coil is the coil that drives the delta start of motor 1, the PL1 output bit is the drive of the starting indicator lamp for motor 1, the MC3 output bit coil is the coil that drives the star start of motor 2, the MC4 output bit coil is the coil that drives the delta start of motor 2, and the PL2 output bit is the drive of the starting indicator lamp for motor 2.

[0060] Each block is described in detail below. The MC1 output bit coil 50 is self-held when the start switch is pressed, and continues to be self-held and activated unless the stop switch is pressed, a thermal trip signal is input, an emergency stop is pressed, switching time measurement is in progress, or motor 2 is in star start mode. The TM1 timer bit coil 51 continues to operate in star start mode, and measurement begins. When the set time of 100 seconds is reached, self-held mode is activated. Unless the stop switch is pressed, a thermal trip signal is input, or an emergency stop switch is pressed, self-held mode continues and the coil is activated. The MC1 output bit coil 52 is activated in delta start mode in accordance with the activation of the TM1 timer. The PL1 output bit coil 53 is repeatedly activated and deactivated every second during star start mode, and remains activated during delta start mode. The MC3 output bit coil (54) is self-held when the start switch is pressed, and remains self-held and activated unless the stop switch is pressed, a thermal trip signal is input, an emergency stop is pressed, switching time measurement is in progress, or motor 1 is in star start mode. The TM2 timer coil (55) continues to operate in star start mode, and when the TM2 timer starts measuring, and reaches the set time of 150 seconds, it becomes self-held. Unless the stop switch is pressed, a thermal trip signal is input, or an emergency stop switch is pressed, it remains self-held and activated. The MC4 output bit coil (56) is activated in delta start mode in accordance with the activation of the TM2 timer bit coil. The PL2 output bit coil (57) is repeatedly activated and deactivated every second during star start mode, and remains activated during delta start mode. The structural command END (58) terminates the program file.

[0061] In order to completely match the ladder program circuit diagram of Figure 5 for operating two motors using this invention, the relevant data is required, and Figures 6 to 20 show a general-purpose device memory map, an image data diagram of the initial settings, detailed data diagrams of each initial setting, an image data diagram of each process, and detailed data diagrams of each process for operating two motors.Since it can handle all algorithms, it is not limited to operating two motors, but ladder program circuit diagrams for input processing, logic processing, output processing, and timing processing used to operate two motors are shown in Figures 21 to 34.

[0062] Figure 6 shows a general-purpose device memory map for driving two motors in one embodiment of the present invention. The general-purpose device memory and general-purpose device bit memory shown in Figure 4 are used. The general-purpose device memory areas are initially set as follows: screen processing from 1800 to 1819, input device data processing from 1820 to 1839, device data calculation processing from 1840 to 1859, input processing from 1860 to 1879, logic processing from 1880 to 1899, sequential stepping operation processing from 1900 to 1939, output processing from 1940 to 1959, and timing processing from 1960 to 1999. The program data area starts at 2000. The general-purpose device bit memory area includes general-purpose bits generated by the program, starting at 0. The numerical values ​​are addresses, tentative, and may be arbitrarily set.

[0063] Figure 7 is an image data diagram displayed on an interface showing the initial settings of one embodiment of the present invention. Because touch panels (TPs), engineering tools, and personal computers (PCs) come in various sizes, the image data diagram displayed on the interface shows the initial settings for input processing, logic processing, output processing, and timing processing required to operate two motors, as well as modified sequential stepping operations and the initial sequential stepping operation settings. While the numerical values ​​are variables and can be changed, the contents are essentially fixed values. Reference numeral 70 denotes the initial setting (input processing) data, 71 denotes the initial setting (logic processing) data, 72 denotes the initial setting (output processing) data, 73 denotes the initial setting (timing processing) data, 74 denotes the initial setting (sequential stepping operation) data, and 75 denotes the initial setting (sequential stepping processing) data.

[0064] FIG. 8 is a detailed data diagram of the initial settings for input processing in one embodiment of the present invention. The left side of the double vertical lines, from top to bottom, contains the TP / PC indicator, value, address, and memory type. Similarly, the items below the double horizontal lines are listed: TP / PC indicator, value, address, and memory type. This is the 70 initial settings (input processing) data in FIG. 7 . The first item to the right of the double vertical lines, the number of input processes, is not included in the 70 initial settings (input processing) data in FIG. 7 . Instead, it is listed at the beginning of the 140 input processing data in FIG. 14 , and after modification, it is listed at the beginning of the 360 ​​input processing data in FIG. 36 . The data below the double horizontal lines contains the data for each item, which are assigned in order starting from address 1860 in FIG. 6 . The second item to the right of the double vertical lines does not contain a TP / PC indicator because it is automatically assigned by the program. The memory types are displayed as external, processing, and transfer, but external refers to memory outside the PLC shown in Fig. 4, processing refers to the processing data (memory) of the device general-purpose memory shown in Fig. 4, and transfer refers to the transfer data (memory) of the device general-purpose memory shown in Fig. 4. The first interval refers to the size of the device selection in Fig. 14, 140 and the size of the device selection in Fig. 15. The second and subsequent intervals in each figure also correspond sequentially.

[0065] FIG. 9 is a detailed data diagram of the initial settings for logical processing in one embodiment of the present invention. The left side of the double vertical lines contains, from top to bottom, the TP / PC indicator, value, address, and memory type. Similarly, the items below the double horizontal lines are listed for the TP / PC indicator, value, address, and memory type. This is the 71 initial setting (logical processing) data in FIG. 7. The first item to the right of the double vertical lines, the number of logical processing operations, is not included in the 71 initial setting (logical processing) data in FIG. 7. Instead, it is listed at the beginning of the 141 logical processing data in FIG. 14, and after modification, it is listed at the beginning of the 361 logical processing data in FIG. 36. The data below the double horizontal lines contains the data for each item, which are assigned in order starting from address 1880 in FIG. 6. The second item to the right of the double vertical lines does not contain a TP / PC indicator because it is automatically assigned by the program. The memory types are shown as external, processing, transition, and repeat. External refers to memory outside the PLC shown in FIG. 4, processing refers to the processing data (memory) of the device general-purpose memory shown in FIG. 4, transition refers to the transition data (memory) of the device general-purpose memory shown in FIG. 4, and repeat data (memory) of the device general-purpose memory shown in FIG. 4. The first interval refers to the size of the general-purpose bit address in FIGS. 14 and 141 and the size of the general-purpose bit address in FIG. 16. The second and subsequent intervals in each figure also correspond sequentially.

[0066] Figure 10 is a detailed data diagram of the initial settings for output processing in one embodiment of the present invention. The left side of the double vertical lines contains, from top to bottom, the TP / PC indicator, value, address, and memory type. Similarly, the items below the double horizontal lines are listed for the TP / PC indicator, value, address, and memory type. This is the 72 initial settings (output processing) data in Figure 7. The first item to the right of the double vertical lines, the number of output processes, is not included in the 72 initial settings (output processing) data in Figure 7, but is listed at the beginning of the 142 output processing data in Figure 14, and after modification, is listed at the beginning of the 371 output processing data in Figure 37. The data below the double horizontal lines contains the data for each item, which are assigned in order starting from address 1940 in Figure 6. The second item to the right of the double vertical lines does not contain a TP / PC indicator because it is automatically assigned by the program. The memory types are shown as external, processing, and transfer, but "external" refers to memory outside the PLC shown in FIG. 4, "processing" refers to the processing data (memory) of the device general-purpose memory shown in FIG. 4, and "transfer" refers to the transfer data (memory) of the device general-purpose memory shown in FIG. 4. The first interval refers to the size of the ON bit address in FIG. 14, 142 and the size of the ON bit address in FIG. 18. The second and subsequent intervals in each figure also correspond sequentially.

[0067] FIG. 11 is a detailed data diagram of the initial setting of the timing process in one embodiment of the present invention. The left side of the double vertical lines, from top to bottom, contains the TP / PC indicator, value, address, and memory type. Similarly, the items below the double horizontal lines are listed: TP / PC indicator, value, address, and memory type. This is the 73 initial setting (timing process) data in FIG. 7 . The first item to the right of the double vertical lines, the number of timing processes, is not included in the 73 initial setting (timing process) data in FIG. 7 . Instead, it is listed at the beginning of the 143 timing process data in FIG. 14 , and after the change, it is listed at the beginning of the 372 timing process data in FIG. 37 . The data below the double horizontal lines contains the data for each item, which are assigned in order starting from address 1960 in FIG. 6 . The second item to the right of the double vertical lines does not contain the TP / PC indicator because it is automatically assigned by the program. The memory types are displayed as external, processing, and transfer, but external refers to memory outside the PLC shown in FIG. 4, processing refers to the processing data (memory) of the device general-purpose memory shown in FIG. 4, and transfer refers to the transfer data (memory) of the device general-purpose memory shown in FIG. 4. The first interval refers to the magnitude of the control selection in FIGS. 14 and 143 and the magnitude of the control selection in FIG. 19. The second and subsequent intervals in each figure also correspond sequentially.

[0068] Figure 12 is a detailed data diagram of the initial settings for sequential step work in one embodiment of the present invention. The left side of the double vertical lines contains, from top to bottom, the TP / PC indicator, value, address, and memory type. Similarly, the items below the double horizontal lines are listed for the TP / PC indicator, value, address, and memory type. This is the 74 initial setting (sequential step work) data in Figure 7 . The first item to the right of the double vertical lines, the number of sequential step work operations, is not included in the 74 initial setting (sequential step work) data in Figure 7 , but is listed at the beginning of the 362 sequential step work data in Figure 36 . The data below the double horizontal lines contains the data for each item, which are assigned in order starting from address 1900 in Figure 6 . The second item to the right of the double vertical lines does not contain a TP / PC indicator because it is automatically assigned by the program. The memory types are displayed as external, processing, and transfer, but external refers to memory outside the PLC shown in FIG. 4, processing refers to processed data (memory) in the device general-purpose memory shown in FIG. 4, and transfer refers to transferred data (memory) in the device general-purpose memory shown in FIG. 4. The first interval refers to the size of the number of processes in FIGS. 36 and 362 and the size of the number of processes in FIG. 40.

[0069] Figure 13 is a detailed data diagram of the initial settings for sequential step processing in one embodiment of the present invention. The left side of the double vertical lines contains, from top to bottom, the TP / PC display, value, address, and memory type, while the below the double horizontal lines contains the same items: TP / PC display, value, address, and memory type. This is the initial setting (sequential step processing) data 75 in Figure 7, but the first item to the right of the double vertical lines, the number of sequential step operations, is not included in the initial setting (sequential step processing) data 74 in Figure 7, but is an item in each row of the sequential step processing data 362 in Figure 36, and is listed either at the beginning of the sequential step processing data 363 for motor 1 operation in Figure 36 or at the beginning of the sequential step processing data 370 for motor 2 operation in Figure 37. Therefore, the value is arbitrary. The below the double horizontal lines contains the data for each item, assigned in order from address 1911 in Figure 6. The second item to the right of the double vertical line does not have a TP / PC indication because it is automatically assigned by the program. The memory types are external, processing, transition, and repeat. External refers to memory outside the PLC shown in FIG. 4, processing refers to the processing data (memory) of the device general-purpose memory shown in FIG. 4, transition refers to the transition data (memory) of the device general-purpose memory shown in FIG. 4, and repeat refers to the repeat data (memory) of the device general-purpose memory shown in FIG. 4. The first interval refers to the size of the absolute condition bit address in FIGS. 36, 363 and 37, 370, and the size of the absolute condition bit address in FIGS. 41 and 43. The second and subsequent items in each figure correspond sequentially.

[0070] Figure 14 shows an image of generic device data displayed on an interface for each process required to operate two motors in one embodiment of the present invention. Because touch panels (TPs), engineering tools, and personal computers (PCs) come in various sizes, the image data displayed on the interface shows the input, logic, output, and timing processes required to operate two motors. The values ​​are variables and can be changed. 140 represents input processing data, 141 represents logic processing data, 142 represents output processing data, and 143 represents timing processing data. This device data was created in a programmable logic controller (PLC) in which the program of the present invention is written to completely match the ladder program circuit diagram for operating two motors shown in Figure 5. However, while the contacts in Figure 5 are configured as input / output devices, they have all been replaced with generic bits to achieve consistency. Typically, to implement an algorithm, a program like the one shown in Figure 5 is written into a programmable logic controller (PLC). However, in this invention, instead of creating a program tailored to the algorithm, device data is created to accommodate changing algorithms. To accommodate the ladder program circuit diagram shown in Figure 5 for operating two motors, an equivalent circuit can be created by setting data for input processing, logic processing, output processing, and timing processing. Because device names vary by manufacturer, the device data shown in Figure 5 is based on a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation. To ensure consistency with the ladder program shown in Figure 5, the input bit is designated X, the system bit is designated SM, and the output bit is designated Y.

[0071] FIG. 14 will be described in detail below with reference to FIG. 5. The creation intent of the input processing data 140 simply defines the input processing, which replaces various device bits with general-purpose bits on a one-to-one basis and outputs the result. In FIG. 5, there are seven input bits, including one system bit. However, since only general-purpose bits can be used in other processing, a system bit that is always ON is added, making a total of nine. Here, the general-purpose bits replaced and output in the input processing are numbered 0 to 8 (in the programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the general-purpose device bit is M), but the numbers are meaningless and can be any value as long as they do not overlap. This is because the general-purpose device memory map in FIG. 6 starts from 0. The order of the numbers is the order of creation, and this also does not have any significant meaning. The creation intent of the logical processing data 141 simply defines the logical processing, which outputs general-purpose bits by activating or deactivating multiple consecutive logical ANDs or consecutive logical ORs. Specifically, in the circuit block 50 of the MC1 output bit coil in Figure 5, this circuit block can be divided into a section where the start switch (contact A) and the MC1 start coil contact (contact A) are continuously connected by a logical AND, a section where the stop switch (contact B), the thermal trip signal (contact B), and the emergency stop switch (contact B) are continuously connected by a logical OR, and a section where the motor 1 star-delta switching time coil contact (contact B) and the MC3 start coil contact (contact B) are continuously connected by a logical OR. These divided sections are further continuously connected by a logical OR, and the output of this general-purpose bit is the MC1 start coil. In this logic processing data, the numbers 1 to 4 are defined, and the output general-purpose bits are 9 to 12 (in the programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the device is designated M). However, since this is a block group, regardless of the order, 9 to 12 are meaningless, and any value can be used as long as they do not overlap.Note that logical processing data Nos. 1 to 4 constitute 50 in FIG. 5, Nos. 5 and 6 constitute 51 in FIG. 5, No. 7 constitutes 52 in FIG. 5, No. 8 constitutes 53 in FIG. 5, Nos. 9 to 12 constitute 54 in FIG. 5, Nos. 13 and 14 constitute 55 in FIG. 5, No. 15 constitutes 56 in FIG. 5, and No. 16 constitutes 57 in FIG. 5. The purpose of creating output processing data 142 is to define the output processing, which replaces general-purpose bits with bits of various devices one-to-one and outputs them. These correspond to the MC1 output bit coil 50, the MC2 output bit coil 52, the PL1 output bit coil 53, the MC3 output bit coil 54, the MC4 output bit coil 56, and the PL2 output bit coil 57 in FIG. 5. Note that the order is meaningless. The purpose of creating the timing process data 143 is to delay a general-purpose bit and output it as another general-purpose bit, or to blink and output it as another general-purpose bit, and so this is simply a definition of that. In Figure 5, this corresponds to the TM1 timer coil 51 with a setting of 100 seconds and the TM1 timer coil 55 with a setting of 150 seconds. Here, the general-purpose bits replaced and output by the timing process are 25 and 26 (in the programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the device is designated M), but the numbers are meaningless and can be any value as long as they do not overlap. The order of the numbers is the order of creation, and this also does not have any significant meaning. However, since only two bits are used here, the order is simply reversed.

[0072] Figure 15 is a detailed data diagram of output processing for driving two motors in one embodiment of the present invention. The left side of the double vertical lines is a grouping of TP / PC display, value, address, and memory type, sandwiched between double horizontal lines. There are five groups, excluding those omitted. The top group, to the right of the double vertical lines, consists of two items: the number of input processes and their numerical values. The remaining four groups, to the right of the double vertical lines, consist of ten items: No., blank, name, blank, blank, device selection, real address (10 / Hex), logic, general-purpose bit address (10 / Hex), and differentiation. Because these items are omitted, and to make the address structure easier to understand, a table of start addresses by number and creation order is attached below each of the five groups, with each row consisting of four items: No., start address, number of words, and creation order. More specifically, input processing data No. 1 starts at address 2000, has 15 words, and is created first. The reason the start address is 2000 is because the program data area in Figure 6 starts at 2000 and it was created first. The number of words varies depending on the name, and since a one-second clock requires six words, it is 15 words. The next input processing data created, No. 2, starts at address 2015, has 13 words, and is created second. The omitted data Nos. 3 through 9 were also created in the same way. This is the same as the input processing data 140 in Figure 15 and Figure 14. However, in Figure 15, Nos. 3 through 8 are omitted, and only three spaces are added to the items. The TP / PC indication is not present because they are automatically assigned by the program. The memory types displayed are external, processing, number, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processing data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0073] Figure 16 is a detailed data diagram 1 / 2 of the logical processing for operating two motors in one embodiment of the present invention. Figure 17 is a detailed data diagram 2 / 2 of the logical processing for operating two motors in one embodiment of the present invention. In Figure 16, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of five groups, excluding those omitted. In Figure 17, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of four groups, excluding those omitted. The right side of the double vertical lines of the top group in Figure 16 consists of two items: the number of input processes and their numerical values. The remaining four groups in Figure 16, to the right of the double vertical lines, span across Figure 17 and consist of 15 items: No., blank, name, blank, blank, general-purpose bit address (10 / Hex), differentiation, logic selection, number of elements, element 1-bit address (10 / Hex), logic, element 2-bit address (10 / Hex), logic, element 3-bit address (10 / Hex), logic. Because of the omissions in Figure 16 and to make the address structure easier to understand, a table of start addresses and creation orders by number is attached below each of the five groups, with each row containing four items: No., start address, number of words, and creation order. More specifically, the logical processing data for No. 1 starts at a start address of 2175, has 20 words, and is tenth in the creation order. The reason the start address is 2175 is because 2175 is the address after the last address 2174, which is ninth in the creation order in Figure 15, and was created tenth. The number of words varies depending on the name, and MC1 requires eight words for self-holding, resulting in a total of 20 words. The next output processing data created, No. 2, starts at address 2195, has 24 words, and is the 11th to be created. The omitted data No. 3 through No. 9 were also created in the same way. Figure 17, which overlaps with Figure 16, is the same as the logical processing data 141 in Figure 14. However, in Figure 17, which overlaps with Figure 16, No. 3 through No. 15 are omitted, and only three spaces are added to the items. There is no TP / PC indication because they are automatically assigned by the program.The memory types displayed are external, number, processing, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processed data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0074] Figure 18 is a detailed data diagram of output processing for driving two motors in one embodiment of the present invention. The left side of the double vertical lines is a grouping of TP / PC display, value, address, and memory type, sandwiched between double horizontal lines. There are five groups, excluding those omitted. The top group, to the right of the double vertical lines, consists of two items: the number of output processes and their numerical values. The remaining four groups, to the right of the double vertical lines, consist of 11 items: No., blank, name, blank, blank, ON bit address (10 / Hex), logic, OFF bit address (10 / Hex), logic, device selection, and real address (10 / Hex). Because these items are omitted, and to make the address structure easier to understand, a table of start addresses by number and creation order is attached below each of the five groups, with each row consisting of four items: No., start address, number of words, and creation order. More specifically, output processing data No. 1 starts at address 2597, has 23 words, and is the 28th in the creation order. The reason for the start address being 2597 is because in Figure 20, which overlaps Figure 19, the address after the last address, 2596, which is the 27th in the creation order, is 2597, making it the 28th to be created. The number of words varies depending on the name, so Motor 1 Start Start (MC1) requires 13 words, making it 23 words. The next created output processing data, No. 2, starts at address 2620, has 23 words, and is the 29th in the creation order. The omitted data Nos. 3 through 9 are also created in the same way. This is the same as the output processing data 142 in Figure 18 and Figure 14. However, in Figure 15, Nos. 3 through 5 are omitted, with only three spaces added to the fields. The TP / PC indication is omitted because they are automatically assigned by the program. The memory types displayed are external, processing, number, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processing data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0075] Figure 19 is a detailed data diagram 1 / 2 of the timing process for operating two motors in one embodiment of the present invention. Figure 20 is a detailed data diagram 2 / 2 of the timing process for operating two motors in one embodiment of the present invention. In Figure 19, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of four groups, excluding those omitted. In Figure 20, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of three groups, excluding those omitted. The right side of the double vertical lines of the top group in Figure 19 consists of two items: the number of timing processes and their numerical values. The remaining three groups in Figure 19, to the right of the double vertical lines, span across Figure 20 and consist of 16 items: No., blank, name, blank, blank, control selection, start bit address (10 / Hex), logic, count stop bit address (10 / Hex), logic, flashing ON time, flashing interval time, elapsed time, general-purpose bit address (10 / Hex), and differentiation. To make the address structure in Figure 19 easier to understand, below each of the four groups is a table showing the start address and creation order by number, with each row containing four items: No., start address, number of words, and creation order. More specifically, the timing processing data for No. 1 starts at address 2539, has 29 words, and is 26th in the creation order. The reason the start address is 2539 is because 2539 is the address following the last address 2538, which is the 25th in the creation order in Figure 17, and was created 26th. The number of words varies depending on the name, so 14 words are required for the motor 1 star-delta switching time, resulting in a total of 29 words. The next created timing processing data, No. 2, starts at address 2568, has 29 words, and is the 27th created. Figure 20, which overlaps with Figure 19, is the same as the timing processing data 142 in Figure 14. The only difference is that three spaces have been added to the item. There is no TP / PC indication because it is automatically assigned by the program.The memory types displayed are external, number, processing, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processed data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0076] (Basic Concept) Before explaining the programs in Figures 21 to 34 and Figures 48 to 54, we will explain the essential modifier registers (denoted as modifier R in each figure) and repeat instructions. Modifier registers are a function that modifies each device data or device bit, allowing its address to be varied. To give a specific example, given an A contact of X0 (in a Mitsubishi Electric programmable logic controller (PLC) the input device is designated X) with a modifier register, setting the modifier register value to 0 results in the A contact of X0, while setting the value to 8 results in the A contact of X8. This modifier register function is a basic function built into programmable logic controller (PLC) manufacturers, regardless of the number of registers that can be used simultaneously. Repeat instructions are a function that repeats a group of instructions between a repeat instruction and a repeat completion instruction a specified number of times. When combined with modifier registers, the program does not require as many programs to be written, reducing the program's description size, but it has the drawback of being constantly changing, making debugging difficult. This repeat command and the repeat structure, which is a structure that performs another repeat within a repeat, are basic functions that programmable logic controller (PLC) manufacturers incorporate, regardless of their numbers.

[0077] FIG. 21 is a first third diagram of a ladder program for input processing according to an embodiment of the present invention. FIG. 22 is a second third diagram of a ladder program for input processing according to an embodiment of the present invention. FIG. 23 is a third third diagram of a ladder program for input processing according to an embodiment of the present invention. In other words, FIGS. 21 through 23 are a series of ladder program circuit diagrams for input processing. This ladder program circuit diagram uses program instructions from a Mitsubishi Electric programmable logic controller (PLC). It changes addresses using a modification register, performs processing for each number, and repeats the processing count with a repeat command. Blocks 210 through 212 are preprocessing blocks, while blocks 214 through 233 perform the processing. Blocks 235 through 238, 239 through 23B, and 23C through 23F are three subroutine programs. Each block is described in detail below. The transition command GOEND 210 does not execute the input processing and transitions to the END of the input processing program if the execution permission contact determined by the identification and initialization program is not activated, or if the number of input processing operations determined by the user is 0. The call command CALL 211 calls and executes the differential reset process. Here, all differential operations are set to "none," so the process is not executed. The transfer command MOV 212 transfers the start address of the input processing data determined by the identification and initialization program to the general-purpose device 1. The repeat command (1) FOR 213 is paired with the repeat command (1) NEXT 233, and here, the number of repetitions is the number of input processing operations. The call command CALL 214 calls and executes the count addition process. An arithmetic instruction + (addition) at 215 adds the interval to the next address number for input processing, which is written in the identification and initial processing program, to the general-purpose device 1 defined at 212, and stores the result in the modification register 20. A transfer instruction MOV at 216 transfers the general-purpose device modified by the modification register 20 to the general-purpose device 2.An arithmetic instruction + (addition) at 217 adds the interval to the device selection address for input processing, which is written in the identification and initialization program, to the modification register 20, and stores the result in the modification register 20. A transfer instruction MOV at 218 transfers the general-purpose device modified by the modification register 20 to modification register 4. An arithmetic instruction + (addition) at 219 adds the interval to the real address for input processing, which is written in the identification and initialization program, to the modification register 20, and stores the result in the modification register 20. A transfer instruction MOV at 21A transfers the general-purpose device modified by the modification register 20 to modification register 1. An arithmetic instruction + (addition) at 21B adds the interval to the logical selection when activating the input processing, which is written in the identification and initialization program, to the modification register 20, and stores the result in the modification register 20. A transfer instruction MOV at 21C transfers the general-purpose device modified by the modification register 20 to modification register 5. The calculation instruction + (addition) in 21D adds the interval to the general-purpose bit address of the input processing described in the identification and initialization program to the modification register 20, and stores the result in the modification register 20. The transfer instruction MOV in 21E transfers the general-purpose device modified by the modification register 20 to the modification register 2. The calculation instruction + (addition) in 21F adds the interval to the differentiation of the input processing described in the identification and initialization program to the modification register 20, and stores the result in the modification register 20. The transfer instruction MOV in 21G transfers the general-purpose device modified by the modification register 20 to the modification register 3. The input-only auxiliary general-purpose bit 1 coil 220 outputs the activation and deactivation levels of the input bit, general-purpose bit, link bit, latch bit, and system bit during device selection. Note that the data is written in words, with 1 representing the input bit, 2 representing the general-purpose bit, 3 representing the link bit, 4 representing the latch bit, and 5 representing the system bit. The logic of the bit is also expressed in words, with 1 being positive logic and 2 being negative logic. The call command CALL 221 calls a subroutine to output the bit-decomposed device and each unit memory at a level.Although not used here, the input-only auxiliary general-purpose bit 2 is activated or deactivated and returned. If the input-only auxiliary general-purpose bit 1 or the input-only auxiliary general-purpose bit 2 is activated by the calculation instruction SET of 222, the general-purpose bit modified by the modification register 2 is activated. This is the final output of this input processing. If differentiation is "yes" by the calculation instruction SET of 223, the input differentiation prohibition general-purpose bit is set at the same time as the final output. Differentiation is also expressed in words, with 1 being "no" and 2 being "yes." If differentiation is "yes", the calculation instruction FIFW of 224 writes modification register 2 to the output differential table following the calculation instruction SET of 72. The calculation instruction RST at 230 deactivates the input-only auxiliary general-purpose bit 1 and the input-only auxiliary general-purpose bit 2, and if the input differentiation prohibition general-purpose bit is active or differentiation is "none," resets (deactivates) the input differentiation prohibition general-purpose bit. This is the final output of this input processing. The calculation instruction RST at 231 simply deactivates the input-only auxiliary general-purpose bit 1 and the input-only auxiliary general-purpose bit 2, and resets the general-purpose bits modified by the modification register. 71 and this are the final output of this input processing. The transfer instruction MOV at 232 transfers general-purpose device 2 to general-purpose device 1 in preparation for repeating. This changes the value of each modification register of the next No. when repeating. The repeat instruction (1) NEXT at 233 is paired with the repeat instruction (1) FOR, and returns to the repeat instruction (1) FOR and repeats the subsequent instructions until the number of repeats is exceeded. The structural instruction FEND of 234 ends the program for this output processing. The number addition processing pointer of 235 is the callee for the call instruction CALL of 214. The arithmetic instruction + (addition) of 236 adds 1 to the general-purpose device 1 and stores it in the modification register 20. The arithmetic instruction + (addition) of 237 adds the modification register 20 to the general-purpose device with the modification register 20 and stores it in the general-purpose device 1. The call is completed by the call back instruction RET of 238, and the program proceeds to the next call instruction of 214. The differential reset processing pointer of 239 is the callee for the call instruction CALL of 211.The subroutine program group for differential reset processing in 23A is not shown because differential differentiation is "none" for all Nos. However, it is sufficient to use the arithmetic instruction FIFR to place the read data in a modifier register and reset the general-purpose bit modified by the modifier register. The call is completed with the recall instruction RET in 23B, and processing proceeds to the next call instruction in 211. The device disassembly bit processing pointer in 23C is for the call instruction CALL in 221. The subroutine program group for device disassembly bit processing in 23D is omitted because it does not use device disassembly bits, but it is possible to create input-only auxiliary general-purpose bits 2 with many classifications by using many move instructions. The call is completed with the recall instruction RET in 23E, and processing proceeds to the next call instruction in 221. The structure instruction END in 23F ends the program file.

[0078] FIG. 24 is a first / fourth diagram of a ladder program circuit for logic processing according to an embodiment of the present invention. FIG. 25 is a second / fourth diagram of a ladder program circuit for logic processing according to an embodiment of the present invention. FIG. 26 is a third / fourth diagram of a ladder program circuit for logic processing according to an embodiment of the present invention. FIG. 27 is a fourth / fourth diagram of a ladder program circuit for logic processing according to an embodiment of the present invention. In other words, FIGS. 24 through 27 are a series of ladder program circuit diagrams for logic processing. This ladder program circuit diagram uses program instructions from a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation. It processes each element of each No. while changing the address using a modifier register. Repeat instructions are used to repeat the process for the number of elements. Once the number of elements has been repeated, the process is repeated for the number of processes. While all logical ANDs are repeated to determine output, logical ORs are terminated and output is generated if even one result is true. Blocks 240 to 242 are preprocessing, while blocks 244 to 265 are the actual processing. Blocks 267 to 26N, 270 to 273, and 274 to 277 are three subroutine programs. Each block is described in detail below. The transition command GOEND at 240 skips the logical processing and transitions to the END of the logical processing program if the execution permission contact determined in the identification and initialization program is not activated, or if the number of logical processing operations determined by the user is zero. The call command CALL at 241 calls and executes the differential reset process. Since all differential operations are set to "none" here, the process is not executed. The transfer command MOV at 242 transfers the starting address of the logical processing data determined in the identification and initialization program to the general-purpose device 1. The repeat instruction (1) FOR 243 is paired with the repeat instruction (1) NEXT 265, and repeats the same number of times as the number of logical operations. The call instruction CALL 244 calls and executes the addition operation of the number.An arithmetic instruction + (addition) at 245 adds the interval to the next number address of the logical processing described in the identification and initialization program to the general-purpose device 1 defined at 242, and stores the result in the modification register 20. A transfer instruction MOV at 246 transfers the general-purpose device modified by the modification register 20 to the general-purpose device 2. An arithmetic instruction + (addition) at 247 adds the interval to the general-purpose bit address of the logical processing described in the identification and initialization program to the modification register 20, and stores the result in the modification register 20. A transfer instruction MOV at 248 transfers the general-purpose device modified by the modification register 20 to the modification register 1. An arithmetic instruction + (addition) at 249 adds the interval to the differential address of the logical processing described in the identification and initialization program to the modification register 20, and stores the result in the modification register 20. A transfer instruction MOV at 24A transfers the general-purpose device modified by the modification register 20 to the modification register 2. An arithmetic instruction + (addition) at 24B adds the interval up to the logic selection of the logical processing described in the identification and initial processing program to the modification register 20, and stores the result in the modification register 20. A transfer instruction MOV at 24C transfers the general-purpose device modified by the modification register 20 to the modification register 4. An arithmetic instruction + (addition) at 24D adds the interval up to the number of elements of the logical processing described in the identification and initial processing program to the modification register 20, and stores the result in the modification register 20. A transfer instruction MOV at 24E transfers the general-purpose device modified by the modification register 20 to the modification register 5. An arithmetic instruction + (addition) at 24F adds the interval up to the element 1-bit address of the logical processing described in the identification and initial processing program to the modification register 20, and stores the result in the general-purpose device 7. The calculation instruction + (addition) at 24G adds the interval up to the logic of element 1 of the logical processing described in the identification and initial processing program to the general-purpose device 7, and stores the result in the general-purpose device 8. The calculation instruction + (addition) at 24H adds the interval of the element 1 bit address and the interval of the logic of the logical processing described in the identification and initial processing program, and stores the result in the general-purpose device 3. The transfer instruction MOV at 24J transfers 0 to the general-purpose device 4.The transfer instruction MOV at 24K transfers 0 to general-purpose device 5. The repeat instruction (2) FOR at 250 is paired with the repeat instruction (2) NEXT at 262, and here, repeats the number of times equal to the value of the general-purpose device modified by modifier register 5. The arithmetic instruction * (multiplication) at 251 multiplies the general-purpose device 3 calculated at 24H by the general-purpose device 4 and stores the result in general-purpose device 6. The arithmetic instruction + (addition) at 252 adds the general-purpose device 6 calculated at 251 to the general-purpose device 7 calculated at 24F and stores the result in modifier register 20. The transfer instruction MOV at 253 transfers the general-purpose device modified by modifier register 20 to modifier register 3. The arithmetic instruction + (addition) at 254 adds the general-purpose device 6 calculated at 251 to the general-purpose device 8 calculated at 24G and stores the result in modifier register 20. The transfer instruction MOV at 255 transfers the general-purpose device modified by the modification register 20 to the modification register 6. The calculation instruction INC at 256 selects logical product, and when an element is activated in the element logic, 1 is added to the general-purpose device 5. The call instruction CALL at 257 selects logical product, and when an element is activated in the element logic for all the elements, an output processing subroutine is called. The move instruction CJ at 258 selects logical product, and when an element is activated in the element logic, a transition is made to the repeat position pointer at 260. The transfer instruction MOV at 259 selects logical product, and when an element is deactivated in the element logic, 0 is transferred to the general-purpose device 5. The call instruction CALL at 25A selects logical product, and when an element is deactivated in the element logic, a non-output processing subroutine is called. The repeat instruction BREAK at 25B selects logical AND, and when the element is deactivated in the element logic, the repeat is canceled and the loop is shifted to the repeat completion position pointer. The call instruction CALL at 25C selects logical OR, and when the element is activated in the element logic, the output processing subroutine is called. The repeat instruction BREAK at 25D selects logical OR, and when the element is activated in the element logic, the repeat is canceled and the loop is shifted to the repeat completion pointer. The call instruction CALL at 25E selects logical OR, and when the element is deactivated in the element logic, the non-output processing subroutine is called.The repeat position pointer 260 is the destination of the move instruction CJ 258. The calculation instruction INC 261 adds 1 to the general-purpose device 4 in preparation for repeating. This changes the value of each modifier register of the next element when repeating. The repeat instruction (2) NEXT 262 is paired with the repeat instruction (2) FOR, and returns to the repeat instruction (2) FOR and repeats the subsequent instructions until the number of repeats is exceeded. The repeat completion position pointer 263 is the destination of the repeat instruction BREAK 25D of 25B. The transfer instruction MOV 264 transfers general-purpose device 2 to general-purpose device 1 in preparation for repeating. This changes the value of each modifier register of the next No. when repeating. The repeat instruction (1) NEXT at 265 is paired with the repeat instruction (1) FOR, and returns to the repeat instruction (1) FOR and repeats the following instructions until the number of repetitions is exceeded. The structural instruction FEND at 266 ends the program for this logical processing. The output processing pointer at 267 is the call destination for the call instructions CALL at 257 and 25C. The calculation instruction SET at 268 sets (activates) the logical auxiliary general-purpose bit when differentiation is "no." The move instruction CJ at 269 moves to the level output pointer when differentiation is "no." The calculation instruction SET at 26A sets (activates) the general-purpose bit modified by the modification register 1 when differentiation is "yes" and the logical differentiation prohibition general-purpose bit is not activated. This is the final output of this logical processing. The calculation instruction SET of 26B sets (activates) the logical differentiation inhibit general-purpose bit following the calculation instruction SET of 26A if differentiation is "enabled" and the logical differentiation inhibit general-purpose bit is not activated. The calculation instruction FIFW of 26C writes the qualification register 2 to the logical differentiation table following the calculation instruction SET of 26B if differentiation is "enabled" and the logical differentiation inhibit general-purpose bit is not activated. The move instruction CJ of 26D moves to the call completion pointer if differentiation is "enabled". The non-output processing pointer of 26E is the call destination for the call instructions CALL of 25A and 25E. The calculation instruction RST of 26F resets (deactivates) the logical auxiliary general-purpose bit if differentiation is "disabled".The move instruction CJ of 26G shifts the level output pointer if differentiation is "no." The calculation instruction RST of 26H resets (deactivates) the logical differentiation prohibition general-purpose bit if differentiation is "yes." The move instruction CJ of 26J shifts the call completion pointer of 26M following the calculation instruction RST. The level output processing pointer of 26K is the destination of the move instructions CJ of 269 and 26G. The general-purpose bit coil modified by the modification register 1 of 26L outputs at a level according to the logical auxiliary general-purpose bit. This is the final output at the level of this logical processing. The call completion pointer of 26M is the destination of the move instructions CJ of 25D and 26J. The call is completed by the call return instruction RET of 26N, and the process moves to the next call instruction corresponding to 257, 25C, 25A, or 25E. The number addition processing pointer 270 is the callee for the call instruction CALL 244. The arithmetic instruction + (addition) 271 adds 1 to general-purpose device 1 and stores it in modifier register 20. The arithmetic instruction + (addition) 272 adds modifier register 20 to the general-purpose device with modifier register 20 and stores it in general-purpose device 1. The call is completed with the callback instruction RET 273, and processing moves to the next call instruction of 244. The differential differentiation reset processing pointer 274 is the callee for the call instruction CALL 241. The differential differentiation reset processing subroutine program group 275 is not shown because differentiation is "none" for all Nos. However, it is only necessary to use the arithmetic instruction FIFR, put the read data into the modifier register, and reset the general-purpose bit modified by the modifier register. A recall instruction RET 276 completes the call and moves to the next instruction after the call instruction 241. A construction instruction END 277 ends the program file.

[0079] Figure 28 is a first third of a ladder program circuit diagram for output processing in one embodiment of the present invention. Figure 29 is a second third of a ladder program circuit diagram for output processing in one embodiment of the present invention. Figure 30 is a third third of a ladder program circuit diagram for output processing in one embodiment of the present invention. In other words, Figures 28 through 30 are a series of ladder program circuit diagrams for output processing. This ladder program circuit diagram uses program instructions from a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation. It changes addresses using a modification register, performs processing for each number, and repeats the processing count with a repeat command. Blocks 280 and 281 are preprocessing before processing, and blocks 283 through 300 perform the processing. Blocks 303 through 305 and 306 through 308 are two subroutine programs. Each block is described in detail below. The transition instruction GOEND 280 does not execute the output processing and transitions to the END of the output processing program if the execution permission node determined by the identification and initialization program and the number of output processing operations determined by the user are 0. The transfer instruction MOV 281 transfers the start address of the output processing data determined by the identification and initialization program to general-purpose device 1. The repeat instruction (1) FOR 282 is paired with the repeat instruction (1) NEXT 301, and in this case, repeats the number of output processing operations. The call instruction CALL 283 calls and executes the addition operation of the number. The arithmetic instruction + (addition) 284 adds the interval to the next number address to the general-purpose device 1 defined in 281 and stores it in the modification register 20. The transfer instruction MOV 285 transfers the general-purpose device modified by the modification register 20 to general-purpose device 2. An arithmetic instruction + (addition) at 286 adds the interval to the ON bit address to the modification register 20 and stores the result in the modification register 20. A transfer instruction MOV at 287 transfers the general-purpose device modified by the modification register 20 to the modification register 1. An arithmetic instruction + (addition) at 288 adds the interval to the ON bit logic to the modification register 20 and stores the result in the modification register 20.The transfer instruction MOV at 289 transfers the general-purpose device modified by the modification register 20 to modification register 4. The arithmetic instruction + (addition) at 28A adds the interval to the OFF bit logic to the modification register 20 and stores it in the modification register 20. The transfer instruction MOV at 28B transfers the general-purpose device modified by the modification register 20 to modification register 2. The arithmetic instruction + (addition) at 28C adds the interval to the OFF bit logic to the modification register 20 and stores it in the modification register 20. The transfer instruction MOV at 28D transfers the general-purpose device modified by the modification register 20 to modification register 5. The arithmetic instruction + (addition) at 28E adds the interval to the device selection to the modification register 20 and stores it in the modification register 20. The transfer instruction MOV at 28F transfers the general-purpose device modified by the modification register 20 to modification register 6. The calculation instruction + (addition) at 28G adds the distance to the real address to the modifier register 20 and stores the result in the modifier register 20. The transfer instruction MOV at 28H transfers the general-purpose device modified by modifier register 20 to modifier register 3. The calculation instruction SET at 290 sets (activates) the output bit modified by modifier register 3 selected in the device selection according to the logic of the ON bit if the general-purpose bit modified by modifier register 1 is activated. The calculation instruction SET at 291 sets (activates) the general-purpose bit modified by modifier register 3 selected in the device selection according to the logic of the ON bit if the general-purpose bit modified by modifier register 1 is activated. The calculation instruction SET at 292 sets (activates) the link bit modified by modifier register 3 selected in the device selection according to the logic of the ON bit if the general-purpose bit modified by modifier register 1 is activated. The calculation instruction SET 293 sets (activates) the latch bit selected in device selection and modified by qualification register 3 according to the logic of the ON bit if the general-purpose bit modified by qualification register 1 is activated. The calculation instruction SET 294 sets (activates) the system bit selected in device selection and modified by qualification register 3 according to the logic of the ON bit if the general-purpose bit modified by qualification register 1 is activated.The call instruction CALL 295 calls a subroutine to set (activate) each resolved value modified by Qualification Register 3 for the bit breakdown of the device and the bit breakdown of each unit memory. It is not used here. The calculation instruction RST 296 resets (deactivates) the output bit modified by Qualification Register 3 selected in device selection according to the logic of the OFF bit if the general-purpose bit modified by Qualification Register 2 is activated. The calculation instruction RST 297 resets (deactivates) the general-purpose bit modified by Qualification Register 3 selected in device selection according to the logic of the OFF bit if the general-purpose bit modified by Qualification Register 2 is activated. The calculation instruction RST 298 resets (deactivates) the link bit modified by Qualification Register 3 selected in device selection according to the logic of the OFF bit if the general-purpose bit modified by Qualification Register 2 is activated. The calculation instruction RST (299) resets (deactivates) the latch bit selected for device selection and modified by Qualification Register 3 according to the logic of the OFF bit if the general-purpose bit modified by Qualification Register 2 is activated. The calculation instruction RST (29A) resets (deactivates) the system bit selected for device selection and modified by Qualification Register 3 according to the logic of the OFF bit if the general-purpose bit modified by Qualification Register 2 is activated. The call instruction CALL (29B) calls a subroutine to reset (deactivate) each resolved value modified by Qualification Register 3 for the bit-resolved device and the bit-resolved unit memory. It is not used here. The transfer instruction MOV (300) transfers general-purpose device 2 to general-purpose device 1. It is paired with the repeat instruction (1) NEXT and repeat instruction (1) FOR (301), and repeats from the repeat instruction (1) FOR until the number of repetitions is exceeded. The program for this output processing is ended by the structural instruction FEND at 302. The number addition processing pointer at 303 is the call destination for the call instruction CALL at 283. The arithmetic instruction + (addition) at 304 adds 1 to the general-purpose device 1 and stores it in the modification register 20.The calculation instruction + (addition) at 305 adds the modifier register 20 to the general-purpose device with modifier register 20 and stores it in general-purpose device 1. The call is completed with the call back instruction RET at 306, and processing moves to the next call instruction at 283. The device disassembly bit set processing pointer at 307 is for the call instruction CALL at 295. The subroutine programs for device disassembly bit set processing at 308 are omitted because they do not use device disassembly bits, but it is possible to set bits for each device in many classifications by making frequent use of move instructions. The call is completed with the call back instruction RET at 309, and processing moves to the next call instruction at 295. The device disassembly bit reset processing pointer at 30A is for the call instruction CALL at 29B. The subroutine program group for device disassembly bit reset processing in 30B is omitted because it does not use device disassembly bits, but it is possible to reset the bits of each device in many classifications by using many move commands. The call is completed with the recall command RET in 30C, and the program moves to the next call command in 29B. The structure command END in 30D ends the program file.

[0080] FIG. 31 is a first / fourth ladder program circuit diagram for counting processing according to an embodiment of the present invention. FIG. 32 is a second / fourth ladder program circuit diagram for counting processing according to an embodiment of the present invention. FIG. 33 is a third / fourth ladder program circuit diagram for counting processing according to an embodiment of the present invention. FIG. 34 is a fourth / fourth ladder program circuit diagram for counting processing according to an embodiment of the present invention. In other words, FIGS. 31 through 34 are a series of ladder program circuit diagrams for counting processing. This ladder program circuit diagram uses program instructions from a Mitsubishi Electric programmable logic controller (PLC). It changes addresses using a modifier register, performs processing for each number, and repeats the process for the number of processes using a repeat command. Blocks 310 and 311 are preprocessing blocks, while blocks 313 through 332 perform the processing. The three subroutine programs are 334 to 337, 338 to 33B, and 340 to 348. Each block is explained in detail below. Note that this program is not a scan-execution type program, but a fixed-period program. Mitsubishi Electric Corporation's programmable logic controllers (PLCs) typically use timers, but because they are not compatible with repetitive commands, a 100 mmsec (0.1 second) fixed-period program is used to measure time. While timers are also available that measure 1 mmsec (0.001 seconds), this program does not use a 0.001 second fixed period, which is rarely used, and therefore is not meaningful. Each block is explained in detail below. The transition command GO END (310) bypasses the counting process and transitions to the END of the counting process program if the execution permission contact determined by the identification and initialization program and the counting process number determined by the user are 0. The transfer command MOV 311 transfers the start address of the clock processing data determined by the identification and initialization program to the general-purpose device 1. The repeat command (1) FOR 312 is paired with the repeat command (1) NEXT 332, and repeats the number of times the clock processing is performed. The call command CALL 313 calls and executes the count addition process.An arithmetic instruction + (addition) at 314 adds the interval to the next address number to general-purpose device 1 defined at 311, and stores the result in modifier register 20. A transfer instruction MOV at 315 transfers the general-purpose device modified by modifier register 20 to general-purpose device 2. An arithmetic instruction + (addition) at 316 adds the interval to the control selection to modifier register 20, and stores the result in modifier register 20. A transfer instruction MOV at 317 transfers the general-purpose device modified by modifier register 20 to modifier register 9. An arithmetic instruction + (addition) at 318 adds the interval to the activation bit address to modifier register 20, and stores the result in modifier register 20. A transfer instruction MOV at 319 transfers the general-purpose device modified by modifier register 20 to modifier register 1. An arithmetic instruction + (addition) at 31A adds the interval to the activation bit logic to modifier register 20, and stores the result in modifier register 20. The transfer instruction MOV at 31B transfers the general-purpose device modified by modifier register 20 to modifier register 10. The arithmetic instruction + (addition) at 31C adds the interval to the count stop bit address to modifier register 20 and stores the result in modifier register 20. The transfer instruction MOV at 31D transfers the general-purpose device modified by modifier register 20 to modifier register 2. The arithmetic instruction + (addition) at 31E adds the interval to the logic of the count stop bit to modifier register 20 and stores the result in modifier register 20. The transfer instruction MOV at 31F transfers the general-purpose device modified by modifier register 20 to modifier register 11. The arithmetic instruction + (addition) at 31G adds the interval to the start address of the blinking ON time to modifier register 20 and stores the result in modifier register 20. The transfer instruction MOV at 31H transfers the general-purpose device modified by modifier register 20 to modifier register 3. The calculation instruction + (addition) at 31J adds the interval to the address of the blinking interval time to the modification register 20 and stores the result in the modification register 20. The transfer instruction MOV at 31K transfers the general-purpose device modified by the modification register 20 to the modification register 4. The calculation instruction + (addition) at 320 adds the interval to the address of the delay time to the modification register 20 and stores the result in the modification register 20.A transfer instruction MOV of 321 transfers the general-purpose device modified by the modification register 20 to modification register 5. An arithmetic instruction + (addition) of 322 adds the interval to the address of the elapsed time to the modification register 20 and stores it in the modification register 20. A transfer instruction MOV of 323 transfers the general-purpose device modified by the modification register 20 to modification register 6. An arithmetic instruction + (addition) of 324 adds the interval to the general-purpose bit address to the modification register 20 and stores it in the modification register 20. A transfer instruction MOV of 325 transfers the general-purpose device modified by the modification register 20 to modification register 7. An arithmetic instruction + (addition) of 326 adds the interval to the differential address to the modification register 20 and stores it in the modification register 20. A transfer instruction MOV of 327 transfers the general-purpose device modified by the modification register 20 to modification register 12. The calculation instruction + (addition) at 328 adds the interval to the address of the differential differentiation prohibition bit to the modification register 20 and stores the result in the modification register 20. The transfer instruction MOV at 329 transfers the general-purpose device modified by the modification register 20 to the modification register 8. The calculation instruction RST at 32A resets (deactivates) the general-purpose bit modified by the modification register 8 according to the logic of the activation bit if the general-purpose bit modified by the modification register 1 is inactivated and the differential differentiation prohibition bit is activated. The calculation instruction RST at 32B resets (deactivates) the general-purpose bit modified by the modification register 7 according to the logic of the activation bit if the general-purpose bit modified by the modification register 1 is inactivated and the general-purpose bit is activated. The transfer instruction MOV at 32C transfers 0 to the general-purpose device modified by the modification register 7 according to the logic of the activation bit if the general-purpose bit modified by the modification register 1 is inactivated and the elapsed time is not 0. The move instruction CJ in 32D moves to the repeat completion pointer when the general-purpose bit modified by the qualification register 1 is inactivated according to the logic of the activation bit. The calculation instruction INC in 32E adds 1 to the general-purpose device modified by the qualification register 6 if the general-purpose bit modified by the qualification register 11 is activated according to the logic of the activation bit, and if the general-purpose bit modified by the qualification register 11 is inactivated according to the logic of the stop bit.The call instruction CALL at 32F activates the general-purpose bit modified by qualifier register 1 according to the logic of the start bit, and inactivates the general-purpose bit modified by qualifier register 11 according to the logic of the stop bit. When blinking processing is selected, the blinking processing subroutine is called. The call instruction CALL at 32G activates the general-purpose bit modified by qualifier register 1 according to the logic of the start bit, and inactivates the general-purpose bit modified by qualifier register 11 according to the logic of the stop bit. When ON delay processing is selected, the ON delay processing subroutine is called. The repeat completion position pointer at 330 is the destination of the move instruction CJ at 32D. The transfer instruction MOV at 331 transfers general-purpose device 2 to general-purpose device 1 in preparation for repeating. This changes the value of each modifier register of the next No. when repeating. The repeat instruction (1) NEXT at 332 is paired with the repeat instruction (1) FOR, and returns to the repeat instruction (1) FOR and repeats the instructions that follow until the number of repeats is exceeded. The structural instruction FEND at 333 ends this logical processing program. The number addition processing pointer at 334 is the call destination for the call instruction CALL at 313. The arithmetic instruction + (addition) at 335 adds 1 to general-purpose device 1 and stores it in modifier register 20. The arithmetic instruction + (addition) at 336 adds modifier register 20 to the general-purpose device with modifier register 20 and stores it in general-purpose device 1. The call is completed by the call back instruction RET at 337, and the program proceeds to the next instruction after the call instruction at 313. The blink processing pointer at 338 is the call destination for the call instruction CALL at 32F. The general-purpose bit coil modified by modification register 7 in 339 is activated if the elapsed time is less than the blinking interval time and less than the blinking ON time. This is the final output by the blinking selection. The transfer command MOV in 33A transfers 0 to the general-purpose device modified by modification register 6 if the elapsed time exceeds the blinking interval time. The call is completed by the callback command RET in 33B, and the process moves to the next call command in 32F. The ON delay processing pointer in 340 is the call destination for the call command CALL in 32G.The general-purpose bit coil modified by the modification register 7 in 341 is activated if the elapsed time exceeds the delay time and differentiation is not performed. This is the final output resulting from the blinking selection. The calculation instruction SET in 342 sets (activates) the general-purpose bit modified by the modification register 7 if the elapsed time exceeds the delay time, differentiation is "enabled," and the logical differentiation prohibition general-purpose bit is not activated. This is the final output resulting from the blinking selection. The calculation instruction FIFW in 343 writes the modification register 7 to the time-counting differentiation table following the calculation instruction SET in 342 if the elapsed time exceeds the delay time, differentiation is "enabled," and the logical differentiation prohibition general-purpose bit is not activated. The calculation instruction FIFW in 344 further writes the constant 2 to the time-counting differentiation table following the calculation instruction FIFW in 343 if the elapsed time exceeds the delay time, differentiation is "enabled," and the logical differentiation prohibition general-purpose bit is not activated. The calculation instruction SET of 345 sets (activates) the general-purpose bit modified by modification register 12 following the calculation instruction FIFW of 33C when the elapsed time exceeds the delay time, differentiation is "enabled," and the logical differentiation prohibition general-purpose bit is not activated. The transfer instruction MOV of 346 transfers the general-purpose device modified by modification register 5 to the general-purpose device modified by modification register 6 when the elapsed time reaches the upper limit value. The call is completed by the recall instruction RET of 347, and processing proceeds to the next call instruction of 32G. The structure instruction END of 348 ends the program file.

[0081] To achieve the equivalent of the ladder program shown in Figure 5, only the input processing ladder program, logic processing ladder program, output processing ladder program, and timing processing ladder program of the present invention are used, and the corresponding data is set. The data corresponding to the input device data processing ladder program and device data calculation ladder program, which are necessary to support all algorithms, can also be created with a structure similar to the input processing ladder program shown in Figures 21 to 23, the logic processing ladder program shown in Figures 24 to 27, the output processing ladder program shown in Figures 28 to 30, and the timing processing ladder program shown in Figures 31 to 34. Both programs perform processing for each number, and are structured to repeat the process for the number of operations using a repeat command. The input device data processing program compares data and activates the resultant bit. Furthermore, if a bit is activated, the device data calculation processing program executes a command set selected by the PLC manufacturer, changing the device data and bits for processing. The bits and device data are stored in a modifier register with address data set.

[0082] (Concept) Here, we will further explain the common structure and definition of each process, comparing it with a typical program. Typical programs began as CPU machine code, essentially assembly language, which had a one-to-one correspondence with machine code that computers could directly interpret. To meet the needs of programmers and users, they gradually evolved into higher-level languages. Current programmable logic controller (PLC) programs are high-level languages ​​that combine powerful relay sequence circuits with assembly language for monitoring. In other words, the ability to structure programs, use interrupt programs frequently, and manage multiple programs is for the convenience of programmers and users; from the CPU's perspective, everything appears as a single program. The program of this invention is also composed of nine core processing programs and three derivative programs, but it can also be created as a single program, or even subdivided. Furthermore, programmable logic controllers (PLCs) often cater to programmers' needs rather than users', and resources such as faster CPUs and cheaper memory have been diverted to structuring for programmers, focusing solely on standardization and consolidation for programmers, further increasing the programmer's freedom. This invention aims to standardize and consolidate the programs themselves, not the programmers, and achieves this by replacing the definitions and allocation specifications of the programmable logic controller (PLC) or the specifications from the flowchart with multiple data. The definitions and allocation specifications of the programmable logic controller (PLC) include the I / O order, counting method, and symbolic names of device bits, which are physically determined by each manufacturer of the programmable logic controller (PLC). The specifications from the flowchart also refer to whether the activation bit, as described above, is positive or negative logic.In addition, multiple data can be specified using modifier registers to specify bits. By substituting bit address data, or by substituting numeric values ​​for case distinction, unification and consolidation can be achieved by substituting numeric values ​​for the symbol names of device data and device bits, positive / negative logic selection, and operation selection. The above substitutions are performed in the order of processing. Processing in the order of processing means that when the input section is activated, it is activated or an operation is performed and output is performed. The input section has three forms: bits, device bits with defined or assigned settings, and device data comparison. All of these can be modified using modifier registers. The output section is a bit that can be modified using modifier registers, and an operation that can be replaced with a numeric value for case distinction. While many operations require subdivision, these are rarely used. By selecting and discarding the current operation instructions, a more ideal program can be created.

[0083] Figure 35 is a modified ladder program circuit diagram for driving two motors in a typical embodiment according to the present invention. Figure 35 is a modified ladder program circuit diagram from Figure 5. The modified specifications were introduced so that when starting Motor 1 and then Motor 2, or when starting Motor 2 and then Motor 1, once either motor was started, the other motor could not be started until the flashing stopped. This change was made because an operator had to be present until the flashing stopped, which was inefficient. An additional change was made to slow down the star-delta switching time for both motors by 10 seconds. The ladder program circuit diagram in Figure 35 consists of only A contacts, B contacts, and coils. It uses the input bit for the signal from the input unit, the output bit for the coil output by the output unit, a general-purpose bit built into the programmable logic controller (PLC), and a timer, and the built-in one-second clock is the one-second clock system bit. Other than the use of the general-purpose bit, the components (PB, MC, etc.) are the same as those in Figure 5. Since 2 seconds does not exist as a system bit, a general-purpose bit is used in a self-holding procedure with a 2-second clock.

[0084] Each block is described in detail below. The 1-second TM1 timer coil 350 starts counting when the TM2 timer is not activated and is activated when the set time of 1 second is reached. The 1-second TM2 timer coil 351 starts counting when the TM1 timer is activated and is activated when the set time of 1 second is reached. The M1 general-purpose bit coil 352 is activated when the TM1 timer is not activated. In other words, it creates a 2-second clock. The M2 general-purpose bit coil 353 is self-holding when the start switch is pressed when motor 1 is not in star start or delta start mode. It continues self-holding and is activated unless the stop switch is pressed, a thermal trip signal is input, or an emergency stop is pressed. The M3 general-purpose bit coil 354 is self-holding and continues to be activated when the M2 general-purpose bit is activated and motor 2 is not in star start mode. The 110-second TM3 timer coil 355 is self-holding when the M2 general-purpose bit is activated and motor 2 is not in star start mode, and starts measuring. It is activated when the set time of 110 seconds is reached. The M4 general-purpose bit coil 356 is self-holding when the start switch is pressed when motor 2 is not in star start mode or delta start mode, and continues self-holding and becomes activated unless the stop switch is pressed, a thermal trip signal is input, or the emergency stop button is pressed. The M5 general-purpose bit coil 357 is self-holding when the M4 general-purpose bit is activated and motor 1 is not in star start mode, and continues self-holding and becomes activated. The 160-second TM4 timer coil 358 is self-holding when the M5 general-purpose bit is activated and motor 1 is not in star start mode, and starts measuring. It is activated when the set time of 160 seconds is reached. The MC1 output bit coil at 359 is active when the M3 general purpose bit is active and the TM3 general purpose timer is inactive. The MC2 output bit coil at 35A is active when the TM3 timer is active.The PL1 output bit coil 35B is activated and deactivated every two seconds when the M2 general-purpose bit is activated and the MC1 and MC2 output bits are deactivated, and is activated and deactivated every second when the MC1 output bit is activated, or is activated when the MC2 output bit is activated. The MC3 output bit coil 35C is activated when the M5 general-purpose bit is activated and the TM4 general-purpose timer is deactivated. The MC4 output bit coil 35D is activated when the TM4 timer is activated. The PL2 output bit coil 35E is activated and deactivated every two seconds when the M4 general-purpose bit is activated and the MC3 and MC4 output bits are deactivated, and is activated and deactivated every second when the MC3 output bit is activated, or is activated when the TM4 timer is activated. Although 35E is supposed to be the same structure as 35B, with the motor changed from 1 to 2, in this case, the timer that activates the MC is used instead of the MC output, in order to achieve the same movement. In other words, this is an example where the creator's choices affect the structure.

[0085] Figure 36 shows image data diagrams 1 / 2 displayed on the interface for each process with a modified specification for operating two motors in one embodiment of the present invention. Figure 37 shows image data diagrams 2 / 2 displayed on the interface for each process with a modified specification for operating two motors in one embodiment of the present invention. That is, Figures 36 and 37 are image data diagrams displayed on the interface for operating two motors with an added procedure. However, rather than the image data displayed on the interface of Figure 14, which is equivalent to the program of Figure 5, the part with the added procedure could of course be created equivalently, but in order to help understand sequential step processing, we have deliberately used image data displayed on the interface realized by sequential step processing. Because this is not created equivalent to Figure 6, we will explain in detail the procedure for creating new data to realize the specifications, including the specifications added in Figure 35, and compare it with the new design of a typical programmable logic controller (PLC) program. When designing a program for a new programmable logic controller (PLC), the hardware circuit (electrical connection diagram) is determined before program design begins, so the first step is to create comments for each input / output address bit. In this invention, we begin by creating part of the input and output processing. We refer to this as "part of the output processing" because when creating new data, the ON and OFF bit addresses of the output processing are not known until the design is complete, so we refer to it as the input portion. The input processing data 360 in Figure 36 is exactly the same as the input processing data 140 in Figure 14. Note that, since input processing data Nos. 1 and 2 are assumed to use a programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, they are system bits (SM in device selection), and Nos. 3 through 9 are input bits (X in device selection). The general-purpose bit 360 can also be determined at this point, but as explained in the detailed explanation of Figure 14, in the programmable logic controller (PLC) manufactured by Mitsubishi Electric Corporation, the general-purpose device bit is M, which is set to 0 to 8 here.This number has no meaning and can be any value as long as it does not overlap. The order of the numbers is the order of creation and does not have any significant significance. Therefore, the number can be determined manually by the data creation system (engineering tool, touch panel (TP), personal computer (PC)). Essentially, the data creation system automatically determines the available addresses. Similarly, the output processing data 371 in FIG. 37 is identical to the output processing data 142 in FIG. 14 in terms of device selection and actual address. At this stage, all settings for the input processing data 360 are complete, and the output portion of the output processing data 371 is complete; no other data is set. Note that with programmable logic controllers (PLCs) other than those manufactured by Mitsubishi Electric Corporation, some devices cannot distinguish between input bits, output bits, and system bits based on device selection, and some even treat all data as 16-bit data (because they are broken down into bits for use). In this case, it is important to note that the function of each bit must be added to the "name" associated with the number. Next, we move on to the core part: designing the specifications. Generally, the specifications are analyzed, and once the analysis is complete, comments are created for the general-purpose device bits. These comments are then used to further draft the specifications and build the program. Here, the specification analysis is the same, but next, the sequential step operation data (362) is set. Since the specification analysis reveals that the basic function is to operate two motors, the number of sequential step operations is set to two, and the names associated with the numbers are set to "Motor 1 Operation" and "Motor 2 Operation." Next, the sequential step processing data for Motor 1 Operation (363) is set. The specification consists of three processes: start acceptance by pressing the start switch, initial start by starting with a star connection, and switching by starting with a delta connection. Since each process simply transitions to the next number, the number of branches associated with the numbers is set to one, and the names are set to "Motor 1 Start Acceptance," "Motor 1 Initial Start," and "Motor 1 Switching." Next, the branch 1 general-purpose bit address and the branch 1 reset bit address associated with No are set.Here, the branch 1 general-purpose bit addresses are set to the numbers 9, 10, and 11 following the input processing, and the branch 1 reset bit addresses are set to the previous numbers except for No. 1. These numbers are meaningless and can be any value as long as they do not overlap, but the branch 1 reset bit address must be the address before the transition. At this stage, the setting of the input processing data (360) is complete, the setting of the sequential stepping operation data (362) is complete, the output data for the output processing data (371) is complete, and the output data for the sequential stepping processing data for motor 1 operation (363) is complete. Next, trigger bits such as the absolute condition bit, activation bit, activation condition bit, branch condition bit, and branch permission bit are constructed for each number of the sequential stepping processing data for motor 1 operation (363). Since no branching occurs, the branch condition bit and branch permission bit for each number are set to 1, so that they do nothing and are always ON. Next, analyzing the absolute condition bits for this process reveals three elements: the stop switch is not pressed, the thermal is not tripped, and the emergency stop switch is not pressed. Therefore, the logical process data 361 is used. At this stage, the general-purpose bit address for the logical process data 361 can be determined, so the number 12, which is the continuation of the sequential step process for motor 1 operation 362, is set to 12. This number also has no meaning, and any value can be used as long as it does not overlap. Next, analyzing the start bits for each No., the start bit for No. 1 is set to 2 because it is the start switch from the input process. The start bit for No. 2 indicates that motor 2 is not star-connected and cannot be determined at this time. The start bit for No. 3, according to the specifications, starts 110 seconds after motor 1 is star-connected, so the timing process data 372 is used. At this stage, the general-purpose bit address for the timing process data 372 can be determined, so the number 13, which is the continuation of the logical process, is set to 13. This number also has no meaning, and can be any value as long as it does not overlap. Also, the start bit of the timing processing data 372 is set to 10 for the initial start of motor 1 in the sequential step processing of motor 1 work 363, and since measurement is not stopped, the count stop bit is set to always ON with negative logic.Note that the control selection for No. 1 is ON delay. Returning to the continuation of the construction of the trigger bits for the sequential step processing data for motor 1 operation (363), we analyze the activation condition bits for each No. The activation condition bit for No. 1 uses the logical processing data (361) with two elements because motor 1 is not activated in star connection, nor is it activated in delta connection. At this stage, the general-purpose bit address for the logical processing data (361) can be determined, so we set it to 14, the number following the timing process. This number is also meaningless, and any value can be used as long as it does not overlap. With the above settings, the ON and OFF bit addresses for No. 1 and No. 2 of the reserved input portion of the output processing data (371) can be set to 10 and 11, respectively, of the sequential step processing data for motor 1 operation (363). To summarize the process up to this stage, the input processing data (360) is complete, the sequential step operation data (362) is complete, the logical processing data (No. 1 and No. 2) (361) is complete, the output processing data (371) is complete for the output portion and the input portion (No. 1 and No. 2) (372), and the sequential step processing data (373) is complete except for No. 2, whose activation condition is that Motor 2 is not star-connected. Next, to complete the control specifications for Motor 1, we must build the lamp control. Since there is only one lamp, the difference is expressed by its lighting or blinking time. A blink every two seconds indicates that the switch is accepted, a blink every one second indicates that the motor is star-connected, and a lit lamp indicates that the motor is delta-connected. Therefore, we will build the logical processing data (361) to address this. Also, although there is a two-second clock system bit, we will deliberately use the blinking control of the timing process. There are three ways to light the lamp, so we set it to No. 3 to No. 5 of the logical processing data of 361. No. 3 indicates the start of MC1, and the general-purpose bit address is set to the next 15. There are two elements, and 10 and 0 are set for the initial start of motor 1 and the one-second clock. No. 4 indicates the acceptance of motor 1 start, and the general-purpose bit address is set to the next 16.The number of elements is two, and the newly created 2-second clock for motor 1 start acceptance is set to 9 and the new 18. The newly created 2-second clock is set to No. 2 in the timing processing data 372, the start bit is set to always ON using positive logic, the count stop bit is set to always ON using negative logic, blinking control is enabled, and the blink ON time and blink interval time are set. At this stage, the input processing data 360 is complete, the logic processing data 361 is complete from No. 1 to No. 5, the sequential stepping work data 362 is complete, the sequential stepping process data for motor 1 work 363 is complete except for the start bit address No. 2, the output processing data 371 is complete except for No. 4 to No. 6 input section settings, and the timing processing data 372 is complete for No. 1 and No. 2. Finally, motor 2 is configured with the same specifications as motor 1. That is, the sequential step processing data for motor 2 operation (370) is set. Since the specifications consist of three processes: start acceptance by pressing the start switch, initial start using star connection, and switching to start using delta connection, and each process simply transitions to the next number, all branch numbers associated with the numbers are set to 1, and the names are set to "Motor 2 start acceptance," "Motor 2 initial start," and "Motor 2 switching." Next, the branch 1 general-purpose bit addresses and branch 1 reset bit addresses associated with the numbers are set. Here, the branch 1 general-purpose bit addresses are set to 19, 20, and 21, which are the continuation numbers of the timing process, and the branch 1 reset bit addresses are set to the previous numbers except for No. 1. These numbers are also meaningless and can be any value as long as they do not overlap; however, the branch 1 reset bit address must be the address before the transition. Here, the start condition for No. 2 in the sequential step processing data for motor 1 operation (363) is set to 20. At this stage, the setting of the input processing data (360) is complete, the setting of the sequential step work data (362) is also complete, the sequential step processing data for motor 1 work (363) is also complete, output processing data No. 1 to No. 3 (371) are complete, output data No. 4 to No. 6 are complete, and timing processing data No. 1 and No. 2 (372) are complete.Next, trigger bits such as absolute condition bits, activation bits, activation condition bits, branch condition bits, and branch permission bits are constructed for each number in the sequential step processing data for motor 2 work (370). Since there is no branching, the branch condition bits and branch permission bits for each number are all set to 1, so that they are always ON and do nothing. Next, analyzing the absolute condition bits for this processing reveals that there are three elements: the stop switch is not pressed, the thermal is not tripped, and the emergency stop switch is not pressed. Therefore, the logical processing data (361) is used. At this stage, the general-purpose bit address for the logical processing data (361) can be determined, so it is set to 22, the number following the sequential step processing for motor 2 work (370). This number also has no meaning, and any value can be used as long as it does not overlap. Next, analyzing the activation bits for each No. reveals that the activation bit for No. 1 is set to 6 because it is a start switch from the input processing. The activation bit for No. 2 is set to 10 because Motor 1 is not star-connected. The activation bit for No. 3 is set to 160 seconds after star-connected activation of Motor 2, so the timing processing data for No. 3 is used. At this stage, the general-purpose bit address for the timing processing data for No. 372 can be determined, so it is set to 23, the number following the logical processing. This number is also meaningless, and any value can be used as long as it does not overlap. Furthermore, the activation bit for No. 372's timing processing data is set to 20, which corresponds to the sequential step processing of Motor 2 operation for No. 370, and the counting stop bit is set to always ON using negative logic because the measurement is never stopped. The control selection for No. 3 is ON delay. Here, we return to the continuation of the construction of the trigger bit for the sequential step processing data for motor 2 operation (370) and analyze the activation condition bit for each No. The activation condition bit for No. 1 shows that motor 2 is not activated in star connection, and is not activated in delta connection either, so we use the logical processing data (361) with two elements. At this stage, we can determine the general-purpose bit address for the logical processing data (361), so we set it to 24, the number following the timing processing. This number also has no meaning, and can be any value as long as it does not overlap.With the above settings, the ON and OFF bit addresses of No. 4 and No. 5 in the reserved input portion of the output processing data 371 can be set to 20 and 21 in the sequential step processing data for motor 2 operation 370. To summarize the process up to this stage, the input processing data 360 is complete, data No. 1 to No. 7 of the logical processing data 361 is complete, the sequential step work data 362 is complete, the sequential step processing data for motor 1 operation 363 is complete, the sequential step processing data for motor 2 operation 370 is complete except for No. 2, whose activation condition is that motor 2 is not star-connected and activated, the output portion data and input portion data No. 1 to No. 5 of the output processing data 371 are complete, and the timing processing data 372 is complete. Next, in order to complete the control specifications for motor 2, lamp control must be constructed. Since there is only one lamp, the differences are expressed by its lighting or blinking time. A two-second blink indicates switch acceptance, a one-second blink indicates the motor is driven by a star connection, and a steady light indicates the motor is driven by a delta connection. Therefore, we will create logical processing data 361 to address this. There are three ways to light the lamp, so we will set logical processing data 361 to bits 8 through 10. No. 8 indicates the start of MC3, and the general-purpose bit address is set to the next bit, 25. Note that there are two elements, and the motor 2 initial start and one-second clock are set to 20 and 0. No. 9 indicates the motor 2 start acceptance, and the general-purpose bit address is set to the next bit, 26. Note that there are two elements, and the motor 2 start acceptance and two-second clock are set to 19 and 18. This completes the setting of all processing data. The processing data is set using address values, but since numerical values ​​are difficult for people to understand intuitively, names may be used as symbols when creating the data.

[0086] Figure 38 is a detailed data diagram 1 / 2 of the logical processing with a modified specification for operating two motors in one embodiment of the present invention. Figure 39 is a detailed data diagram 2 / 2 of the logical processing with a modified specification for operating two motors in one embodiment of the present invention. In Figure 38, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of five groups, excluding those omitted. In Figure 39, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of four groups, excluding those omitted. The right side of the double vertical lines of the top group in Figure 38 consists of two items: the number of input processes and their numerical values. The remaining four groups in Figure 38, to the right of the double vertical lines, span across Figure 39 and consist of 15 items: No., blank, name, blank, blank, general-purpose bit address (10 / Hex), differentiation, logic selection, number of elements, element 1-bit address (10 / Hex), logic, element 2-bit address (10 / Hex), logic, element 3-bit address (10 / Hex), logic. Because of the omissions in Figure 38 and to make the address structure easier to understand, a table of start addresses and change orders by number is attached below each of the five groups, with each row containing four items: No., start address, number of words, and change order. More specifically, the logical processing data for No. 1 starts at a start address of 2759, has 22 words, and is third in the change order. The reason the start address is 2759 is because the address after the last address 2758, which is second in the change order in Figure 40, is 2759, which is the third change order. The number of words varies depending on the name, so the absolute condition for motor 1 requires 8 words, making it 22 words. The next created motor 1 activation condition, No. 2, starts at address 2195, has 24 words, and is the seventh in the change order. The reason the start address is 2195 is because the number of words in the previously created line did not increase, so no new area was needed. Note that the 20 words from 2175 used previously are unused area. Nos. 3 to 9, which are omitted, were also created in the same way.Figure 39, which overlaps with Figure 38, is the same as the logical processing data 361 in Figure 36. However, in Figure 39, which overlaps with Figure 38, No. 3 through No. 9 are omitted, and only three spaces are added to the items. The TP / PC indication is omitted because they are automatically assigned by the program. Note that the memory types are displayed as external, number, processing, and transfer, but "external" refers to memory outside the PLC shown in Figure 4, "processing" refers to the processing data (memory) of the device general-purpose memory shown in Figure 4, "number" refers to the number data (memory) of the device general-purpose memory shown in Figure 4, and "transfer" refers to the transfer data (memory) of the device general-purpose memory shown in Figure 4.

[0087] Figure 40 is a detailed data diagram of sequential stepping operations with modified specifications for operating two motors in one embodiment of the present invention. The left side of the double vertical lines is a grouping of TP / PC display, value, address, and memory type, sandwiched between double horizontal lines, consisting of four groups. The top group, to the right of the double vertical lines, consists of two items: the number of sequential stepping operations and their numerical values. The remaining three groups, to the right of the double vertical lines, consist of 10 items: No., space, name, space, space, number of operations, space. To make the address structure easier to understand, a table of starting addresses and change orders by number is attached below each of the four groups, with each row containing four items: No., starting address, number of words, and change order. Specifically, the sequential stepping operation data for No. 1 starts at address 2735, has 11 words, and is created first. The reason why the first address is 2735 is because the last row created previously in Figure 18 was output processing data No. 6, and the address after the last address 2734 was 2735, making it the first row created. The number of words varies depending on the name, so Motor 1 operation requires 6 words, resulting in 11 words. The next created sequential step work data, No. 2, starts at a first address of 2747, has 11 words, and is second in the change order. This is the same as the sequential step work data 362 in Figure 40 and Figure 36. Note that in Figure 15, the item is simply written with four spaces added. There is no TP / PC indication because it is automatically assigned by the program. The memory types displayed are external, processing, number, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processing data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0088] Figure 41 is a detailed data diagram 1 / 2 of motor 1 operation in sequential step processing with a modified specification for operating two motors in one embodiment of the present invention. Figure 42 is a detailed data diagram 2 / 2 of motor 1 operation in sequential step processing with a modified specification for operating two motors in one embodiment of the present invention. In Figure 41, the left side of the double vertical lines is a group consisting of TP / PC display, value, address, and memory type, from top to bottom, with five groups sandwiched between double horizontal lines and omitted sections. In Figure 42, the left side of the double vertical lines is a group consisting of TP / PC display, value, address, and memory type, from top to bottom, with four groups sandwiched between double horizontal lines and omitted sections. The right side of the double vertical lines of the top group in Figure 41 consists of two items: the number of sequential step processing operations and their numerical values. The remaining four groups in Figure 41, to the right of the double vertical lines, span across Figure 42 and consist of 18 items: No., blank, name, blank, blank, absolute condition bit address (10 / Hex), logic, activation bit address (10 / Hex), logic, activation condition bit address (10 / Hex), logic, number of branches, branch 1 condition bit address (10 / Hex), logic, branch 1 enable bit address (10 / Hex), logic, branch 1 general purpose bit address (10 / Hex), branch 1 reset bit address (10 / Hex). To make the address structure in Figure 41 easier to understand, a table of start addresses and change orders by number is attached below each of the five groups, with each row containing four items: No., start address, number of words, and change order. More specifically, the sequential step processing data for No. 1 starts at a start address of 2781, has 25 words, and is fifth in the change order. The reason why the starting address is 2781 is that in Figures 38 and 39, the address after the last address 2780, which is the third in the change order, is 2781, and the fourth in the change order is No. 1 in Figure 41, which is the fifth in the change order because it was a change with the same address. The number of words varies depending on the name, so the motor 1 start reception requires 8 words, making it 25 words. The next created motor 1 initial start, No. 2, starts at a starting address of 2806, has 25 words, and is sixth in the change order.The reason why the first address is 2781 is because it is a continuation from No. 1. The next created Motor 1 Switch, No. 3, starts at a first address of 2831, has 23 words, and is the eighth in the change order. The reason why the first address is 2831 is because the seventh change in No. 2 in Figures 38 and 39 was the eighth because it was a change with the same address. Figure 42, which overlaps with Figure 41, is the same as the sequential step processing data 363 in Figure 36. Note that in Figure 42, which overlaps with Figure 41, the item is simply written with three spaces added. There is no TP / PC indication because it is automatically assigned by the program. The memory types displayed are external, number, processing, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processed data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0089] Figure 43 is a detailed data diagram 1 / 2 of motor 2 operation, sequential step processing, with a modified specification for operating two motors, according to one embodiment of the present invention. Figure 44 is a detailed data diagram 2 / 2 of motor 2 operation, sequential step processing, with a modified specification for operating two motors, according to one embodiment of the present invention. In Figure 43, the left side of the double vertical lines is a group consisting of TP / PC display, value, address, and memory type, from top to bottom, with five groups sandwiched between double horizontal lines, excluding omitted sections. In Figure 44, the left side of the double vertical lines is a group consisting of TP / PC display, value, address, and memory type, from top to bottom, with four groups sandwiched between double horizontal lines, excluding omitted sections. The right side of the double vertical lines of the top group in Figure 43 consists of two items: the number of sequential step processing operations and their numerical values. The remaining four groups in Figure 43, to the right of the double vertical lines, span across Figure 44 and consist of 18 items: No., blank, name, blank, blank, absolute condition bit address (10 / Hex), logic, activation bit address (10 / Hex), logic, activation condition bit address (10 / Hex), logic, number of branches, branch 1 condition bit address (10 / Hex), logic, branch 1 enable bit address (10 / Hex), logic, branch 1 general purpose bit address (10 / Hex), branch 1 reset bit address (10 / Hex). To make the address structure in Figure 43 easier to understand, a table of start addresses and change orders by number is attached below each of the five groups, with each row containing four items: No., start address, number of words, and change order. More specifically, the sequential step processing data No. 1 has a start address of 2876, 25 words, and is 11th in the change order. The reason why the starting address is 2876 is because the address after the last address 2875, which is the ninth in the change order in Figures 38 and 39, is 2876, and the tenth in the change order is No. 2 in Figure 46, which is the eleventh because it is a change with the same address. The number of words varies depending on the name, so the motor 2 start reception requires eight words, making it 25 words. The next created motor 2 initial start, No. 2, starts at a starting address of 2901, has 25 words, and is 12th in the change order.The reason why the first address is 2901 is because it is a continuation from No. 1. The next created motor 2 switch, No. 3, starts at a first address of 2926, has 23 words, and is 14th in the change order. The reason why the first address is 2926 is because No. 7 in Figures 38 and 39, which is 13th in the change order, is 14th because it is a change with the same address. Figure 44, which overlaps with Figure 43, is the same as the sequential step processing data 370 in Figure 37. Note that in Figure 44, which overlaps with Figure 43, only three spaces are added to the item. There is no TP / PC indication because it is automatically assigned by the program. The memory types displayed are external, number, processing, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processed data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0090] Figure 45 is a detailed data diagram of output processing with modified specifications for driving two motors in one embodiment of the present invention. The left side of the double vertical lines, from top to bottom, is a group of TP / PC display, value, address, and memory type, sandwiched between double horizontal lines. There are five groups, excluding those omitted. The right side of the double vertical lines in the top group consists of two items: the number of output processes and their numerical values. The remaining four groups to the right of the double vertical lines consist of 11 items: No., blank, name, blank, blank, ON bit address (10 / Hex), logic, OFF bit address (10 / Hex), logic, device selection, and real address (10 / Hex). Because these items are omitted, and to make the address structure easier to understand, a table showing the start address and change order by number is attached below each of the five groups, with each row containing four items: No., start address, number of words, and creation order. More specifically, output processing data No. 1 starts at address 2597, has 23 words, and is the 22nd in the change order. The reason the start address is 2597 is because all addresses and names are the same, including those in Figure 18. This is the same as output processing data 371 in Figure 45 and Figure 37. However, in Figure 45, Nos. 3 to 5 are omitted, and only three spaces are added to the items. The TP / PC indication is omitted because they are automatically assigned by the program. Note that the memory types are displayed as external, processing, number, and transfer. External refers to memory outside the PLC shown in Figure 4, processing refers to the processing data (memory) of the device general-purpose memory shown in Figure 4, number refers to the number data (memory) of the device general-purpose memory shown in Figure 4, and transfer refers to the transfer data (memory) of the device general-purpose memory shown in Figure 4.

[0091] Figure 46 is a detailed data diagram 1 / 2 of a timing process with a modified specification for operating two motors in one embodiment of the present invention. Figure 47 is a detailed data diagram 2 / 2 of a timing process with a modified specification for operating two motors in one embodiment of the present invention. In Figure 46, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of four groups, excluding those omitted. In Figure 47, the left side of the double vertical lines is a group of TP / PC display, value, address, and memory type, from top to bottom, sandwiched between double horizontal lines, and consists of three groups, excluding those omitted. The right side of the double vertical lines of the top group in Figure 46 consists of two items: the number of timing processes and their numerical values. The remaining three groups in Figure 46, to the right of the double vertical lines, span across Figure 47 and consist of 16 items: No., blank, name, blank, blank, control selection, start bit address (10 / Hex), logic, count stop bit address (10 / Hex), logic, flashing ON time, flashing interval time, elapsed time, general-purpose bit address (10 / Hex), and differentiation. To make the address structure in Figure 46 easier to understand, below each of the four groups is a table showing the start address and change order by number, with each row containing four items: No., start address, number of words, and change order. More specifically, the timing processing data for No. 1 starts at a start address of 2539, has 29 words, and is fourth in the change order. The start address is 2539 because the same address is used as when it was created. The same is true for No. 2, which is tenth in the change order. The timing processing data No. 3 starts at address 2949, has 21 words, and is 16th in the creation order. The reason why the starting address is 2949 is because the last address of the 14th change order in Figures 43 and 44 is 2948, and the next is 2949, and furthermore, because the 15th change order in Figure 38 uses the address at the time of creation. Figure 47, which overlaps with Figure 46, is the same as the timing processing data 372 in Figure 37. The only difference is that three spaces have been added to the item. There is no TP / PC indication because these are automatically assigned by the program.The memory types displayed are external, number, processing, and migration, where external refers to memory outside the PLC shown in Figure 4, processing refers to processed data (memory) of the device general-purpose memory shown in Figure 4, number refers to number data (memory) of the device general-purpose memory shown in Figure 4, and migration refers to migration data (memory) of the device general-purpose memory shown in Figure 4.

[0092] FIG. 48 is a ladder program circuit diagram 1 / 7 for sequential stepping operations and processing according to one embodiment of the present invention. FIG. 49 is a ladder program circuit diagram 2 / 7 for sequential stepping operations and processing according to one embodiment of the present invention. FIG. 50 is a ladder program circuit diagram 3 / 7 for sequential stepping operations and processing according to one embodiment of the present invention. FIG. 51 is a ladder program circuit diagram 4 / 7 for sequential stepping operations and processing according to one embodiment of the present invention. FIG. 52 is a ladder program circuit diagram 5 / 7 for sequential stepping operations and processing according to one embodiment of the present invention. FIG. 53 is a ladder program circuit diagram 6 / 7 for sequential stepping operations and processing according to one embodiment of the present invention. FIG. 54 is a ladder program circuit diagram 7 / 7 for sequential stepping operations and processing according to one embodiment of the present invention. In other words, FIGS. 48 to 49 are a series of ladder program circuit diagrams for sequential stepping operations. This ladder program circuit diagram uses program instructions from a Mitsubishi Electric programmable logic controller (PLC). It processes each branch of each task number, each process number, while changing addresses using a modifier register. It then repeats the process for the number of branches with a repeat instruction. Once the branch count is reached, the process count is repeated for the number of tasks. Blocks 480 and 481 are preprocessing blocks, and blocks 483 through 51B perform the processing. Blocks 520 through 53F, 540 through 543, 544 through 547, and 548 through 54C are four subroutine programs. Each block is described in detail below. The transition instruction GO END in 480 bypasses the sequential step processing and transitions to the END of the sequential step processing program if the execution permission node determined by the identification and initialization program and the number of sequential step tasks determined by the user are zero. The transfer command MOV at 481 transfers the start address of the sequential step work data determined by the identification and initial processing program to the general-purpose device 1. The repeat command (1) FOR at 482 is paired with the repeat command (1) NEXT at 51B, and here, repeats are performed the number of times equal to the number of sequential step work operations.The call instruction CALL 483 calls and executes the number addition process 1. The arithmetic instruction + (addition) 484 adds the interval to the next operation number address to general-purpose device 1 and stores it in the modification register 20. The transfer instruction MOV 485 transfers the general-purpose device modified by the modification register 20 to general-purpose device 2. The arithmetic instruction + (addition) 486 adds the interval to the operation number to the modification register 20 and stores it in the modification register 20. The transfer instruction MOV 487 transfers the general-purpose device modified by the modification register 20 to general-purpose device 3. The arithmetic instruction + (addition) 488 adds the interval to the operation number start address to the modification register 20 and stores it in the modification register 20. The transfer instruction MOV 489 transfers the general-purpose device modified by the modification register 20 to general-purpose device 4. The transfer instruction MOV 48A transfers general-purpose device 4 to general-purpose device 6. The repeat instruction (2) FOR at 48B is paired with the repeat instruction (2) NEXT at 517, and here, repeats the number of sequential step processes. The call instruction CALL at 48C calls and executes the number addition process 2. The calculation instruction + at 48D adds the interval to the next process number address to the general-purpose device 4 and stores it in the modification register 20. The transfer instruction MOV at 48E transfers the general-purpose device with the modification register 20 to the general-purpose device 5. The calculation instruction + at 48F adds the interval to the absolute condition bit address to the modification register 20 and stores it in the modification register 20. The transfer instruction MOV at 48G transfers the general-purpose device with the modification register 20 to the modification register 1. The calculation instruction + at 48H adds the interval to the absolute condition logic to the modification register 20 and stores it in the modification register 20. At 48J, a transfer instruction MOV transfers a general-purpose device with a modifier register 20 to modifier register 9. At 490, an operation instruction + adds the interval to the activation bit address to the modifier register 20 and stores the result in the modifier register 20. At 491, a transfer instruction MOV transfers a general-purpose device with a modifier register 20 to modifier register 2. At 492, an operation instruction + adds the interval to the activation bit logic to the modifier register 20 and stores the result in the modifier register 20.A transfer instruction MOV at 493 transfers a general-purpose device with a qualification register 20 to qualification register 10. An operation instruction + at 494 adds the interval to the activation condition bit address to the qualification register 20 and stores it in the qualification register 20. A transfer instruction MOV at 495 transfers a general-purpose device with a qualification register 20 to qualification register 3. An operation instruction + at 496 adds the interval to the logic of the activation condition bit to the qualification register 20 and stores it in the qualification register 20. A transfer instruction MOV at 497 transfers a general-purpose device with a qualification register 20 to qualification register 11. An operation instruction + at 498 adds the interval to the branch number to the qualification register 20 and stores it in the qualification register 20. A transfer instruction MOV at 499 transfers a general-purpose device with a qualification register 20 to qualification register 4. An operation instruction + at 49A adds the interval of the branch 1 condition bit address to the qualification register 20 and stores it in the general-purpose device 10. In 49B, the arithmetic instruction + adds the branch 1 condition bit logic interval to the general-purpose device 10 and stores the result in the general-purpose device 11. In 49C, the arithmetic instruction + adds the branch 1 enable bit address interval to the general-purpose device 11 and stores the result in the general-purpose device 12. In 49D, the arithmetic instruction + adds the branch 1 enable bit logic interval to the general-purpose device 12 and stores the result in the general-purpose device 13. In 49E, the arithmetic instruction + adds the branch 1 general-purpose bit address interval to the general-purpose device 13 and stores the result in the general-purpose device 14. In 49F, the arithmetic instruction + adds the branch 1 reset bit address interval to the general-purpose device 14 and stores the result in the general-purpose device 15. In 49G, the arithmetic instruction + adds both the branch 1 condition bit address and logic interval and stores the result in the general-purpose device 7. In 49H, the arithmetic instruction + adds the branch 1 enable bit address interval to the general-purpose device 7 and stores the result in the general-purpose device 7. In the arithmetic instruction + of 49J, the logical interval of the branch 1 permission bit is added to the general-purpose device 7 and stored in the general-purpose device 7. In the arithmetic instruction + of 49K, the interval of the branch 1 general-purpose bit address is added to the general-purpose device 7 and stored in the general-purpose device 7. In the arithmetic instruction + of 49L, the interval of the branch 1 reset bit address is added to the general-purpose device 7 and stored in the general-purpose device 7.The transfer instruction MOV at 49M transfers 0 to general-purpose device 8. The repeat instruction (3) FOR at 500 is paired with the repeat instruction (3) NEXT at 513, and in this case, iterates the number of times the number of general-purpose devices with modifier register 4 is the same. The arithmetic instruction * at 501 multiplies general-purpose device 7 by general-purpose device 8 and stores the result in general-purpose device 7. The arithmetic instruction + at 502 adds general-purpose device 10 to general-purpose device 9 and stores the result in modifier register 20. The transfer instruction MOV at 503 transfers the general-purpose device with modifier register 20 to modifier register 5. The arithmetic instruction + at 504 adds general-purpose device 9 to general-purpose device 7 and stores the result in modifier register 20. The transfer instruction MOV at 505 transfers the general-purpose device with modifier register 20 to modifier register 12. The arithmetic instruction + at 506 adds general-purpose device 10 to general-purpose device 7 and stores the result in modifier register 20. The transfer instruction MOV at 507 transfers the general-purpose device with modifier register 20 to modifier register 6. The arithmetic instruction + at 508 adds general-purpose device 7 to general-purpose device 11 and stores the result in modifier register 20. The transfer instruction MOV at 509 transfers the general-purpose device with modifier register 20 to modifier register 13. The arithmetic instruction + at 50A adds general-purpose device 7 to general-purpose device 12 and stores the result in modifier register 20. The transfer instruction MOV at 50B transfers the general-purpose device with modifier register 20 to modifier register 7. The arithmetic instruction + at 50C adds general-purpose device 7 to general-purpose device 13 and stores the result in modifier register 20. The transfer instruction MOV at 50D transfers the general-purpose device with modifier register 20 to modifier register 8. A call instruction CALL at 50E calls a subroutine for all general-purpose bit reset processing at 520 if the general-purpose bits modified by the qualification register 1 are inactivated according to the logic of the absolute condition bits. An operation instruction SET at 50F sets (activates) the general-purpose bit during order discarding according to the logic of the absolute condition bits if the general-purpose bits modified by the qualification register 1 are inactivated.The repeat instruction BREAK at 50G, according to the logic of the absolute condition bit, if the general-purpose bit modified by qualification register 1 is inactivated, discards the repeat instruction (3) and moves to the repeat completion position 1 pointer. The calculation instruction RST at 510, when the general-purpose bit modified by qualification register 1 is activated according to the logic of the absolute condition bit, the general-purpose bit modified by qualification register 2 is activated according to the logic of the activation bit, the general-purpose bit modified by qualification register 3 is activated according to the logic of the activation condition bit, the general-purpose bit modified by qualification register 5 is activated according to the logic of the branch condition bit, and the general-purpose bit modified by qualification register 6 is activated according to the logic of the branch permission bit, resets the general-purpose bit with qualification R8. The arithmetic instruction SET at 511 activates the general-purpose bit modified by qualifier register 1 according to the logic of the absolute condition bit, activates the general-purpose bit modified by qualifier register 2 according to the logic of the activation bit, activates the general-purpose bit modified by qualifier register 3 according to the logic of the activation condition bit, activates the general-purpose bit modified by qualifier register 5 according to the logic of the branch condition bit, and activates the general-purpose bit modified by qualifier register 6 according to the logic of the branch permission bit, and then sets the general-purpose bit with qualifier register 7. The arithmetic instruction INC at 512 adds 1 to general-purpose device 6. This changes the value of each qualifier register for the next branch when repeating. The repeat instruction (3) NEXT at 513 is paired with the repeat instruction (3) FOR, and returns to the repeat instruction (3) FOR and repeats the subsequent instructions until the number of repeats is exceeded. The repeat completion location 1 pointer 514 is the destination of the repeat instruction BREAK 50G. If the general-purpose bit during order discarding is activated, the repeat instruction BREAK 515 discards the repeat instruction (2) and moves to the repeat completion location 2 pointer. The transfer instruction MOV 516 transfers general-purpose device 4 to general-purpose device 3. The repeat instruction (2) NEXT 517 is paired with the repeat instruction (2) FOR, and returns to the repeat instruction (2) FOR and repeats the subsequent instructions until the number of repeats is exceeded. The repeat completion location 2 pointer 518 is the destination of the repeat instruction BREAK 515.The calculation instruction RST at 519 resets (deactivates) the general-purpose bit during order discarding if it is activated. The transfer instruction MOV at 51A transfers general-purpose device 2 to general-purpose device 1. The repeat instruction (1) NEXT at 51B is paired with the repeat instruction (1) FOR, and returns to the repeat instruction (1) FOR and repeats the instructions that follow until the number of repetitions is exceeded. The structure instruction FEND at 51C ends the program for this order-incrementing process. The all-general-bit reset processing pointer at 520 is the call destination for the call instruction CALL at 50E. The transfer instruction MOV at 521 transfers general-purpose device 1 to general-purpose device 20. The transfer instruction MOV at 522 transfers the general-purpose device with the qualification register 20 to general-purpose device 14. The repeat instruction (4) FOR at 523 is paired with the repeat instruction (4) NEXT at 53E, and here, repeats the number of sequential step processes. The call instruction CALL at 524 calls and executes the number addition process 3. The calculation instruction + at 525 adds the interval to the next process number address to the general-purpose device 16 and stores it in the modification register 20. The transfer instruction MOV at 526 transfers the general-purpose device with the modification register 20 to the general-purpose device 17. The calculation instruction + at 527 adds the interval to the absolute condition bit address to the modification register 20 and stores it in the modification register 20. The calculation instruction + at 528 adds the interval to the absolute condition logic to the modification register 20 and stores it in the modification register 20. The calculation instruction + at 529 adds the interval to the start bit address to the modification register 20 and stores it in the modification register 20. In the calculation instruction + of 52A, the interval to the logic of the activation bit is added to the modification register 20 and stored in the modification register 20. In the calculation instruction + of 52B, the interval to the activation condition bit address is added to the modification register 20 and stored in the modification register 20. In the calculation instruction + of 52C, the interval to the logic of the activation condition bit is added to the modification register 20 and stored in the modification register 20. In the calculation instruction + of 52D, the interval to the branch number is added to the modification register 20 and stored in the modification register 20.The transfer instruction MOV at 52E transfers the general-purpose device with modifier register 20 to modifier register 4. The arithmetic instruction + at 52F adds the branch 1 condition bit address interval to modifier register 20 and stores the result in general-purpose device 10. The arithmetic instruction + at 52G adds the branch 1 condition bit logic interval to general-purpose device 10 and stores the result in general-purpose device 11. The arithmetic instruction + at 52H adds the branch 1 enable bit address interval to general-purpose device 11 and stores the result in general-purpose device 12. The arithmetic instruction + at 52J adds the branch 1 enable bit logic interval to general-purpose device 12 and stores the result in general-purpose device 13. The arithmetic instruction + at 52K adds the branch 1 general-purpose bit address interval to general-purpose device 13 and stores the result in general-purpose device 14. The arithmetic instruction + at 52L adds the branch 1 reset bit address interval to general-purpose device 14 and stores the result in general-purpose device 15. The arithmetic instruction + at 530 adds the intervals of both the branch 1 condition bit address and logic and stores the result in the general-purpose device 7. The arithmetic instruction + at 531 adds the interval of the branch 1 enable bit address to the general-purpose device 7 and stores the result in the general-purpose device 7. The arithmetic instruction + at 532 adds the interval of the branch 1 enable bit logic to the general-purpose device 7 and stores the result in the general-purpose device 7. The arithmetic instruction + at 533 adds the interval of the branch 1 general-purpose bit address to the general-purpose device 7 and stores the result in the general-purpose device 7. The arithmetic instruction + at 534 adds the interval of the branch 1 reset bit address to the general-purpose device 7 and stores the result in the general-purpose device 7. The transfer instruction MOV at 535 transfers 0 to the general-purpose device 8. The repeat instruction (5) FOR at 536 is paired with the repeat instruction (5) NEXT at 53E, and here, repetition is performed the number of times equal to the number of general-purpose devices with modifier register 4. The arithmetic instruction * at 537 multiplies general-purpose device 7 by general-purpose device 8 and stores the result in general-purpose device 9. The arithmetic instruction + at 538 adds general-purpose device 10 to general-purpose device 9 and stores the result in modifier register 20. The transfer instruction MOV at 539 transfers the general-purpose device with modifier register 20 to modifier register 7. The arithmetic instruction RST at 53A resets (deactivates) the general-purpose bit with modifier register 7.The calculation instruction INC at 53B adds 1 to the general-purpose device 8 in preparation for repetition. This changes the value of the next branch number when repetition occurs. The repeat instruction (5) NEXT at 53C is paired with the repeat instruction (5) FOR, and returns to the repeat instruction (5) FOR and repeats the instructions that follow until the number of repetitions is exceeded. The transfer instruction MOV at 53D transfers the general-purpose device 17 to the general-purpose device 16 in preparation for repetition. This changes the values ​​of each modifier register for the next No. when repetition occurs. The repeat instruction (4) NEXT at 53E is paired with the repeat instruction (4) FOR, and returns to the repeat instruction (4) FOR and repeats the instructions that follow until the number of repetitions is exceeded. The call is completed by the recall instruction RET at 53F, and the program proceeds to the next call instruction at 50E. The number addition processing 1 pointer 540 is the callee for the call instruction CALL 483. The arithmetic instruction + (addition) 541 adds 1 to general-purpose device 1 and stores it in modifier register 20. The arithmetic instruction + (addition) 542 adds modifier register 20 to the general-purpose device with modifier register 20 and stores it in general-purpose device 1. The call is completed by the callback instruction RET 543, and processing moves to the next call instruction of 483. The number addition processing 2 pointer 544 is the callee for the call instruction CALL 48C. The arithmetic instruction + (addition) 545 adds 1 to general-purpose device 4 and stores it in modifier register 20. The arithmetic instruction + (addition) 546 adds modifier register 20 to the general-purpose device with modifier register 20 and stores it in general-purpose device 4. The call is completed with a callback instruction RET at 547, and processing moves to the next step after the call instruction at 48C. The number addition processing 3 pointer at 548 is the call destination for the call instruction CALL at 524. The arithmetic instruction + (addition) at 549 adds 1 to the general-purpose device 16 and stores it in the modification register 20. The arithmetic instruction + (addition) at 54A adds the modification register 20 to the general-purpose device with the modification register 20 and stores it in the general-purpose device 16. The call is completed with a callback instruction RET at 54B, and processing moves to the next step after the call instruction at 524. The structure instruction END at 54C ends the program file.

[0093] (Concept) This sequential step processing allows for flexible data configuration, leaving the process largely at the discretion of the data creator. However, here we will explain flowcharts and the tasks and processes involved. Flowcharts created to control equipment and devices represent each step of a process, which is a characteristic of dynamic systems, or each means, procedure, or operation used to find a solution to a problem, as boxes containing their contents. The flow is represented by lines and arrows between the boxes, or by distributing these lines and arrows, or by composing multiple flowcharts. Processes and algorithms ranging from simple to complex are expressed. Each step of a process, which is a characteristic of dynamic systems, is a process step in process control. Furthermore, dynamic systems are systems that take time to return a certain result or do not reach a certain result at all. Each means, procedure, or operation used to find a solution to a problem is a function that converts some input into an output. Specifically, this could be a sensor turning on, a set speed being reached, or a temperature reaching a set temperature. In this invention, multiple flowcharts created to control equipment and devices are replaced with a structure (task) that controls the processes. In other words, because controlling equipment and devices can involve multiple independent flowcharts or flowcharts that affect other flowcharts, multiple processes are managed under the name of "task." Specifically, in the sequential stepwise task data 362 in Figure 36, each is independent but influences the other, such as No. 1 Motor 1 task and No. 2 Motor 2 task. Furthermore, each step of a process, means, procedure, and operation in a flowchart created to control equipment and devices is replaced with a series of multiple data items linked to the order of the process in sequential stepwise processing. In other words, the sequential stepwise processing data treats a series of multiple data items linked to the order of the process as a unit, and by repeating the process using a series of multiple data items linked to the order of the process as a unit, it corresponds to an increase or decrease in the number of steps, means, procedures, and operations in the flowchart's process.In addition, the branching and diverging flows of flowcharts created to control devices and equipment are replaced by the number of branches and corresponding items. Flowcharts created to control devices and equipment may have different destinations depending on decisions and conditions, or may have additional destinations depending on decisions and conditions, and may even transition to external flowcharts. Considering the above scenarios, transitions cannot be made solely within the flow chart itself; the status of the other flow chart must be taken into account. Therefore, a branch permission bit is provided for each branch in the item. Specifically, when transfer devices with the same structure are lined up in succession, if the previous device is not in its receiving position, the subsequent device must be stopped. While a single step or procedure is generally executed within a single flow chart, this is not completely prohibited and is left to the creator's discretion. Furthermore, the contents of all flowchart boxes are derived from bit address data and selection data. This is also based on bits created by external processes. The selection data, for example, determines whether a bit is activated by positive logic or negative logic, and is determined by a predetermined numerical value. Furthermore, when a series of trigger bits, such as absolute condition bits, activation bits, activation condition bits, branch condition bits, and branch permission bits, modified by a modifier register containing the address data of the bits based on the selection data, are activated, the bits modified by the modifier register containing the address data of the bits are activated, and the bits modified by the modifier register containing the address data of the bits that caused the No. that activated the bit to be monitored are deactivated. In other words, the activation of each bit indicates the completion of each step or procedure of the process, and the bit remains activated until the currently monitored series of trigger bits are activated. Through the above substitutions and other methods, all algorithms are replaced with data changes.

[0094] Figure 55 is a flowchart of a programmable logic controller (PLC) according to one embodiment of the present invention. When the power is turned from OFF to ON, or from STOP to RUN, at 550 in Figure 55, the programmable logic controller (PLC) starts up. First, a program check process is performed at 551. Next, an I / O refresh is performed at 552, and the process proceeds to END process 1 at 553. Identification and initial processing programs are performed in the specified order at 555, and the process proceeds to END process 2 at 554. Next, an I / O refresh is performed at 552, and the process proceeds to END process 1 at 553. The differential reset processing program for timing processing at 556, the input device data processing program at 557, the device data calculation processing (input reference) program at 558, the input processing program at 559, the interface processing program at 55A, the logic processing program at 55B, the sequential stepping processing program at 55C, the device data calculation processing (output reference) program at 55D, and the output processing program at 55E are executed in the specified order, and the process proceeds to END process 2 at 554, and the process returns to before the I / O refresh at 552, and is repeated until the power is turned from ON to OFF or from RUN to STOP. In other words, the initial execution type program group 25 in the flowchart of FIG. 2 has been combined into a single identification and initial processing program of the initial execution type program 555, the scan execution type program group 26 has been combined into ten programs, namely, the differential reset processing program of timing processing 556, the input device data processing program 557, the device data calculation processing (input reference) program 558, the input processing program 559, the interface processing program 55A, the logic processing program 55B, the sequential stepping processing program 55C, the device data calculation processing (output reference) program 55D, and the output processing program 55E, the fixed cycle execution type program group 27 has been combined into a single timing processing program 55F, and an algorithm function equivalent to that of the flowchart of FIG. 2 has been obtained without using the standby type program group 28.All algorithms can be constructed using the above alone, but programs can be added if you want to apply previously created and proven program assets or to handle complex arithmetic calculations, etc., but the insertion location is important. When adding an initial execution type program, it should be inserted either between END processing 1 of 553 and the identification and initialization processing program of 555 before the loop, or between the identification and initialization processing program of 555 and the I / O refresh of 552, depending on whether it affects or is affected by this invention and the identification and initialization processing program of 555. Also, when adding a scan execution type program, it should be inserted between END processing 1 of 553 and END processing 2 of 554 within the loop, but it can also be inserted anywhere from the differential reset processing program of the clock processing of 556 to the output processing program of 55E, but care must be taken to determine how it will affect or be affected by this invention. In particular, the program from the differential reset processing program for the timekeeping process (556) to the interface processing program (55A) processes incoming data, while the program from the logic processing program (55B) to the output processing program (55E) processes outgoing data, so careful attention is required. Furthermore, once a program is inserted, it is no longer a general-purpose program but becomes a custom-made program, so great care must be taken. Before explaining why the differential reset processing program for the timekeeping process (556) is the first program in this invention's scan execution type program, we must first explain differentiation. Differentiation is a method of command or output. Typically, when a condition is met, a command continues to be executed or output. This is also called level output, and when the condition is no longer met, the command or output stops. When this is differentiated, the operation is changed so that a command is executed or output only once, even if it is repeated. Furthermore, even if the condition continues to be met, once a command is executed or output, it will not be executed or output again until the condition is no longer met. This method of command and output is called differentiation and is widely used.In this invention, instruction differentiation is intentionally omitted for simplicity's sake or because conditions can be replaced by differentiation. Furthermore, it should be noted that only the timing processing program that controls output by time measurement is a fixed-period execution type program. While existing timers exist in programmable logic controllers (PLCs), many of these timers do not function properly with program repetition structures that use numbers as units. Therefore, fixed-period execution type programs are used by counting fixed periods. While there is no problem with output at the level, differentiation can lead to missed pulses in scan execution type programs depending on the duration of one scan and the interval between fixed periods. Therefore, as a scan execution type program outside of fixed-period execution programs, the pulse width is differentiated to be between one scan and two scans, rather than one scan. There is no particular reason why the timing processing differentiation reset processing program is at the beginning of the scan execution type program in this invention; the differentiation processing that occurs in other scan execution type programs is processed at the beginning after one scan, so it is simply positioned in a similar manner. The input device data processing program, which compares device data, the device data calculation processing (input reference) program that executes calculation instructions, and the input processing program in the first half sandwiched between the scan execution type program do not pose a major problem as long as they do not exceed the logic processing program, sequential step processing program, device data calculation processing (output reference) program, and output processing program in the second half that determine the output. However, since the first half of the program is likely to use the results of the programs before it, the order of the input device data processing program, device data calculation processing (input reference) program, and input processing program is such that it is not a major problem if you are prepared for a delay of one scan. The same applies to the second half of the program.In this invention, the program can be made compatible with all algorithms by simply changing the device data through the construction of a conventional program without modifying the existing programmable logic controller (PLC). However, when a manufacturer of programmable logic controllers (PLCs) constructs this invention, the program may be reduced to a level similar to I / O refresh processing or END processing that cannot be accessed by the person creating the program, in order to eliminate the risk of modifications. Furthermore, the concept of a program may be eliminated altogether, and a datable logic controller (DLC) may be used.

[0095] 56 is a diagram showing the relationship between main programs in one embodiment of the present invention. The main programs are programs essential for realizing various algorithms, and include an input processing program 561 that is constrained by input processing device data 560 set on the touch panel (TP) screen, a logic processing program 563 that is constrained by logic processing device data 562 set on the touch panel (TP) screen, a sequential step processing program 565 that is constrained by sequential step processing device data 564 set on the touch panel (TP) screen, an output processing program 567 that is constrained by output processing device data 566 set on the touch panel (TP) screen, and a program 568 that is constrained by logic processing device data 567 set on the touch panel (TP) screen. The eight programs are: an input device data processing program 569, which is constrained by input device data processing device data 568; a timing processing program 56B, which is constrained by timing processing device data 56A, which is set on the touch panel (TP) screen; a device data calculation processing (input reference) program 56D, which is constrained by device data calculation processing (input reference) device data 56C, which is set on the touch panel (TP) screen; and a device data calculation processing (output reference) program 56F, which is constrained by device data calculation processing (output reference) device data 56E, which is set on the touch panel (TP) screen. The dashed lines and their arrows indicate the direction in which general-purpose device bits (general-purpose bits) are generated and consumed, and the thick dashed lines and their arrows indicate the direction in which general-purpose device data is generated and consumed. While shifting the timing, the output device bits and output device data, which are shown as rectangles protruding to the left, are ultimately released to complete various algorithms. The touch panel (TP) screen is controlled by interface processing.

[0096] Figure 57 is a diagram illustrating the device memory layout used by each program in one embodiment of the present invention. 570 is a representative device memory area of ​​the physical memory area. Device types exist for each manufacturer in the device memory, but this is a representative device. The area from the beginning of the physical device memory area to the first address of device data used in process 1 (572) is used as an initial constant area (571) and a touch panel display area. From this point on, the first and second data groups of device data used in process 1 (572) from the first address of device data used in process 1 to the first address of device data used in process 2 (573) are included; the first and second data groups of device data used in process 2 (573) from the first address of device data used in process 2 to the first address of device data used in process 3 (574) are included; the first and second data groups of device data used in process 2 (574) from the first address of device data used in process 3 to the first address of device data used in process 4 (575) are included; and the first data group of device data used in process 4 (575) from the first address of device data used in process 4 to the first address of device data used in process 5 (576) are included. and the second data group, the first and second data groups of device data used in processing 5 from the first starting address of device data used in processing 5 of 576 to the first starting address of device data used in processing 6 of 577, the first data group of device data used in processing 6 from the first starting address of device data used in processing 6 of 577 to the first starting address of device data used in processing 6 of 578, ..., the first data group of device data used in processing from the first starting address of device data used in processing 578, ... to the first starting address of device data used in processing n of 579, ..., the first data group of device data used in processing n from the first starting address of device data used in processing n of 579 to the third starting address of device data used in processing 1 of 57A,The third data group of device data used in processing 1 from the third starting address of the device data used in processing 1 in 57A to the third starting address of the device data used in processing 2 in 57B; the third data group of device data used in processing 2 from the third starting address of the device data used in processing 2 in 57B to the third starting address of the device data used in processing 3 in 57C; the third data group of device data used in processing 3 from the third starting address of the device data used in processing 3 in 57C to the second starting address of the device data used in processing 6 in 57D; the second data group of device data used in processing 6 from the second starting address of the device data used in processing 6 in 57D to the third starting address of the device data used in processing 4 in 57E; the third data group of device data used in processing 4 from the third starting address of the device data used in processing 4 in 57E to the second starting address of the device data used in processing 57F...; the second data group of device data used in processing 5 in 57G from the second starting address of the device data used in processing 57F... the second data group of device data used in processing ... from the third starting address of device data used in processing 5 of 57G to the second starting address of device data used in processing n of 57H; the second data group of device data used in processing n of 57H from the second starting address of device data used in processing n of 57J to the third starting address of device data used in processing ...; the third data group of device data used in processing ... from the third starting address of device data used in processing n of 57J to the third starting address of device data used in processing 6 of 57K; the third data group of device data used in processing 6 of 57K from the third starting address of device data used in processing n of 57L; the third and ...th data group of device data used in processing n from the third starting address of device data used in processing n of 57L to the ...th starting address of device data used in processing 6 of 57MThe ...th data group of device data used in processing 6 from the ...th starting address of device data used in processing 6 of 57M to the ...th starting address of device data used in processing 4 of 57N, the ...th data group of device data used in processing 4 from the ...th starting address of device data used in processing 4 of 57N to the ...th starting address of device data used in processing 2 of 57P, the ...th data group of device data used in processing 2 from the ...th starting address of device data used in processing 2 of 57P to the ...th starting address of device data used in processing 3 of 57Q, the ...th data group of device data used in processing 3 of 57Q from the ...th starting address of device data used in processing 3 of 57R, the ...th data group of device data used in processing ... from the ...th starting address of device data used in processing ... of 57R to the ...th starting address of device data used in processing 1 of 57S, the ...th data group of device data used in processing ... from the ...th starting address of device data used in processing 1 of 57S to the ...th starting address of device data used in processing 5 of 57T the ...th data group of device data used in processing 1 up to the ...th starting address of the device data, the ...th data group of device data used in processing 5 from the ...th starting address of device data used in processing 5 of 57T to the nth starting address of device data used in processing n of 57U, the nth data group of device data used in processing n from the nth starting address of device data used in processing n of 57U to the nth starting address of device data used in processing ... of 57V, the nth data group of device data used in processing ... from the nth starting address of device data used in processing ... of 57V to the nth starting address of device data used in processing 6 of 57W, the nth data group of device data used in processing 6 from the nth starting address of device data used in processing 6 of 57W to the nth starting address of device data used in processing 5 of 57X, the nth data group of device data used in processing 5 from the nth starting address of device data used in processing 5 of 57X to the nth starting address of device data used in processing 4 of 57YThe nth data group of device data used in process 4 from the nth start address of device data used in process 4 in 57Y to the nth start address of device data used in process 3 in 57Z, the nth data group of device data used in process 3 from the nth start address of device data used in process 3 in 57Z to the nth start address of device data used in process 2 in 57a, the nth data group of device data used in process 2 from the nth start address of device data used in process 2 in 57a ​​to the nth start address of device data used in process 1 in 57b, and the nth data group of device data used in process 1 from the nth start address of device data used in process 1 in 57b to the start address of the unused area of ​​device memory in 57c are used. This order is the order of creation, meaning that they were created in this order. In other words, even if the exact same device is created in a different order, the order will not be the same, so this order is meaningless. However, even if the size of each process number is not constant, the device memory can be densely packed, but for each process number, the return address value of the previous number and the destination address value of the next number must be elements.

[0097] If the device memory area for that number becomes smaller, there is no problem, but if the device memory area for that number becomes larger, a new area must be created, which results in a large gap. Therefore, a measure is required to create a program to fill in the gaps when the equipment or device is down.

[0098] Figure 58 is a device memory allocation diagram in which the device memory is rearranged for each process in one embodiment according to the present invention. This Figure 58 shows the device memory allocation diagram used in each program in Figure 57 rearranged for each process. This arrangement is important for executing each process program row by row. 580 is process 1, 581 is the element group for process 1, 582 is the order of process 1, 583 is the device data group for process 1, 584 is process 2, 585 is the element group for process 2, 586 is the order of process 2, 587 is the device data group for process 2, 588 is process 3, 589 is the element group for process 3, 58A is the element group for process 3, 58B is the device data group for process 3, 58C is process 4, 58D is the element group for process 4, 58E is the order of process 4, 58F is the device data group for process 4. 58G is process 5, 58H is the element group for process 5, 58J is the order of process 5, 58K is the device data group for process 5, 58L is process 6, 58M is the element group for process 6, 58N is the order of process 6, 58P is the device data group for process 6, 58Q is process..., 58R is the element group for process..., 58S is the order of process..., 58T is the device data group for process..., 58U is process n, 58V is the element group for process n, 58W is the order of process n, and 58X is the device data group for process n. To rearrange the device memory for each process, the first address value is stored in the initial setting data for each process, and the return address value for the previous number and the destination address value for the next number are stored for each process number. From a program perspective, the desired element can be easily reached without rearranging the elements. The order and specifications of the elements are also important, and initial setting data and comments must be stored as rules. For elements whose size varies, such as character strings, the number of words used is provided as a separate element.Furthermore, for elements whose number of elements varies, such as the number of elements (number of consecutive elements) in a logical sum or logical product, the number of words used is provided as a separate element.In the case of the logical sum and logical product shown as examples, the address and logic (positive logic or negative logic) are increased by two elements at a time.As another example, the number of branches in sequential step processing is also increased by six elements: the branch condition bit address and its logic (positive logic or negative logic), the branch permission bit address and its logic (positive logic or negative logic), the branch general-purpose bit address, and the branch reset bit address.

[0099] (Concept) Further explanation will be provided based on the detailed descriptions of Figures 57 and 58. Generally, memory is a storage device, but some have power failure retention functions and some do not. Memory is also classified by function and area, such as program memory and device memory. The memory of this invention is a device memory that can store data and can retain data during power failures, and stores processing data. The processing data is processing data for implementing steps or algorithms. When processing is performed based on processing data with multiple items, it is replaced with the next processing data with multiple items using a modifier register, and further processing is performed until the processing data is exhausted. When the processing data is exhausted, it returns to the beginning and repeats the process. If there are multiple processing data for different processes that repeat this series of processes, the number of processing data to be processed varies for each process, and the processing data for different processes cannot be arranged in the next free memory area. A typical method involves allocating an area in memory for each process and arranging multiple processing data at equal intervals. Not only does this result in a large amount of unused area and waste, but it is also impossible to exceed the area determined by prediction. Therefore, for data other than the processing data having multiple items, the starting address of the processing data having multiple items to be executed next and the starting address of the processing data having multiple items executed previously are added as migration data to the processing data having multiple items for each process. By correcting the migration data when adding processing data or changing or deleting processing data that exceeds the range, not only can the processing data having multiple items containing different processes be continuously arranged in memory, but also only the multiple data having multiple items that perform the same process can be sequentially extracted from the mixed processing data based on the starting address of the migration data. Furthermore, when processing data having multiple items and data other than the migration data are repeated within a process, adding the number of repetitions as repetition data not only allows the data to be continuously arranged in memory even if the number of data in the process and the next process are different, but also allows the data to be sequentially extracted based on the starting address of the migration data. Incidentally, data is generally allocated by providing a memory area with the maximum number of repetitions for each process.

[0100] Figure 59 shows the relationship between the device memory for a process and the display device memory when a touch panel (TP) according to one embodiment of the present invention is used and has a function for changing the device memory for each process. In recent years, in factories, physical switches, physical lamps, and physical digital switches are being replaced by touch panels (TP) as interfaces, except for safety-related areas, due to reduced wiring labor and physical size. Touch panels (TP), which have become widespread in this context, were initially considered large input / output devices, and it was the programmable logic controller (PLC) programmer who was responsible for the touch panel (TP) compatibility. Recently, touch panels (TP) are no longer considered large input / output devices, and some even have the function of creating and changing programmable logic controller (PLC) programs. However, touch panels (TP) vary in size and resolution, and some factories even display the manufacturer's logo, creating screens specifically for that device, leading to a tendency to create unique screen data. This is the opposite of the purpose of this invention, and is presented here as a method for doing so. Reference numeral 590 in Figure 59 represents a device memory group resulting from rearranging the device memory for a certain process. Reference numeral 591 represents a group of numbers that can be displayed on the touch panel (TP), tentatively set to 15 lines. In other words, the maximum number of lines for that model is 15 lines. Reference numeral 592 represents a display device data group for a certain process, 593 represents a number variable group for the touch panel (TP), 594 represents a display device data group for the touch panel (TP), 595 represents a number as an element on the touch panel (TP), and 596 represents a group of elements that can be displayed on the touch panel (TP), tentatively set to two elements. In other words, the maximum number of elements for that model is two.Assuming that the maximum possible model is selected, in Figure 59, what is currently displayed on the display touch panel (TP) is the number variable group for touch panel (TP) 593, which displays values ​​from 7 to 21, that is, the value of D01-00 is 7, the value of D02-00 is 8, the value of D03-00 is 9, the value of D04-00 is 10, the value of D05-00 is 11, the value of D06-00 is 12, the value of D07-00 is 13, the value of D08-00 is 14, the value of D09-00 is 15, the value of D10-00 is 16, the value of D11-00 is 17, the value of D12-00 is 18, the value of D13-00 is 19, the value of D14-00 is 20, and the value of D15-00 is 21.Furthermore, in the group of elements that can be displayed on the 86 touch panel (TP), the value of 1-72 is displayed in D01-02 corresponding to 1-72, the value of 1-73 is displayed in D01-03 corresponding to 1-73, the value of 1-82 is displayed in D02-02 corresponding to 1-82, the value of 1-83 is displayed in D02-03 corresponding to 1-83, the value of 1-92 is displayed in D03-02 corresponding to 1-92, the value of 1-93 is displayed in D03-03 corresponding to 1-93, the value of 1-102 is displayed in D04-02 corresponding to 1-102, The value of 1-103 in D04-03 corresponds to 103, the value of 1-112 in D05-02 corresponds to 1-112, the value of 1-113 in D05-03 corresponds to 1-113, the value of 1-122 in D06-02 corresponds to 1-122, the value of 1-122 in D06-03 corresponds to 1-123, the value of 1-123 in D07-02 corresponds to 1-132, the value of 1-132 in D07-03 corresponds to 1-133, the value of 1-133 in D08-02 corresponds to 1-142 The value of 2 is 1-143 in D08-03, the value of 1-143 in D09-02, the value of 1-152 in D09-03, the value of 1-153 in D09-03, the value of 1-153 in D10-02, the value of 1-162 in D10-03, the value of 1-163 in D10-03, the value of 1-163 in D11-02, the value of 1-172 in D11-03, the value of 1-173 in D11-03, the value of 1-173 in D12-02, The value of 1-182 is displayed in D12-02 corresponding to 1-183, the value of 1-183 is displayed in D12-03 corresponding to 1-183, the value of 1-192 is displayed in D13-02 corresponding to 1-192, the value of 1-193 is displayed in D13-03 corresponding to 1-193, the value of 1-202 is displayed in D14-02 corresponding to 1-202, the value of 1-203 is displayed in D14-03 corresponding to 1-203, the value of 1-212 is displayed in D15-02 corresponding to 1-212, and the value of 1-213 is displayed in D15-03 corresponding to 1-213. When the up transition switch or the down transition switch is used to move in the direction of the up arrow or the down arrow, the device data of the display device data group on the device data group side of a certain process (592) changes, and therefore the corresponding device data is updated with the device data of the number variable group for the touch panel (TP) (593), the display device data group on the touch panel (TP) side (594), and the element group that can be displayed on the touch panel (TP) (596).When the right or left transition switch is used to move in the direction of the right or left arrow, the corresponding device data is updated with the device data of the element group that can be displayed on the touch panel (TP) 596. Note that for models that do not meet the maximum number of rows or the maximum number of elements, a real number variable group for the touch panel (TP) and a real element group that can be displayed on the touch panel (TP) are provided in addition to the number variable group for the touch panel (TP) 593 and the element group that can be displayed on the touch panel (TP) 596, and movement can be made within the number variable group for the touch panel (TP) 593 and the element group that can be displayed on the touch panel (TP) 596, and when the upper or lower limit is reached, the device data of each required group is updated. The touch panel (TP) referred to here is used as an interface.

[0101] This invention uses a single program to change data, so it must be compatible with a variety of devices and equipment. One feature is that a display memory is provided for each process. This is because, when creating a screen, all addresses must be entered for numerical and comment displays. Another feature of this invention is that memory is managed using transitional data and repeated data. This means that it is impossible to know how much data will be used. The mechanism is simple: when the display memory is rewritten, the corresponding data is also rewritten. By using this method, the number of screens can be consolidated.

[0102] 60 is a system relationship diagram between programmable logic controllers (PLCs) and an engineering tool for identifying programmable logic controllers (PLCs) that can execute a program and allowing the program to be executed only on those programmable logic controllers (PLCs) in one embodiment according to the present invention. In FIG. 60, reference numeral 600 denotes the engineering tool, 601 denotes a network, 602 denotes programmable logic controller (PLC) A, 603 denotes programmable logic controller (PLC) B, 604 denotes programmable logic controller (PLC) C, 605 denotes programmable logic controller (PLC) D, 606 denotes programmable logic controller (PLC) n, 607 denotes a project file for programmable logic controller (PLC) A, 608 denotes a project file for programmable logic controller (PLC) B, 609 denotes a project file for programmable logic controller (PLC) C, 60A denotes a project file for programmable logic controller (PLC) D, and 60B denotes a project file for programmable logic controller (PLC) n. 60, the engineering tool 600 contains a project file for programmable logic controller (PLC) A 607, a project file for programmable logic controller (PLC) B 608, a project file for programmable logic controller (PLC) C 609, a project file for programmable logic controller (PLC) D 60A, and a project file for programmable logic controller (PLC) n 60B. Note that a project file is a data group made up of a plurality of programs and parameters describing the contents for controlling the algorithms for operating the programmable logic controllers (PLC).Furthermore, whether this was via the network 601 or was there from the beginning, it is unclear whether the project file for programmable logic controller (PLC) A 607 is written in programmable logic controller (PLC) A 602, the project file for programmable logic controller (PLC) B 608 is written in programmable logic controller (PLC) B 603, the project file for programmable logic controller (PLC) C 609 is written in programmable logic controller (PLC) C 604, the project file for programmable logic controller (PLC) D 605 is written in programmable logic controller (PLC) D 60A, and the project file for programmable logic controller (PLC) n 60B is written in programmable logic controller (PLC) n 606. The project file for programmable logic controller (PLC) A 607 contains the identification program labeled A of the present invention, programs 1 to n of the present invention, and user programs 1 and 2 to nA created by the user. The project file for programmable logic controller (PLC) B 608 contains an identification program labeled B of the present invention, programs 1 through n of the present invention, and user-created user programs 3 and 4 through nB. The project file for programmable logic controller (PLC) C 609 contains user-created user programs 5 and 6 through nC. The project file for programmable logic controller (PLC) D 60A contains an identification program labeled D of the present invention and programs 1 through n of the present invention. The project file for programmable logic controller (PLC) n 60B contains an identification program labeled D of the present invention, programs 1 through n of the present invention, and user-created user programs 1 and 2 through nA.In the above state, the unique data loaded by programmable logic controller (PLC) A (602) matches the data written in the identification program, so both the program group of the present invention and the user program group operate. The unique data loaded by programmable logic controller (PLC) B (603) does not match the data written in the identification program, so the program group of the present invention does not operate, but only the user program group operates. The program group of the present invention does not exist in programmable logic controller (PLC) C (604), so only the user program group operates. The unique data loaded by programmable logic controller (PLC) D (605) matches the data written in the identification program, so the program group of the present invention operates, but the user program group does not exist, so it does not operate. The unique data loaded by programmable logic controller (PLC) n (603) does not match the data written in the identification program, so the program group of the present invention does not operate, but only the user program group operates. In this situation, it is presumed that the person using the 600 engineering tool can read and write the programs of the present invention, but at the very least, does not have the editing privileges to view or change the programs that have been read. This is because, in order to operate all the programmable logic controllers (PLCs), it is easy to operate them by rewriting the identification contents written in the identification program of each programmable logic controller (PLC)'s project file using the 600 engineering tool. Since interests differ depending on the position, it is difficult to say for sure, but for the present invention, authority and identification processing are important factors.

[0103] The mechanism is simple: at the beginning of a program, the program reads the unique physical data possessed by the microprocessor (MPU). If the data does not match the data compared in the program, the program proceeds to the END and terminates. The unique physical data possessed by the microprocessor (MPU) generally refers to a serial number, but if a local area network (LAN) is used, it can also be a media access control address (MAC address), or any other arbitrary value. When creating a program for this invention, the unique data must be written into the program either as a constant or as initial data. This process alone makes it no different from a typical program created individually. Who will create the final version of the program for this invention? To whom will the program be sold? Who will create the data for the program? Who will verify that the equipment or devices running the program for this invention function according to specifications? Who will use the equipment or devices running the program for this invention? These are important considerations. Since entry to production sites such as factories is prohibited, malicious individuals can easily imitate the invention since it is disclosed in this specification. However, if the program cannot be analyzed, it can be prevented simply by mixing legitimate programs with counterfeit programs using purchase history, etc.

[0104] Figure 61 is a device data setting diagram showing common initial settings for one embodiment of the present invention. Reference numeral 610 in Figure 61 denotes a common initial data group. Figure 61 shows two items: the number of programs and the starting address of the initial device data. As noted in Figure 3, the number of programs can vary depending on the model, as well as who is creating the device and for what purpose. Note that this common initial setting should include free space in advance to allow for additional items in case of unforeseen circumstances.

[0105] Figure 62 is a device data setting diagram showing the initial settings for each program in one embodiment of the present invention. Reference numeral 620 in Figure 62 denotes the initial data group for each process. This corresponds to the number of programs set in Figure 61. In Figure 57, 571 is used as the initial constant area and touch panel display area, but this is the same structure as in Figure 57, where each process number is incorporated into the device memory. In other words, by adding destination and return addresses to the initial settings for each process program, rather than numbers, it is possible to easily accommodate changes.

[0106] Figure 63 is a program flowchart for identifying an initial execution type and starting initial processing in one embodiment according to the present invention. When the program proceeds to "Identification and Initial Processing" 555 in Figure 55, it transitions to "Identification of Initial Execution Type and Start of Initial Processing" 630 in Figure 63, where identification and initial processing begins. First, it "Resets (turns OFF) the execution permission flag" 631, then it "Reads identification data stored in the CPU" 632, and selects "Compares the read identification data with the stored identification data" 633. If the selection results in "Match," it transitions to "Sets (turns ON) the execution permission flag" 634. If the comparison results in "Mismatch," it transitions to "Identification of Initial Execution Type and End of Initial Processing" 637, where identification and initial processing ends. When "Compare read identification data with listed identification data" 633 is selected and the selection result is "Match", "Set execution permission flag (turn ON)" 634 is performed, "Reset input / display device connection flag (turn OFF)" 635 is performed, "Read initial values ​​of each program" 636 is performed, and the process moves to "Identify initial execution type and end initial processing" 637, and the identification and initial processing are completed.

[0107] Based on the program flowchart above, further explanation is provided. This "identification of initial execution type and initial processing" is executed only once when the power is turned from OFF to ON or from STOP to RUN, so it performs two tasks. One is the identification process, from "resetting (turning OFF) the execution permission flag" at 631 to "setting (turning ON) the execution permission flag" at 634. The other is the general preliminary initial processing of all processing. The identification process is a process that ensures that the program is executed only on the CPU in question. Because programs can be easily duplicated, they can be executed identically on different CPUs. In other words, all algorithms can be constructed simply by changing the data. By duplicating and using this program, it is no longer necessary to create programs for each algorithm, as is commonly done for devices and equipment. Here, a bit called an "execution permission flag" is created to implement the identification process. However, relying solely on the ON / OFF state of the execution permission flag is too weak. This is because it is easy to imagine this by closely observing the monitor. To make it more robust, it would be possible to compare the identification data read in for each process with the recorded identification data rather than using the execution permission flag, but this would take some time because it would require several words. More complex processing, such as applying a prime number table, could also be added. 635 performs "resetting (turning OFF) the input / display device connection flag," but this is done to deliberately reset (turn OFF) the bit set from the touch panel (TP) and monitor whether the touch panel (TP) is set (turned ON). The reading of the initial values ​​of each program in 636 is a standard read. It can also be done at the beginning of each process.

[0108] Figure 64 is a program flowchart showing the start of a reset (OFF) process for the differentiation of timing processing for a scan execution type in one embodiment of the present invention. When the process advances to "Reset process for differentiation of timing processing" 556 in Figure 55, the process proceeds to "Start reset (OFF) process for differentiation of timing processing for a scan execution type" 640 in Figure 64, where the reset (OFF) process for differentiation of timing processing begins. First, a selection is made for "Whether or not there is a data count in table data" 641. If the selection is "Yes," the process proceeds to "Disable interrupts of periodic programs" 642. If the selection is "No," the process proceeds to "End reset (OFF) process for differentiation of timing processing for a scan execution type" 64D, where the reset (OFF) process for differentiation of timing processing ends. The "Whether there is data count in table data" 641 is selected, and if the selection result is "Yes," the "Disable interrupt of periodic program" 642 is performed, the "Calculate number of checks from number of data in table data" 643 is performed, the "Initialize number of checks currently being executed" 644 is performed, and the "Compare number of checks with number of checks currently being executed" 645 is selected. If the selection result is "Less than," the process proceeds to the "Read from table data to qualification register" and the "Read scan counter value from table data" 646, and if the selection result is "Equal to or greater than," the process proceeds to the "Enable interrupt of periodic program" 64C. If the "Compare number of checks with number of checks currently being executed" 645 is selected, and if the selection result is "Equal to or greater than," the process proceeds to the "Enable interrupt of periodic program" 64C, and the process proceeds to the "End of reset (OFF) process of differentiation of timing process for scan execution type" 64D, and the process of resetting (OFF) differentiation of timing process is completed. Select "Compare the number of checks with the number of checks currently being executed" at 645, and if the comparison result is "less than", perform "Read from table data to qualification register" at 646 and "Read scan counter value from table data", and select "Scan counter value is" at 647.If the selection result is "1 or less," the process proceeds to "Reset (turn OFF) the generic device bit modified by the modifier register" at 648, and if the selection result is "2 or more," the process proceeds to "Change the scan counter value to 1" at 649. If "Scan counter value is" at 647 is selected and the selection result is "2 or more," the process proceeds to "Change the scan counter value to 1" at 649, and performs "Write modifier register to table data" at 64A and "Write scan counter value to table data" at 64A, and then merges again and repeats, so the process proceeds to "Change the scan counter value to 1" at 649. If "Scan counter value is" at 647 is selected and the selection result is "1 or less," the process proceeds to "Reset (turn OFF) the generic device bit modified by the modifier register" at 648, and performs "Add 1 to the number of checks currently being executed" at 64B, and then merges again and repeats, so the process proceeds to "Compare the number of checks and the number of checks currently being executed" at 645.

[0109] Based on the program flowchart above, further explanation will be provided. This "scan execution type timing differentiation reset (OFF) process" is a program for responding to differentiation performed in the "timing process" of a periodic execution type program. Differentiating bits, acquiring contacts by differentiation, and differentiating instructions can be substituted for output methods, acquisition methods, and instruction execution methods, and are one form of such. Specifically, execution of a scan execution type program group is a repetition of a scan execution type program group, and one execution is called one scan. In other words, differentiation is a form in which only one scan is executed. Differentiating bits means outputting a bit for one scan, acquiring contacts by differentiation means acquiring contacts for one scan, and differentiating instructions means executing an instruction for one scan. However, since one scan of a periodic execution type program is followed by the next cycle, unlike scan execution type programs, if the periodic time of a periodic execution type program is shorter than one scan of a scan execution type program, one scan of the scan execution type program will be interrupted multiple times. Even if differentiation is performed in a periodic execution program, it is not possible to guarantee one scan of a scan execution program. Therefore, scan execution programs may miss data. Therefore, the differentiation is reset (turned OFF) in the scan execution program. In this program, the differentiation is turned ON for a maximum of two scans. Incidentally, in a scan execution program, differentiation can be achieved by setting a bit for differentiation and resetting it in the next scan—that is, by reversing the order of setting and resetting. To better understand program flowcharts, we need to explain table data. Table data is a data group containing a list of devices. The first row indicates the number of items in the table data, and the next row indicates the data itself. Instructions are also available that increment the count each time data is written and decrement the count each time data is read. Details of each code are provided below.The "presence or absence of data in table data" selection in 641 checks whether the beginning of the table data is 0 or not to determine whether differentiation has occurred. The "prohibition of periodic program interrupts" in 642 is performed because the table data is changed during the differentiation reset process of this timing process, and creating differentiation during the timing process of the periodic program would cause the table data to become unstable. The "calculation of the number of checks from the number of data in table data" in 643, the "initialization of the number of checks currently being executed" in 644, the "comparison of the number of checks with the number of checks currently being executed" in 645, and the "addition of 1 to the number of checks currently being executed" in 64B are performed to take into account the occurrence of differentiation at the same time. The "calculation of the number of checks from the number of data in table data" in 643 is performed because when differentiation occurs, two pieces of data, the address and the scan counter, and the address value and the number of checks, are written to the data table, and therefore, when differentiation occurs, the value increases by an even number. "Initialize the number of checks currently being performed" (644) compares the number of checks and the number of checks currently being performed, so it is always performed before each iteration. "Compare the number of checks and the number of checks currently being performed" (645) is the final decision to exit this process. "Read from table data to modifier register" (646) and "Read scan counter value from table data" use table data to transfer the address value and the number of checks. "Scan counter value" (647) is selected to check how many scans have been performed, since differentiation and scanning are closely related. "Reset (turn OFF) the general-purpose device bit modified by the modifier register" (648) resets (turns OFF) after one scan, making the level output appear differentiated. "Change scan counter value to 1" (649) is set to 1 because the scan counter value is set to 2, indicating that one scan has been performed. Since it is not the time to process "Write modifier register to table data" and "Write scan counter value to table data" in 64A, the data is written again to the data table, including the changed scan counter."Add 1 to the number of checks currently being executed" in 64B is performed to establish a comparison between the number of checks and the number of checks currently being executed. "Allow periodic program interrupts" in 64C restores periodic program interrupts because this process does not change the data table.

[0110] Figure 65 is a program flowchart of one embodiment of the present invention, showing the start of scan execution type processing (each processing has the same structure) other than interface processing, sequential step processing, and timing processing. The program flowchart of Figure 65 shows that when you proceed to "Input Device Data Processing" 557, "Device Data Calculation Processing (Input Reference)" 558, "Input Processing" 559, "Logic Processing" 55B, "Device Data Calculation Processing (Output Reference)" 55D, or "Output Processing" 55E in Figure 55, you move to "Processing Other Than Interface Processing, Sequential Stepping Processing, and Timing Processing" 650 in Figure 65, and processing other than interface processing, sequential stepping processing, and timing processing begins. First, you select whether the "Execution Permission Flag" 651 is ON or OFF. If the selection result is "ON", the process moves to "Whether to perform that process" selection in 652, and if the selection result is "OFF", the process moves to "End scan execution type processing other than interface processing, sequential step processing, and timing processing" in 658, and ends scan execution type processing other than interface processing, sequential step processing, and timing processing. If "Whether to perform that process" is selected in 652 and the selection result is "No", the process moves to "End scan execution type processing other than interface processing, sequential step processing, and timing processing" in 658, and ends scan execution type processing other than interface processing, sequential step processing, and timing processing. If the selection result is "Yes", the process performs "Initialize currently executing process number of that process" in 653, performs "Reset (OFF) differentiation of that process" in 654, and selects "Compare process number number of that process with currently executing process number" in 655. If the selection result is "less than", the process proceeds to "execute processing for each number of that process" at 656, and if the selection result is "greater than or equal to", the process proceeds to "end processing other than interface processing, sequential stepping processing, and timing processing" at 657, and processing other than interface processing, sequential stepping processing, and timing processing is terminated. Note that the "differentiation reset (turn OFF) processing" at 654 is not performed in output processing, so this processing is not performed in output processing, and the process proceeds to "compare the processing number number of that process with the processing number currently being executed" at 655.When "Compare the process number of that process with the process number currently being executed" is selected at 655 and the selection result is "less than", "Execute process for each number of that process" at 656 is performed, and "Add 1 to the process number of that process currently being executed" at 657 is performed, and then the processes are joined again and repeated, so the process moves to "Compare the process number of that process with the process number currently being executed" at 655.

[0111] Further explanation will be given based on the above program flowchart. This program flowchart represents the processing that occurs when proceeding to "Input Device Data Processing" 557, "Device Data Calculation Processing (Input Reference)" 558, "Input Processing" 559, "Logic Processing" 55B, "Device Data Calculation Processing (Output Reference)" 55D, and "Output Processing" 55E in Figure 55. Therefore, these are not performed simultaneously. However, since the processing from 653 to 656 differs depending on the processing being executed, six identically structured processes are created and performed. While this is a matter of preference, since the processes are not performed simultaneously, it is possible to structure them by adding data identifying each process and identifying each process using the data identifying each process. This program flowchart also provides a glimpse into the features of the present invention. The currently executing process number is changed by "adding 1 to the currently executing process number of that process" at 656, while "executing each process number of that process" at 655 is repeated, and the repetition is terminated by "comparing the process number number of that process with the currently executing process number" at 654. All of the important processes in the program of this invention ("input device data processing," "device data calculation processing (input reference)," "input processing," "logic processing," "sequential step processing," "device data calculation processing (output reference)," "output processing," and "timing processing") are executed while changing the number, and the repetition is terminated when the number reaches the upper limit. In other words, by changing the number of repetitions, not only can the created program be easily added or deleted, but the structure is also compatible with the construction of all algorithms. Details of each code are provided below. "Is the execution permission flag ON or OFF?" 651 is only performed once when the power is turned from OFF to ON or from STOP to RUN, but this process is enabled depending on whether "the execution permission flag is reset (turned OFF)" 351 in Fig. 35 is performed and "the execution permission flag is set (turned ON)" 354 is performed. "Whether there is data count for that process" 652 is performed to shorten one scan time. "Initialization of the process number currently being executed for that process" 653 is always performed before repeating, in order to compare the process number count with the process number currently being executed.The "reset (turn off) differentiation process for that process" at 654 is performed at the beginning to delay one scan. The selection of "compare the process number number of that process with the process number currently being executed" at 655 is the final decision to exit this process. The "execute process for each number of that process" at 656 clearly indicates that the transition will be made to the detailed program flowchart for each process and each number. The "add 1 to the process number currently being executed for that process" at 657 is performed to establish the comparison between the process number number and the process number currently being executed.

[0112] Figure 66 is a program flowchart for starting a process for resetting (turning off) differentiation other than timing processing (each process has the same structure) in one embodiment of the present invention. When the program flowchart in Figure 66 advances to "Reset (turn off) differentiation for that process" in 654 of Figure 65, it transitions to "Start reset (turn off) differentiation for that process other than timing processing" in 660 of Figure 66 for each process, thereby starting the reset (turn off) process for differentiation other than timing processing. First, a selection is made as to whether or not "the number of data items in table data for that process" is present in 661. If the selection result is "present," it transitions to "Read from table data to modifier register for that process" in 662. If the selection result is "absent," it transitions to "End reset (turn off) differentiation for that process other than timing processing" in 664, thereby ending the reset (turn off) process for differentiation other than timing processing. Select "Whether there is data count in the table data for that process" in 661, and if the confirmation result is "Yes", "Read from the table data for that process to the modification register" in 662, and then "Reset (turn OFF) the general-purpose device bit modified by the modification register" in 663, and then merge again and repeat, so proceed to select "Whether there is data count in the table data for that process" in 661.

[0113] Based on the program flowchart above, further explanation will be provided. This process is paired with "Device Data Processing," "Input Processing," and "Logic Processing," which perform differentiation for each number other than timing processing. Because the table data for each process is different, three identically structured processes are required. While this is a matter of preference, since the processes are not performed simultaneously, it is possible to structure them by adding data identifying each process and identifying the process using the data identifying each process. Furthermore, this process is not a scan execution type program, but rather a part of the program, but is a simplified version of the "Scan execution type timing processing differentiation reset process" in Figure 64. In other words, "Whether there is a number of data items in the table data" 641 in Figure 64 is the same as "Whether there is a number of data items in the table data for that process" 661 in Figure 66, "Read from table data to modifier register" 646 in Figure 64 is the same as "Read from table data to modifier register for that process" 662 in Figure 66, and "Reset (turn OFF) the generic device bit modified by the modifier register" 648 in Figure 64 is the same as "Reset (turn OFF) the generic device bit modified by the modifier register" 663 in Figure 66, with only a slight difference in the arrow, with the other processes removed. Details of each symbol are provided below. The selection of "Whether there is a number of data items in the table data for that process" 661 checks whether the beginning of the table data for that process is 0 or not, and determines whether differentiation has been performed. As shown in Figure 64, table data is a data group in which certain devices are lined up, with the number of items in the table data at the beginning and the data stored thereafter. Instructions are also available that increment the number each time data is written and decrement the number each time data is read. "Read the processing from the table data to the modification register" in 662 uses the table data to pass the address and decrement the number of table data items. "Reset (turn OFF) the general-purpose device bit modified by the modification register" in 663 resets (turns OFF) the bit in one scan, making the level output appear differentiated.

[0114] Fig. 67 is a program flow chart showing the start of execution of processing for each number in input device data processing in one embodiment according to the present invention. When "input device data processing" 558 in Fig. 55 proceeds to "execution of processing for each number of that processing" 376 in Fig. 37, where each processing has the same structure, it moves to "start execution of input device data processing for each number" 670 in Fig. 67, and execution of input device data processing for each number is started. First, in 671, "sequentially track the currently executing processing number from the initial value of the start address of this program and extract the start address of the number", then in 672, "extract the address of each element for the number of elements from the start address of the number", then in 673, "determine the type, comparison symbol, source and destination devices for comparison, and whether or not differentiation is performed from the element value", then in 673, "write the element value of the source address to modification register 1", "write the element value of the destination address to modification register 2", "write the element value of the general-purpose bit address to modification register 3", "write the address of the differentiation prohibition bit determined from the start address of the number to modification register 4", and then in 674, "modify using modification register 1 and compare the determined source device with the determined destination device modified using modification register 2" is selected. If the selection result is "true," the process proceeds to "Whether differentiation is true" at 675, and if the selection result is "false," the process proceeds to "Do not output the general-purpose bit modified by modification register 3 at a level" at 679. If "Compare the comparison source of the device modified by modification register 1 and determined with the comparison destination of the device modified by modification register 2" at 674 is selected, and if the selection result is "false," the process proceeds to "Do not output the general-purpose bit modified by modification register 3 at a level" at 679, and then selects "Is the differentiation prohibition bit modified by modification register 4 true?" at 67A. If the selection result is "true," the process proceeds to "Reset (turn OFF) the differentiation prohibition bit modified by modification register 4" at 67B, and if the selection result is "false," the process proceeds to "End execution of processing for each number of input device data processing" at 67C, and the execution of input device data processing for each number is ended.A selection is made at 67A for "Is the differential differentiation prohibition bit modified by modifier register 4 set?", and if the selection result is "Not set," the process proceeds to "End execution of input device data processing for each number" at 67C, and execution of input device data processing for each number is terminated. At 674, "Compare the comparison source of the device determined by modifying modifier register 1 with the comparison destination of the device determined by modifying modifier register 2" is selected, and if the selection result is "Set," a selection is made at 675 for "Whether or not differential differentiation is performed." If the selection result is "Set," the process proceeds to "Is the differential differentiation prohibition bit modified by modifier register 4 not set?" at 676, and if the selection result is "Not set," the process proceeds to "Output the general-purpose bit modified by modifier register 3 at a level" at 678. The process selects "Whether to perform differentiation" at 675, and if the selection result is "No," the process executes "Output the general-purpose bit modified by modification register 3 at a level" at 678, and proceeds to "End execution of input device data processing by number" at 67C, thereby ending execution of input device data processing by number. The process selects "Whether to perform differentiation" at 675, and if the selection result is "Yes," the process selects "Is the differentiation prohibition bit modified by modification register 4 not established?" at 676. If the selection result is "Not established," the process proceeds to "Set (turn ON) the general-purpose bit modified by modification register 3," "Write modification register 3 to table data," and "Set (turn ON) the differentiation prohibition bit modified by modification register 4" at 677, and if the selection result is "Established," the process proceeds to "End execution of input device data processing by number" at 67C, thereby ending execution of input device data processing by number. Select "Is the differentiation prohibition bit modified by modification register 4 not set?" at 676, and if the selection result is "not set", perform "Set (turn ON) the general-purpose bit modified by modification register 3" at 677, "Write modification register 3 to table data", and "Set (turn ON) the differentiation prohibition bit modified by modification register 4", then proceed to "End execution of input device data processing by number" at 67C, and end execution of input device data processing by number.

[0115] Based on the program flowchart above, we will provide further explanation. This "input device data processing" program handles only comparisons of device data. It performs only judgments such as "equal," "inequality," "greater than or equal," "less than or equal," "exceeds," and outputs the results in general-purpose bits. Naturally, since numeric values ​​have different types, judgments must be written for each type. Because there are also devices and constants, judgments must be written for each, and they must be modified using modifier registers. At first glance, this may seem complex and difficult to interpret. However, once a program is established, its reliability improves quickly because it is characterized by repetition. In typical programs, this block is only created intentionally and is typically written where necessary. As a result, it may be "greater than or equal" in some places and "exceeds" in others, which can lead to bugs. Furthermore, the large amount of description often obscures the final result, and the different shapes, even when repeated, make it difficult to read, which can lead to bugs. Below are details about each symbol. The "extraction of the starting address of the number by tracing the initial value from the starting address of this program for the currently executing processing number in sequence" in 671 proceeds from "identification and initial processing" in 555 of Fig. 55 to "start of identification and initial processing" in 630 of Fig. 63, and the value written in the starting address of the input device data processing read in "reading initial values ​​of each program" in 636 is written to a modification register, the device data modified by the modification register becomes the next destination, and by repeating this the number of times specified by the number, the starting address of the number can be extracted. The "extraction of the address of each element for the number of elements from the starting address of the number" in 672 proceeds from "identification and initial processing" in 555 of FIG. 55 to "start of identification and initial processing" in 630 of FIG. 63, and is performed using the position of each element read in "reading the initial value of each program" in 636 and the starting address of the number extracted in "extracting the starting address of the number by tracing the initial value from the starting address of this program for the number of processing numbers currently being executed in sequence" in 671.The steps 673, "determine the type, comparison symbol, source and destination devices, and whether differentiation is enabled or disabled from the element value," "write the element value of the source address to modification register 1," "write the element value of the destination address to modification register 2," "write the element value of the general-purpose bit address to modification register 3," and "write the address of the differentiation disabled bit determined from the starting address of the number to modification register 4," are preparations for the step 674, "compare the source device of the device determined after modification using modification register 1 with the destination device of the device determined after modification using modification register 2." The selection of the step 674, "compare the source device of the device determined after modification using modification register 1 with the destination device of the device determined after modification using modification register 2," is made to output based on the result of this selection. The selection of the step 675, "whether differentiation is enabled or disabled," determines whether the final general-purpose bit output is differentiated. The selection of "Is the differential differentiation prohibition bit modified by Modification Register 4 not established?" in 676 is because, in the case of differential differentiation, if the condition is established, the bit is turned ON for only one scan, but this bit remains ON until the condition is no longer established. "Set (turn ON) the general-purpose bit modified by Modification Register 3," "Write Modification Register 3 to table data," and "Set (turn ON) the differential differentiation prohibition bit modified by Modification Register 4" in 677 are the final outputs in differential differentiation when the condition is established. "Output the general-purpose bit modified by Modification Register 3 as a level" in 678 is the final output when no differential differentiation is performed. "Do not output the general-purpose bit modified by Modification Register 3 as a level" in 679 is a non-output process when the condition is not established. This is paired with 678. The selection of "Is the differential differentiation prohibition bit modified by Modification Register 4 established?" in 67A selects initialization of the differential differentiation prohibition bit. "Reset (turn OFF) the differential differentiation prohibition bit modified by the modification register 4" in 67B initializes the differential differentiation prohibition bit.

[0116] Fig. 68 is a program flow chart showing the start of execution of processing for each number in device data calculation processing (both input and output criteria are identical) in one embodiment according to the present invention. From "Device Data Calculation Processing (Input Criteria)" 558 and "Device Data Calculation Processing (Output Criteria)" 55D in Fig. 55, which have identical input and output criteria, to "Execution of Processing for Each Number of That Processing" 656 in Fig. 65 (each processing has the same structure), the program proceeds to "Start execution of processing for each number of device data calculation processing" 680 in Fig. 68, and execution of device data calculation processing for each number is started. First, "sequentially trace the currently executed processing numbers from the initial value of the start address of this program and extract the start address of the number" is performed in 681, then "extract the addresses of each element for the number of elements from the start address of the number" is performed in 682, then "determine the logic of the activation bit from the element value" and "write the element value of the activation bit address to modification register 1" are performed in 683, and a selection is made as to whether the activation bit modified by modification register 1 is established according to the logic of the activation bit in 684. If the selection result is "established", the process proceeds to "determine the type, operation instruction, and number of operands from the element value" and "determine the device corresponding to each operand" in 685, and "write the element values ​​of the addresses corresponding to each operand in order from modification register 2"; if the selection result is "not established", the process proceeds to "end execution of device data operation processing for each number" in 687, and the execution of device data operation processing for each number is terminated. At 684, "According to the logic of the activation bit, is the activation bit modified by modification register 1 set?" is selected, and if the selection result is "set", then at 685, "type, operation instruction, and number of operands are determined from element value", "device corresponding to each operand is determined", and "element values ​​of addresses corresponding to each operand are written in order starting from modification register 2", then at 686, "each operand modified by modification register 2 onwards is executed with the determined operation instruction having only the number of operands", and the process proceeds to "end execution of device data operation processing by number" at 687, thereby ending execution of device data operation processing by number.

[0117] Based on the program flowchart above, further explanation will be provided. This "Device Data Calculation Processing (Input-Based, Output-Based)" is a program that handles only instruction processing. Since this processing is a step that proceeds to "Device Data Calculation Processing (Input-Based)" 558 and "Device Data Calculation Processing (Output-Based)" 55D in Figure 55, they are not performed simultaneously. However, since the processing from 681 to 686 differs depending on the processing being performed, two identically structured processes are required. The division into input-based and output-based is due to the fact that input-based processing is used to generate results for other processing, while output-based processing is used to generate results from other processing. While instruction processing differs depending on the manufacturer of the programmable logic controller (PLC), all manufacturers perform the same operations. There are 200 to 300 types available. Some manufacturers call these "sources" and "destinations," but the maximum number of operands is around seven. Simply put, around 2,800 case distinctions would be required. However, since there are very few programs with seven operands, around 400 case distinctions are sufficient. In addition, when device selection is included, the number of cases increases, but it is still sufficient to handle them. Incidentally, while the number of instruction words used by each company is increasing, based on my many years of experience building programmable logic controller (PLC) software, I can't help but feel that specifying instruction words that are rarely used is pointless. While this is a matter of preference, since input-based processing and output-based processing are not performed simultaneously, it is possible to structure the processing by adding data specifying input-based processing and output-based processing, and then specifying the processing using the data specifying input-based processing and output-based processing. Details of each code are provided below. The "extraction of the starting address of the number by tracing the initial value from the starting address of this program for the currently executing processing number in sequence" in 681 proceeds from "identification and initial processing" in 555 of Fig. 55 to "start of identification and initial processing" in 630 of Fig. 63, and the value written in the starting address of the input device data processing read in "reading initial values ​​of each program" in 636 is written to a modification register, the device data modified by the modification register becomes the next destination, and by repeating this the number of times specified by the number, the starting address of the number can be extracted."Extracting the address of each element for the number of elements from the starting address of the number" in 682 proceeds from "Identification and initial processing" in 555 of Fig. 55 to "Start of identification and initial processing" in 630 of Fig. 63, and is performed using each element position read in "Reading initial values ​​of each program" in 636 and the starting address of the number extracted in "Extracting the starting address of the number by tracing the initial value from the starting address of this program for the currently executing processing number in sequence" in 681. "Determining the logic of the activation bit from the element value" in 683 and "Writing the element value of the activation bit address to modification register 1" are performed in advance to prepare for selecting "Whether the activation bit modified by modification register 1 is established according to the logic of the activation bit" in 684. "Whether the activation bit modified by modification register 1 is established according to the logic of the activation bit" in 684 is performed based on the result of this selection. The “type, operation instruction, and number of operands are determined from the element values”, “a device corresponding to each operand is determined”, and “element values ​​of addresses corresponding to each operand are written in order starting from modification register 2” in 685 are preparations before the “operands modified by modification register 2 and onwards are executed by a determined operation instruction having the number of operands” in 686. The “operands modified by modification register 2 and onwards are executed by a determined operation instruction having the number of operands” in 686 is the final operation process.

[0118] Fig. 69 is a program flow chart showing the start of execution of processing for each number in the input processing in one embodiment according to the present invention. When proceeding from "input processing" 559 in Fig. 55 to "execution of processing for each number of that processing" 656 in Fig. 65 (each processing has the same structure), it moves to "start execution of processing for each number of input processing" 690 in Fig. 69, and execution of the input processing for each number is started. First, "sequentially trace the currently executing processing number from the start address of this program as the initial value, and extract the start address of the number" is performed in 691, "extract the address of each element for the number of elements from the start address of the number" is performed in 692, "determine the device, input bit logic, and presence or absence of differentiation from the element value" is performed in 693, "write the element value of the real address to modification register 1" is performed, "write the element value of the general-purpose bit address to modification register 2" is performed, and "write the address of the differentiation prohibition bit determined from the start address of the number to modification register 3" is performed, and then "modify with modification register 1, and is the determined bit of the device set?" is selected in 694. If the selection result is "set", the process proceeds to "presence or absence of differentiation" in 695, and if the selection result is "not set", the process proceeds to "do not output the general-purpose bit modified with modification register 2 at a level" in 699. The program selects "Is the bit of the determined device modified by Modification Register 1 set?" at 694, and if the selection result is not "set," it executes "Do not output the general-purpose bit modified by Modification Register 2 at a level" at 699, and selects "Is the differential differentiation prohibition bit modified by Modification Register 3 set?" at 69A. If the selection result is "set," it proceeds to "Reset (turn OFF) the differential differentiation prohibition bit modified by Modification Register 3" at 69B, and if the selection result is "not set," it proceeds to "End execution of processing for each number of input processing" at 69C, and ends execution of input processing for each number. The program selects "Is the differential differentiation prohibition bit modified by Modification Register 3 set?" at 69A, and if the selection result is "set," it executes "Reset (turn OFF) the differential differentiation prohibition bit modified by Modification Register 3" at 69B, and then proceeds to "End execution of processing for each number of input processing" at 69C, and ends execution of input processing for each number."Is the bit of the determined device modified by the modifier register 1 set?" is selected at 694, and if the selection result is "set", a selection of "whether or not to set differential differentiation" is made at 695. If the selection result is "set", the process proceeds to "whether or not to set differential differentiation prohibition bit modified by the modifier register 3?" at 696, and if the selection result is "not set", the process proceeds to "output the general-purpose bit modified by the modifier register 2 at a level" at 698. If "whether or not to set differential differentiation" is selected at 695 and the selection result is "not set", the process proceeds to "output the general-purpose bit modified by the modifier register 2 at a level" at 698, and then the process proceeds to "end execution of processing for each number of input processing" at 69C, and the execution of the input processing for each number is ended. If "whether or not to set differential differentiation" is selected at 695 and the confirmation result is "set", a selection of "whether or not to set differential differentiation prohibition bit modified by the modifier register 3?" is made at 696. If the selection result is "not established," the process proceeds to "Set (turn ON) the general-purpose bit modified by modification register 2," "Write modification register 2 to table data," and "Set (turn ON) the differential differentiation prohibition bit modified by modification register 3" at 697, and if the selection result is "established," the process proceeds to "End execution of input processing for each number" at 69C, and the execution of input processing for each number is terminated. If "Is the differential differentiation prohibition bit modified by modification register 3 not established?" at 696 is selected and the confirmation result is "not established," the process proceeds to "Set (turn ON) the general-purpose bit modified by modification register 2," "Write modification register 2 to table data," and "Set (turn ON) the differential differentiation prohibition bit modified by modification register 3" at 697, and the process proceeds to "End execution of input processing for each number" at 69C, and the execution of input processing for each number is terminated.

[0119] Let's take a closer look at the program flowchart above. This "input processing" is a program that replaces bits specified by the device with general-purpose bits. While its main purpose is to replace externally input bits with general-purpose bits, it also performs logic inversion, converting positive logic to negative logic and negative logic to positive logic, and differentiation. In general programs, externally input bits are not replaced with general-purpose bits, but are instead written directly in the desired locations. Replacing with general-purpose bits is rarely done, and when the list becomes long, it is only done on a whim. This direct writing of bits in the desired locations is one of the factors that makes programs complex. For example, suppose there is input A, 10 Bs that move when A is input, 10 Cs that continue to move when A is input, 10 Ds that stop when A is input, 10 Es that stop when A is input, 10 Fs that can move when A is input, and 10 Gs that must stop when A is input. If you want to change 10 Bs to input X instead of input A, you need to change 10 of them. If that's all you need, you can get away with just 10 changes. However, if A and X interact with each other, it will affect 50 other points, further increasing the complexity. In other words, B, which moves when input is input, and C, which continues to move when input is input, differ in the location of input A incorporated into B and C. This can be solved by creating a general-purpose bit for input A for each role, but this is not often done because it is time-consuming and increases program size. For the above reasons, device input bits are replaced with general-purpose bits. There is also a logical inversion command, which can be used freely wherever desired. This ability to freely perform logical inversion is one of the factors that makes programs difficult to understand. In the worst cases, logical inversion is further inverted, and when logical products and logical sums are added, the program becomes even more difficult to understand. This logical inversion can be solved by simply creating another output. In this invention, this "input processing" is not present on the output side at all, and is only provided on the input side. Differentiation can also be used freely where desired, as it is possible to differentiate outputs, contacts, and calculation commands.Differentiation is a very important output format, but because it only takes one scan and cannot be captured on a monitor, engineering tools are trying to improve their tracing capabilities. However, pointless differentiation is becoming a problem. In this invention, differentiation is only possible for "device data processing," "logic processing," and "timekeeping processing," including "input processing." Details of each code are provided below. The "sequential tracing of the initial value of this program from the start address of the currently executing processing number to extract the start address of the number" in 691 proceeds from "identification and initialization processing" in 555 of Figure 55 to "start of identification and initialization processing" in 630 of Figure 63, where the value written at the start address of the input processing read in "reading the initial value of each program" in 636 is written to a modification register. The device data modified by the modification register becomes the next destination. Repeating this process the number of times indicated by the number allows the start address of the number to be extracted. 55 to "Start of identification and initialization processing" 630 in Fig. 63, and then using each element position read in "Read initial value of each program" 636 and the starting address of the number extracted in "Extract starting address of number by tracing the currently executing processing number from the starting address of this program of the initial value in sequence" 691. "From the element value, determine the device, input bit logic, and presence or absence of differentiation, and write the element value of the real address to modification register 1" 693, "write the element value of the general-purpose bit address to modification register 2", and "write the address of the differentiation prohibition bit determined from the starting address of the number to modification register 3" are performed for advance preparation such as selecting "modify with modification register 1, and whether the bit of the determined device is set" 694. The output is determined based on the result of the selection of "is the bit of the determined device established after modification using the modification register 1?" in 694. The selection of "whether to differentiate" in 695 determines whether the final general-purpose bit output is differentiated.The selection of "Is the differential differentiation prohibition bit modified by Modification Register 3 not established?" in 696 is because, in the case of differential differentiation, if the condition is established, the bit is turned ON for only one scan, but this bit remains ON until the condition is no longer established. "Set (turn ON) the general-purpose bit modified by Modification Register 2" in 697, "Write Modification Register 3 to table data," and "Set (turn ON) the differential differentiation prohibition bit modified by Modification Register 3" are the final outputs in differential differentiation when the condition is established. "Output the general-purpose bit modified by Modification Register 2 as a level" in 698 is the final output when no differential differentiation is performed. "Do not output the general-purpose bit modified by Modification Register 2 as a level" in 699 is a non-output process when the condition is not established. This is paired with 698. "Is the differential differentiation prohibition bit modified by Modification Register 3 established?" in 69A determines the initialization of the differential differentiation prohibition bit. "Reset (turn OFF) the differential differentiation prohibition bit modified by the modification register 3" in 69B initializes the differential differentiation prohibition bit.

[0120] FIG. 70 is a program flowchart for starting interface processing for a scan execution type in one embodiment according to the present invention. Proceeding to "Interface Processing" 55A in FIG. 55 transitions to "Start Interface Processing for Scan Execution Type" 700 in FIG. 70, where interface processing begins. First, a selection is made as to whether the "Execution Permission Flag is ON or OFF" in 701. If the selection result is "ON," the process transitions to "An Uncontrolled Input Device is Not Writing" in 702. If the selection result is "OFF," the process transitions to "End Interface Processing for Scan Execution Type" in 70H, where touch panel processing ends. After selecting "Execution Permission Flag is ON or OFF" in 701, if the selection result is "ON," the process transitions to "An Uncontrolled Input Device is Not Writing" in 702. If the selection result is "No", the process proceeds to "Is the input display device connection flag ON or OFF?" in 703, and if the selection result is "Yes", the process proceeds to "End of interface processing of scan execution type" in 70H, and the touch panel processing ends. If "Is the non-controlled input device writing?" in 702 is selected and the selection result is "No", the process proceeds to "Is the input display device connection flag ON or OFF?" in 703. If the selection result is "On", the process proceeds to "Is any of the device data input screens to be used displayed?" in 704, and if the selection result is "Off", the process proceeds to "End of interface processing of scan execution type" in 70H, and the touch panel processing ends. If "Is the input display device connection flag ON or OFF?" in 703 is selected and the selection result is "On", the process proceeds to "Is any of the device data input screens to be used displayed?" in 704. If the selection result is "yes", the process proceeds to "Redisplay selected screen data" at 705, and if the selection result is "no", the process proceeds to "End interface processing of scan execution type" at 70H, and the touch panel processing ends. If "Any of the device data input screens to be used is displayed" at 704 is selected, and the selection result is "yes", the process proceeds to "Redisplay selected screen data" at 705, and the process proceeds to "Do not switch screens" at 706.If the selection result is "no", the process proceeds to "Is a final decision window displayed?" in 707, and if the selection result is "yes", the process proceeds to "End interface processing of scan execution type" in 70H, and the touch panel processing ends. If "Do not change screen?" in 706 is selected and the selection result is "no", the process proceeds to "Is a final decision window displayed?" in 707. If the selection result is "yes", the process proceeds to "Specify which process and which element" in 708, and if the selection result is "no", the process proceeds to "End interface processing of scan execution type" in 70H, and the touch panel processing ends. If "Is a final decision window displayed?" in 707 is selected and the selection result is "yes", the process proceeds to "Specify which process and which element" in 708, and the process proceeds to "End interface processing of scan execution type" in 70H, and the touch panel processing ends. If the selection result is "yes," the process proceeds to "Does...

Claims

1. A program for use in a programmable logic controller (PLC) comprising a CPU, a first memory, and a second memory, the CPU reading first data, which is stored in the first memory and has a structure corresponding to data arranged in a matrix format for each process of controlling a device, and in which each row contains a next row address, which is the address of the row to be read after that row, as one column of data, rewriting second data, which is data stored in a second memory and specifies the operation of the device, according to the first data read, reading the rewritten second data from the second memory, and controlling the device according to the second data read, the program being read by the CPU and causing the CPU to: read the first data row by row, and when all rows have been read, return to the top row and repeat the reading; and use the next row address to read column data of the row whose address is indicated by the next row address after reading of the column data of the row including the next row address has been completed.

2. The program according to claim 1, wherein the first data has column data to be repeatedly read by the CPU lined up in one row for the number of repetitions, and the column preceding the column data for the number of repetitions contains the repetition number as a single piece of column data, and each row of the first data further contains, as a single piece of column data, a previous row address which is the address of a row that should be read and completed before the row that should be read next to that row, and the program causes the CPU to, in response to an external instruction, when making a change to increase the number of repetitions, copy all of the column data of the row in which the change is to be made, using as a starting address the address next to the last address used as the first data in the first memory, and after the change is completed, use the previous row address of the row in which the change was made to change the next row address of the row in which the change was made to the address of the row in which the change was made.

3. The program according to claim 1 or 2, wherein the first data has a different number of words in the same column between at least two rows, the number of words in the same column being included as one column data in the column preceding the same column in each row, and each row of the first data further includes, as one column data, a previous row address which is the address of a row that should be read before the row to be read next to the row in question, and the program causes the CPU to execute the following when making a change to increase the number of words in response to an external instruction: copy all of the column data of the row in which the change is to be made, using as a starting address the address next to the last address used as the first data in the first memory, and after the change is completed, use the previous row address of the row in which the change was made to change the next row address of the row that should be read before the row in which the change was made to the address of the row in which the change was made.

4. The program according to claim 1, wherein each line of the first data further includes, as one column of data, a previous row address which is the address of a row that should be read immediately before the next line to be read after the line, and the program causes the CPU to execute, in response to an external instruction, using the previous row address to change the next row address of the address of the line indicated by the previous row address to the next row address of the line to be deleted when deleting a line including the previous row address.

5. The program according to claim 3, wherein each line of the first data further includes, as one column of data, a previous row address which is the address of a row that should be read immediately before the next line to be read after the line, and the program causes the CPU to execute, in response to an external instruction, using the previous row address to change the next row address of the row indicated by the previous row address to the next row address of the line to be deleted when deleting a line including the previous row address.

6. The program according to claim 1, wherein each line of the first data further includes, as one column of data, a previous row address which is the address of a row which should be read just before the next line to be read after the line, and the program causes the CPU to execute, in response to an external instruction, when adding a new line, set the start of the address of the line to be added to the address next to the last address used as the first data in the first memory, change the next row address of the line to be added to the next row address of the line to be added, and use the previous row address to change the next row address of the line to be added, which should be read just before the line to be added.

7. The program according to claim 3, wherein each line of the first data further includes, as one column of data, a previous row address which is the address of a row which should be read just before the next line to be read after the line, and the program causes the CPU to execute, in response to an external instruction, when adding a new line, set the start of the address of the line to be added to the address next to the last address used as the first data in the first memory, change the next row address of the line to be added to the next row address of the line to be added, and use the previous row address to change the next row address of the line to be added, which should be read just before the line to be added.

8. The second data includes device data, the device data includes device bits, the device bits include general-purpose bits, input bits, and output bits, and the program causes the CPU to: execute an input device data process for comparing the device data for each row across all rows of the first data and changing the ON / OFF state of the general-purpose bits according to the results; an input process for changing the ON / OFF state of the general-purpose bits according to the state of the input bits for each row across all rows of the first data; a logic process for replacing the ON / OFF state of the general-purpose bits with the ON / OFF state of the general-purpose bits when a logical AND or OR of a plurality of general-purpose bits output from another process becomes true for each row across all rows of the first data; a sequential step process for transferring and transmitting an execution state of a process to another row or to a row of another process by transitioning the ON state of the general-purpose bits based on the general-purpose bits output from the other process for each row across all rows of the first data; and a device data calculation process for calculating and executing device data or device bits according to a calculation function defined for the CPU for each row across all rows of the first data. The program according to claim 1 or 2, characterized in that it executes an output process that changes the ON / OFF state of an output bit by a general-purpose bit output from another process, for each row of the first data.

9. The second data includes device data, the device data includes device bits, and the device bits include general-purpose bits, input bits, and output bits, and the program causes the CPU to: execute an input device data process for comparing the device data for each row across all rows of the first data and changing the ON / OFF state of the general-purpose bits according to the results; an input process for changing the ON / OFF state of the general-purpose bits according to the state of the input bits for each row across all rows of the first data; a logic process for replacing the ON / OFF state of the general-purpose bits with the ON / OFF state of the general-purpose bits when a logical AND or OR of a plurality of general-purpose bits output from another process becomes true for each row across all rows of the first data; a sequential step process for transferring and transmitting an execution state of a process to another row or to a row of another process by transitioning the ON state of the general-purpose bits based on the general-purpose bits output from the other process for each row across all rows of the first data; and a device data calculation process for calculating and executing device data or device bits according to a calculation function defined for the CPU for each row across all rows of the first data. and an output process for changing the ON / OFF state of an output bit by a general-purpose bit output from another process, for each row of the first data.

10. The program according to claim 1 or 2, characterized in that the second data includes device data, which includes device bits, which include general-purpose bits, and the program causes the CPU to repeatedly execute, at regular time intervals, a timing process that changes the ON / OFF state of a general-purpose bit depending on the general-purpose bit output from another process and the passage of time, for each row across all rows of the first data.

11. The program according to claim 3, characterized in that the second data includes device data, the device data includes device bits, and the device bits include general-purpose bits, and the program causes the CPU to repeatedly execute, at regular time intervals, a timing process that changes the ON / OFF state of the general-purpose bits by using general-purpose bits output from another process and the passage of time, for each row across all rows of the first data.

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