Display tile for a display assembly with transferred pixel emitters

Abstract

Display tiles for a display assembly with transferred pixel emitters are described herein. For example, a display assembly may include a carrier substrate and a display tile with a subset of pixel emitters and an integrated circuit electrically connected to the subset of pixel emitters. The set of pixel emitters and the integrated circuit may both be transferred to the carrier substrate after fabrication. The integrated circuit may include, a set of pixel drivers configured to drive the subset of pixel emitters, as well as a modulator configured to control, based on signaling associated with a portion of a content frame, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique. Corresponding methods and integrated circuits are also disclosed.

Description

DISPLAY TILE FOR A DISPLAY ASSEMBLYWITH TRANSFERRED PIXEL EMITTERSCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority- to, and the benefit of, U.S. Provisional Application No. 63 / 595,950, filed on November 3, 2023, the disclosure of which is hereby incorporated by reference in its entirety.BACKGROUND

[0002] Semiconductor fabrication processes allow for the creation of extremely small electronic components such as transistors, resistors, capacitors, light emitting diodes (LEDs), and so forth. Fabrication of these semiconductor products may involve a series of precise steps, including depositing thin films of materials, patterning circuits using photolithography and etching techniques, and finally connecting everything through metallization.

[0003] For many electronic components, it may be advantageous to miniaturize the components to a nearly unlimited extent. For instance, the more that transistor logic can be miniaturized, the more functionality (e.g., processing and storage capability) may fit on a single chip to result in electronic devices that are fast, portable, low power, and so forth. For other electronic components, however, their usefulness may be limited as the components become smaller in size. As one example, micro light emitting diodes (microLEDs) and other small light emission components used as pixels in electronic displays may, when miniaturized beyond a certain extent, become so small that magnification is required for a user to see and appreciate the high resolution being provided. While such magnification may be acceptable or desirable for certain applications, the high resolution possible with these ty pes of pixel emitters may be wasteful and undesirable for direct-view applications in which display screens are not magnified.SUMMARY

[0004] Extremely small pixel emitters such as microLEDs can be sparsely distributed on a display assembly to make the display suitable for direct viewing while still being efficient in various respects. One challenge with such a configuration, however, is that fanout to possibly many thousands of individual pixel emitters (or more) may be virtuallyimpossible to accomplish using a single integrated circuit configured to perform all the tasks typically handled by backplane circuitry in conventional display assemblies. Accordingly, display tiles are described herein that may be used for display assemblies with transferred pixel emitters (i.e., display assemblies that use pixel emitters transferred to a carrier substrate after being fabricated elsewhere). Using an architecture in which one controller circuit controls a plurality of the display tiles described herein, operations conventionally performed by backplane circuitry (e.g., data processing, image buffering, pulse-width-modulation (PWM) sequencing, pixel driving, etc.) may be accomplished for direct-view display assemblies with a set of pixel emitters that have any desirable quantity (not being limited by the fanout issue), are placed at any desirable pixel pitch (to produce a desirable pixel resolution), and are arranged with respect to any desirable lattice and in any desirable shape (to produce a display assembly tailored to any shape of device).

[0005] To this end, one implementation described herein involves a display assembly that includes: 1) a carrier substrate; 2) a subset of pixel emitters included within a set of pixel emitters, the set of pixel emitters being transferred to the carrier substrate after fabrication of the set of pixel emitters; and 3) an integrated circuit electrically connected to the subset of pixel emitters, the integrated circuit being transferred to the carrier substrate after fabrication of the integrated circuit and including: (a) a set of pixel drivers configured to drive the subset of pixel emitters, and (b) a modulator configured to control, based on signaling associated with a portion of a content frame, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

[0006] Other implementations described herein involve methods that may be performed by various components of an integrated circuit configured for use in a display tile for a display assembly with transferred pixel emitters such as described herein. For instance, one example method may include: 1) receiving, by an integrated circuit transferred to a carrier substrate after fabrication of the integrated circuit, signaling associated with a portion of a content frame; 2) controlling, by a modulator of the integrated circuit and based on the signaling, a set of pixel drivers of the integrated circuit; and 3) driving, by the set of pixel drivers based on the controlling by the modulator, a subset of pixel emitters included within a set of pixel emitters that is transferred to the carrier substrate after fabrication of the set of pixel emitters. For example, this driving of the subset of pixel emitters may be configured to present the portion of the content frame using a pulse width modulation technique.

[0007] Still other implementations described herein involve integrated circuits configured for use in a display tile for a display assembly with transferred pixel emitters. Forinstance, one example integrated circuit may include: 1) a first signal interface configured to electrically connect to a subset of pixel emitters included within a set of pixel emitters, the set of pixel emitters being transferred to a carrier substrate after fabrication of the set of pixel emitters; 2) a second signal interface configured to receive signaling associated with a portion of a content frame; 3) a set of pixel drivers configured to drive the subset of pixel emitters; and 4) a modulator configured to control, based on the signaling, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

[0008] Various additional implementations are explicitly described herein or may follow from principles described below. It will be understood that each of the examples mentioned above and described below may be implemented in different types of implementations. For example, the various display systems described herein could each be implemented in a variety’ of different types of devices, methods described herein could be implemented by instructions stored in a non-transitory computer-readable medium, a non- transitory computer-readable medium storing such instructions could be implemented in a display system or integrated circuit, and so forth.

[0009] The details of these and other implementations are set forth in the accompanying drawings and the description below. Other features will also be made apparent from the following description, drawings, and claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows illustrative aspects of a display tile for a display assembly with transferred pixel emitters in accordance with principles described herein.

[0011] FIG. 2A shows illustrative aspects of transferring a set of pixel emitters to a carrier substrate after fabrication of the set of pixel emitters in accordance with principles described herein.

[0012] FIG. 2B shows additional illustrative aspects of transferring a set of pixel emitters to a carrier substrate after fabrication of the set of pixel emitters in accordance with principles described herein.

[0013] FIG. 3A shows illustrative aspects of a plurality of display tiles of an example direct-view display with transferred pixel emitters in accordance with principles described herein.

[0014] FIG. 3B shows an illustrative way that display tiles having respective integrated circuits and subsets of pixel emitters may be arranged in accordance withprinciples described herein.

[0015] FIG. 3C shows another illustrative way that display tiles having respective integrated circuits and subsets of pixel emitters may be arranged in accordance with principles described herein.

[0016] FIG. 3D shows yet another illustrative way that display tiles having respective integrated circuits and subsets of pixel emitters may be arranged in accordance with principles described herein.

[0017] FIG. 4 shows an illustrative method that may be performed by an integrated circuit used in a display tile for a display assembly with transferred pixel emitters in accordance with principles described herein.

[0018] FIG. 5A shows an illustrative way that pixel emitters may be arranged on a lattice in accordance with principles described herein.

[0019] FIG. 5B shows another illustrative way that pixel emitters may be arranged on a lattice in accordance with principles described herein.

[0020] FIG. 6A shows an illustrative way that redundant pixel emitters may be integrated with the pixel emitters of FIG. 5 A in accordance with principles described herein.

[0021] FIG. 6B shows an illustrative way that redundant pixel emitters may be integrated with the pixel emitters of FIG. 5B in accordance with principles described herein.

[0022] FIGS. 7A-7F show illustrative steps of a process for fabricating a chiplet in accordance with principles described herein.

[0023] FIG. 8 shows illustrative elements of a direct- view display with monolithic RGB chiplets such as illustrated in FIGS. 7A-7F.

[0024] FIG. 9 shows an illustrative computing system that may be used to implement various devices and / or systems in accordance with principles described herein.DETAILED DESCRIPTION

[0025] Display tiles configured for use with display assemblies with transferred pixel emitters are described herein. While various advantages can be gained by distributing small pixel emitters (e.g., microLEDs) to a direct-view display, various technical problems described herein may also be addressed. As one example, there may be far too many individual pixel emitters on a given display (e.g., many thousands or more) for a singular integrated circuit to connect to and drive. Accordingly, display tiles described herein each include a subset of pixel emitters and a dedicated integrated circuit (referred to herein as a driver circuit) that is configured to drive the subset of pixel emitters based on direction from ahigher-level integrated circuit (referred to herein as a controller circuit). In this way, display tiles described herein may facilitate the display of content frames of arbitrary size and shape under direction from, an in cooperation with, the controller circuit as the controller circuit handles a variety of operations (e.g., data processing, buffering, pixel driving, pulse-width- modulation (PWM) sequencing, etc.) typically handled by backplane circuitry in conventional display assemblies.

[0026] Display assemblies featuring pixel emitters such as microLEDs offer significant advantages compared to other display technologies (e.g., OLED, LCD). For example, each pixel emitter (e.g., each individual microLED or each cluster of red, green, and blue microLEDs) may be controllable to emit light (ON) or not emit light (OFF), leading to extremely high (e.g.. infinite) contrast ratios. Moreover, response times of microLED pixels may be very short, leading to crisp and responsive displays with bright colors, high frame rates, and high power efficiency. To gain these and other significant benefits of microLEDs on a direct- view display, however, a variety of technical problems may need to be addressed.

[0027] A first technical problem relates to the size and angular pitch of microLED pixel emitter technologies. MicroLED fabrication processes may produce pixel panels with a pixel pitch in the range of a few microns, allowing for the fabrication of panels with hundreds of thousands or millions of pixels per square centimeter. Such pixel resolution goes well beyond the resolving capacity of the human visual system, such that panels with pixel density in this range are typically magnified significantly before being viewed by the user. As one example of where these technologies have been useful, extended reality headsets (e.g., augmented reality glasses, etc.) are a good fit for extremely dense pixel panels, since the form factor provides very limited space for the pixel panel and since a complex optical stack (including magnification and other optical manipulation) between the pixel panel and the heads-up display viewed by the user may help process and prepare the light to be viewed by the user in the intended way.

[0028] While high-density microLED pixel panels may be a natural fit for magnified displays such as may be integrated into head-mounted display devices (e.g., extended reality glasses, etc.), the bnghtness. power efficiency, and other attributes of microLED devices may make these devices desirable for other types of applications as well, including for direct-view display applications. As used herein, a direct-view' display refers to a display that is configured for viewers to look at directly, without significant manipulation of the light (e.g., beyond natural distortion that may be introduced by a cover glass or other such optical device integrated with the display for protection or aesthetic purposes). For example, direct-viewdisplays may stand in contrast to displays, such as may be included in head-mounted extended reality devices, that manipulate light in more significant ways (e.g.. significantly magnifying the light, moving the light through a waveguide, projecting the light to form an image on a display separate from the pixel panel or directly on the user’s retina, etc.). While it may be common for head-mounted display devices to magnify and otherwise process the light for their displays, a few example applications that typically use direct-view displays are smartwatch devices, mobile devices (e.g., smartphones, tablets, etc.), computer monitors, and television screens.

[0029] This first technical problem that may arise relates to extremely small pixel emitters (such as microLEDs) being employed for direct-view displays and the pixel pitch being so small as to be wasteful and inefficient. For example, even though a smartwatch display may only be a few square centimeters in size, the number of microLEDs that could fit on a direct-view display of that size could be in the tens of millions. Along with adding significant cost to the device’s bill of materials, a display with this type of resolution would place significant strain on power and heat requirements of the device, along with creating other complications and resource requirements associated with driving the display and processing / storing the high-resolution images it would produce. Even if all of these issues were addressed by a certain design, the design would still be wasteful and inefficient as the human visual system would not have the capacity to even resolve such high pixel resolution.

[0030] In response to this technical problem, at least one technical solution described herein involves producing direct-view display assemblies that use sparse distributions of pixel emitters. For example, after fabrication of a set of pixel emitters on a donor wafer at a first pixel pitch (e.g.. a very small pixel pitch that the human visual system would be unable to resolve), the set of pixel emitters may be transferred to a carrier substrate in a manner that distributes the pixel emitters more sparsely to increase the pixel pitch to a greater pitch that is more reasonably resolvable by the human visual system (though an arbitrarily high display resolution can still be provided). In this way, the waste and inefficiency of overly high display resolution may be avoided for the direct-view display, while the desired brightness, power-efficiency, dynamic range, and other benefits of microLED technology can be provided. While smartwatch displays provide one good example of an application where direct-view display assemblies with sparse distributions of pixel emitters could be used, it will be understood that principles described herein could similarly be used with a variety of other direct-view display applications such as mobile devices, computer monitors, television screens, appliance panels, automotive interfaces, and so forth.

[0031] Along with distributing pixel emitters more sparsely on a display assembly (so as to increase the pixel pitch to a level that can be more reasonably resolved by users), another technical problem addressed by display assemblies described herein relates to how power and signaling can be distributed to the pixel emitters in their sparsely-distributed positions. While conventional microLED displays may include pixel emitters disposed on a backplane circuit, spreading the pixel emitters out over a larger area (to thereby increase the pixel pitch in the ways that have been described) may involve communicating with all of the pixel emitters from a centralized circuit (e.g., a controller circuit) configured to perform various roles of the conventional backplane circuit such as image processing, data buffering, pixel emitter driving, pulse-width-modulation (PWM) sequencing, and so forth. For display assemblies described herein with transferred pixel emitters (i.e., display assemblies in which pixel emitters are transferred from a donor substrate on which they were fabricated, to a display assembly where the pixel emitters can operate with more space between them), signal routing from a centralized display controller to pixel emitters that are sparsely fanned out across a relatively large display area becomes a significant technical problem for the display assembly to address.

[0032] Accordingly, for this technical problem of signal distribution to large numbers of sparsely placed pixel emitters, at least one technical solution described herein involves a centralized controller circuit being configured to communicate to the set of pixel emitters indirectly through a plurality of display tiles. For example, as will be described in more detail below, each display tile of a display assembly may receive direction from a controller circuit (or a hierarchy of multiple controller circuits for certain larger displays) at an integrated circuit that is responsible for a particular subset of the pixel emitters corresponding to the display tile. These integrated circuits included in each display tile are referred to herein as driver circuits (or tile drivers) and may be electrically connected to, and configured to drive (using their own set of pixel drivers), the subset of pixel emitters to which they correspond. As such, the driver circuits may be transferred to the carrier substrate after being fabricated elsewhere, just as the pixel emitters are transferred to the carrier substrate after they are fabricated. The driver circuit of each display tile may then include a signal interface for communication to the controller circuit, as well as circuitry for properly driving the corresponding subset of pixel emitters. For example, this circuitry may include, among other circuitry (e g., buffering circuitry', signal processing circuitry, etc.), at least the set of pixel drivers and a modulator configured to control the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulationtechnique.

[0033] Various technical effects and benefits may be provided by use of display tiles for display assemblies with transferred pixel emitters such as described herein. For example, when a plurality of such display tiles is used together with a controller circuit (or hierarchy of cascading controller circuits in certain examples), a tiled architecture may be implemented that allows for direct-view display assemblies with sparse distributions of pixel emitters that take advantage of the considerable benefits of microLEDs, even as wasteful inefficiency is avoided that might otherwise accompany displays with extremely high pixel density. These benefits include bright, sharp-looking displays that are also power efficient as non-emissive power consumption (e.g., from leakage power, memory access, interface signal transitions, etc.) is minimized. Additionally, emitter density may be reduced (i.e., pixel pitch may be increased) to more efficiently account for the capacity of the human visual system and without sacrificing display performance.

[0034] Another significant technical effect arising from technical solutions described herein relates to the ability of individual display tiles (e.g., individual driver circuits and their respective subsets of pixel emitters) to manage themselves at least somewhat independently (e.g., with signaling from the controller circuit when changed content is to be presented). As will be described in more detail, a given display tile may be configured to not only display, on its subset of pixel emitters, an assigned portion of image content from a content frame, but to efficiently deal with contingencies like having one or more underperforming or dysfunctional pixel emitters. For example, if it is detected that a particular pixel emitter in the subset is not fully operational, the driver circuit may instead use a redundant pixel emitter (when such emitters are available, as described in more detail below) or may otherwise mitigate the issue in other suitable ways. As a result, the quality of the display assemblies, as well as manufacturing yield and cost may be significantly improved.

[0035] Additional technical effects of display assemblies described herein include significant flexibility and a variety of options for how the displays may be constructed so as to potentially provide unique features for the device in which the display assembly is used. As described and illustrated in more detail below, the flexibility with how pixel emitters are placed may also advantageously support a variety of shapes and sizes and layouts of pixel emitter arrays to produce display assemblies that are tailored to a wide variety of use cases and applications. Other example benefits may include that display assemblies in accordance with principles described herein may tend to be very thin (which may be a critical design constraint for certain applications), may allow for flexible controller circuit placement, maybe fully integrated (e.g., with all the driver circuits and even the controller embedded in the assembly with the carrier sheet), and so forth.

[0036] Various implementations will now be described in more detail with reference to the figures. It will be understood that particular implementations described below are provided as non-limiting examples and may be applied in various situations. Additionally, it will be understood that other implementations not explicitly described herein may also fall within the scope of the claims set forth below. Systems and methods described herein for display tiles for display assemblies with transferred pixel emitters may result in any or all of the technical effects mentioned above, as well as various additional effects and benefits that will be described and / or made apparent below.

[0037] FIG. 1 shows illustrative aspects of a display tile for a display assembly with transferred pixel emitters in accordance with principles described herein. More particularly, FIG. 1 shows a side view of a portion of a display assembly 100 that includes a carrier substrate 102, a subset of pixel emitters 104, and an integrated circuit 106. FIG. 1 further shows a block diagram illustrating certain components that may be included within integrated circuit 106. For example, as shown in the block diagram, integrated circuit 106 may include a controller signal interface 108 that may be used to receive signaling 110 from another source such as a controller circuit (not explicitly shown in FIG. 1). Signaling 110 may be associated with a portion of a content frame. Integrated circuit 106 is further shown to include an emitter signal interface 112 configured to electrically connect to the subset of pixel emitters 104 so as to provide signaling 114 to the subset of pixel emitters 104. Integrated circuit 106 also includes a set of pixel drivers 116, a modulator 118, and a power supply 120. Each of these elements will now be described in more detail.

[0038] Carrier substrate 102 may be specifically dedicated to carrying the components of display assembly 100, and, as such, may be distinct from donor substrates that may be used to fabricate the various components (e.g., substrates of donor w afers used to fabricate the pixel emitters 104 and / or driver circuits such as integrated circuit 106). Carrier substrate 102 may be constructed of suitable substrate materials and built up, layer by layer, to be able to perform the functions described herein. In certain implementations, carrier substrate 102 may be transparent to visible light and / or to other frequencies of light. In this way, certain components within a device featuring the finished display assembly 100 may be able to operate with little or no interference from the display assembly. For example, an antenna, camera, fingerprint scanner, facial recognition module, or other such component may be configured to operate under display assembly 100 with minimal interference in thisway. Additionally, carrier substrate 102 may, in some implementations, be constructed from material that is thin and flexible (i.e., bendable) so as to be suitable for use in devices requiring non-flat display panels.

[0039] While not explicitly shown in the side view of FIG. 1, it will be understood that carrier substrate 102 may host various electrical connections (e.g., conductive traces, etc.) on one or more planes that may each be separated by layers of insulative dielectric material. For example, a set of controller traces (not explicitly shown) between the controller circuit and the integrated circuit 106 may be implemented on one or more layers of carrier substrate 102 to cam' signaling 110, while a set of emitter traces (also not show n) between the integrated circuit 106 and the various pixel emitters 104 may be implemented on the same or other layers of carrier substrate 102 to carry’ signaling 114. Traces connecting integrated circuit 106 to the controller circuit and / or the subset of pixel emitters 104 may be routed on a single layer of the carrier substrate if possible, or may, in other implementations, be implemented on two or more layers. It will be understood that it may be desirable to have as few layers as possible for a given implementation (e.g., so that display assembly 100 may have a low profile, may possibly be flexible, may avoid certain thermal issues, and so forth). As such, to the extent that it is possible to include the routing of emitter traces and controller traces on a single layer or on a relatively small number of layers, this may be desirable for certain implementations.

[0040] The subset of pixel emitters 104 associated with one display tile (e.g.. the display tile illustrated by FIG. 1 ) may be included within an overall set of pixel emitters that is transferred to the carrier substrate after fabrication of the set of pixel emitters. In some implementations, for example, many thousands or more pixel emitters could be included in a set of pixel emitters used by a display assembly, and each display tile may include a fraction of those pixel emitters (e.g., a subset including 30 pixel emitters, 64 pixel emitters, 100 pixel emitters, or any other suitable quantity as may serve a particular implementation). The transfer process for the pixel emitters 104 will be described and illustrated in more detail below.

[0041] Pixel emitters 104 may be implemented by any suitable light emission devices that may sen e as a pixel for a display. A principal example used throughout this disclosure is that of a microLED device. For instance, as illustrated and described in more detail below’, each pixel emitter 104 could represent a microLED cluster with a red emitter, a green emitter, and a blue emitter that combine to emit white light or light of any desired color (based on the influence given to each of the primary colors). As another example, each pixel emitter 104could represent a single microLED of one individual color (e.g., a red microLED, a green microLED. etc.). While microLEDs are used as the principal example in the disclosure, it will be understood that principles described herein could be applied to other types of pixel emitters, particularly those that, like microLEDs, may be extremely small such that sparser distribution is desirable before they can be used for an efficient direct-view display.

[0042] Integrated circuit 106 may be electrically connected to the subset of pixel emitters 104. and, like the subset of pixel emitters 104, may be transferred to earner substrate 102 after fabrication. An integrated circuit associated with a display tile such as represented by integrated circuit 106 will also be referred to herein as a driver circuit, and may be distinguished from a controller circuit, which may be responsible for controlling a plurality of driver circuits. Integrated circuit 106 may be implemented by a semiconductor product such as an unpackaged semiconductor die, a fully packaged chip, or another suitable semiconductor product along these lines. For example, integrated circuit 106 may represent a complementary-metal-oxide-semiconductor (CMOS) integrated circuit that is fabricated separately (e.g., on a donor wafer) and then integrated into display assembly 100 to serve the driver circuit functions described herein. In some examples, integrated circuit 106 may be configured to be relatively thin and low profile (e.g., with a thickness less than 300 microns, less than 50 microns, less than 20 microns, etc.). While not the focus of FIG. 1 or this disclosure, it is noted that the controller circuit may also be implemented in a similar way as integrated circuit 106, and that a plurality of driver circuits similar or identical to integrated circuit 106 may also be included within display assembly 100 (similarly disposed on carrier substrate 102 with their own subsets of the set of pixel emitters).

[0043] Controller signal interface 108 and emitter signal interface 112 are each shown to be included within integrated circuit 106. These signal interfaces may provide a connection from logical components of integrated circuit 106 (e.g., the set of pixel drivers 116, modulator 118, etc.) to external devices such as the controller circuit (in the case of controller signal interface 108) and the subset of pixel emitters 104 (in the case of emitter signal interface 112) so that signaling 110 and 114 may be received and provided in accordance with principles described herein. For example, signaling 110 from the controller circuit may include frame data representing image content such as a portion of a content frame (i.e., a portion that is to be displayed by this particular display tile), as well as other signaling to facilitate proper display of the image content portion (e.g., timing signals, enable signals, etc.). Signaling 114 to the pixel emitters 104 may then provide voltage / current to turn the pixel emitters on and off in accordance with the image content that is being displayed.

[0044] Pixel drivers 116 may be configured to generate these voltages and currents for signaling 114, based on direction from modulator 118 as it performs pulse width modulation (PWM) of frame data received from the controller circuit by way of controller signal interface 108. In this way, the set of pixel drivers 116 may drive the subset of pixel emitters 104 that integrated circuit 106 is responsible for. In some examples, the various set of pixel drivers 116 may drive different analog voltages or currents based on a predetermined characterization of the attributes (e.g.. brightness, efficiency, etc.) of the various pixel emitters 104 being driven. For example, a first pixel driver 116 responsible for driving a first pixel emitter 104 that has been characterized as being relatively dim and / or inefficient could be configured to supply a higher voltage and / or current to that pixel emitter than a second pixel driver 116 that is responsible for driving a second pixel emitter 104 that has been characterized as being relatively bright and / or efficient.

[0045] Modulator 118 may be configured to control, based on signaling 110 from the controller circuit, the set of pixel drivers 116 to thereby drive the subset of pixel emitters 104 to present portions of content frames using a PWM technique. For example, video data may be buffered, processed, and eventually converted (e.g., either on the controller circuit or in other components of integrated circuit 106 not explicitly shown) so as to create bitplane data representing a series of subframes for a given content frame. More particularly, a portion of a series of subframes may be generated so that the display tile can display a portion of the content frame.

[0046] In accordance with the PWM technique, modulator 118 may be configured to receive timing data from a sequencer (implemented on integrated circuit 106 or on the controller circuit in different architectures) and bitplane data from frame buffer (not explicitly shown). Modulator 118 may then perform pulse- width modulation to drive the pixel emitters 104 (by way of pixel drivers 1 16) to display the relevant portion of the content frame as a series of bitplanes or subframes. For example, upon receiving an advance signal from the sequencer that it is time for the next bitplane to be display ed, modulator 118 may direct each pixel driver 116 for each pixel emitter 104 that this integrated circuit 106 is responsible for to either drive or cease driving its pixel emitter in accordance with binary bitplane data for the next subframe in the sequence.

[0047] The set of pixel drivers 116, modulator 118, and other components and circuitry of integrated circuit 106 not explicitly shown may all rely on power provided by power supply 120. For example, integrated circuit 106 may include power supply circuitry configured to produce several voltage rails having different voltages for powering differentportions or functions of the circuit. In some implementations, pixel emitters of all colors may be powered by one voltage rail to which the set of pixel drivers 116 are all connected. In these examples, the set of pixel drivers 116 could be supplied power by a singular power supply implementing power supply 120.

[0048] In other implementations, pixel emitters of different colors may be powered by different voltage rails configured to supply power to the different colors. In these examples, the set of pixel drivers 116 could include: 1) a first subset of pixel drivers configured to drive red pixel emitters within the subset of pixel emitters and being supplied power by a first power supply; 2) a second subset of pixel drivers configured to drive green pixel emitters within the subset of pixel emitters and being supplied power by a second power supply; and 3) a third subset of pixel drivers configured to drive blue pixel emitters within the subset of pixel emitters and being supplied power by a third power supply. In these examples, power supply 120 would therefore represent each of the first, second, and third power supplies and would provide the different voltage rails for the supported colors (red, green, and blue in this example).

[0049] In some examples, the ground return after the pixel emitters could be shared by all the colors (e.g., after the power rails are split up by color). In other examples, different ground returns (e.g., for red, green, and blue) after the pixel emitters could be implemented (e.g., after a shared power is used for all the colors).

[0050] FIG. 2A shows illustrative aspects of transferring a set of pixel emitters to a carrier substrate after fabrication of the set of pixel emitters in accordance with principles described herein. More particularly, FIG. 2A illustrates aspects of an implementation of the display assembly 100 described above. In this example, a direct- view display 202 is illustrated and described as being configured for use as a smartwatch display (e.g., based on its shape, size, etc.). However, as mentioned above, it will be understood that the same principles described in relation to direct-view display 202 may be applied to other types of direct-view displays configured for us in other applications such as mobile device displays, laptop screens, televisions, appliance panels, and so forth.

[0051] As shown in FIG. 2A, a small segment 204 of direct-view display 202 is broken out and zoomed in to illustrate certain aspects of the display that will be described. Additionally, FIG. 2A shows a donor wafer 206 (not drawn to scale in relation to direct-view display 202) that may undergo lithographic and / or other processing to fabricate a large number of pixel emitters (e.g.. microLED devices or the like). More particularly, as shown by a small segment 208 of donor wafer 206 that is similarly shown to be broken out and zoomedinto, a set of pixel emitters 210 (represented by small squares within segment 208, only a few of which are explicitly labeled) is fabricated on donor wafer 206 before undergoing a transfer 212 to direct- view display 202.

[0052] Transfer 212 may be performed in any suitable way. For example, after the pixel emitters 210 have been fabricated with high density on donor wafer 206, the donor wafer may be aligned with a carrier substrate of the display assembly and the pixel emitters 210 may be released or detached from the donor wafer to be coupled (e.g., electrically connected, adhesively connected, etc.) at the desired location on the carrier substrate (i.e., the location to which the pixel emitter has been aligned). This detachment may be facilitated by a laser that is focused (e.g., from a first side of the donor wafer) in a manner that creates a defect (e.g., a crack) at a specified depth within the wafer under the emitter or emitters that are to be released. With the donor wafer and carrier aligned, another laser (e.g., introduced from the opposite side of the donor wafer) may then cause the defect to expand (e.g., the crack to spread) within boundaries that have been set around a particular pixel emitter (or group of pixel emitters) that is to be released by the action of the laser. As such, the pixel emitter or group may detach from the donor wafer where it or they were fabricated and may attach to the carrier substrate. As mentioned above and as will be described in more detail below, the pixel pitch of the pixel emitters may be increased by transfer 212 so that the pixel emitters are not so densely packed. In some cases, for instance, the donor wafer may be aligned and then only one in every N pixel emitters may be released to the carrier sheet (where N could equal 2, 10, 25, 50, or any other suitable number) prior to the donor wafer being realigned to the same or another carrier sheet to repeat the process for other, not-yet- released pixel emitters.

[0053] The set of pixel emitters 210 will be understood to correspond to the set of pixel emitters that includes the subset of pixel emitters 104 described above in relation to FIG. 1. However, while this pixel emitter set refers to the pixel emitters included on a given direct-view display, it will be understood that the set of pixel emitters 210 produced on donor wafer 206 may be transferred not only to direct-view display 202 but also to one or more other display assemblies. For example, pixel emitters fabricated on one large donor wafer may be transferred to dozens or hundreds of relatively small display assemblies (such as for smartwatch displays).

[0054] Segment 204 shows that the set of pixel emitters 210 is disposed in direct- view display 202 subsequent to being transferred (transfer 212) to the carrier substrate of direct-view- display 202 from the donor wafer 206 on which the set of pixel emitters 210 w asfabricated. As further illustrated in FIG. 2A, the set of pixel emitters 210 may be fabricated at a first pixel pitch 214-1 and may be distributed on the carrier substrate of direct-view display 202 at a second pixel pitch 214-2 that is greater than pixel pitch 214-1. In some examples, the pixel pitch 214-1 at which the set of pixel emitters 210 are fabricated may be a very small pixel pitch, such as in the range of about 2-4 microns. In contrast, the pixel pitch 214-2 at which the set of pixel emitters 210 is distributed within the direct- view display 202 may be significantly larger than pixel pitch 214-1. While not necessarily drawn to scale in relation to pixel pitch 214-1 in FIG. 2A, pixel pitch 214-2 could be, in various examples, at least double pixel pitch 214-1, at least four times greater than pixel pitch 214-1, at least ten times greater than pixel pitch 214-1, at least twenty times greater than pixel pitch 214-1, at least forty' times greater than pixel pitch 214-1, or another suitable increase as may serve a particular implementation. As a specific example, for instance, pixel pitch 214-1 could represent a high- density pitch in the range of 2-4 microns while pixel pitch 214-2 could represent a low- density (sparse) pitch in the range of 50-120 microns (e.g., 80 microns).

[0055] While transfer 212 may involve spacing out the set of pixel emitters 210 to a significantly greater pixel pitch, it may not be the case that every individual emitter (e.g., every' microLED fabricated on donor wafer 206) is spaced equally sparsety from the others. For example, as will be described and illustrated in more detail below, individual pixel emitters (e.g., red, green, and blue microLEDs, also referred to as subpixels) may be distributed individually at pixel pitch 214-2 in certain implementations, while, in other implementations, these individual subpixels may be clustered together into emitter clusters that each include all the primary' colors (e.g., clusters that include at least one red, at least one green, and at least one blue microLED) and are distributed with the larger pixel pitch 214-2. In certain examples, different donor wafers could be used to fabricate different pixel emitter colors (e.g., a donor wafer for red pixel emitters, a donor wafer for green pixel emitters, and a donor wafer for blue pixel emitters, etc.) and then transfers from each of these donor wafers could combine to create the multicolor pixel array.

[0056] Whether distributed individually or in clusters, and whether transferred from one or multiple donor wafers, the set of pixel emitters 210 may be arranged on the carrier substrate with respect to a lattice that includes a plurality of pixel nodes where the individual pixel emitters or clusters of pixel emitters are placed. In other words, the set of pixel emitters 210 may be fabricated at first pixel pitch 214-1 on donor wafer 206 and this first pixel pitch 214-1 may be smaller than the second pixel pitch 214-2 at which the plurality’ of pixel nodes is disposed on the lattice. To illustrate, FIG. 2A shows a lattice 216-A that, in this example, isa rectilinear lattice that includes pixel nodes 218- A arranged in a grid of rows 220 and columns 222. As shown, pixel nodes 218-A (only a few of which are explicitly labeled) are located at the intersections of dashed lines representing rows 220 and columns 222.

[0057] While a rectilinear lattice such as lattice 216-A may be appropriate or optimal for certain implementations, it will be understood that the shape and lattice type into which pixel emitters of any given display tile need not be rectilinear. For instance, pixel emitters could be disposed on a triangular lattice, a hexagonal lattice, a lattice with serpentine rows and / or columns (rather than straight rows and columns such as illustrated by rows 220 and columns 222), another suitable type of lattice, or even no lattice at all (e.g., an irregular pattern). For example, this flexibility in pixel emitter placement and shaping, as well as the sparseness of the pixel emitters, may facilitate the placement and function of certain components under the display assembly. For example, one or more antennas (e.g., near-field communication (NFC) antennas) beneath display assembly may have significant visibility for wireless communication through the gaps between the pixel emitters, sensors (e.g., cameras, fingerprint readers, facial recognition modules, etc.) could be placed under the display, and so forth.

[0058] To illustrate another way that the set of pixel emitters 210 could be arranged on a particular display, for example, FIG. 2B shows another implementation of direct-view display 202 with all the same elements as described in relation to FIG. 2A (i.e.. the segment 204 on direct-view display 202, the donor wafer 206 with the segment 208. the set of pixel emitters 210 fabricated at pixel pitch 214-1 and their transfer 212 to the carrier substrate at pixel pitch 214-2). In FIG. 2B, however, lattice 216-A is replaced with a lattice 216-B that is implemented as a non-rectilinear lattice. More particularly, lattice 216-B is shown to be a triangular lattice in this example, that includes pixel nodes 218-B that form triangles (e.g., equilateral triangles, isosceles triangles, etc.) illustrated by dashed lines similar to those illustrating rows 220 and columns 222 in FIG. 2A. It will be understood that lattices 216-A and 216-B are provided as examples only, and that other implementations could implement other types of lattices (such as those mentioned above) as may serve a particular application.

[0059] One advantage of having pixel emitters distributed relatively sparsely (i.e., with a pitch such as shown by pixel pitch 214-2) is that the space between sparsely- distributed pixel emitters may be used by other components (e.g., antennas, alternate wavelength emitters, imaging sensors, ambient light sensors, etc.). For example, these spaces may provide placement locations for the other components (e.g., when integrated directly into the display assembly) or may at least facilitate surface access and visibility for suchcomponents (e.g., in the event they are placed beneath the display assembly, deeper into the device).

[0060] To illustrate how such usage could be advantageous, a conventional display assembly will be considered. If an antenna or set of sensors (e.g., light detectors for a fingerprint reader, etc.) were to be integrated into a device such as a smartwatch, these components would typically need to be placed beneath the conventional display assembly. Such placement would not be ideal, since the antenna or sensors would be farther from the surface of the display, forcing attenuation of signals that are transmitted and / or received through the display itself. In contrast, the ample space between sparsely distributed pixel emitters 210 (as illustrated in FIGS. 2A-2B) leaves room for such components to be integrated directly into the display assembly so that they are located right at the surface and have direct access and visibility. For example, an antenna could be made to weave between the pixel emitters (e.g., on a redistribution layer without traces or with fewer traces connecting the emitters to their respective driver circuit) so that it could be right at the surface and not buried deeper in the device under the display assembly. As another example, manysmall sensors such as might be used to capture an image (e.g., sensors forming a camera, a fingerprint or facial identity detector, an ambient light detector, etc.) could be interspersed with the pixel emitters and routed to a controller in a similar way as described herein for the pixel emitters.

[0061] Even if antennas and sensors (such as have been described) are not integrated into the display assembly itself in these ways, the sparseness of the pixel emitters and potential thinness of display assemblies described herein may mitigate the antenna / sensor issues described above (i.e., issues faced by conventional display assemblies). For example, even for antennas and sensors that happen to be incorporated outside of the display assembly (e.g., deeper within a device, beneath the display assembly), the relatively sparse distribution of pixel emitters and the flexibility with which they may be placed may facilitate surface access for antennas and sensors anywhere within the device.

[0062] FIG. 3A shows illustrative aspects of a plurality of display tiles of direct-view display 202 in accordance with principles described herein. More particularly, in this example, direct-view display 202 is shown to be divided into a 4x4 grid of 16 display tiles 302-1 through 302-16 (i.e., display tiles 302-1, 302-2, 302-3, 302-4, 302-5, 302-6, 302-7, 302-8, 302-9, 302-10, 302-11, 302-12, 302-13, 302-14, 302-15. and 302-16) that will each be understood to include a respective driver circuit (i.e., an implementation of integrated circuit 106) and a respective subset of pixel emitters 104 (from a total set of pixel emitters of thedisplay assembly). For example, display tile 302-8 (selected arbitrarily) is shown, in a zoomed-in segment outlined by a dotted line in FIG. 3 A, to include an integrated circuit 106 implementing a driver circuit that is connected, by various electrical connections 304 (e.g., traces on the carrier substrate, only a few of which are explicitly labeled), to a subset of pixel emitters 104 associated with display tile 302-8.

[0063] Respective driver circuits (similar to the integrated circuit 106 of display tile 302-8) and respective subsets of pixel emitters (similar to the subset of pixel emitters 104 of display tile 302-8) will be understood to be included within each of the display tiles 302-1 through 302-16. As mentioned above, these driver circuits may be implemented by unpackaged semiconductor dies, fully -packaged chips, or other suitable types of integrated circuits (e.g.. CMOS integrated circuits). Additionally, a controller circuit, which may also be implemented as a CMOS integrated circuit, may be disposed somewhere within direct-view display 202 (e.g., within one of the display tiles or positioned on a boundary between two or more of the display tiles). All of these components (i.e., the pixel emitters, the driver circuits, the controller circuit, etc.) may be fabricated separately and then transferred to the carrier substrate used for direct-view display 202 in the ways that have been described.

[0064] Appropriate electrical connections (e.g., electrical connections 304) interconnecting these components may also be added to one or more layers of the carrier substrate to facilitate the functions described herein. For example, the various electrical connections 304 may be implemented as emitter traces implemented on a single plane (as shown), or, in cases where more complex fanout is necessary (e.g., to a subset of pixel emitters with several dozens or hundreds of pixel emitter devices) may be implemented on two or more planes separated by layers of insulative dielectric material. A set of controller traces (not explicitly shown) between a controller circuit and each of the driver circuits may similarly be implemented on the same plane of insulating material as the controller circuit and / or the driver circuits themselves, or on a separate layer.

[0065] FIG. 3 A show s direct-view display 202 to be divided into 16 square (or nearly square) display tiles and shows the example display tile 302-8 to include a subset of pixel emitters 104 in an 8x8 square grid including 64 pixel emitters. These numbers, shapes, and layout are provided only for the sake of illustration, and it will be understood that a given implementation of direct-view display 202 could include any suitable number of display tiles (more or less than the 16 shown in the example of FIG. 3 A), each with any suitable number of pixel emitters (more or less than the 64 shown in FIG. 3A). Indeed, different implementations may handle a tradeoff between routing complexity and display thickness onthe one hand (which may be optimized by having fewer portions and driver circuits for the controller circuit to be routed to) and power and chip complexity / cost on the other hand (which may be optimized by having more portions and driver circuits that are each responsible for fewer pixel emitters and thus use less power and buffering resources, etc.) in different ways according to their unique design goals.

[0066] Additionally, just as the comer display tiles of direct-view display 202 (i.e.. display tiles 302-1. 302-4, 302-13. and 302-16) are shown to be non-square shapes (i.e., due to the rounded comers), it will be understood that the shape and lattice type of the pixel emitters in any given portion need not be square or rectilinear. For instance, as described and illustrated above, pixel emitters could be disposed on other types of lattices (e.g.. a triangular lattice, a hexagonal lattice, etc.) or may be arranged in irregular ways that do not necessarily conform with any standard lattice type. Along with this flexibility in how pixel emitters may be arranged within a given display tile, display tiles themselves may be implemented in a variety of ways. For example, depending on certain characteristics of the display being constructed, display tiles could have different shapes and sizes, could be overlapping or nonoverlapping. could arrange their driver circuits in different places with respect to their pixel emitters, and so forth. FIGS. 3B-3D will now be described to illustrate a few examples of the design flexibility' that display tiles may have in various implementations.

[0067] FIG. 3B shows a first illustrative way that display tiles having respective integrated circuits and subsets of pixel emitters may be arranged. As shown in FIG. 3B, a first subset of pixel emitters included within the overall set of pixel emitters is drawn using a first ty pe of fill pattern (diagonal cross-hatching in this example) while a second subset of pixel emitters included w ithin the overall set of pixel emitters is drawn using a second type of fill pattern (a solid black in this example). In both subsets, the pixel emitters are shown to be arranged on a rectilinear grid and to have a square shape. Respective integrated circuits 106-1 and 106-2 (driver circuits with fill patterns matching their pixel emitters) are shown to be centered in their respective tiles so as to have good access to each of the pixel emitters they are responsible for (e.g., using electrical connections not shown in FIG. 3B but that will be understood to be similar to electrical connections 304 illustrated above).

[0068] As shown, the first subset of pixel emitters may be disposed on the carrier substrate together w ith the second subset of pixel emitters, and the first subset of pixel emitters and the second subset of pixel emitters may be disposed in an adjacent and nonoverlapping arrangement on the carrier substrate. In other words, the display tiles in FIG. 3B are shown to be square-shaped and with rectilinear lattices to implement a design similar tothe display tiles 302-1 through 302-16 illustrated in FIG. 3A.

[0069] FIG. 3C shows another illustrative way that display tiles having respective integrated circuits and subsets of pixel emitters may be arranged. As shown in FIG. 3C, a first subset of pixel emitters included within the overall set of pixel emitters is drawn using a first ty pe of fill pattern (diagonal cross-hatching in this example), a second subset of pixel emitters included within the overall set of pixel emitters is drawn using a second type of fill pattern (a solid black in this example), and a third subset of pixel emitters included within the overall set of pixel emitters is drawn using a third type of fill pattern (a dotted pattern in this example). In all three subsets, the pixel emitters are again shown to be arranged on a rectilinear grid and to have a square shape. Respective integrated circuits 106-1, 106-2, and 106-3 (driver circuits with fill patterns matching their pixel emitters) are shown to be centered in their respective tiles so as to have good access to each of the pixel emitters they are responsible for (e.g., using electrical connections not shown in FIG. 3C but that will be understood to be similar to electrical connections 304 illustrated above).

[0070] Similar to FIG. 3B, FIG. 3C shows that the first subset of pixel emitters may be disposed on the earner substrate together with the second subset of pixel emitters and the third subset of pixel emitters. While the first and second subsets of pixel emitters are show n to be disposed in an adjacent and non-overlapping arrangement with each other (similar to the one described above in relation to FIG. 3B), however. FIG. 3C shows that each of the first and second subsets of pixel emitters may be disposed in an overlapping arrangement with the third subset of pixel emitters on the carrier substrate. Indeed, the third subset of pixel emitters is shown to overlap with both of the first and second subsets and to include pixel emitters that are arranged on a triangular lattice with respect to the pixel emitters of the first and second subsets. While not shown in this illustration, it will be understood that other neighboring display tiles, with their own respective subsets of pixel emitters, could similarly overlap such that all of the pixel emitters are arranged on a square lattice with respect other pixel emitters in their own display tile but arranged on a triangular lattice (or other suitable lattice) with respect to pixel emitters in other display tiles.

[0071] In some examples, display tiles may include pixel emitters of only a single primary color (e.g., a red display tile, a green display tile, a blue display tile, etc ). As such, tiles that overlap in the manner shown by FIG. 3C (or a similar way) may allow7for the integration of multiple primary7colors with one another while each is controlled by its own driver circuit. The routing of pixel emitters to their respective integrated circuits 106-1, 106- 2, and 106-3 in a set of overlapping display tiles such as illustrated in FIG. 3C may use atleast two layers of the carrier substrate so that electrical connections associated with one display tile may cross electrical connections of other display tiles without interference.

[0072] FIG. 3D shows yet another illustrative way that display tiles having respective integrated circuits and subsets of pixel emitters may be arranged. As shown in FIG. 3D, a first subset of pixel emitters included within the overall set of pixel emitters is draw n using a first type of fill pattern (a dotted pattern in this example) and a second subset of pixel emitters included within the overall set of pixel emitters is drawn using a second type of fill pattern (a diagonal cross-hatching in this example). In both subsets, the pixel emitters are again shown to be arranged on a rectilinear grid, and respective integrated circuits 106-1 and 106-2 (driver circuits with fill patterns matching their pixel emitters) are shown to be associated with their respective tiles. However, in contrast to the examples of FIGS. 3B and 3C, the display tiles formed by these subsets of pixel emitters are shown to have irregular shapes (rather than the square shapes of other examples above). Specifically, the pixel emitters of the first display tile are show n to go around the pixel emitters of the second display tile around the top left comer of a shape that is mostly rectangular but is missing its bottom left comer. In other words, as shown, both of the shapes of these display tiles are irregular and do not conform to any standard geometric shape (square, rectangular, or otherwise). As has been mentioned, irregular shapes such as show n in FIG. 3D may be useful for avoiding portions of the carrier substrate where other circuitry is located (e.g., avoiding a camera or fingerprint sensor under the display, etc.) or when the shape of the display itself is such that flexibility is required to fill the space with pixel emitters.

[0073] FIG. 4 shows an illustrative method 400 that may be performed by an integrated circuit used in a display tile for a display assembly with transferred pixel emitters in accordance with principles described herein. It will be understood that method 400, as well as other similar methods described herein (and / or variants of method 400 in accordance with principles described herein) may, in certain examples, be encoded in instructions that may be stored by a non-transitory computer-readable medium, and that, w hen executed, may cause an integrated circuit to perform one or more of the operations of method 400.

[0074] While FIG. 4 shows illustrative operations 402-406 according to a specific implementation, it will be understood that other implementations of this method may omit, add to, reorder, and / or modify any of operations 402-406 that are explicitly represented in FIG. 4. Additionally, while operations shown in FIG. 4 are illustrated with arrows suggestive of a sequential order of operation, it will be understood that some or all of the operations of method 400 may be performed concurrently (e.g., in parallel) with one another. Each of theoperations of these methods will now be described in more detail as the operations may be performed by an integrated circuit (e.g., a driver circuit within a particular display tile of a display assembly) or other component within a display assembly.

[0075] At operation 402, a signal interface of an integrated circuit may receive signaling from a controller circuit. For example, the integrated circuit may be a driver circuit such as described herein (e.g., integrated circuit 106) and both this integrated circuit and the controller circuit may have been transferred to a carrier substrate after fabrication of the integrated circuit and controller circuit elsewhere (e.g., on respective donor wafers). This signal interface may be implemented by a controller signal interface (e.g., controller signal interface 108) that is distinct from an emitter signal interface 112 (e.g., emitter signal interface 112) which may be used to drive a subset of pixel emitters.

[0076] The signaling received at operation 402 may be associated with a portion of a content frame. For example, a content frame that is to be displayed by direct-view display 202 could be divided into 16 portions corresponding to display tiles 302-1 through 302-16. As new content frames are received by the controller circuit, the controller circuit may determine which portions (if any) contain at least some changed content (i.e., content that is to be updated from what is displayed from a previous frame), which portions (if any) contain only unchanged content from the previous frame being displayed, which portions (if any) contain no content, and so forth. The controller circuit may then send frame data representing any content updates that are to be made, as well as other signaling (e.g., timing signals, instructions, etc.) to direct each of the driver circuits to present the portions of the content frame on their respective subsets of pixel emitters. Accordingly, the signaling received by the signal interface at operation 402 may include a clock signal, a data signal, an advance signal (i.e., instructing the integrated circuit to display the next subframe in a sequence of subframes being presented in a PWM technique), a frame synchronization signal, an enable signal, and / or any other suitable signaling as may serve to facilitate the display of the portion of the content frame in a particular implementation.

[0077] At operation 404. a modulator of the integrated circuit (e.g., modulator 118) may control, based on the signaling received at operation 402 (e.g.. signaling 110). a set of pixel drivers (e.g., pixel drivers 116) of the integrated circuit. For example, as has been described, the modulator may present the portion of the content frame by advancing through corresponding portions of a series of subframes (bitplanes) that have been generated based on video data for the content frame. Pulse-width modulation of subframes of binary data may allow for each pixel emitter to be turned on for a portion of the frame time corresponding tothe desired brightness of the pixel emitter for the content frame. For example, a dim pixel emitter will not be driven for much of the frame time (e.g., many of the subframes), while a brighter pixel emitter will be driven on for more of the frame time. Accordingly, the modulator may provide signaling to the various pixel drivers to rapidly drive their respective pixel emitters off and on in accordance with the subframes that have been determined for the PWM technique.

[0078] At operation 406. the set of pixel drivers may drive, based on the controlling of the drivers by the modulator at operation 404, the subset of pixel emitters of the display tile. As has been described, this subset of pixel emitters may be included within a set of pixel emitters that is transferred to the carrier substrate after fabrication of the set of pixel emitters and may be associated with (e.g., assigned to, controlled by, etc.) this particular integrated circuit. Based on the driving of the pixel emitters at operation 406, the subset of pixel emitters may present the portion of the content frame using the pulse width modulation technique as has been described. For example, portions of various subframes may be displayed in sequence (e g., based on signaling, such a subframe advance signal, provided by a sequencer implemented by the driver circuit or the controller circuit) by the subset of pixel emitters so that each pixel emitter, by turning off and on for appropriate amounts of time, may emit the desired amount of light (thereby appearing at the desired brightness) for the content frame.

[0079] In some examples, the content frame may be associated with a set of content subframes and the signaling received from the controller circuit at operation 402 may include a timing signal (e.g., a frame synchronization signal, a subframe advance signal, etc.) and frame data for respective portions of each content subframe of the set of content subframes. The portion of the content frame may then be presented using the pulse width modulation technique by presenting, in a timed sequence based on the timing signal, the respective portions of each content subframe of the set of content subframes.

[0080] In some implementations, a method such as method 400 may be embodied as a process within a memory’. For example, a non-transitory computer-readable medium may store instructions that, when executed, cause a driver circuit of a display assembly (e.g., such as implemented by integrated circuit 106) to perform a process embodying method 400. Specifically, when executing the instructions on the non-transitory computer-readable medium, the driver circuit may: 1) receive signaling from a controller circuit, the signaling associated with a portion of a content frame; 2) control, based on the signaling, a set of pixel drivers of the integrated circuit; and 3) drive, based on the controlling by the modulator, asubset of pixel emitters (included within a set of pixel emitters that is transferred to the carrier substrate after fabrication of the set of pixel emitters) so as to present the portion of the content frame using a pulse width modulation technique.

[0081] As has been described, a set of pixel emitters of a display assembly may be disposed at pixel nodes of a variety' of different lattice ty pes (e.g., rectilinear lattices, triangular lattices, hexagonal lattices, etc.). Another aspect of the placement flexibility offered by principles described herein involves the ways that individual pixel emitters or clusters of emitters may be arranged with respect to the pixel nodes. In some arrangements, for example, each of a plurality' of pixel nodes may contain a singular pixel emitter. The singular pixel emitter could be implemented, for instance, by a red pixel emitter, a green pixel emitter, a blue pixel emitter, or another suitable emitter (based on the color scheme being used). In other arrangements, however, each of the plurality of pixel nodes may contain a cluster of pixel emitters. For instance, the cluster could include at least one of all the primary colors being used, so that any color (including white) could be emitted from each pixel node. In other words, the cluster of pixel emitters may include at least one red pixel emitter, at least one green pixel emitter, and at least one blue pixel emitter.

[0082] To illustrate, FIG. 5 A shows the first illustrative way that pixel emitters may be arranged on a lattice (i.e., with the singular pixel emitter at each pixel node), while FIG. 5B shows the second illustrative way that pixel emitters may be arranged on the lattice (i.e., with the cluster of pixel emitters at each pixel node). More particularly, both FIGS. 5 A and 5B show an illustrative rectilinear lattice 216 similar to lattice 216-A of FIG. 2A. The choice of a rectilinear lattice for this illustration is arbitrary' and the same principles will be understood to apply to a triangular lattice (such as lattice 216-B of FIG. 2B) or other lattice types or non-lattice arrangements. As shown, lattice 216 includes a plurality of pixel nodes 218 similar to pixel nodes 218-A and pixel nodes 218-B described above. Arrows from a few of the plurality' of pixel nodes 218 are drawn to show corresponding pixel emitters that may be placed at the pixel nodes.

[0083] First, in an arrangement 500-A illustrated in FIG. 5A, each of the pixel nodes 218 are shown to include individual pixel emitters implemented by one of a red pixel emitter ’R”), a green pixel emitter (“G”), or a blue pixel emitter (“B”). In this example, these different primary' colors are placed in columns with red emitters on the left, green emitters in the middle, and blue emitters on the right. It w ill be understood that, for this example, a pattern of columns (R G B R G B. etc.) could continue in this way across the display. It will also be understood that the colors could correspond to rows rather than columns, could beinterleaved (such that rows and columns would each include all three colors), or could form any other suitable pattern. Additionally, it will be understood that red, green, and blue primary colors are used by way of example and that other implementations could use different primary colors (e g., RGBY to add yellow, RGBW to add white, IrRGB to add infrared, etc.). In any of these examples, however, each pixel node 218 will be understood to have a singular principal pixel emitter, as illustrated.

[0084] In contrast, an arrangement 500-B illustrated in FIG. 5B shows that each of the pixel nodes 218 may instead include clusters of pixel emitters with all three primary colors (i.e., a red pixel emitter (“R”), a green pixel emitter (“G”), and a blue pixel emitter (“B”)). Here again, the ordering and local arrangement of the emitters at any given pixel node 218 will be understood to be arbitrarily chosen for purposes of illustration. Instead, the pixel emitters of a given cluster could be arranged in a vertical stack, a triangular (or other nonlinear) grouping, or in other suitable shapes. Instead of being ordered as RGB at each pixel node, the order could be BGR, GBR, or any other suitable order. Additionally, while at least one of each of the primary colors may be present within each pixel emitter cluster, it may be advantageous for certain colors to be overrepresented (e.g.. two red pixel emitters clustered together with one green pixel emitter and one blue pixel emitter, since red may appear dimmer than the other colors and may benefit from being boosted by another pixel emitter).

[0085] Whether each pixel node includes singular pixel emitters (of a singular primary color) or clusters of pixel emitters (including all of the primary colors), there may be plenty of space at the pixel node site for (and significant benefit to be gained by) adding redundancies in case a given pixel emitter is underperforming. Whether a given pixel emitter is completely dead or just underperforming (e g., dim, inefficient, etc.), a pixel deficiency anywhere on the display may have a large downside. As one example, pixel deficiencies could reduce the quality or perceived quality of the display by creating a dead spot or dim spot that could be irritating to viewers of the display. As another example, the display could fail to pass quality control measures as a result of deficiencies of this type and manufacturing yields could decrease (leading to increased fabrication costs, waste, etc ).

[0086] Even if only a very small percentage of pixel emitters have any performance issue, it may not be extremely unlikely that a display assembly with hundreds of thousands or more pixel emitters could have at least a few deficient pixel emitters. Accordingly, to help mitigate and address these potential downsides, certain redundancies may be built into display assemblies described herein. For example, whether singular emitters (FIG. 5A) or emitter clusters (FIG. 5B) are used in a given implementation, redundant pixel emitters of thesame colors (or at least options to facilitate the addition of such redundancies) may be provided. More particularly, for instance, each of the plurality’ of pixel nodes 218 in an arrangement such as arrangement 500-A may further contain a backup pixel emitter that is a same color as the singular pixel emitter. As another example, each of the plurality of pixel nodes 218 in an arrangement such as arrangement 500-B may further contain a backup cluster of pixel emitters that includes a backup red pixel emitter, a backup green pixel emitter, and a backup blue pixel emitter.

[0087] To illustrate, FIG. 6A shows an illustrative way that redundant (i.e., backup) pixel emitters may be integrated with the pixel emitters of arrangement 500-A, while FIG. 6B shows an illustrative way that redundant pixel emitters may be integrated with the pixel emitters of arrangement 500-B. In both figures, the rectilinear lattice 216, the plurality of pixel nodes 218, and the principal pixel emitters are illustrated in the same manner as described above in relation to FIG. 5A. For example, the principal pixel emitters are drawn as solid boxes marked “R”, “G"’, or “B’’ to indicate their color. In FIGS. 6A and 6B, however, additional backup pixels are added to the various pixel nodes 218, drawn with dotted boxes using the same color markings (“R”. “GA or “B”).

[0088] More specifically, as shown, each of the principal pixel emitters in FIG. 6A is shown to be accompanied by a corresponding backup pixel (drawn with a dotted outline) of the same color (“R” with “R”, “G"’ with “G"’, etc.). Similarly, each cluster of RGB pixel emitters in FIG. 6B is shown with a backup cluster of RGB pixel emitters at the same pixel node. Because the pixel emitters are so small and sparsely distributed on the direct-view display, FIGS. 6A and 6B shows that there may be plenty' of room at each pixel node to fit the redundant pixel emitters (though it will be understood that these figures are not necessarily drawn to scale). Additionally, there may be options for addressing other complications or challenges introduced by the addition of these redundancies.

[0089] For instance, while space may not be a concern on the direct-view display with the sparse distribution of pixel emitters, the cost and / or manufacturing complexity7of doubling up every pixel emitter in the array just to mitigate a likely very small percentage of underperforming pixel emitters could be of greater concern. In these situations, the routing for all of the backup pixels could be put in place, but the backup pixels could only be placed after the display assembly has been tested and a particular principal pixel emitter has been determined to be deficient. In this way, there would be a convenient and dedicated repair site for each pixel emitter in case it is determined to be deficient, but the redundant backup would only be populated in the event that it would actually be used. In other examples, the costsaved by the increase in display assembly yield provided by the redundancy may more than make up for the marginal cost of fabricating and placing the extra pixel emitters, so each backup may be placed even though the large majority may not be used.

[0090] Another complication that could be addressed relates to the routing complexity from the driver circuits to their various subsets of pixel emitters. Even though there may be only a single trace from the integrated circuit to each pixel emitter, doubling the number of pixel emitters could create a much more complex routing challenge that could require more layers, a thicker carrier substrate, and other undesirable elements. Accordingly, one way to mitigate this complication may be to have the principal and backup pixel emitters share an electrical connection (i.e., share the trace that extends to the driver circuit). More particularly, in the example of arrangement 600- A. each pixel node 218 of the plurality of pixel nodes 218 of the lattice 216 may contain a pixel emitter and a backup pixel emitter that both share an electrical trace routed from the integrated circuit to the pixel node. Similarly, in the example of arrangement 600-B, each pixel node 218 of the plurality7of pixel nodes 218 of the lattice 216 may contain a pixel emitter cluster and a backup pixel emitter cluster that both share a set of electrical traces (i.e., three electrical traces in this example where the clusters include three pixel emitters) routed from the integrated circuit to the pixel node.

[0091] Once the electrical trace extends out from the integrated circuit 106 to the site of the pixel node 218, the principal and backup pixel emitters could be connected in parallel so that both pixel emitters share the current provided by the pixel drivers (assuming both of the pixel emitters are functional). In the event that one of the pixel emitters is deficient, a trace could be cut and its backup would receive the full current provided by the pixel driver, thereby achieving the same brightness either way (i.e., one emitter at full brightness or two emitters at half brightness). In the event that the pixel emitter is completely dead and forms an open circuit, the trace would not even need to be cut to achieve the same result. In any of these scenarios, there will likely be at least one functional pixel emitter at each site (e.g., either the principal or its backup) so the desired brightness may also be handled by the controller circuit and / or the driver circuit using standard calibration and demura techniques (e.g.. the circuitry being calibrated to cause dimmer or less efficient pixels to be driven a little heavier and to cause brighter or more efficient pixels to be driven a little lighter, etc ).

[0092] As described above, certain direct-view displays may include singular pixel emitters at each pixel node (as shown in FIG. 5A) or singular pixel emitters along with backup pixel emitters at each pixel node (as shown in FIG. 6A). Other direct-view displays may include clusters of pixel emitters at each pixel node (as shown in FIG. 5B) or clusters ofpixel emitters along with backup clusters of pixel emitters at each pixel node (as show n in FIG. 6B). In these examples, the emitter or emitters included at each pixel node may be referred to herein as a pixel, and it will be understood that the direct-view display may include a large number (e.g., hundreds, thousands, or more) of these pixels.

[0093] In still other implementations, each pixel may include or be implemented by what is referred to herein as a chiplet. Rather than a singular pixel emitter or a cluster of pixel emitters (and any backup pixel emitters or backup clusters), certain or all of the pixel nodes may include respective chiplets, each of which may include at least one red, one green, and one blue pixel emitter (e.g., InGaN-based emitters). In a chiplet, the red (R), green (G), and blue (B) emitters may all be attached to a common member, rather than being separate devices as described and illustrated above in other examples.

[0094] In some cases, this member may be a semiconductor template, and the R, G, B emitters may be formed monolithically on the template. More specifically, a growth substrate (e.g. a silicon substrate, a sapphire substrate, etc.) may be provided on which a template (e.g. a GaN layer or other Ill-nitride layer) is formed. This template may be planar and may have a thickness of a few microns. The R, G, and B emitters may then be formed on top of the template. In some examples, they may be formed monolithically (i.e., all three colors grown by epitaxy on the template). The R, G, and B emitters may be Ill-nitride emitters. The R, G and B emitters may be micro-LEDs that include doped GaN-based layers and InGaN-based light-emitting layers. Substrates may include light-scattering features (such as patterned or roughened interfaces) to enhance light extraction. In some cases, the interface between the substrate and the template may be textured (i.e., non-planar). This results in a monolithic LED wafer with a substrate, a template, and arrays of R, G, B emitters.

[0095] To form a chiplet such as described above, a lateral region of a wafer may be defined that includes at least one R, one G, and one B emitter. The template may be etched around this lateral region and the substrate may be separated from the template in this region. The chiplet resulting from these actions may therefore include a template member carrying the R, G, and B emitters.

[0096] To illustrate, FIGS. 7A-7F show example steps of a process for fabricating a chiplet in accordance with principles described herein. Each of these example steps will now be described in more detail.

[0097] FIG. 7A shows a monolithic donor wafer (shown upside down), with a substrate (i.e., labeled as a “growth substrate” to distinguish from other substrates described below), a template on a surface of the substrate (e.g., a Ill-nitride template), and RGB pixelemitters (e.g., microLEDs such as have been described).

[0098] FIG. 7B uses dashed lines to illustrate streets that may be etched in the template to isolate a lateral portion. For instance, the etching of these streets could be performed using lithography, dry etch, or other suitable techniques. In this example, the lateral portion is shown to include two R emitters, two G emitters, and two B emitters.

[0099] In FIG. 7C, the donor wafer is shown to be attached to a carrier sheet. For example, this carrier could be a temporary substrate configured to provide suitable structural support for the chiplets being manufactured (only one of which is shown in these figures) as the growth substrate of the donor wafer is detached from the template.

[0100] In FIG. 7D, the growth substrate is removed, leaving the finished chipl et (i. e. , the R, G. and B emitters attached to the common template member) on the carrier. For example, the growth substrate could be removed by way of a chemical etch, wet etch, dry etch, laser lift-off, or other suitable technique. The resulting chiplet on the carrier sheet may then be transferred (e.g., using a pick and place technique represented by the arrow labeled “Pick and Place”) to a backplane of a direct-view display. In certain examples, a plurality of chiplets (e.g. tens or hundreds of chiplets) that have been fabricated and are being supported on the same carrier sheet could be transferred at once.

[0101] FIGS. 7E and 7F show an alternative w ay that the etched chiplets may be transferred to a backplane after being fabricated on a donor wafer as described and illustrated above in relation to FIGS. 7A and 7B.

[0102] FIG. 7E show" an example process step that may be performed after the step illustrated in FIG. 7B. In FIG. 7E, the donor w afer (with its laterally-isolated regions formed by the etched streets illustrated in FIG. 7B) may be aligned and contacted directly with the carrier substrate of the direct-view display (e.g.. the display backplane).

[0103] In FIG. 7F, the growth substrate may then be separated from the chiplets (or at least from certain chiplets) by, for example, local laser processing to lift off the substrate. The pixel emitters of the chiplets may be bonded to the backplane such that use of the pick-and- place approach described above is not necessary.

[0104] As with the singular pixel emitters and clusters of pixel emitters described above in FIGS. 6A and 6B, certain chiplet implementations may have more than one subpixel (e.g., more than one emitter) of each color. As described above, these additional subpixels may provide redundancy. For instance, as shown in FIGS. 7A-7F, a chiplet could have two R, two G, and two B subpixels, w here at least one subpixel of each color is functional. In some cases, only one subpixel of a given color is operated. In other cases, both subpixels of a givencolor are operated to achieve a minimum desired brightness.

[0105] In some examples, the display may be capable of emitting light with a maximum brightness of at least 1000 nits (or at least 2000 nits, 5000 nits, etc.). Each pixel may have a lateral dimension of less than 100 pm (or less than 80 pm, 100 pm, etc.). Each pixel may emit a maximum white photometric power of at least 2e-5 Im (or 4e-5 Im, 10e-5 Im, etc.). Accordingly, each chiplet may be capable of emitting light with a maximum radiometric power of at least 50 nW (or at least 100 nW, 300 nW, etc.).

[0106] The chiplet architecture described herein may enable such flux requirements while retaining a very small chiplet footprint. This may be advantageous in various ways, including by minimizing the reflectivity of the display (since LEDs can cause unwanted reflection from the display). Each pixel emitter (e.g., microLED) on the chiplet may have a radius (or equivalently, a characteristic lateral dimension) of less than 3 pm (or less than 2 pm, 1 pm, etc.). Accordingly, each LED may have an area of less than 30e-12 m2(or 10e-12 m2, 3e-12 m2, etc.), and the chiplet may have a total area less than 15e-l 1 m2(or less than Sel im2, 1.5e-l l m2, etc.) with a corresponding lateral dimension of less than 12 pm (or less than 7 pm, 4 pm, etc.). This may lead to a low fill factor (defined as the fraction of a pixel’s area occupied by the chiplet), such as a fill factor less than 3% (or less than 1%, 0.3%, etc.). Such low fill factors may be advantageous for low reflectivity and for other reasons (e.g., transparency of underlying antennas, sensors, etc., as has been described). The chiplets may be combined with a pixel backplane that has a low reflectivity around the chiplet (e.g. reflectivity less than 5%, 1%, 0.1 %, etc.).

[0107] In some examples, the lateral dimensions of a chiplet may be relatively small (to enable low EPI usage and low cost), but the dimensions may remain large enough that mechanical manipulation (such as pick and place) remains possible. For instance, the lateral dimensions may be at least 2 pm (or at least 3 pm, 5 pm, 8 pm, 10 pm, etc.).

[0108] In examples where all the pixel emitters are GaN-based, the red subpixels may be characterized by their emission properties. The red emitters may have a pronounced wavelength shift with current density, such as at least 30 nm of wavelength shift per decade of current density. Accordingly, the red emitters may be driven at a sufficiently low current density, to enable a sufficiently long emission wavelength. In some cases, the current density may be less than 100 A / cm2(or less than 30 A / cm2, less than 10 A / cm2, etc.). The peak wavelength may be at least 600 nm (or at least 610 nm, 620 nm, etc.). Conversely, the current density may be at least 1 A / cm2(or at least 3 A / cm2, 10 A / cm2. etc.) to achieve a desired brightness. In some examples, the red subpixels may be larger than the other subpixels tofacilitate a lower current density. For instance, the area of the red subpixels may be at least twice the area of the green or blue subpixels.

[0109] In some examples, a chiplet could be encapsulated in a high-index encapsulant (such as silicone) with an index higher than 1.4. This may facilitate a high light extraction. As a result of small dimensions of the chiplet, the encapsulant may remain small, facilitating a low reflectivity from the display. The encapsulant may have a diameter less than 20 pm (or less than 10 pm, 5 pm. etc.).

[0110] FIG. 8 shows various elements of a direct-view display with monolithic RGB chiplets such as described above and illustrated in FIGS. 7A-7F.

[0111] A view 800-A of the direct-view display shows an array of pixels 802 in a rectilinear arrangement. As has been described, other examples may use other types of lattices (e.g., non-rectilinear lattices such as triangular or hexagonal lattices, etc.) and each pixel 802 may represent a pixel node of the lattice and the area in its vicinity.

[0112] A view 800-B shows more detail for one particular pixel 802 of the array of pixels illustrated in view 800-A. Within this particular pixel 802, view 800-B shows a chiplet 804 centered within the pixel space. View 800-B is not necessarily drawn to scale, but illustrates that chiplet 804 may have a considerably smaller footprint than the total space of its pixel 802. As described above, this differential means that the array of pixels may have a low fill factor to provide various benefits and advantages that have been described.

[0113] A view 800-C shows more detail for the example chiplet 804 illustrated in view 800-B. As shown, the chiplet 804 is held together by a grow th template (e.g. a transparent Ill-nitride based template) on which red, green, and blue pixel emitters (in this case, tw o microLEDs of each color) have been fabricated (grow n). The R, G. and B pixel emitters are shown to be connected to a backplane 806 of the direct-view display. For example, backplane 806 may include a carrier substrate such as has been described above. More particularly, the pixel emitters are shown to connect to a driver connection 808. In certain examples, this driver connection 808 may represent pixel driver circuitry (e.g., CMOS circuitry configured to drive each of the pixel emitters) implemented on the backplane at the site of the chiplet placement. In other examples, driver connection 808 may represent electrical connections (e.g., traces of a redistribution layer, etc.) to a driver circuit (e.g., a CMOS driver circuit) that is located elsewhere on the backplane, such as described above.

[0114] Direct-view7displays such as the display illustrated in views 800-A to 800-C may be fabricated with monolithic chipsets in accordance with principles described herein. For example, an illustrative method for making such a display may include: 1) formingmonolithic RGB emitters on a growth wafer (e.g. GaN-based micro-LEDs on a sapphire wafer with a template) to obtain an LED wafer; 2) singulating lateral regions of the LED wafer and removing the substrate, to obtain singulated chiplets, each having at least one R, one G, and one B subpixel and a portion of the template; and 3) transferring the chiplets to corresponding pixels of a display backplane having driving circuitry .

[0115] As has been mentioned, various methods and processes described herein may be implemented at least in part as instructions embodied in a non-transitory computer- readable medium and executable by one or more computing devices. In general, a processor (e.g., a microprocessor) receives instructions, from a non-transitory computer-readable medium (e.g., a memory, etc.), and executes those instructions, thereby performing one or more operations such as the operations described herein. Such instructions may be stored and / or transmitted using any of a variety of known computer-readable media.

[0116] A computer-readable medium (also referred to as a processor-readable medium) includes any non-transitory medium that participates in providing data (e.g., instructions) that may be read by a computer (e.g., by a processor of a computer). Such a medium may take many forms, including, but not limited to, non-volatile media, and / or volatile media. Non-volatile media may include, for example, optical or magnetic disks and other persistent memory. Volatile media may include, for example, dynamic random-access memory (DRAM), which typically constitutes a main memory. Common forms of computer- readable media include, for example, a disk, hard disk, magnetic tape, any other magnetic medium, a compact disc read-only memory (CD-ROM), a digital video disc (DVD), any other optical medium, random access memory' (RAM), programmable read-only memory' (PROM), electrically erasable programmable read-only memory' (EPROM), FLASH- EEPROM, any other memory chip or cartridge, or any other tangible medium from which a computer can read.

[0117] FIG. 9 shows an illustrative computing system 900 that may be used to implement various devices and / or systems described herein. For example, computing system 900 may include or implement (or partially implement) display assemblies (e.g., display assembly 100) described herein, devices featuring such as display assemblies (e.g.. smartwatch devices, mobile devices, extended reality displays, televisions, etc.), any implementations thereof, any components thereof, and / or other devices used therewith.

[0118] As shown in FIG. 9, computing system 900 may include a communication interface 902, a processor 904. a storage device 906, and an input / output (I / O) module 908 communicatively connected via a communication infrastructure 910. While an illustrativecomputing system 900 is shown in FIG. 9. the components illustrated in FIG. 9 are not intended to be limiting. Additional or alternative components may be used in other embodiments. Components of computing system 900 shown in FIG. 9 will now be described in additional detail.

[0119] Communication interface 902 may be configured to communicate with one or more computing devices. Examples of communication interface 902 include, without limitation, a wired network interface (such as a network interface card), a wireless network interface (such as a wireless network interface card), a modem, an audio / video connection, and any other suitable interface.

[0120] Processor 904 generally represents any ty pe or form of processing unit capable of processing data or interpreting, executing, and / or directing execution of one or more of the instructions, processes, and / or operations described herein. Processor 904 may direct execution of operations in accordance with one or more applications 912 or other computerexecutable instructions such as may be stored in storage device 906 or another computer- readable medium.

[0121] Storage device 906 may include one or more data storage media, devices, or configurations and may employ any ty pe, form, and combination of data storage media and / or device. For example, storage device 906 may include, but is not limited to, a hard drive, network drive, flash drive, magnetic disc, optical disc, RAM. dynamic RAM, other non-volatile and / or volatile data storage units, or a combination or sub-combination thereof. Electronic data, including data described herein, may be temporarily and / or permanently stored in storage device 906. For example, data representative of one or more executable applications 912 configured to direct processor 904 to perform any of the operations described herein may be stored within storage device 906. In some examples, data may be arranged in one or more databases residing within storage device 906.

[0122] I / O module 908 may include one or more I / O modules configured to receive user input and provide user output. One or more I / O modules may be used to receive input for a single virtual experience. I / O module 908 may include any hardware, firmware, software, or combination thereof supportive of input and output capabilities. For example, I / O module 908 may include hardware and / or software for capturing user input, including, but not limited to, a keyboard or keypad, a touchscreen component (e.g., touchscreen display), a receiver (e.g., an RF or infrared receiver), motion sensors, and / or one or more input buttons.

[0123] I / O module 908 may include one or more devices for presenting output to a user, including, but not limited to, a graphics engine, a display (e.g., a display screen), one ormore output drivers (e.g., display drivers), one or more audio speakers, and one or more audio drivers. In certain embodiments, I / O module 908 is configured to provide graphical data to a display for presentation to a user. The graphical data may be representative of one or more graphical user interfaces and / or any other graphical content as may sen e a particular implementation.

[0124] The following examples describe implementations of display tiles for a display assembly with transferred pixel emitters in accordance with principles described herein.

[0125] Example 1. 1 : A display assembly comprising: a carrier substrate; a subset of pixel emitters included within a set of pixel emitters, the set of pixel emitters being transferred to the carrier substrate after fabrication of the set of pixel emitters; and an integrated circuit electrically connected to the subset of pixel emitters, the integrated circuit being transferred to the carrier substrate after fabrication of the integrated circuit and including: a set of pixel drivers configured to drive the subset of pixel emitters, and a modulator configured to control, based on signaling associated with a portion of a content frame, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

[0126] Example 1.2: A display assembly comprising: a carrier substrate; a subset of pixel emitters included within a set of pixel emitters, the set of pixel emitters being disposed on the carrier substrate; and an integrated circuit electrically connected to the subset of pixel emitters, the integrated circuit being disposed on the carrier substrate and including: a set of pixel drivers configured to drive the subset of pixel emitters, and a modulator configured to control, based on signaling associated with a portion of a content frame, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

[0127] Example 2: The display assembly of any of Examples 1.1 to 1.2, wherein: the set of pixel emitters is transferred to the carrier substrate from a donor wafer on which the set of pixel emitters is fabricated, the set of pixel emitters being arranged on the carrier substrate with respect to a lattice that includes a plurality of pixel nodes; and the set of pixel emitters is fabncated at a first pitch on the donor wafer, the first pitch being smaller than a second pitch at which the plurality of pixel nodes are disposed on the lattice.

[0128] Example 3: The display assembly of Example 2, w herein each of the plurality of pixel nodes contains a singular pixel emitter, the singular pixel emitter implemented by one of a red pixel emitter, a green pixel emitter, or a blue pixel emitter.

[0129] Example 4: The display assembly of Example 3, wherein each of the pluralityof pixel nodes further contains a backup pixel emitter that is a same color as the singular pixel emitter.

[0130] Example 5: The display assembly of Example 2, wherein each of the plurality of pixel nodes contains a cluster of pixel emitters, the cluster of pixel emitters including a red pixel emitter, a green pixel emitter, and a blue pixel emitter.

[0131] Example 6: The display assembly of any of Example 5, wherein each of the plurality of pixel nodes further contains a backup cluster of pixel emitters including a backup red pixel emitter, a backup green pixel emitter, and a backup blue pixel emitter.

[0132] Example 7: The display assembly of any of Examples 2 to 6, wherein a pixel node of the plurality of pixel nodes of the lattice contains a pixel emitter and a backup pixel emitter that both share an electrical trace routed from the integrated circuit to the pixel node.

[0133] Example 8: The display assembly of any of Examples 2 to 7, wherein the lattice is a rectilinear lattice that includes pixel nodes arranged in a grid of rows and columns.

[0134] Example 9: The display assembly of any of Examples 2 to 7, wherein the lattice is a non-rectilinear lattice.

[0135] Example 10: The display assembly of any of Examples 1.1 to 9, wherein the set of pixel drivers are supplied power by a singular power supply.

[0136] Example 11 : The display assembly of any of Examples 1.1 to 9, wherein the set of pixel drivers includes: a first subset of pixel drivers configured to drive red pixel emitters within the subset of pixel emitters and being supplied power by a first power supply; a second subset of pixel drivers configured to drive green pixel emitters within the subset of pixel emitters and being supplied power by a second power supply; and a third subset of pixel drivers configured to drive blue pixel emitters within the subset of pixel emitters and being supplied power by a third power supply.

[0137] Example 12: The display assembly of any of Examples 1.1 to 11, wherein: the subset of pixel emitters is a first subset of pixel emitters included within the set of pixel emitters, the first subset of pixel emitters being disposed on the carrier substrate together with a second subset of pixel emitters included within the set of pixel emitters; and the first subset of pixel emitters and the second subset of pixel emitters are disposed in an adjacent and nonoverlapping arrangement on the carrier substrate.

[0138] Example 13: The display assembly of any of Examples 1.1 to 11, wherein: the subset of pixel emitters is a first subset of pixel emitters included within the set of pixel emitters, the first subset of pixel emitters being disposed on the earner substrate together with a second subset of pixel emitters included within the set of pixel emitters; and the first subsetof pixel emiters and the second subset of pixel emiters are disposed in an overlapping arrangement on the carrier substrate.

[0139] Example 14: The display assembly of any of Examples 1.1 to 13, wherein: the set of pixel emiters is implemented by a set of micro light emiting diodes (microLEDs); and the integrated circuit is implemented by a complementary-metal-oxide-semiconductor (CMOS) integrated circuit.

[0140] Example 15: The display assembly of any of Examples 1.1 to 14, wherein the display assembly is configured for use as a smartwatch display.

[0141] Example 16.1 : A method comprising: receiving, by an integrated circuit transferred to a carrier substrate after fabrication of the integrated circuit, signaling associated with a portion of a content frame; controlling, by a modulator of the integrated circuit and based on the signaling, a set of pixel drivers of the integrated circuit; and driving, by the set of pixel drivers based on the controlling by the modulator, a subset of pixel emiters included within a set of pixel emiters that is transferred to the carrier substrate after fabrication of the set of pixel emiters, the driving of the subset of pixel emiters configured to present the portion of the content frame using a pulse width modulation technique.

[0142] Example 16.2: A method comprising: receiving, by an integrated circuit disposed on a carrier substrate, signaling associated with a portion of a content frame; controlling, by a modulator of the integrated circuit and based on the signaling, a set of pixel drivers of the integrated circuit; and driving, by the set of pixel drivers based on the controlling by the modulator, a subset of pixel emiters included within a set of pixel emiters that is disposed on the carrier substrate, the driving of the subset of pixel emiters configured to present the portion of the content frame using a pulse width modulation technique.

[0143] Example 17: The method of any of Examples 16.1 to 16.2, wherein: the content frame is associated with a set of content subframes; the signaling includes a timing signal and frame data for respective portions of each content subframe of the set of content subframes; and the portion of the content frame is presented using the pulse width modulation technique by presenting, in a timed sequence based on the timing signal, the respective portions of each content subframe of the set of content subframes.

[0144] Example 18.1: An integrated circuit comprising: a first signal interface configured to electrically connect to a subset of pixel emitters included within a set of pixel emiters, the set of pixel emiters being transferred to a carrier substrate after fabrication of the set of pixel emiters; a second signal interface configured to receive signaling associated with a portion of a content frame; a set of pixel drivers configured to drive the subset of pixelemitters; and a modulator configured to control, based on the signaling, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

[0145] Example 18.2: An integrated circuit comprising: a first signal interface configured to electrically connect to a subset of pixel emitters included within a set of pixel emitters, the set of pixel emitters being disposed on a carrier substrate; a second signal interface configured to receive signaling associated with a portion of a content frame; a set of pixel drivers configured to drive the subset of pixel emitters; and a modulator configured to control, based on the signaling, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

[0146] Example 19: The integrated circuit of any of Examples 18. 1 to 18.2, wherein: the set of pixel emitters is implemented by a set of micro light emitting diodes (microLEDs); and the integrated circuit is implemented by a complementary-metal-oxide-semiconductor (CMOS) integrated circuit.

[0147] Example 20: The integrated circuit of any of Examples 18.1 to 19, configured for use as part of a display assembly implemented within a smartwatch device.

[0148] Various implementations of the systems and techniques described herein can be realized in digital electronic circuitry', integrated circuitry', specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0149] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the description and claims. In addition, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.

[0150] Specific structural and functional details disclosed herein are merely representative for purposes of describing example implementations. Example implementations, however, may be embodied in many alternate forms and should not beconstrued as limited to only the implementations set forth herein.

[0151] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. A first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the implementations of the disclosure. As used herein, the term and / or includes any and all combinations of one or more of the associated listed items.

[0152] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the implementations. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used in this specification, specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0153] It will be understood that when an element is referred to as being “coupled,” “connected,” or “responsive” to, or “on,” another element, it can be directly coupled, connected, or responsive to, or on, the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, or “directly on,” another element, there are no intervening elements present. As used herein the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0154] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature in relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 130 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0155] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0156] Further to the descriptions above, a user may be provided with controls allowing the user to make an election as to both if and when systems, programs, or features described herein may enable collection of user information (e.g., information about a user's social network, social actions, or activities, profession, a user's preferences, or a user's current location), and if the user is sent content or communications from a server. In addition, certain data may be treated in one or more ways before it is stored or used, so that personally identifiable information is removed. For example, a user's identity may be treated so that no personally identifiable information can be determined for the user, or a user's geographic location may be generalized, or location information may be obtained (such as to a city, zip code, or state level), so that a particular location of a user cannot be determined. Thus, the user may have control over what information is collected about the user, how that information is used, and what information is provided to the user.

[0157] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents may occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover such modifications and changes as fall within the scope of the implementations. It will be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described. As such, the scope of the present disclosure is not limited to the particular combinations hereafter claimed, but instead extends to encompass any combination of features or example implementations described herein irrespective of whether or not that particular combination has been specifically enumerated in the accompanying claims at this time.

Claims

WHAT IS CLAIMED IS:

1. A display assembly comprising: a carrier substrate; a subset of pixel emitters included within a set of pixel emitters, the set of pixel emitters being transferred to the carrier substrate after fabrication of the set of pixel emitters; and an integrated circuit electrically connected to the subset of pixel emitters, the integrated circuit being transferred to the carrier substrate after fabrication of the integrated circuit and including: a set of pixel drivers configured to drive the subset of pixel emitters, and a modulator configured to control, based on signaling associated with a portion of a content frame, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

2. The display assembly of claim 1. wherein: the set of pixel emitters is transferred to the carrier substrate from a donor wafer on which the set of pixel emitters is fabricated, the set of pixel emitters being arranged on the carrier substrate with respect to a lattice that includes a plurality of pixel nodes; and the set of pixel emitters is fabricated at a first pitch on the donor wafer, the first pitch being smaller than a second pitch at which the plurality of pixel nodes is disposed on the lattice.

3. The display assembly of claim 2. wherein each of the plurality of pixel nodes contains a singular pixel emitter, the singular pixel emitter implemented by one of a red pixel emitter, a green pixel emitter, or a blue pixel emitter.

4. The display assembly of claim 3. wherein each of the plurality of pixel nodes further contains a backup pixel emitter that is a same color as the singular pixel emitter.

5. The display assembly of claim 2, wherein each of the plurality of pixel nodes contains a cluster of pixel emitters, the cluster of pixel emitters including a red pixel emitter, a green pixel emitter, and a blue pixel emitter.

6. The display assembly of claim 5, wherein each of the plurality of pixel nodes further contains a backup cluster of pixel emitters including a backup red pixel emitter, a backup green pixel emitter, and a backup blue pixel emitter.

7. The display assembly of any of claims 2 to 6, wherein a pixel node of the plurality of pixel nodes of the lattice contains a pixel emitter and a backup pixel emitter that both share an electrical trace routed from the integrated circuit to the pixel node.

8. The display assembly of any of claims 2 to 7, wherein the lattice is a rectilinear lattice that includes pixel nodes arranged in a grid of rows and columns.

9. The display assembly of any of claims 2 to 7, wherein the lattice is a non- rectilinear lattice.

10. The display assembly of any of claims 1 to 9, wherein the set of pixel drivers are supplied power by a singular power supply.

11. The display assembly of any of claims 1 to 9, wherein the set of pixel drivers includes: a first subset of pixel drivers configured to drive red pixel emitters within the subset of pixel emitters and being supplied power by a first power supply; a second subset of pixel drivers configured to drive green pixel emitters within the subset of pixel emitters and being supplied power by a second power supply; and a third subset of pixel drivers configured to drive blue pixel emitters within the subset of pixel emitters and being supplied power by a third power supply.

12. The display assembly of any of claims 1 to 11, wherein: the subset of pixel emitters is a first subset of pixel emitters included within the set of pixel emitters, the first subset of pixel emitters being disposed on the carrier substrate together with a second subset of pixel emitters included within the set of pixel emitters; and the first subset of pixel emitters and the second subset of pixel emitters are disposed in an adjacent and non-overlapping arrangement on the carrier substrate.

13. The display assembly of any of claims 1 to 11, wherein: the subset of pixel emitters is a first subset of pixel emitters included within the set of pixel emitters, the first subset of pixel emitters being disposed on the carrier substrate together with a second subset of pixel emitters included within the set of pixel emitters; and the first subset of pixel emitters and the second subset of pixel emitters are disposed in an overlapping arrangement on the carrier substrate.

14. The display assembly of any of claims 1 to 13, wherein: the set of pixel emitters is implemented by a set of micro light emitting diodes (microLEDs); and the integrated circuit is implemented by a complementary-metal-oxide-semiconductor (CMOS) integrated circuit.

15. The display assembly of any of claims 1 to 14, wherein the display assembly is configured for use as a smartwatch display.

16. A method comprising: receiving, by an integrated circuit transferred to a carrier substrate after fabrication of the integrated circuit, signaling associated with a portion of a content frame; controlling, by a modulator of the integrated circuit and based on the signaling, a set of pixel drivers of the integrated circuit; and driving, by the set of pixel drivers based on the controlling by the modulator, a subset of pixel emitters included within a set of pixel emitters that is transferred to the carrier substrate after fabrication of the set of pixel emitters, the driving of the subset of pixel emitters configured to present the portion of the content frame using a pulse width modulation technique.

17. The method of claim 16, wherein: the content frame is associated with a set of content subframes; the signaling includes a timing signal and frame data for respective portions of each content subframe of the set of content subframes; and the portion of the content frame is presented using the pulse width modulation technique by presenting, in a timed sequence based on the timing signal, the respective portions of each content subframe of the set of content subframes.

18. An integrated circuit comprising: a first signal interface configured to electrically connect to a subset of pixel emitters included within a set of pixel emitters, the set of pixel emitters being transferred to a carrier substrate after fabrication of the set of pixel emitters; a second signal interface configured to receive signaling associated with a portion of a content frame; a set of pixel drivers configured to drive the subset of pixel emitters; and a modulator configured to control, based on the signaling, the set of pixel drivers to drive the subset of pixel emitters to present the portion of the content frame using a pulse width modulation technique.

19. The integrated circuit of claim 18, wherein: the set of pixel emitters is implemented by a set of micro light emitting diodes (microLEDs); and the integrated circuit is implemented by a complementary-metal-oxide-semiconductor (CMOS) integrated circuit.

20. The integrated circuit of any of claims 18 to 19, configured for use as part of a display assembly implemented within a smartwatch device.

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