Nested quantum error correction codes for fault-tolerant quantum computation

Abstract

A method for operating a quantum computer with a set of qubits is disclosed. A quantum algorithm redundantly encodes quantum information in each physical qubit. Each physical qubit redundantly encodes the quantum information. The set of physical qubits is employed to form a set of logical qubits. Each logical qubit is formed via a separate subset of the physical qubits. Each logical qubit redundantly encodes the quantum information. Each separate subset of physical qubits is disjoint from each other separate subset of physical qubits. A first quantum error correction (QEC) code is performed on each logical qubit. The first QEC code detects a first set of parity conditions across the separate subset of physical qubits forming the logical qubit. A second QEC code may be performed on the set of logical qubits. The second QEC code detects a second set of parity conditions across the set of logical qubits.

Description

NESTED QUANTUM ERROR CORRECTION CODES FOR FAULT-TOLERANT QUANTUM COMPUTATIONPRIORITY CLAIM

[0001] This application claims priority to U.S. Provisional Application No. 63 / 594,865, filed on October 31, 2023, entitled “NESTED QUANTUM ERROR CORRECTION CODES FOR FAULT-TOLERANT QUANTUM COMPUTATION,” the contents of which are incorporated in their entirety herein.FIELD

[0002] The present disclosure relates generally to quantum computing systems, and more particularly to the nested quantum error correction (QEC) codes for fault-tolerant quantum computationBACKGROUND

[0003] Quantum computing is a computing method that takes advantage of quantum effects, such as superposition of basis states and entanglement to perform certain computations more efficiently than a classical digital computer. In contrast to a digital computer, which stores and manipulates information in the form of bits, e.g., a “1” or “0,” quantum computing systems can manipulate information using quantum bits (“qubits”). A qubit can refer to a quantum device that enables the superposition of multiple states, e.g., data in both the “0” and “1” state, and / or to the superposition of data, itself, in the multiple states. In accordance with conventional terminology, the superposition of a “0” and “1” state in a quantum system may be represented, e.g., as a |0) + b | 1) The “0” and “1” states of a digital computer are analogous to the |0) and | 1) basis states, respectively of a qubit.SUMMARY

[0004] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or can be learned from the description, or can be learned through practice of the embodiments.

[0005] One example aspect of the present disclosure is directed to a method for operating a fault-tolerant quantum computing system. The method includes the quantum computing system operating a quantum algorithm. The quantum algorithm redundantly encodes quantum information in each physical qubit of the set of qubits such that each physical qubit of the set of physical qubits redundantly encodes the quantum information. When executing the quantum algorithm, the set of physical qubits is employed to form a set of logical qubits.Each logical qubit of the set of logical qubits being formed via a separate subset of the set of physical qubits such that each logical qubit of the set of logical qubits redundantly encodes the quantum information. Each separate subset of physical qubits is disjoint from each other separate subset of physical qubits. While executing the quantum algorithm, a first quantum error correction (QEC) code is performed on each logical qubit of the set of logical qubits. The first QEC code detects a first set of parity conditions across the separate subset of physical qubits forming the logical qubit. While executing the quantum algorithm, a second QEC code may be performed on the set of logical qubits. The second QEC code detects a second set of parity conditions across the set of logical qubits.

[0006] Other aspects of the present disclosure are directed to various systems, methods, apparatuses, non-transitory computer-readable media, computer-readable instructions, and computing devices.

[0007] These and other features, aspects, and advantages of various embodiments of the present disclosure will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and, together with the description, explain the related principles.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Detailed discussion of embodiments directed to one of ordinary skill in the art is set forth in the specification, which refers to the appended figures, in which:

[0009] FIG. 1 depicts an example quantum computing system according to example embodiments of the present disclosure.

[0010] IG. 2 depicts a conceptual visualization of a nested quantum error correction code, according to various embodiments.

[0011] FIG. 3A depicts a ID nested quantum error correction code, according to various embodiments.

[0012] FIG. 3B depicts a 2D nested quantum error correction code, according to various embodiments.

[0013] FIG. 3C shows a table that indicates stabilizers and logical generators for a 2D yoked surface code, according to various embodiments.

[0014] FIG. 4A shows pipe diagrams for measuring multi-body stabilizers, according to various embodiments.

[0015] FIG. 4B shows a pipe diagram of operations that increase the protection against hook errors, according to various embodiments.

[0016] FIG. 5 A demonstrates checking X and Z-type stabilizers of an iceberg code using lattice surgery, according to various embodiments.

[0017] FIG. 5B shows pipe diagrams for a full syndrome cycle of a nested QEC code, according to various embodiments.

[0018] FIG. 6 demonstrates decoding the outer code abstracted from complementary gaps, according to various embodiments.

[0019] FIG. 7 shows layouts for both cold and hot storage architectures for lattice surgery, according to various embodiments.

[0020] FIG. 8 depicts a flow chart diagram of an example method for operating a fault- tolerant quantum computing system, according to example embodiments of the present disclosure.DETAILED DESCRIPTION

[0021] Example aspects of the present disclosure are directed to nested quantum error correction (QEC) codes for fault-tolerant quantum computation. Throughout, a nested surface code (e.g., a yoked surface code) is discussed. However, the embodiments are not limited to surface codes and may be generalized to nested versions of other QEC codes (e.g., toric codes other than a surface code). The discussion throughout is focused on a two-layered nested QEC code, with an inner QEC code (e.g., a surface code) and an outer QEC code (e.g., a ID or 2D parity check code). However, the embodiments are not limited to two-layers of nestedcodes. Similar to programmatic loop- structures, any number of nested-layers may be employed in the embodiments. For example, an intermediate QEC code may be sandwiched between the inner and outer codes to form a three-layered nested QEC code. The number of layers may be dependent upon the underlying physical qubit error rate, the target logical qubit error rate, the total number of physical qubits available, the ability to scale the layers, and / or the complexity of the underlying quantum algorithm deployed on the hardware.

[0022] The inner surface code may operate on each logical qubit of a set of logical qubits. Each logical qubit of the set of logical qubits is implemented by a set of physical qubits. Each logical qubit of the set of qubits (including the stabilizers employed to detect and correct errors) may be referred to as a separate surface code of a set of surface codes. These stabilizers may be referred to as inner stabilizers. The inner code may be comprised of the set of surface codes (or alternatively the set of logical qubits and the set of inner stabilizers). The inner code detects and corrects at least a subset of errors occurring in the physical qubits that form the logical qubits. The surface codes of the set of surface codes may be coupled (e.g., yoked) via one or more outer stabilizers (e.g., a set of yoke stabilizers). The outer code may be comprised of the set of logical qubits and the set of yoke stabilizers that couple (or yoke) the logical qubits (e.g., a set of outer stabilizers). The outer code detects and corrects at least a subset of errors that are undetectable via the inner code (e.g., multiple errors that are beyond the detection threshold of the inner code). Thus, because the outer code can detect higher- multiplicity errors, the inner code may employ surface codes with a smaller distance to achieve the same (or lesser) overall error rate.

[0023] Stated another way, the inner surface code suppresses noise to levels at which the outer code’s superior parameters becomes more important than the surface code’s high errortolerance. The inner surface codes also provide mechanisms like lattice surgery to perform operations between distant qubits. The outer code then suppresses the remaining noise down to the level required by the algorithm, with a final footprint lower than just using the surface code alone.

[0024] A traditional surface code may be tolerant to noise (e.g., qubit errors), but also comes with significant qubit overhead. As noted above, some of the embodiments herein employ a surface code as an inner code that is concatenated with a high-rate outer code (e.g., a ID or a 2D parity check code). This two-layered nested approach is referred to as a yokedsurface code throughout. However, as also noted above, other embodiments may employ additional layers and / or other QEC codes. These outer parity-check codes prioritize coding rate over low-weight check operators and distance. The ID parity-check code may be a [[ / ?, n - 2, 2]] code, where n-2 is the number of logical qubits implemented by the inner code. By nesting error codes, the embodiments provide a reduction of the qubit overhead. That is, because the outer code detects and corrects errors on logical qubits within the inner code, each (inner code) logical qubit may be formed by a reduced number of physical qubits, as compared with a traditional surface code. The overall error rate of the nested code is less than or equal to the overall error rate of a traditional surface code, however, the qubit overhead in the nested code is significantly reduced, as compared to the traditional code. For instance, as shown below, compared to traditional surface codes, the ID yoked surface code of the embodiments employ half as many qubits to achieve target logical error rates of < 10-^. A 2D yoked surface code of the embodiments employ a third as many qubits to achieve target logical error rates of < 10“ 15 Therefore, the embodiments provide a notable improvement in the expected cost of building large scale fault-tolerant quantum computers.

[0025] Because of its forgiving quality and connectivity requirements, the surface code is a leading contender for the error correcting code to use in the architecture of large scale fault tolerant quantum computers. The surface code’s major downside is its extremely demanding quantity requirements. Given the underlying error rate of current qubit implementations, it may take 1000 to 2000 physical qubits per logical qubit for the surface code to reach error rates low enough to run classically intractable algorithms such as Shor’s algorithm at plausible physical error rates.

[0026] The embodiments herein reduce this overhead by implementing nested QEC codes (e.g., an inner code and an outer code). The inner surface code suppresses noise to levels at which the outer code’s superior parameters becomes more important than the inner surface code’s high error-tolerance. The inner surface codes also provide mechanisms like lattice surgery to perform operations between distant qubits. The outer code then suppresses the remaining noise down to the level required by the algorithm, with a final footprint lower than just using the surface code alone.

[0027] Some QEC codes contemplate that the overlying code has high distance, high rate, and low-density parity checks. Small parity checks provide two important advantages.First, their syndrome extraction circuits are small, and so the entropy injected into the system while measuring stabilizers is low. Second, their locality limits the damage caused by correlated errors, sometimes for free. However, requiring these properties together tends to demand complexity and larger block sizes to see improved overheads, as the inner surface codes provide a costly inner qubit.

[0028] Some embodiments employ parity check codes as outer codes, focusing on achieving a high coding rate. In some embodiments, a ID parity -check outer code is employed, e.g., a [ [n, n~ 2, 2]] code. The need for higher distance constructions may be avoided by utilizing the “soft” information afforded by surface codes, in the form of the complementary gap of a minimum-weight perfect matching. This greatly enhances the performance of the outer code, with these gaps determining edge weights of an outer error graph that can be decoded using standard matching techniques. In the ID case, it promotes an otherwise error detecting code to one that behaves like an error correcting code. By using surface codes to suppress the error of each individual operation, it can be ensured that the noise injected when measuring many logical qubits is not too large. Furthermore, damaging high-weight hook errors can be avoided by adding protection against them during lattice surgery. Specifically, these damaging errors may be oriented in the time-like direction, and the parity checks are “slowed- down” to enforce added protection against them.

[0029] Aspects of the present disclosure provide a number of technical effects and benefits. For instance, the embodiments employ nested QEC codes (e.g., a yoke surface code). Various embodiments of yoke surface codes are 2 / 3 the size of normal surface codes, at reasonable target logical error rates. Reducing the quantity of qubits required by surface codes is extremely useful because the required quantity of physical qubits limits the applicability of standard surface codes. The embodiments contemplate both Yberg codes and iceberg codes as yoke surface codes.

[0030] With reference now to the Figures, example embodiments of the present disclosure will be discussed in further detail.

[0031] FIG. 1 depicts an example quantum computing system 100. The system 100 is an example of a system of one or more classical computers and / or quantum computing devices in one or more locations, in which the systems, components, and techniques described below can be implemented. Those of ordinary skill in the art, using the disclosures provided herein, willunderstand that other quantum computing devices or systems can be used without deviating from the scope of the present disclosure.

[0032] The system 100 includes quantum hardware 102 in data communication with one or more classical processors 104. The classical processors 104 can be configured to execute computer-readable instructions stored in one or more memory devices to perform operations, such as any of the operations described herein. The quantum hardware 102 includes components for performing quantum computation. For example, the quantum hardware 102 includes a quantum system 110, control device(s) 112, and readout device(s) 114 (e.g., readout resonator(s)). The quantum system 110 can include one or more multi-level quantum subsystems, such as a register of qubits (e.g., qubits 120). In some implementations, the multilevel quantum subsystems can include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, spin-based qubits, and the like.

[0033] The type of multi-level quantum subsystems that the system 100 utilizes may vary. For example, in some cases it may be convenient to include one or more readout device(s) 114 attached to one or more superconducting qubits, e.g., transmon, flux, gmon, xmon, or other qubits. In other cases, ion traps, photonic devices or superconducting cavities (e.g., with which states may be prepared without requiring qubits) may be used. Further examples of realizations of multi-level quantum subsystems include fluxmon qubits, silicon quantum dots or phosphorus impurity qubits.

[0034] Quantum circuits may be constructed and applied to the register of qubits included in the quantum system 110 via multiple control lines that are coupled to one or more control devices 112. Example control devices 112 that operate on the register of qubits can be used to implement quantum gates or quantum circuits having a plurality of quantum gates, e.g., Pauli gates, Hadamard gates, controlled-NOT (CNOT) gates, controlled-phase gates, T gates, multi-qubit quantum gates, coupler quantum gates, etc. The one or more control devices 112 may be configured to operate on the quantum system 110 through one or more respective control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystems may be superconducting qubits and the control devices 112 may be configured to provide control pulses to control lines to generate magnetic fields to adjust the frequency of the qubits.

[0035] The quantum hardware 102 may further include readout devices 114 (e.g., readout resonators). Measurement results 108 obtained via measurement devices may be provided to the classical processors 104 for processing and analyzing. In some implementations, the quantum hardware 102 may include a quantum circuit and the control device(s) 112 and readout devices(s) 114 may implement one or more quantum logic gates that operate on the quantum system 102 through physical control parameters (e.g., microwave pulses) that are sent through wires included in the quantum hardware 102. Further examples of control devices include arbitrary waveform generators, wherein a DAC (digital to analog converter) creates the signal.

[0036] The readout device(s) 114 may be configured to perform quantum measurements on the quantum system 110 and send measurement results 108 to the classical processors 104. In addition, the quantum hardware 102 may be configured to receive data specifying physical control qubit parameter values 106 from the classical processors 104. The quantum hardware 102 may use the received physical control qubit parameter values 106 to update the action of the control device(s) 112 and readout devices(s) 114 on the quantum system 110. For example, the quantum hardware 102 may receive data specifying new values representing voltage strengths of one or more DACs included in the control devices 112 and may update the action of the DACs on the quantum system 110 accordingly. The classical processors 104 may be configured to initialize the quantum system 110 in an initial quantum state, e.g., by sending data to the quantum hardware 102 specifying an initial set of parameters 106.

[0037] In some implementations, the readout device(s) 114 can take advantage of a difference in the impedance for the |0) and |1) states of an element of the quantum system, such as a qubit, to measure the state of the element (e.g., the qubit). For example, the resonance frequency of a readout resonator can take on different values when a qubit is in the state |0) or the state 11), due to the nonlinearity of the qubit. Therefore, a microwave pulse reflected from the readout device 114 carries an amplitude and phase shift that depend on the qubit state. In some implementations, a Purcell filter can be used in conjunction with the readout device(s) 114 to impede microwave propagation at the qubit frequency.

[0038] In some embodiments, the quantum system 110 can include a plurality of qubits 120 arranged, for instance, in a two-dimensional grid 122. For clarity, the two-dimensional grid 122 depicted in FIG. 1 includes 4x4 qubits, however in some implementations the system1 10 may include a smaller or a larger number of qubits. In some embodiments, the multiple qubits 120 can interact with each other through multiple qubit couplers, e.g., qubit coupler 124. The qubit couplers can define nearest neighbor interactions between the multiple qubits 120. In some implementations, the strengths of the multiple qubit couplers are tunable parameters. In some cases, the multiple qubit couplers included in the quantum computing system 100 may be couplers with a fixed coupling strength.

[0039] In some implementations, the multiple qubits 120 may include data qubits, such as qubit 126 and measurement qubits, such as qubit 128. A data qubit is a qubit that participates in a computation being performed by the system 100. A measurement qubit is a qubit that may be used to determine an outcome of a computation performed by the data qubit. That is, during a computation an unknown state of the data qubit is transferred to the measurement qubit using a suitable physical operation and measured via a suitable measurement operation performed on the measurement qubit.

[0040] In some implementations, each qubit in the multiple qubits 120 can be operated using respective operating frequencies, such as an idling frequency and / or an interaction frequency and / or readout frequency and / or reset frequency. The operating frequencies can vary from qubit to qubit. For instance, each qubit may idle at a different operating frequency. The operating frequencies for the qubits 120 can be chosen before a computation is performed.

[0041] FIG. 1 depicts one example quantum computing system that can be used to implement the methods and operations according to example aspects of the present disclosure. Other quantum computing systems can be used without deviating from the scope of the present disclosure.

[0042] FIG. 2 depicts a conceptual visualization of a nested quantum error correction (QEC) code 200, according to various embodiments. It should be noted that the nested QEC code 200 of FIG. 2 provides a visualization of the various embodiments. The visualization shows various concepts of non-limiting embodiments. The nested QEC code 200 includes an inner code and an outer code. More particularly, the inner code is a surface code that is run on eight logical qubits. One of the eight logical qubits is indicated as the logical qubit 202. The inner code is a surface area code that operates on each of the eight logical qubits, including logical qubit 202. Thus, the inner code may implement eight separate surface codes, one foreach of the eight logical qubits. The inner surface codes include XXXX and ZZZZ stabilizers for the non-boundary checks. The boundary checks include XX and ZZ stabilizers.

[0043] The outer code of nested QEC code 200 includes a yoke stabilizer 204 that couples (or yokes) the eight logical qubits. In the non-limiting embodiments of FIG. 2, the yoke stabilizer is a Ysstabilizer, where the L subscript indicates that the yoke stabilizer 204 is stabilizing the logical qubits (and not individual physical qubits) and the tensor product superscript indicates that it has eight Y-checks, one for each of the eight logical qubits.Quantum Parity Check Codes

[0044] This section describes the ID and 2D (quantum) parity check codes that form the outer code in various embodiments. Quantum parity check Calderbank, Shorm, Steane (CSS) codes are generalizations of classical parity check codes. Qubits are laid out in a ID or 2D array, and the parity of each row or each row and column are checked. The following discussion focuses on these codes because their parity checks are geometrically simple, and their rate quickly trends to 1 as their volume increases. However, the embodiments are not limited to ID or 2D CSS codes.

[0045] Unlike classical parity check codes, certain parity requirements may be enforced to ensure that the stabilizers of these codes commute. In a ID embodiment, the length of the code may be required to be divisible by two. In a 2D embodiment, the side length of the code may be required to be divisible by four. More generally, an r-D parity check code may have each side length divisible by 2r. The reason is that row and column operators of opposite Pauli type anti-commute, since they intersect in a single location. With these restricted side length parities, this can be fixed by changing the ordering of the qubits for different Pauli type rows and columns. In particular, for row vectors ft E F^2and e£E F2 the support of the Z-type row and column parity checks may be modified as ft 0 ej ft ® 6j and fi ® e - / £T0 ej, to ensure that they always commute with row and column Y-type checks.

[0046] An r-dimensional parity check code has distance 2r, with minimum weight logical operators forming the vertices of an r-dimensional cube. By counting the number ofindependent checks, it has parameters [[fl n;,2 n(ni—1)—11nt,2r]], where nt are the side lengths of the r-dimensional array. In particular, for ID and 2D codes, code families of [[n, n - 2, 2]] and [\n2, n2— 4 / ? + 2, 4]] may respectively be obtained.

[0047] FIG. 3A depicts a ID nested quantum error correction (QEC) code 300, according to various embodiments. That is, the outer code of QEC code 300 includes ID X and Z parity checks. The outer code is overlayed on the inner code, which includes a surface code on each “patch” of physical qubits. Each surface code of the inner code protects its logical qubit to a distance =6. The combination of the outer code and the inner code protects the logical qubits to a distance=12. Each logical qubit is indicated by a square outline enclosing a set of physical qubits (represented by the dots). Thus, a 2D array of logical qubits is shown in FIG. 3. There are six rows and eight columns of logical qubits in the 2D array of logical qubits. Each row of logical qubits (e.g., surface code patches) includes six (e.g., the six left-most six logical qubits in the row) logical qubits that are “yoked” (or coupled) via ID (X and Z) parity checks. The two right-most logical qubits in a row represent the degrees of freedom that are fixed to measure each parity check.

[0048] In each row, an eight-body X stabilizer and a Z stabilizer are measured. An X- stabilizer measurement is marked as the operator X in the uppermost row, where the row is shaded to show the yoking that the X operator is providing. A Z-stabilizer is marked as the operator Z in the fourth row, where the row is shaded to show the yoking that the Z operator is providing. These ID parity check stabilizers are formed from the logical operators of the underlying distance-6 surface codes. Thus, the ID QEC code 300 protects 36 logical qubits to a distance-12. In some embodiments, and in an ideal scenario, the ID QEC code 300 can increase the coding rate of the surface code by a factor of four.

[0049] FIG. 3B depicts a 2D nested quantum error correction (QEC) code 320, according to various embodiments. That is, the outer code of QEC code 320 includes 2D X and Z parity checks. As shown in FIG. 3B, the X and Z parity checks are performed across the rows and the columns. That is, in each row and each column, both X and Z stabilizers are measured. The Z-type stabilizers are applied to a permutation of the code (as shown by the arrows) to commute with the X-type stabilizers. In total, 2D QEC code 320 holds 34 logical qubits to a distance=12. In some embodiments, the 2D QEC code 320 can increase the coding rate of the surface code by a factor of sixteen.

[0050] FIG. 3C shows a table 340 that indicates stabilizers and logical generators for a 2D yoked surface code, according to various embodiments. More particularly, table 340 describes a 2D [[16, 2, 4]] yoked surface code. Each cell of table 340 shows entries of a stabilizer as a 4 x 4 grid of Pauli terms; one term for each of the 16 physical qubits. Note that two of the listed checks are redundant. For instance, the product of all X column checks is equal to the product of all X row checks, and the product of all Z bi-column checks is equal to the product of all Z bi-row checks.Lattice Surgery Constructions

[0051] This section discusses details of the lattice surgery constructions for measuring stabilizers and analyzing their overhead and fault-tolerance properties. When concatenating a code over the surface code, the stabilizers of the overlying code may be measured. The workspace needed to periodically measure the stabilizers of the overlying code may be larger than the space needed to just store the qubits. Also, the effects of errors occurring during the lattice surgery need to be accounted for in order to understand the behavior of the overlying code.

[0052] From one perspective, lattice surgery may be thought of as being built out of parity measurement. However, a more useful perspective is to view lattice surgery as an instantiation of the ZX calculus. In the latter perspective, the building blocks of lattice surgery are not operations on qubits but rather connections between junctions. Making a good lattice surgery construction then becomes an exercise in packing, routing, and rotating pipes (within a ZX calculus pipe diagram), so that they link together in the required way.

[0053] FIG. 4A shows pipe diagrams for measuring multi-body stabilizers, according to various embodiments. In FIG. 4A, the lighter shading corresponds to an X-type boundary and the darker shading corresponds to a Z-type boundary. A first pipe diagram 400 (on the left) demonstrates measuring an 8-body Z-type row check, with the measured observable running parallel to the X-type boundary highlighted in hatched shading. Second pipe diagram 410 (on the right) demonstrates measuring an 8-body Z-type bi-row check. In the interior, a hatched correlation surface relating a Z-type error string in the interior of the central bar to four Z-type error strings on the outer corridors. This is analogous to a Z-type hook error propagating froma measure qubit to four data qubits of the outer code. Some of these correlated errors may not be protected against by the outer code.

[0054] When executing a fault-tolerant circuit described in terms of these pipe diagrams, it may be of little importance to be concerned with which observables are corrupted during the circuits execution. It may be assumed that any corrupted observable may ruin the circuit. However, when concatenating the surface code into an outer code, it may be important to be concerned about error propagation in much the same way as when designing fault-tolerant syndrome extraction at the base code level. One disadvantage of using high density parity check (HDPC) codes is that the presence of these high weight stabilizers can cause correlated failures of multiple observables simultaneously, which may not be correctable by the outer code. These may be analogous to hook errors propagating from a measure qubit to many data qubits.

[0055] However, unlike physical qubits, surface code qubits have a property that modulates the distances between boundaries to bias protection against different error mechanisms. For example, the protection against the correlated error may be extended to suppress its probability below that of the concatenated code. This may enlarge the footprint of the concatenated code by extending the size of the base code. However, a second property of the surface code is that its circuits may be agnostic to their orientation in space and time. Consequently, this extended protection may be oriented in the time direction, holding the spatial footprint of the yoked surface codes fixed. The cost may increase the length of the outer code’s syndrome cycle, which in turn may increase the distance required by the inner code. However, the error rate scales polynomially with the length of the syndrome cycle and inverse exponentially with the distance of the inner code.

[0056] FIG. 4B shows a pipe diagram 420 of operations that increase the protection against hook errors, according to various embodiments. In FIG. 4A, the protection against a hook error (i.e., the boundary in the shared pipe on the hatched correlation surface) is protected by extending the distance between the boundaries that it condenses on. This would increase the overall qubit footprint by the circuit. However, this may be oriented as an extension of time, trading a smaller qubit footprint for a longer syndrome extraction cycle.

[0057] As ID and 2D yoked surface codes, having distance 2 (e.g., see FIG. 4B) and 4 respectively, the stabilizer checks may be extended by a factor of two and a factor of four, respectively. This is likely overly conservative for four reasons. First, ‘narrow’ surface codesshould have increased error suppression relative to their square counterparts. Second, the effective error suppression factor of ID (2D) yoked surface codes is sub-quadratic (sub-quartic) in the underlying surface code error suppression factor. Third, the cumulative probability of this error mechanism scales linearly in the number of patches and rounds. It can be shown that the cumulative error probability of the error mechanisms protected against by yoked surface codes scale superlinearly. These three observations indicate that the error per patch-round caused by one of these hook errors should be far lower than the error per patch-round caused by the other, protected errors. Fourth, the total number of patch-rounds which are exposed to this hook error are a small fraction of the total number of patch-rounds in the overall memory. However, the estimates may err on the side of caution in our estimates, and some embodiments may use overly slow syndrome measurements.

[0058] FIG. 5 A demonstrates checking X- and Z-type stabilizers of an iceberg code using lattice surgery, according to various embodiments. More particularly, in FIG. 5A, the stabilizer flows of the ZX calculus graph may be evaluated to confirm the X®nand Z®" stabilizers are being measured, and that the encoded logical qubits are being propagated. The defect diagrams are not to scale; the connections between pieces are stretched out to show the topology. The process occupies 2 x n logical qubit patches for 4<7 rounds. The patch rotations are alternating between left handed and right handed, to satisfy the boundary hugging constraint. The defect diagrams with highlighted observables show how the yoke stabilizers are measured and prepared.

[0059] FIG. 5B shows pipe diagrams for a full syndrome cycle of a nested QEC code, according to various embodiments. Pipe diagram 570 (e.g., the top diagram) shows a full syndrome cycle for a ID yoked surface code. Pipe diagram 580 (e.g., the bottom diagram) shows a full syndrome cycle for a 2D yoked surface code.

[0060] To construct the full syndrome extraction circuit, the circuit may be built up from pieces. In FIG. 5 A the A- and Z-type row stabilizers are measured by combining the parity measurements with patch rotations, along with the corresponding ZX diagram. As shown in FIG.5B, these puzzle pieces may be fit together to form the full syndrome cycle circuits. Note that there may be extra workspace required to measure these checks. For example, for ID yoked surface codes, a single workspace row may be used to sequentially measure each ID yoked surface code block, analogous to a measure qubit migrating across the code blocks toextract stabilizer measurements. Having a single extra row attend to each block reduces the overall footprint, but again lengthens the outer code’s syndrome extraction cycle. Striking a balance between these effects is important, as we must include the overhead of this workspace in a yoked surface code’s overall footprint.Complementary Gap Distributions

[0061] This section discusses distributions of the complementary gap of surface codes and how such distributions and the coarse graining of lattice surgeries can be employed to estimate the performance of a yoked surface code. From the perspective of the outer code, the syndrome of the inner code gives valuable information about the likelihood of an error in a particular location. Minimum-weight perfect matching can be used to evaluate the confidence of the decoder’s decision and pass this information to the outer code to identify likely culprit errors. Operationally, given a block of surface code memory with boundaries, a detector connecting to all the boundary edges on one side of the error graph can be formed. This augmentation maintains the graph structure and turning this boundary detector on / off forces the decoder to match / not match to the corresponding boundary. The resulting two matchings are the decoder’s best hypotheses for the set of errors explaining these two topologically distinct classes of errors. The log-likelihood ratio of these two hypotheses may be referred to as the complementary gap - the log-ratio of the probabilities of the minimum- weight matching and the complementary matching. A complementary gap close to 0 indicates that the decoder is not confident in its decision, while a high complementary gap indicates the decoder is highly confident. As shown in FIG. 6, this information may be critical to the outer code - and may be used to decode the outer code.

[0062] FIG. 6 demonstrates decoding the outer code abstracted from complementary gaps, according to various embodiments. More particularly, FIG. 6 shows an error graph 600. The error graph 600 is an A-type error graph of 2D yoked surface codes in a phenomenological error model on an x array. The error graph 600 is a complete bipartite graph Ku extended into time. The two sides of the bipartition correspond to row and column detectors. Highlighted in broken (e.g., hashed) line is a single edge and its endpoint detectors, with other time-like edges removed for clarity. In the middle of the error graph 600 is a slice of the underlying surface code error graph, with the two yoke detectors highlighted in ahashed pattern at the boundaries. Dark-shaded (e.g., filled in) nodes are detectors and light- shaded (e.g., not filled-in) nodes are detection events. Dark edges correspond to a minimumweight matching other edges correspond to the complementary matching, while lighter edges are common to both. Assuming all edges have equal probability p, the log-likelihood ratio of the two matchings is 2 log. The outer error graph will then be formed from XORing the yokes triggered by the minimum weight error configuration. Assuming all edges have equal 1— probability p, the log-likelihood ratio of the two matchings is 2 ■ log—^~. The outer error graph will then be formed from XORing the yokes triggered by the minimum weight error configuration. Assuming all edges have equal probability p, the cost of flipping these yokes is given by the log-likelihood ratio of the two matchings, in this case 2 ■ which isassigned as the weight of the outer edge.

[0063] These distributions of the complementary gap of surface codes may be important to the outer code and may be used to decode the outer code. To decode the outer code, minimum-weight perfect matching may be used. These complementary gaps may be passed to assign instance specific edge weights to the outer error graph, as shown in FIG. 6.

[0064] There are several ways to generalize this procedure to a correlated matching decoder. In this work, a two-pass correlated matching decoder may be employed. To compute the complementary gap in a Z-basis memory experiment, the X-type error graph 600 may be used to reweight the Z-type error graph, and then compute the complementary gap for this reweighted Z-type error graph.

[0065] These gap distributions may take a smooth, simple form after an initially noisy start at low distance, likely due to finite-size effects. The gaps may be observed to be well- calibrated - the likelihood of success predicted by the gap is close to the true empirical likelihood of success - after modifying the gap by 0.9x. That is, the decoder’s confidence may be rescaled to account for its slight over-confidence in its high-confidence predictions.Furthermore, this calibrated output may degrade slowly as the number of rounds is scaled to higher rounds. The distribution on complementary gaps over mn rounds may be well- approximated as the minimum of m samples from the distribution on gaps over n rounds. Taken together, these approximations may allow for the ability to extrapolate the probabilityof observing a particular gap and the resulting likelihood of failure from a distribution of gaps on relatively few (e.g. 1 Or / ) rounds.Hot and Cold Storage Architectures

[0066] Above the abstraction level of lattice surgery is the notion of a storage architecture. The embodiments contemplate two types of storage architectures: “cold storage” and “hot storage.” Some embodiments employ cold storage, other embodiments employ hot storage, while still other embodiments employ a combination of hot and cold storage architectures.

[0067] FIG. 7 shows layouts for both cold and hot storage architectures for lattice surgery, according to various embodiments. More particularly, FIG. 7 shows layouts for hot and cold storage, assuming the yoke is checked every 1000 rounds. The top two cold storage and hot storage 2D “footprint diagrams” show how space is allocated for the two different storage architectures. The bottom two cold storage and hot storage 3D “defect diagrams” show operations occurring over time for the two different storage architectures. In the 2D footprint diagrams, each row is a separate group of yoked qubits. The white-filled squares correspond to usable storage while other squares correspond to various overheads. In cold storage, one row of workspace is shared between the various rows of storage to measure the yokes. In hot storage, the yokes are measured using the access hallways that would have been present anyways.

[0068] In “cold storage”, qubits are stored in a form where they are as dense as possible but can’t be immediately operated upon. Operating on a qubit in cold storage requires first getting it out of storage. Concretely, this means the qubits don’t all have access hallways next to them. It still may be necessary for some workspace to be present, because it’s necessary to periodically check the yokes, but this workspace can be shared between many groups of qubits. As noted above, FIG. 7 shows the space layout, and spacetime layout, that may be used for estimates of the size of cold storage architectures.

[0069] Storage can be “even hotter” than is considered herein, by having each surface code patch expose two boundaries. Note that it may be assumed that qubits in hot storage are rotated on an as-needed basis, when lattice surgery needs to access the boundary that isn’t exposed. The need to do these rotations is a key consideration when laying out an algorithm.

[0070] Yoked qubits in hot storage can be operated on by lattice surgery while they’re encoded. Each encoded qubit’s observable is spread over two surface code patches, but lattice surgery can stitch to two patches as easily as one. In context the cost is actually identical, because the entrance to the access hallway is occupied regardless of how many patches are touched. There are two main caveats on the ability to do lattice surgery on yoked qubits. First, the lattice surgery may not always satisfy the boundary hugging constraint. Second, because the yoke is only checked periodically, it’s not known whether the lattice surgery was affected by a correction until the next yoke check finishes. If the lattice surgery was part of performing a non-Clifford gate, the non-Clifford gate will be blocked from finishing until after the yoke is checked again.Example Methods

[0071] FIG. 8 depicts a flow chart diagram of an example method 800 for operating a fault-tolerant quantum computing system, according to example embodiments of the present disclosure. The quantum computing system includes a set of physical qubits. At block 802, the quantum computing system may execute a quantum algorithm. The quantum algorithm may redundantly encode quantum information in each physical qubit of the set of qubits such that each physical qubit of the set of physical qubits redundantly encodes the quantum information. When executing the quantum algorithm, the set of physical qubits may be employed to form a set of logical qubits. Each logical qubit of the set of logical qubits may be formed via a separate subset of the set of physical qubits such that each logical qubit of the set of logical qubits redundantly encodes the quantum information. Each separate subset of physical qubits may be disjoint from each other separate subset of physical qubits. Although FIG. 8 depicts steps performed in a particular order for purposes of illustration and discussion, the methods of the present disclosure are not limited to the particularly illustrated order or arrangement. The various steps of the method 800 can be omitted, rearranged, combined, and / or adapted in various ways without deviating from the scope of the present disclosure

[0072] At block 804, and while executing the quantum algorithm, the quantum computing system may perform a first quantum error correction (QEC) code on each logical qubit of the set of logical qubits. The first QEC code may detect a first set of parity conditions across the separate subset of physical qubits forming the logical qubit.

[0073] At block 806, and while executing the quantum algorithm, the quantum computing system may perform a second QEC code on the set of logical qubits. The second QEC code detects a second set of parity conditions across the set of logical qubits.

[0074] At block 808, and while executing the quantum algorithm, the quantum computing system may perform lattice surgery on at least a portion of the set of qubits based on at least one of the first set of parity conditions across the separate subsets of physical qubits or the second set of parity conditions across the set of logical qubits. From block 808, method 800 may return to block 804 as long as the quantum algorithm is being executed.

[0075] In some embodiments, the first QEC code is a surface code. The second QEC code may be a ID parity check code. In other embodiments, the second QEC code may be a 2D parity check code.

[0076] The set of physical qubits may be arranged in a first two-dimensional (2D) grid of physical qubits. Each separate subset of physical qubits that forms a logical qubit of the set of logical qubits may be a contiguous 2D patch of physical qubits in the first 2D grid. The set of logical qubits may be arranged in a second 2D grid of logical qubits. The second 2D grid of logical qubits may be superimposed on the first 2D grid of physical qubits. The second 2D grid of logical qubits may be coarser than the first 2D grid of physical qubits.

[0077] In some embodiments, the second set of parity conditions of the second QEC code includes one or more parity checks for each row of the second 2D grid of logical qubits. In such embodiments, the one or more parity checks for each row of the second 2D grid of logical qubits may include one or more Z-basis parity checks. The second QEC code may include one or more Z-type stabilizers that measures the one or more Z-basis parity checks for each row of the second 2D grid of logical qubits. The one or more Z-type stabilizers may yoke the logical qubits included in a row of the 2D grid of logical qubits. The one or more parity checks for each row of the second 2D grid of logical qubits may include one or more X- basis parity checks. The second QEC code may include one or more X-type stabilizers that measures the one or more X-basis parity checks for each row of the second 2D grid of logical qubits. In such embodiments, the one or more X-type stabilizers yokes the logical qubits included in a row of the 2D grid of logical qubits.

[0078] In various embodiments, the second set of parity conditions of the second QEC code includes one or more parity checks for each column of the second 2D grid of logicalqubits. In such embodiments, the one or more parity checks for each column of the second 2D grid of logical qubits may include one or more Z-basis parity checks. The second QEC code may include one or more Z-type stabilizers that measure the one or more Z-basis parity checks for each column of the second 2D grid of logical qubits. The one or more Z-type stabilizers may yoke the logical qubits included in a column of the 2D grid of logical qubits. The one or more parity checks for each column of the second 2D grid of logical qubits may include one or more X-basis parity checks. The second QEC code may include one or more X-type stabilizers that measure the one or more X-basis parity checks for each column of the second 2D grid of logical qubits. In such embodiments, the one or more X-type stabilizers yokes the logical qubits included in a column of the 2D grid of logical qubits.

[0079] In some embodiments, performing lattice surgery may include employing a hot storage architecture operating on the portion of the set of qubits. In other embodiments, performing lattice surgery may include employing a hot storage architecture operating on the portion of the set of qubits.

[0080] Implementations of the digital, classical, and / or quantum subject matter and the digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly-implemented digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computing systems” may include, but is not limited to, quantum computer s / computi ng systems, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0081] Implementations of the digital and / or quantum subject matter described in this specification can be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits / qubit structures, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on anartificially-generated propagated signal that is capable of encoding digital and / or quantum information (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode digital and / or quantum information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

[0082] The terms quantum information and quantum data refer to information or data that is carried by, held, or stored in quantum systems, where the smallest non-trivial system is a qubit, i.e., a system that defines the unit of quantum information. It is understood that the term “qubit” encompasses all quantum systems that may be suitably approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states (e.g., qubits) are possible.

[0083] The term “data processing apparatus” refers to digital and / or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and / or quantum data, including by way of example a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, or multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), or an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus that is designed to simulate or produce information about a specific quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The apparatus can optionally include, in addition to hardware, code that creates an execution environment for digital and / or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0084] A digital or classical computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled orinterpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or can be written in a quantum programming language, e.g., QCL, Quipper, Cirq, etc..

[0085] A digital and / or quantum computer program may, but need not, correspond to a fde in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code. A digital and / or quantum computer program can be deployed to be executed on one digital or one quantum computer or on multiple digital and / or quantum computers that are located at one site or distributed across multiple sites and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that may transmit quantum data using quantum systems, e.g. qubits. Generally, a digital data communication network cannot transmit quantum data, however a quantum data communication network may transmit both quantum data and digital data.

[0086] The processes and logic flows described in this specification can be performed by one or more programmable digital and / or quantum computers, operating with one or more digital and / or quantum processors, as appropriate, executing one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or quantum simulators and one or more programmed digital and / or quantum computers.

[0087] For a system of one or more digital and / or quantum computers or processors to be “configured to” or “operable to” perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that inoperation cause the system to perform the operations or actions. For one or more digital and / or quantum computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by digital and / or quantum data processing apparatus, cause the apparatus to perform the operations or actions. A quantum computer may receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

[0088] Digital and / or quantum computers suitable for the execution of a digital and / or quantum computer program can be based on general or special purpose digital and / or quantum microprocessors or both, or any other kind of central digital and / or quantum processing unit. Generally, a central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory, or a random access memory, or quantum systems suitable for transmitting quantum data, e.g. photons, or combinations thereof.

[0089] Some example elements of a digital and / or quantum computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry or quantum simulators. Generally, a digital and / or quantum computer will also include, or be operatively coupled to receive digital and / or quantum data from or transfer digital and / or quantum data to, or both, one or more mass storage devices for storing digital and / or quantum data, e.g., magnetic, magneto-optical disks, or optical disks, or quantum systems suitable for storing quantum information. However, a digital and / or quantum computer need not have such devices.

[0090] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks; and quantum systems, e.g., trapped atoms or electrons. It is understood that quantum memories are devices that can store quantum data fora long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

[0091] Control of the various systems described in this specification, or portions of them, can be implemented in a digital and / or quantum computer program product that includes instructions that are stored on one or more tangible, non-transitory machine-readable storage media, and that are executable on one or more digital and / or quantum processing devices. The systems described in this specification, or portions of them, can each be implemented as an apparatus, method, or electronic system that may include one or more digital and / or quantum processing devices and memory to store executable instructions to perform the operations described in this specification.

[0092] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

[0093] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0094] Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

WHAT IS CLAIMED IS:

1. A method for operating a quantum computing system that includes a set of physical qubits, the method comprising: executing a quantum algorithm that redundantly encodes quantum information in each physical qubit of the set of qubits such that each physical qubit of the set of physical qubits redundantly encodes the quantum information, wherein when executing the quantum algorithm, the set of physical qubits is employed to form a set of logical qubits, each logical qubit of the set of logical qubits being formed via a separate subset of the set of physical qubits such that each logical qubit of the set of logical qubits redundantly encodes the quantum information and each separate subset of physical qubits is disjoint from each other separate subset of physical qubits; while executing the quantum algorithm, performing a first quantum error correction (QEC) code on each logical qubit of the set of logical qubits, wherein the first QEC code detects a first set of parity conditions across the separate subset of physical qubits forming the logical qubit; and while executing the quantum algorithm, performing a second QEC code on the set of logical qubits, wherein the second QEC code detects a second set of parity conditions across the set of logical qubits.

2. The method of claim 1, wherein the first QEC code is a surface code.

3. The method of claim 2, wherein the second QEC code is a ID parity check code.

4. The method of claim 2, wherein the second QEC code is a 2D parity check code5. The method of claim 1, wherein the set of physical qubits is arranged in a first two- dimensional (2D) grid of physical qubits, each separate subset of physical qubits that forms a logical qubit of the set of logical qubits is a contiguous 2D patch of physical qubits in the first 2D grid, and the set of logical qubits is arranged in a second 2D grid of logical qubits that is superimposed on the first 2D grid of physical, and wherein the second 2D grid of logical qubits is coarser than the first 2D grid of physical qubits.

6. The method of claim 5, wherein the second set of parity conditions of the second QEC code includes one or more parity checks for each row of the second 2D grid of logical qubits.

7. The method of claim 6, wherein the one or more parity checks for each row of the second 2D grid of logical qubits includes one or more Z-basis parity checks and the second QEC code includes one or more Z-type stabilizers that measure the one or more Z-basis parity checks for each row of the second 2D grid of logical qubits.

8. The method of claim 7, wherein the one or more Z-type stabilizers yokes the logical qubits included in a row of the 2D grid of logical qubits.

9. The method of claim 6, wherein the one or more parity checks for each row of the second 2D grid of logical qubits includes one or more X-basis parity checks and the second QEC code includes one or more X-type stabilizers that measure the one or more X-basis parity checks for each row of the second 2D grid of logical qubits.

10. The method of claim 9, wherein the one or more X-type stabilizers yokes the logical qubits included in a row of the 2D grid of logical qubits.

11. The method of claim 5, wherein the second set of parity conditions of the second QEC code includes one or more parity checks for each column of the second 2D grid of logical qubits.

12. The method of claim 11, wherein the one or more parity checks for each column of the second 2D grid of logical qubits includes one or more Z-basis parity checks and the second QEC code includes one or more Z-type stabilizers that measure the one or more Z-basis parity checks for each column of the second 2D grid of logical qubits.

13. The method of claim 12, wherein the one or more Z-type stabilizers yokes the logical qubits included in a column of the 2D grid of logical qubits.

14. The method of claim 11, wherein the one or more parity checks for each column of the second 2D grid of logical qubits includes one or more X-basis parity checks and the second QEC code includes one or more X-type stabilizers that measure the one or more X-basis parity checks for each column of the second 2D grid of logical qubits.

15. The method of claim 14, wherein the one or more X-type stabilizers yokes the logical qubits included in a column of the 2D grid of logical qubits.

16. The method of claim 1, further comprising: while executing the quantum algorithm, performing lattice surgery on at least a portion of the set of qubits based on at least one of the first set of parity conditions across the separate subsets of physical qubits or the second set of parity conditions across the set of logical qubit.

17. The method of claim 16, wherein performing the lattice surgery includes employing a hot storage architecture operating on the portion of the set of qubits.

18. The method of claim 16, wherein performing the lattice surgery includes employing a cold storage architecture operating on the portion of the set of qubits19. A quantum computing system, comprising: a quantum processor that includes a set of qubits; one or more memory devices, the one or more memory devices storing computer- readable instructions that when executed by the one or more processors cause the one or more processors to perform operations for characterizing the QLC, the operations comprising: executing a quantum algorithm that redundantly encodes quantum information in each physical qubit of the set of qubits such that each physical qubit of the set of physical qubits redundantly encodes the quantum information, wherein when executing the quantum algorithm, the set of physical qubits is employed to form a set of logical qubits, each logical qubit of the set of logical qubits being formed via a separate subset of the set of physical qubits such that each logical qubit of the set of logical qubits redundantly encodes the quantuminformation and each separate subset of physical qubits is disjoint from each other separate subset of physical qubits; while executing the quantum algorithm, performing a first quantum error correction (QEC) code on each logical qubit of the set of logical qubits, wherein the first QEC code detects a first set of parity conditions across the separate subset of physical qubits forming the logical qubit; and while executing the quantum algorithm, performing a second QEC code on the set of logical qubits, wherein the second QEC code detects a second set of parity conditions across the set of logical qubits.

20. The quantum computing system of claim 19, wherein the first QEC code is a surface code and the second QEC code is a ID or a 2D parity check code.

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