Machine learning enabled signal processor

Abstract

A machine-learning-enabled signal processor includes a signal routing unit that receives a first analog input signal and produces a plurality of analog channels, each based at least in part on the first analog input signal; an array of analog-to-digital converters that produces a plurality of digital features, each based at least in part on a respective channel from the plurality of analog channels; a machine-learning unit, including a machine-learning algorithm, that produces an instruction set, based at least in part on the plurality of digital features; an array of digital-to-analog converters, that produces a plurality of analog features, each based at least in part on a respective instruction from the instruction set; and a combining unit that produces a first analog output signal, based at least in part on the plurality of analog features.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to US Provisional Patent Application Serial No. 63 / 547,927, filed November 9, 2023, entitled “Machine Learning Enabled Signal Processor.” The entire contents of that application are incorporated by reference.

[0003] BACKGROUND

[0004] Technical Field

[0005] This disclosure relates generally to the field of digital signal processing (DSP), and more specifically to methods and systems for processing analog signals through machine-learning techniques.

[0006] Related Art

[0007] Digital signal processing (DSP) of analog signals plays a crucial role in applications where analog data needs to be processed, analyzed, or transformed into digital information for further manipulation or control. This process often involves first converting the analog signal to a digital form using an analog-to-digital converter (ADC), followed by processing the digital data using various DSP techniques, and then converting the processed data back to an analog signal via a digital-to-analog converter (DAC) for output or control purposes.

[0008] Traditional DSP techniques applied to analog signals are often focused on tasks such as filtering, amplification, modulation, noise reduction, and signal compression. Analog signal processing systems often suffer from limitations related to bandwidth, distortion, and noise interference. To address these issues, digital techniques have been developed to enhance signal quality, improve noise immunity, and enable more sophisticated signal manipulation.

[0009] For example, analog signal processing systems typically rely on passive components like resistors and capacitors for filtering and amplification. However, these systems may struggle with precision, especially in the face of temperature variations or component aging. Digital signal processing provides a more stable and precise means of signal manipulation, offering advantages such as improved accuracy and the ability to implement more complex algorithms that would be difficult or impossible with analog circuits.

[0010] Despite these benefits, the digital signal processing of analog signals is often limited by the quality and speed of the ADC and DAC components. Analog-to-digital conversion introduces quantization errors, and digital-to-analog conversion can result in artifacts such as jitter or distortion, particularly in systems requiring high fidelity. Additionally, the power consumption of high-speed ADCs and DACs can be a limiting factor in low-power or battery-operated devices.

[0011] Furthermore, DSP algorithms that are traditionally designed for discrete-time signals may require adaptation to handle continuous-time analog inputs. This includes designing systems that account for the non-idealities in the conversion process, such as aliasing and signal degradation, which can introduce errors during both the sampling and reconstruction stages.

[0012] Current DSP-based systems for analog signal processing continue to face challenges related to accuracy, efficiency, and performance, particularly in high-speed or high-resolution applications.

[0013] BRIEF SUMMARY

[0014] A machine-learning enabled signal processor is an apparatus that can perform signal processing to an analog signal. The system comprises a signal routing unit, an array of digital feature generators, a machine-learning unit, an array of analog feature generators, and a combining unit. The signal routing unit receives an analog input signal and produces a plurality of analog channels, each based at least in part on the analog input signal. The array of digital feature generators receives the plurality of analog channels, and each digital feature generator produces a digital feature based on its respective analog channel. The machine-learning unit receives the plurality of digital features and produces an instruction set. The array of analog feature generators receives the instruction set, and each analog feature generator produces an analog feature based on a respective instruction from the instruction set. The combining unit receives the analog features and produces an analog output signal based at least in part on the analog features. The analog output signal represents a signal processing technique applied to the analog input signal. The advantage of this approach comes from the ability of machine-learning to automatically translate between complex data formats. This ability allows for the elements of the system to be built of parts that are easy to manufacture, but have complex or nonlinear characteristics.

[0015] The machine-learning unit includes a machine-learning algorithm. The machine-learning algorithm, having been previously calibrated, operates in inference mode, in which it receives a plurality of digital features. The machine-learning enabled signal processor can also be configured to accept multiple digital input signals, generate multiple digital output signals, receive multiple analog input signals, and / or generate multiple analog output signals. The device can also include a range of sensors to monitor the environment and behavior of the device, which can be fed as additional inputs into the device’s machine-learning unit. The device can also incorporate onboard calibration and / or real-time dimensionality reduction units to optimize the performance of the device after manufacturing.

[0016] BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0017] FIG. 1 illustrates an example of a standard machine-learning enabled signal processor, according to an implementation of the present disclosure.

[0018] FIG. 2 illustrates the machine-learning unit of a machine-learning enabled signal processor containing a neural network, according to an implementation of the present disclosure.

[0019] FIG. 3 illustrates a machine-learning unit configured in a three-stage configuration, in which an ADC machine-learning algorithm produces a digital signal from digital features, a user-defined process produces a modified digital signal based at least in part on the digital signal, and finally a DAC machine-learning algorithm produces an instruction set based at least in part on the modified digital signal, according to an implementation of the present disclosure.

[0020] FIG. 4 illustrates a machine-learning unit configured to produce an instruction set based at least in part on a digital input signal, according to an implementation of the present disclosure.

[0021] FIG. 5 illustrates a machine-learning unit configured to produce an instruction set based at least in part on an environmental sensor input, according to an implementation of the present disclosure.

[0022] FIG. 6 illustrates a machine-learning unit configured to produce a digital output signal based at least in part on digital features, according to an implementation of the present disclosure.

[0023] FIG. 7 illustrates a signal routing unit configured to produce a plurality of analog channels, based at least in part on a second analog input signal, according to an implementation of the present disclosure. FIG. 8 illustrates a combining unit configured to produce a second analog output signal, based at least in part on the plurality of analog features, according to an implementation of the present disclosure.

[0024] FIG. 9 illustrates a machine-learning enabled signal processor, wherein the digital features produced by the ADC array are stored in a storage system, and the digital features are retrieved later to be applied to the machine-learning unit, allowing for asynchronous operation, according to an implementation of the present disclosure.

[0025] FIG. 10 illustrates a machine-learning enabled signal processor, wherein the instruction set produced by the machine-learning unit is stored in a storage system, and the instruction set is retrieved later to be applied to the DAC array, allowing for asynchronous operation, according to an implementation of the present disclosure.

[0026] FIG. 11 illustrates a flow-chart outlining the operation of a machine-learning enabled signal processor, according to an implementation of the present disclosure.

[0027] FIG. 12 illustrates a flow-chart outlining the process of producing an instruction set from a plurality of digital features using a machine-learning unit in the three-stage configuration, according to an implementation of the present disclosure.

[0028] FIG. 13 illustrates a flow-chart outlining the process of producing an instruction set from a plurality of digital features using a machine-learning unit in the two-stage configuration, according to an implementation of the present disclosure.

[0029] FIG. 14 illustrates a flow-chart outlining the process of calibrating a machine-learning algorithm to convert a plurality of digital features into an instruction set for a machine-learning enabled signal processor, according to an implementation of the present disclosure.

[0030] FIG. 15 illustrates a flow-chart outlining the subprocess of producing a second machine-learning algorithm that receives a plurality of digital features and produces an instruction set, based at least in part on the digital input signal, according to an implementation of the present disclosure. FIG. 16 illustrates a flow-chart outlining the subprocess of producing a first dataset of training examples, each example comprising a plurality of digital features and a digital signal, to train an ADC machine-learning algorithm, according to an implementation of the present disclosure.

[0031] FIG. 17 illustrates a flow-chart outlining the subprocess of producing a first DAC machine-learning algorithm that receives a digital input signal and produces an instruction set, based at least in part on the digital input signal, according to an implementation of the present disclosure.

[0032] FIG. 18 illustrates an example of the standard operation, in which a machine-learning enabled signal processor converts an analog WiFi signal into an analog cellular signal, according to an implementation of the present disclosure.

[0033] FIG. 19 illustrates a second example of the standard operation, in which a machine-learning enabled signal processor removes noise affecting an analog signal, according to an implementation of the present disclosure.

[0034] FIG. 20 illustrates a third example of the standard operation, in which a machine-learning enabled signal processor converts an analog sensor signal from a robotic system into a motor control signal, according to an implementation of the present disclosure.

[0035] FIG. 21 illustrates a fourth example of the standard operation, in which a machine-learning enabled signal processor converts analog audio of spoken English into analog audio of spoken Greek, according to an implementation of the present disclosure.

[0036] FIG. 22 illustrates an example of operation with a digital input signal, in which a machine-learning enabled signal processor converts analog audio of spoken English into a language selected by a language option digital input. In this example the language option is French, so the output analog signal is analog audio of the spoken English translated into analog audio of spoken French, according to an implementation of the present disclosure.

[0037] FIG. 23 illustrates a second example of operation with a digital input signal, in which a machine-learning enabled signal processor receives an analog audio signal containing instrumental music and a digital text file with lyrics. The output analog signal is an analog audio signal combining the instrumental music with the lyrics from the text file, according to an implementation of the present disclosure.

[0038] FIG. 24 illustrates an example of operating with a digital output signal, in which an analog audio signal of speech in an unknown language is fed into a machine-learning enabled signal processor. The output digital signal is the name of the language used in the analog audio signal input, and the analog output signal is that speech translated into analog audio of spoken Greek, according to an implementation of the present disclosure.

[0039] FIG. 25 illustrates a second example of operating with a digital output signal, in which an analog audio signal of spoken English is fed into a machine-learning enabled signal processor. The output digital signal is a digital transcript of the spoken English translated into Greek, and the analog output signal is an analog audio signal of that speech translated into analog audio of spoken Greek, according to an implementation of the present disclosure.

[0040] FIG. 26 illustrates an example of receiving multiple analog input signals, in which a machine-learning enabled signal processor merges two analog audio signals, one containing spoken English and the other containing spoken French, into a single analog audio signal including the speech of both audio input signals translated into analog audio of spoken Greek, according to an implementation of the present disclosure.

[0041] FIG. 27 illustrates an example of producing multiple analog output signals, in which a machine-learning enabled signal processor converts an analog audio signal of spoken English into an analog audio signal of the spoken English translated into analog audio of spoken Greek and a second audio signal of the spoken English translated into analog audio of spoken French, according to an implementation of the present disclosure.

[0042] FIG. 28A Illustrates the production of an ADC training dataset for calibrating an ADC machine-learning model that produces a digital signal based at least in part on a plurality of digital features.

[0043] FIG. 28B Illustrates the production of a DAC machine-learning algorithm that produces an instruction set based at least in part on a digital input signal. FIG. 28C Illustrates the production of the training data needed to calibrate a one-stage Signal Processing machine-learning algorithm that produces an instruction set based at least in part on a plurality of digital features.

[0044] FIG. 28D Illustrates how the data needed to calibrate the one-stage Signal Processing machine-learning algorithm is organized, and how the Signal Processing algorithm is produced

[0045] 1. DEVICE

[0046] There remains a need for improved DSP techniques that better address conversion errors, reduce power consumption, and provide more precise, real-time processing of analog signals without compromising signal integrity.

[0047] The disclosure pertains to the conversion, manipulation, and reconstruction of analog signals using machine-learning processing techniques, with applications across a wide range of fields including telecommunications, audio and video systems, medical equipment, and control systems. In particular, the disclosure can address challenges associated with the conversion of continuous-time analog signals into digital form and the subsequent reconstruction of those signals back to analog outputs, with improved accuracy, efficiency, and reduced errors in high-speed and high-resolution applications.

[0048] In one implementation, a machine-learning-enabled signal processor is a system that applies an arbitrary signal processing technique to an analog signal and outputs the result. A machine-learning enabled signal processor comprises a signal routing unit, an array of analog-to-digital converters (“ADCs”), a machine-learning unit, an array of digital-to-analog converters (“DACs”), and a combining unit.

[0049] Before operation, a machine-learning algorithm is calibrated to operate the machine-learning unit. The machine-learning algorithm maps digital features to instruction sets. The algorithm is calibrated using a method described subsequently.

[0050] In operation, the machine-learning-enabled signal processor receives an analog signal into its signal routing unit. The signal routing unit breaks up the signal into a collection of analog channels and passes those channels to the ADC array. The ADC array converts the analog channels into digital features in a high-dimensional format, and passes those digital features to the machine-learning unit. The machine-learning unit applies a process to those digital features that is equivalent to applying an arbitrary signal processing technique to the digital signal represented by the analog input signal, and maps the result of its process to a high-dimensional instruction set. An instruction set comprises instructions, which are digital values. Unlike a mathematical set, here the term “set” is used to mean an ordered collection that permits multiple instances of the same value to exist within the set. Here, the term “ordered” means that the order of elements matters: {0, 1} #= {1, 0}. The digital values can be Booleans, integers, floating point numbers, complex numbers with real and imaginary components, pairs, lists or any other kind of information that can be represented digitally. An instruction can be a composite data structure, for example a pair of pairs of integers. The implementation of the DAC that receives the instruction determines which types of information are suitable as instruction values. The overall structure of the instruction set and the validity of information types for each value are together the format of the instruction set. The configuration of the DAC array 140 determines the format of the instruction set.

[0051] For example, an individual Monte Carlo DAC, which is configured to generate a pulse with a fixed amplitude, duration, and timing offset, can use a single Boolean bit instruction to determine whether it triggers on a given clock strike. As another example, a multiplexer unit DAC, which generates an analog feature that it frequency-shifts into a predetermined range, can use an integer or a floating point number instruction to set the variable amplitude gain on its feature. As yet another example, a spectral generator DAC, which generates a sine wave and a cosine wave at a frequency that is set by a local oscillator, can use a pair of integers to set the variable gain on the sine and cosine waves. As a further example, a nested DAC comprising multiple Monte Carlo DACs configured to produce the analog feature for a multiplexer unit can use an instruction including a pair in which the first half is an ordered collection of bits and the second half is an integer.

[0052] The machine-learning unit passes the instruction set to the DAC array. The DACs within the DAC array use respective instructions from the instruction set to produce a plurality of analog features, and pass these analog features to the combining unit. The combining unit produces an analog output signal based at least in part on these analog features. The analog output signal is then transmitted as the overall output of the device.

[0053] The machine-learning enabled signal processor approaches the task of transforming an analog signal in a more flexible way than a traditional digital signal processor does. At heart, the machine-learning enabled signal processor is performing three operations: capturing information into digital values, applying some process to those digital values, and then generating an analog signal representing the result of applying that process. However, by relying on a machine-learning enabled ADC to capture information and a machine-learning enabled DAC to generate the analog output signal, it allows the machine-learning unit to operate on abstracted representations of the signals. Specifically, the machine-learning enabled ADC can capture the input signal’s information in a high-dimensional set of digital features that is easier to capture than samples in the standard Shannon-Nyquist format, and the machine-learning enabled DAC can generate a plurality of analog features that are each easier to generate than the traditional digital-to-analog method of producing the final analog output with a single digital-to-analog converter. As an example of digital features being easier to capture than the normal samples, the machine-learning enabled ADC can capture multiple bandlimited representations of the input signal, each of which is captured at a slower rate than that to capture the full signal. As an example of analog features that are easier to generate than the normal analog output, the machine-learning DAC can produce multiple multiplexed analog features, each covering only a different small portion of the final analog output’s bandwidth. Those analog features can be added together, resulting in the final analog output. Since each feature covers only a small portion of the total signal bandwidth, they are each easier to produce than directly creating the complete analog signal with a single digital-to-analog converter.

[0054] These representations are highly complex and very difficult to analytically process. Defining and carrying out analytical operations on these complex abstract representations could not realistically be performed by human engineers. However, machine-learning algorithms are well suited to interpreting complex, high-dimensional data. Instead of operating functions analytically, some algorithms approximate these functions through empirical reinforcement. This means that, for some algorithms, the results can approximate the analytical computations to an arbitrary degree of accuracy and not require as many computational resources.

[0055] The machine-learning enabled signal processor allows input signals to be captured with arbitrarily complex representations, allows arbitrarily complex functions to operate on those representations, and allows the analog output to be produced with arbitrarily complex components. By disconnecting the information and operations from the limitations of what physical analog circuits can be easily and reliably fabricated, the machine-learning enabled signal processor moves much of the complexity of analog signal processing into the digital realm.

[0056] This flexibility brings many of the advantages of digital logic to the analog realm. This ability allows the basic components in the signal routing unit, ADC array, DAC array, and combining unit to be built from parts that are easier to manufacture and / or have improved performance characteristics, but complex or nonlinear behavior. The device can include a range of sensors to monitor the environment and behavior of the device, which can be fed as additional input into the device’s machine-learning unit. The device’s machine-learning algorithm can be configured to accept multiple analog input signals and / or multiple digital input signals, as well as produce multiple analog output signals and / or multiple digital output signals. The device can incorporate a real-time dimensionality reduction unit to optimize the performance of the device after manufacturing, and can incorporate process failure units to identify faulty system performance.

[0057] 1.1 Standard Configuration

[0058] As shown in FIG. 1 , a machine-learning-enabled signal processor 100 comprises the following components: a signal routing unit 110, an ADC array 120, a machine-learning unit 130, a DAC array 140, and a combining unit 150. The signal routing unit 110 receives a first analog input signal 105. The signal routing unit 110 produces a plurality of analog channels 115, at least in part based on the first analog input signal 105. The ADC array 120 produces a plurality of digital features 125, each based at least in part on a respective analog channel in the plurality of analog channels 115. The machine-learning unit 130 produces, with a machine-learning algorithm, an instruction set 135, based at least in part on a predefined transform process and the plurality of digital features 125. The DAC array 140 produces a plurality of analog features 145, each based at least in part on a respective instruction from the instruction set 135. The combining unit 150 produces a first analog output signal 155, based at least in part on the plurality of analog features 145. The first analog output signal 155 represents the predefined transform process applied to the first analog input signal 105.

[0059] 1.2 Analog Components

[0060] 1.2.1 Signal Routing Unit

[0061] The signal routing unit 110 produces a plurality of analog channels 115 based at least in part on a first analog input signal 105. A variation of the signal routing unit 110 produces the analog channels 115 based at least in part on a second analog input signal 710. In the simplest configuration, the plurality of analog channels 115 are each direct copies of the first analog input signal 105. This can be built using simple wires to directly connect the analog signal 105 to each ADC in the ADC array 120, or, to maintain impedance of the signal routing unit 110, the signal routing unit 110 can comprise multiple buffer amplifiers that duplicate the analog input signal 105 for each respective analog channel. The signal routing unit 110 can also apply signal processing to the analog input signal 105 using analog circuitry. An example is producing each respective analog channel using a bandpass filter. The cutoff frequencies of each bandpass filter can be adjusted, such that each analog channel covers a different portion of the analog input’s 105 frequency range. If the analog input signal 105 is wideband (such that the entire frequency spectrum contains information), then the signal routing unit 110 implementing bandpasses can be configured to have the combined activity of the analog channels 115 cover the entire frequency range of the analog inputs channel 105. If only select portions of the analog input signal’s 105 frequency spectrum contains information, then the analog channels can produce analog channels that only cover the predetermined frequency ranges that are known to contain information. The signal routing unit 110 can also be nested, such that a respective analog channel can be further processed by the signal routing unit 110, resulting in another analog channel. An example is a bandpass analog channel being one of the analog channels 115, and that channel being further processed by a second bandpass filter, resulting in a second analog channel.

[0062] 1.2.2 Analog-to-Digital Converter Array

[0063] The ADC array 120 comprises multiple analog-to-digital converter elements. The analog-to-digital converter elements in the ADC array 120 are digital feature generators that are processed by the machine-learning unit 130. These circuits all receive a respective analog channel from the plurality of analog channels 115, and together produce a plurality of digital features 125 as a response, and the method by which they achieve that response differs with the category of converter. An example is a standard ADC, such as a successive approximation register, a sigma-delta, or a flash ADC, which takes instantaneous voltage readings from a respective analog channel. Another example is a bandpass ADC, which applies a high-pass and low-pass filter to the respective analog channel, and samples the result. Each bandpass ADC can apply a different low-pass and high-pass filter, such that the combined activity of the ADC array 120 covers the entire frequency range of the analog input signal 105. Another example is a Monte Carlo ADC, which applies a binary comparison between the respective analog channel and a fixed voltage value at a fixed timing offset. The ADC array 120 can comprise a large number of Monte Carlo ADCs, each with a unique voltage value and timing offset. This will result in a large number of digital features 125 that are binary values, and contain all the information of the analog input signal 105. The categories of approaches vary in their accuracy, power efficiency, manufacturing complexity, and response times, so different approaches to generating the digital features 125 are suitable in different applications. The ADC array 120 can be constructed from ADCs selected to make best use of the characteristics of one or more approaches, resulting in a heterogeneous ADC array 120. 1.2.3 Digital-to-Analog Converter Array

[0064] The DAC array 140 comprises multiple digital-to-analog converter elements. The digital-to-analog converter elements in the DAC array 140 are analog feature generators that provide the building blocks of the first analog output signal 155. These circuits all receive a respective digital instruction and together produce a plurality of analog features 145 as a response, and the method by which they achieve that response differs with the category of converter. An example method includes a multiplexing element, which produces an intermediate analog signal and multiplexes that intermediate analog signal with a local oscillator. This results in an analog feature that is frequency shifted to a predetermined frequency band. Multiple multiplexing elements can be deployed in the DAC array 140, such that their combined output covers the entire frequency range of the desired analog output signal 155. Another example method includes a Monte Carlo element, which produces a single voltage pulse at a fixed amplitude, duration, and timing offset. The DAC array 140 can comprise a vast number of Monte Carlo elements, each of different amplitudes, durations, and timing offsets. Their individual voltage pulses can be combined to create the analog output signal 155. The categories of approaches vary in their accuracy, power efficiency, manufacturing complexity, and response times, so different approaches to generating the analog features 145 are suitable in different applications. The DAC array 140 can be constructed from DACs selected to make best use of the characteristics of one or more approaches, resulting in a heterogenous DAC array 140.

[0065] 1.2.4 Combining Unit

[0066] The combining unit 150 combines analog features 145 into an analog output signal 155. In the standard configuration it produces a single analog output signal 155. In an alternative configuration, it can produce multiple analog output signals 810. Operations conventionally performed in analog circuitry, by which multiple analog features 145 are combined to produce an output 155 based at least in part on each respective analog feature, can form a basis for a combining unit 150. Simple operations such as addition, multiplication, subtraction and division are examples of suitable bases for the combining unit 150. The combining unit 150 also can combine features by performing comparisons, such as selecting the maximum, minimum, mode or median feature from among the available features. These operations can also be nested, for example, by multiplying two features together and then adding that product to a third feature. A combination operation can be performed in conjunction with operations that modify a single feature, such as modulating that feature’s frequency or amplitude, integrating or differentiating that feature. In addition, combination operations can be performed with a feature and itself, for example, squaring a feature by multiplying it against itself.

[0067] 1.3 Machine-Learning Unit

[0068] 1.3.1 One-Stage Machine-Learning Unit

[0069] It can be advantageous to produce devices of commonly-needed functionality as simply as possible. The one-stage process described here allows for dedicated functionality with lesser requirements placed on a machine-learning unit. In this implementation, the machine-learning unit 130 can be configured to produce, in a single stage, the instruction set 135 based at least in part on the plurality of digital features 125. In this one-stage configuration, the machine-learning algorithm contained in the machine-learning unit 130 is preconfigured to produce the instruction set 135 from the plurality of digital features 125. This allows for a fast and low-power implementation of the machine-learning algorithm.

[0070] 1.3.2 Three-Stage Machine-Learning Unit

[0071] A key concern in designing a machine-learning enabled signal processor is providing a stable and easy method to customize the behavior of the device 100. If the machine-learning unit 130 is implemented as a one-stage machine-learning unit, then a change in the machine-learning algorithm might involve a massive recalibration procedure. One option is to send the device back to the manufacturer, where it can be placed in a precise test rig and the calibration procedure can be overseen by the manufacturer. This can be costly and time consuming. Another option is for the manufacturer to provide each customer with detailed knowledge about the operation of the device, thereby enabling the customer to perform calibration on its own. This can be disadvantageous for manufacturers, as this would reveal detailed trade secrets, and it can be onerous for the user. The goal, instead, is to provide an interface for the customer to innovate and manipulate the machine-learning unit 130 without assistance from the manufacturer. The word “interface” here is used in its meaning from software engineering, in which it refers to an abstract layer that fixes the means by which functions interact with functions and data on the other side of the layer, but allows the specific implementations of those functions and data to change. A user can define a process 330 by, for example, writing a software routine accessing values from the ADC interface and assigning values to the DAC interface. The user-defined process 330 can be installed with code that is written onto a microprocessor. The user-defined process 330 can be installed as a dedicated set of digital circuitry. The user-defined process 330 can be a machine-learning algorithm, executed on machine-learning accelerated hardware. Although a process 330 can be user-defined, it can just as easily be defined by the manufacturer of the device.

[0072] A solution to the customization problem is to configure the machine-learning unit 130 as a three-stage machine-learning unit, as shown in FIG. 3.

[0073] In this implementation, the machine-learning unit 130 includes an ADC machine-learning algorithm 310, a user-defined process 330, and a DAC machine-learning algorithm 350. In stage one, the ADC machine-learning algorithm 310 converts the plurality of digital features 125 into a digital signal 320 that represents the first analog input signal 105. This digital signal 320 can, for example, represent the Shannon-Nyquist samples of the first analog input signal 105. In stage two, the user-defined process 330 transforms (e.g., applies a predefined transform process to) the digital signal 320. Examples of the user-defined process 330 include a software routine that applies digital signal processing techniques, and a machine-learning algorithm configured to apply a specific technique to the digital signal 320. The user-defined process 330 produces a modified digital signal 340, based at least in part on the digital signal 320. In stage three, the DAC machine-learning algorithm 350 produces an instruction set 135, based at least in part on the modified digital signal 340.

[0074] The advantage of this approach comes from the stable interfaces provided by the ADC machine-learning algorithm 310 and the DAC machine-learning algorithm 350. These two components can be designed and implemented by the manufacturer of the device using techniques for calibrating machine-learning enabled ADCs and machine-learning enabled DACs, described elsewhere. The ADC machine-learning algorithm 310 acts as an interface to the signal routing unit 110 and the ADC array 120 by abstracting away the behavior of that underlying analog circuitry. The DAC machine-learning algorithm 350 acts as an interface to the DAC array 140 and the combining unit 150 by abstracting away that underlying analog circuitry. As a result, the user-defined process 330 can be defined to interact with the interfaces provided by the ADC machine-learning algorithm 310 and the DAC machine-learning algorithm 350. 1.3.3 Two-Stage Machine-Learning Unit

[0075] As a balance between the speed of a one-stage machine-learning unit and the flexibility of a three-stage machine-learning unit, the machine-learning unit 130 can be configured as a two-stage machine-learning unit. In this configuration, a user-defined process is combined with the DAC machine-learning algorithm 350 of the three-stage setup. This two-stage configuration operates by first producing, with the ADC machine-learning algorithm 310, a digital signal 320 based at least in part on the plurality of digital features 125, and then producing, with the user-defined / DAC machine-learning algorithm, the instruction set 135 based at least in part on the digital signal 320.

[0076] 1.4 Machine-Learning Algorithm

[0077] 1.4.1 Machine-Learning Algorithm - Feedforward Neural Network

[0078] FIG. 2 illustrates an example of the machine-learning enabled signal processor that implements the machine-learning algorithm with a feedforward neural network. In this implementation, the machine-learning unit 130 includes a digital neural network 210 that receives the plurality of digital features 125 at the network’s input and produces the instruction set 135 at the network’s output. This approach involves a collection of nodes that form weighted connections with each other, arranged in sequential layers. The nodes in an input layer 220 of the neural network 210 receive the plurality of digital features 125 in the form of a vector of digital values of length P. Each node j in a layer sums the products of weights (w .) and digital kj values ( ), applies an activation function (<p) to that sum, and outputs the result of that activation function as the output o of the node. p o . = <p( £ W ■ x

[0079] 1I ki k k=l1

[0080] The exact weighting w . at each node j is previously calculated during the calibration procedure, / cj

[0081] The activation function can be an open design choice. Activation functions such as rectified linear unit, hyperbolic tangent, or sigmoid each have advantages. The rectified linear unit is particularly suitable because it is relatively simple to calculate.

[0082] The input layer 220 passes its outputs to the nodes in a hidden layer from among the hidden layers 230 in the neural network 210. The network 210 contains one or more hidden layers. Each neuron in the hidden layer applies the activation function to the sums of its weighted inputs, and passes its output to the next layer. The number of hidden layers, the topology of the connections between nodes, and the number of nodes in each layer can be open design choices.

[0083] The final hidden layer passes its outputs to the output layer 240. The neurons in the output layer apply the same weighted sum and activation process, and each of their respective outputs is a digital value that represents an instruction among the instruction set 135.

[0084] 1.4.2 Machine-Learning Algorithm - Recurrent Neural Network

[0085] In a standard neural network design, the nodes in the network form a set of sequential layers. As a result, there are no loops in the system, such that the output of one node is never fed backwards to the same or a lower layer. There is a class of neural networks that do allow these loops to occur, called recurrent neural networks (RNN).

[0086] One implementation of an RNN is the fully recurrent neural network. In this implementation, each node in a layer connects its output with an edge to each other node in the layer. This means that for any nodes i and j in a layer L, i #= j, node i connects its output to node j with an edge. Other recurrent neural network architectures, such as Long Short-Term Memory, Jordan, Elman, or Hopfield networks, can be implemented as fully recurrent neural networks in which certain weights w are set to zero, effectively disconnecting those edges.

[0087] These networks apply similar techniques as the standard neural networks for optimizing and processing data. The key advantage is that the recurrent loops allow the network to maintain a form of memory, which can affect future results. One could think of a standard neural network as applying a finite response filter (FIR) and the recurrent neural network as applying an infinite response filter (HR). An RNN can be advantageous when applying a particular filter to the expected analog output, or if using a collection of non-time-invariant elements in the DAC array 140.

[0088] In this implementation, the machine-learning unit 130 includes a digital recurrent neural network that receives the plurality of digital features 125 at the network’s input and produces the instruction set 115 at the network’s output. At least one node within at least one layer of the digital recurrent neural network passes its output to a node in the same layer or a previous layer in the network, such that at least one node’s output is based at least in part on the output of a node in the same or a subsequent layer. 1.4.3 Other Machine-Learning Algorithms

[0089] The machine-learning algorithm is not limited to being a neural network. Other implementations include support vector machine (SVM), ridge regression, hidden Markov models, clustering algorithms, and a naive Bayes classifier.

[0090] 2. Optional Configurations

[0091] 2.1 Digital Input Signal

[0092] The machine-learning signal processor 100 can be configured to accept digital signals. FIG. 4 illustrates this digital input configuration. In this implementation, the machine-learning unit 130 receives the plurality of digital features 125 and a digital input signal 410. The machine-learning unit 130 produces an instruction set 135 based at least in part on the digital features 125 and the digital input 410.

[0093] FIG. 22 illustrates an example use case of this configuration. In this example, a machine-learning unit signal processor translates audio from English into another language. A microphone, not shown, produces an analog input signal 105 that contains the English audio. The digital input 410 contains a setting specifying the language to output (for example, French). The machine-learning enabled signal processor receives the analog input signal 105 and the digital input signal 410. The ADC array produces the digital features 125 as in the standard configuration, and passes the digital features 125 to the machine-learning unit 130. The machine-learning unit 130 receives the digital input signal 410 and the digital features 125. The machine-learning unit 130 produces the instruction set 135 based at least in part on the English audio and the output language, then passes the instruction set to the DAC array as in the standard configuration. The overall effect is that the machine-learning enabled signal processor can produce an analog output signal that represents the English audio translated into French. The digital input signal 410 can be changed to a new language value (such as Greek), and the device would then receive an analog audio signal containing English audio and produce an analog audio signal containing Greek audio.

[0094] 2.2 Optional Environmental Sensors

[0095] If the external environment of the machine-learning signal processor 100 is unknown or changes over time, the machine-learning unit 130 can incorporate an environmental signal 510 as input, illustrated in FIG. 5. The environmental sensor input 510 can monitor various environmental conditions, such as temperature, stress / strain, age, magnetic fields, jitter, etc, that can affect the underlying analog circuitry contained in the signal routing unit 110, the ADC array 120, the DAC array 140, and / or the combining unit 150. Before operation, the machine-learning unit 130 can be calibrated to reduce the error between the analog output signal 155 and an expected analog output signal, using the environmental sensor input 510 as an input in each example evaluated by the calibration process. In operation, the calibrated machine-learning unit 130 produces the instruction set 135 based at least in part on the environmental sensor input 510.

[0096] 2.3 Digital Output

[0097] The machine-learning signal processor 100 can also be configured to produce a digital signal output. The digital signal output configuration is seen in FIG 6. The machine-learning unit 130 produces the instruction set 135 and a digital output signal 610, each based at least in part on the plurality of digital features 125.

[0098] FIG. 24 illustrates an example use case of this configuration. In this example, a machine-learning signal processor translates audio from an unknown spoken language into Greek. A microphone, not shown, produces an analog input signal 105 that contains the unknown speech. The machine-learning unit 130 can produce the instruction set 135 and a digital output signal identifying the language of origin, at least in part based on the analog input signal 105. The overall effect is that the machine-learning enabled signal processor produces an analog output signal 155 that represents the speech translated into Greek, and a text identifier indicating the language of origin.

[0099] FIG. 25 illustrates a further example use case of this configuration. In this example, a machine-learning unit signal processor translates audio from spoken English into Greek. A microphone, not shown, produces the analog input signal 105 that contains spoken English speech. The machine-learning unit 130 produces the instruction set 135 and a digital transcript of the spoken English translated into Greek, at least in part based on the analog input signal 105. The overall effect is that the analog output signal 155 represents the speech translated into Greek, and the machine-learning enabled signal processor 100 produces a digital transcript containing the text translated into Greek. 2.4 Multiple Input

[0100] The machine-learning signal processor 100 can be configured to receive a second analog input signal. FIG. 7 illustrates this configuration. The signal routing unit 110 receives a second analog input signal 710 in addition to the first analog input signal 105. The signal routing unit 110 then produces the plurality of analog channels 115, based at least in part on the first analog input signal 105 and the second analog input signal 710. An example use of this configuration is to receive the second analog input 710 from a second analog antenna, not shown, at the machine-learning enabled signal processor 100, and thus alter the connected antennae’s effective receiving performance.

[0101] 2.5 Multiple Outputs

[0102] The machine-learning signal processor 100 can be configured to produce a second analog output signal. FIG. 8 illustrates this configuration. The combining unit 150 produces a second analog output signal 810, based at least in part on the plurality of analog features 145. An example use of this configuration is to send a second analog output signal 810 to a second analog antenna, not shown, and thus alter the connected antennae’s effective transmitting performance.

[0103] 2.7 Other configurations

[0104] 2.7.1 Process Failure Flags

[0105] There may be conditions in which the machine-learning-enabled signal processor 100 produces a faulty analog output signal 155. A potential source of this error is a miscalibration of the machine-learning unit 130 by the dimensionality reduction unit. To account for these miscalibrations, a machine-learning-enabled signal processor can be designed with a digital process failure unit.

[0106] The digital process failure unit performs a check on the system 100. The digital process failure unit receives the plurality of digital features 125. The digital process failure unit then applies the old machine-learning unit algorithm (operated before the dimensionality reduction unit update) to the plurality of digital features 125. This generates an expected instruction set. The digital process failure unit then receives the actual instruction set 135. The digital process failure unit then calculates the error between the expected instruction set and the actual instruction set 135. If the error is greater than a predetermined threshold, a process failure flag is thrown, and the old machine-learning algorithm can be reinstalled in the machine-learning unit 130.

[0107] While the digital process failure unit can identify when a miscalibration of the machine-learning unit 130 has occurred by the dimensionality reduction unit, it can not identify if an unexpected change in the environment has distorted its underlying analog circuitry of the signal routing unit 110, the ADC array 120, the DAC array 140, and / or the combining unit 150. To account for this potential problem, an analog process failure unit can be installed.

[0108] In this configuration, the analog process failure unit includes an first analog-to-digital converter that measures a feature of the analog input signal 105 and an second analog-to-digital converter that measures a feature of the analog output signal 155. The analog process failure unit also receives the digital features 125 produced by the ADC array 120. The method implemented by the analog process failure unit occurs in two general stages.

[0109] The first check performed by the analog process failure unit is on the analog input signal 105. The analog process failure unit contains an ADC machine-learning algorithm 310, identical to the machine-learning algorithm applied during the three-part design 300. The plurality of digital features 125 are passed through the ADC machine-learning unit 310 to create a digital signal. The analog process failure unit then estimates, using this digital signal, the feature measured from the first analog input 105 with the first ADC. The analog process failure unit then calculates the error between the measured analog feature and its estimated analog feature. If the error is above a predetermined threshold, a process failure flag can be thrown.

[0110] The second check performed by the analog process failure unit is on the analog output signal 155. The analog process failure unit contains the user-defined process applied during the three-part design 300. The digital signal, produced during the analog input check, is passed through the user-defined process, and the resulting processed digital code is generated. From this processed digital code, the analog process failure unit estimates the feature of the analog output signal 155. The analog process failure unit then calculates the error between the measured analog feature and the estimated analog feature. If the error is above a predetermined threshold, a process failure flag can be thrown.

[0111] 2.7.2 Dimensionality reduction unit

[0112] There may be cases where the first analog input signal 105 has structure that is unknown before operation. The first analog input signal 105 may only contain information in a sparse frequency domain, or be a consistent repeating pattern. In this case, the device may operate more efficiently (either through speed or power consumption) with a simplified machine-learning unit 130. This can be achieved by installing a dimensionality reduction unit. In this configuration, the dimensionality reduction unit passively monitors the plurality of digital features 125 and the instruction set 135. A training example is created by pairing the plurality of digital features with the resulting instruction set. Multiple training examples can be collected over time, and stored in a dataset. A new machine-learning algorithm can then be trained on the dataset, to produce the instruction code 135 based at least in part on a plurality of digital features 125. If the new algorithm performs within tolerance, the new machine-learning algorithm is installed on the machine-learning unit 130, and the instruction set 135 can be produced with the new machine-learning unit, based at least in part on the plurality of digital features 125..

[0113] This dimensionality reduction unit can be configured to simplify a three-stage machine-learning unit 300 or a two-stage machine-learning unit into a one-stage design 200. The dimensionality reduction unit can also be used to reduce the complexity of the one-part design 200. In this complexity-reduction case, the new machine-learning algorithm can be initialized with fewer parameters than the machine-learning algorithm contained in machine-learning unit 130.

[0114] 3. METHOD OF OPERATION

[0115] 3.1 Standard Operation

[0116] FIG. 11 illustrates an algorithm 1100 performed by various implementations of the present disclosure. Prior to executing the algorithm, the machine-learning unit 130 should converge on an appropriate input-output solution, described in section 4 (Method of Calibration). The algorithm 1100 begins at S1105 and advances to S1110.

[0117] In S1110, the signal routing unit 110 receives the first analog input signal 105. The algorithm 1100 advances to optional S1115.

[0118] In S1115, the signal routing unit 110 receives a second analog input signal 710. For example, a microphone can be connected to the machine-learning enabled signal processor 100 and can produce the second analog input signal 710. The algorithm 1100 advances to S1120.

[0119] In S1120, the signal routing unit 110 produces the plurality of analog channels 115, each based at least in part on the first analog input signal 105. In implementations in which S1115 is performed, the plurality of analog channels 115 are produced based at least in part on the second analog input signal 710. The algorithm 1100 advances to S1125.

[0120] In S1125, the array of analog-to-digital converters 120 produces a plurality of digital features 125, each based at least in part on a respective channel from the plurality of analog channels 115. The algorithm 1100 advances to optional S1130.

[0121] In S1130, the machine-learning unit 130 receives an external digital input signal 410, such as a setting for a language to output. The external digital signal 410 is not so limited and can be any digital signal within the operating specifications of the machine-learning unit 130. The algorithm 1100 advances to optional S1135.

[0122] In S1135, the machine-learning unit 130 receives an environmental signal from a sensor, for example. The environmental signal can be an external digital input signal containing information about the environmental conditions 510. The environmental conditions 510 affect the underlying analog circuitry in the signal routing unit 110, the ADC array 120, the DAC array 140, and / or the combining unit 150. The algorithm 1100 advances to S1140.

[0123] In S1140, a machine-learning unit 130 produces the instruction set 135, based at least in part on the plurality of digital features 125. For example, a neural network in the machine-learning unit 130 applies weights or biases to the digital features 125 to produce the instruction set 135. In implementations in which S1130 is performed, the instruction set 135 can be produced based at least in part on the external digital input signal 410. In implementations in which S1135 is performed, the instruction set 135 can be produced based at least in part on the external digital signal 410. The algorithm 1100 advances to optional S1145.

[0124] In S1145, the machine-learning unit 130 produces a digital output signal 610, based at least in part on the plurality of digital features 125. For example, the machine-learning unit 130 can create a high temperature alert, if the analog input signal is a thermometer’s analog signal. The algorithm 1100 advances to S1150.

[0125] In S1150, the array of digital-to-analog converters 140 produces the plurality of analog features 145, each based at least in part on a respective instruction from the instruction set 135. The algorithm 1100 advances to S1155.

[0126] In S1155, the combining unit 150 produces the first analog output signal 155 based at least in part on the plurality of analog features 145. The algorithm 1100 advances to optional S1160.

[0127] In S1160, the combining unit 150 produces the second analog output signal 810, based at least in part on the plurality of analog features 145. For example, if the combining unit 150 outputs high frequency sounds in the first analog output signal 155, then the combining unit 150 can output low frequency sounds in the second analog output signal 810 to be routed to a different audio output from the high frequency sounds.

[0128] The algorithm 1100 advances to S1165 and concludes.

[0129] 3.2 Three-Stage Operation

[0130] FIG. 12 illustrates a subprocess algorithm 1200 implementing S1140 in algorithm 1100. This subprocess algorithm 1200 is the three-stage operation that can allow increased flexibility in reconfiguring the operation of the device. The distinguishing characteristic of this three-stage operation is that the machine-learning algorithms 310, 350 do not perform any signal processing techniques on the signal. The machine-learning algorithms can operate merely as interfaces to transform the signal from analog form to digital form and vice versa.

[0131] The subprocess algorithm begins at S1210 and advances to S1220.

[0132] In S1220, the ADC machine-learning algorithm 310 produces a digital signal 320, based at least in part on the plurality of digital features 125. In various implementations, this digital signal 320 can represent the first analog input signal 105. The algorithm 1200 advances to S1230.

[0133] In S1230, the algorithm 1200 produces a modified digital signal 340, with a process 330, based at least in part on the digital signal 320. This process 330 can be defined by the user of the machine-learning enabled signal processor 100. This process 330 can be defined by the manufacturer of the machine-learning enabled signal processor 100. This process 330 can be an arbitrary signal processing technique. This process 330 can be executed in software, digital circuitry, or with another machine-learning algorithm. The algorithm 1200 advances to S1240.

[0134] In S1240, the algorithm 1200 produces an instruction set 135, with the DAC machine-learning algorithm 350, based at least in part on the modified digital signal 340. The algorithm 1200 advances to S1250 and concludes.

[0135] 3.3 Two-Stage Operation

[0136] As discussed above in section 1.3.3 Two-Stage Machine-Learning Unit, there is a method of two-stage operation, wherein a machine-learning algorithm is configured to perform the operations of both the process 330 and the DAC machine-learning algorithm 350.

[0137] FIG. 13 illustrates a subprocess algorithm 1300 implementing S1140 in algorithm 1100. This subprocess algorithm is a two-stage operation that can allow some flexibility in reconfiguring the operation of the device and also can allow some speed advantages compared to the three-stage operation.

[0138] The subprocess algorithm begins at S1305 and advances to S1310.

[0139] In S1310, the ADC machine-learning algorithm 310 produces the digital signal 320, based at least in part on the plurality of digital features 125. The digital signal 320 represents the first analog input signal 105. The algorithm 1300 advances to S1320.

[0140] In S1320, the algorithm 1300 produces an instruction set 135, with the user-defined I DAC machine-learning algorithm, based at least in part on the digital signal 320. The algorithm 1300 advances to S1330 and concludes.

[0141] 4. METHOD OF CALIBRATION

[0142] The three modes of operation of the machine-learning algorithm, namely one-stage, three-stage, and two-stage, can use a slightly different calibration procedure.

[0143] 4.1 Calibrating a One-Stage Machine-Learning Unit

[0144] 4.1.1 Overview

[0145] FIG. 14 illustrates an algorithm 1400 performed by various implementations of the present disclosure. This algorithm calibrates a one-stage machine-learning algorithm for a machine-learning unit 130. For example, a machine-learning unit that includes a neural network 210 can be calibrated by the algorithm 1400.

[0146] The algorithm 1400 begins at S1405 and advances to S1410.

[0147] In S1410, the algorithm 1400 produces an ADC dataset 2840 of training examples, each example 2835 including an input vector including a plurality of training digital features 2830 and an output vector including a training digital signal 2810. The method of producing the ADC dataset 2840 is described in connection with Fig. 16 and Fig. 28A. In operation, a machine-learning algorithm trained on the ADC dataset 2840 is the ADC machine-learning algorithm 310, and can produce the digital signal 320, based at least in part on the plurality of digital features 125, such that the digital signal 320 represents the first analog input signal 105. The algorithm 1400 advances to S1415.

[0148] In S1415, the algorithm 1400 produces a DAC machine-learning algorithm 350 that is trained to produce an instruction set based at least in part on a digital signal. The method of producing this DAC machine-learning algorithm 350 is later described in connection with Fig. 17 and Fig. 28B. The algorithm 1400 advances to 1420. In S1420, the algorithm 1400 produces a Signal Processor machine-learning algorithm 2891 that produces an instruction set 135, based at least in part on a plurality of digital features 125. This Signal Processor machine-learning algorithm 2891 is produced using the ADC dataset 2840 from S1410 and the DAC machine-learning algorithm 350 from S1415, as later described in connection with Fig. 15 and Fig. 28C. This Signal Processor machine-learning algorithm 2891 is then installed in the machine-learning unit 130, and the machine-learning signal processor 100 produces the instruction set 135 using the Signal Processor machine-learning algorithm 2891 , based at least in part on the plurality of digital features 125. An example of this Signal Processor machine-learning algorithm 2891 is a neural network 210 that maps from the plurality of digital features 125 to the instruction set 135. The machine-learning signal processor 100 can now operate in the one-stage configuration.

[0149] The algorithm 1400 advances to S1425 and concludes.

[0150] 4.1.2 Producing the ADC Dataset

[0151] FIG. 16 and FIG. 28A illustrates a subprocess algorithm 1600 for implementing S1410. This subprocess algorithm is a method for creating an ADC dataset 2840 of ADC training examples 2835. The ADC machine-learning algorithm 310 can be produced by training 2845 on this ADC dataset 2840

[0152] The subprocess algorithm 1600 begins at S1605 and advances to S1615.

[0153] In S1615, the algorithm produces, with a digital signal generator process 2805, a training digital signal 2810. An example digital signal generator process 2805 uses a random number generator, and the digital signal 2810 is a random digital signal. The algorithm 1600 advances to S1620.

[0154] In S1620, a first digital-to-analog converter 2815 produces a training analog signal 2820 that represents the training digital signal 2810. The algorithm 1600 advances to S1625.

[0155] In S1625, the signal routing unit 110 produces the plurality of training analog channels 2825, each based at least in part on the training analog signal 2820. The algorithm 1600 advances to S1630.

[0156] In S1630, the ADC array 120 produces the plurality of training digital features 2830, each based at least in part on a respective analog channel in the plurality of training analog channels 2825. The algorithm 1600 advances to S1635.

[0157] In S1635, the algorithm 1600 produces a first ADC training example 2835, based at least in part on the digital signal 2810 and the plurality of training digital features 2830. In particular, the first training example 2835 comprises an input vector including the plurality of training digital signals 2830 produced in S1630, and an output vector including the training digital signal 2810 produced in S1615. The algorithm 1600 advances to S1640.

[0158] In S1640, the ADC training example 2835 is stored in the ADC dataset 2840 produced in S1610. Multiple training examples can be created by repeating steps S1615 through S1635 multiple times. For example, if the digital signal generator process 2805 is a random number generator, then repeating S1615 can produce a new random digital signal 2810, resulting in a new plurality of digital features 2830, and thus a new training example 2835. An arbitrary number of training examples can be generated to populate the ADC dataset 2840.

[0159] The algorithm 1600 advances to S1645 and concludes.

[0160] 4.1.3 Producing the DAC Machine-Learning Algorithm

[0161] FIG. 17 and FIG 28B illustrates a subprocess algorithm 1700 for implementing S1415 in algorithm 1400. This subprocess algorithm 1700 is a method for creating the DAC machine-learning algorithm 350.

[0162] The subprocess algorithm 1700 begins at S1705 and advances to S1715.

[0163] In S1715, the algorithm 1700 produces an instruction set 2855 with an instruction set generator process 2850. The domain of valid instruction sets is determined by the particular implementation of DAC elements included in the DAC array 140. In many implementations, each DAC element receives one instruction. An example instruction set generator process 2850 is a process that transforms the output of a random number generator into instructions in the format of the DAC array 140. As another example, the instruction set generator process 2850 can iterate through a list of instruction sets provided by a third party. The algorithm 1700 advances to S1720.

[0164] In S1720, the DAC array 140 produces a plurality of training analog features 2860, each based at least in part on a respective instruction from the training instruction set 2855. The algorithm 1700 advances to S1725.

[0165] In S1725, the combining unit 150 produces a training analog output signal 2865, based at least in part on the plurality of training analog features 2860. The algorithm 1700 advances to S1730.

[0166] In S1730, a first analog-to-digital converter 2867 samples the first training analog output signal 2865, and produces a first DAC training digital signal 2870 based on the first training analog output signal 2865. The algorithm 1700 advances to S1735.

[0167] In S1735, the algorithm 1700 produces a test result by applying a test process to the first DAC training digital signal 2870 produced in S1730. An example test process is determining if the first training analog output signal 2865 represented by the first DAC training digital signal 2870 is within the voltage, current, and frequency range of the machine-learning enabled signal processor 100. The algorithm 1700 advances to S1740.

[0168] In S1740, the algorithm 1700 produces a first DAC training example 2875 including an input vector including the instruction set 2855 from S1715 and an output vector including the first DAC training digital signal 2870 from S1730. The algorithm 1700 advances to S1745.

[0169] In S1745, the algorithm 1700 stores the first DAC training example 2875 in the DAC dataset 2880 from S1710 if the test result from S1735 is positive. For example, if the resulting first training analog output signal 2865 from S1725 is within the voltage, current, and frequency ranges of the machine-learning signal processor 100, the first DAC training example 2875 is added to the DAC dataset 2880. If the test result is S1735 is negative, the DAC training example 2875 can be discarded. This process can be repeated from step S1715 through S1745 multiple times. For example, if the instruction set generator 2850 is a random number generator, then repeating S1715 can produce a new random training instruction set 2855, resulting in a new DAC training digital signal 2870, and thus a new DAC training example 2875. An arbitrary number of training examples can be generated to populate the DAC dataset 2880. The algorithm 1700 advances to S1750.

[0170] In S1750, the DAC machine-learning algorithm 350 is then produced by training 2885 a machine-learning algorithm on the populated DAC dataset 2880. For example, the neural network 210 can be trained, using the back-propagation method. The algorithm 1750 advances to S1755 and concludes.

[0171] 4.1.4 Producing the Signal Processor Machine-Learning Algorithm

[0172] FIG. 15, FIG. 28C, and FIG. 28D illustrates a subprocess algorithm 1500 for implementing S1420 in algorithm 1400. This subprocess algorithm 1500 is a method for creating a Signal Processor machine-learning algorithm 2891 that produces the instruction set 135 based at least in part on the plurality of digital features 125. This Signal Processor machine-learning algorithm 2891 is produced using the ADC dataset 2840 and the DAC machine-learning algorithm 350. After production, this Signal Processor machine-learning algorithm 2891 can be installed in the machine-learning unit 130 to operate the machine-learning unit 130 in a one-stage operation. The machine-learning unit 130 can produce the instruction set 135, using this Signal Processor machine-learning algorithm 2891. The machine-learning unit 130 can be implemented in a one-stage operation as a neural network 210. The subprocess algorithm 1500 begins at S1505 and advances to S1515.

[0173] In S1515, a first ADC training example 2835 is taken from the ADC dataset 2840, and the respective plurality of digital features 2830 are read out from the first training example 2835. The algorithm 1500 advances to S1520.

[0174] In S1520, the respective training digital signal 2810 from the first training example 2835 is read out. The algorithm 1500 advances to optional S1525.

[0175] In S1525, a training digital output signal 2895 is produced using a digital output generator process 2894, based at least in part on the training digital signal 2810 from S1520. This digital output generator process 2894 can be defined by the user, or alternatively by the manufacturer of the machine-learning enabled signal processor. This digital output generator process 2894 can be an arbitrary signal processing technique. This digital output generator process 2894 can be executed in software, digital circuitry, or with another machine-learning algorithm. The algorithm 1500 advances to optional 1530.

[0176] In S1530, a training external digital input signal 2893 is produced using a digital input generator process 2892. An example digital input generator process 2892 is a random number generator. In this example, the external digital input signal 2893 is used to control the gain of a first analog output signal 155 produced by the machine-learning signal processor 100. A random number generator produces a number between 0 and 1 , and that number is later used by the process 330 to adjust the amplitude of a modified signal. This production can result in one training example 2888 at one gain setting.

[0177] Repeating the process 1500 with a random number generator produces a multitude of training examples, each at different gain values. The system can then learn that the external digital input signal 410 represents gain. Another example of a digital input generator process 2892 is producing a measurement of an environmental condition using an environmental sensor that measures the environmental conditions affecting the signal routing unit 110, the ADC array 120, the DAC array 140, and / or the combining unit 150. For example, a digital thermometer can be placed near the ADC array 120 during this calibration procedure 1400, and the training external digital input signal 2893 can be based at least in part on digital temperature readings produced by the digital thermometer. The system can then learn the correlation between the measurement of the environmental condition and modified behavior of the circuit components.

[0178] The algorithm 1500 advances to S1535.

[0179] In S1535, a process 330 is applied to the respective training digital signal 2810 from S1520. This process 330 can be defined by the user, or alternatively by the manufacturer of the machine-learning enabled signal processor. This process 330 can be an arbitrary signal processing technique. This process 330 can be executed in software, digital circuitry, or with another machine-learning algorithm. This process 330 produces a modified digital signal 2886, based at least in part on the respective training digital signal 2810. In implementations in which S1530 is performed, the process 330 can produce the modified digital signal 2886, based at least in part on the training external digital input signal 2893. In the gain control example, the training modified digital signal 2886 can be the respective training digital signal 2810 multiplied by the training external digital input signal 2893. The algorithm 1500 advances to S1540.

[0180] In S1540, the DAC machine-learning algorithm 350 from S1415 produces a training modified instruction set 2887 based at least in part on the training modified digital signal 2886 from S1535. The algorithm 1500 advances to S1545.

[0181] In S1545, a first signal processor training example 2888 is produced, including an input vector including the respective plurality of training digital features 2830 and an output vector including the training modified instruction set 2887. In implementations in which S1525 is performed, the output vector of the first training example 2888 includes the training digital output signal 2895. In implementations in which S1530 is performed, the input vector of the first signal processor training example 2888 comprises the training external digital input signal 2893. The algorithm 1500 advances to S1550.

[0182] In S1550, the first signal processor training example 2888 can be stored in the Signal Processor dataset 2889 from S1510. Steps S1515 through S1545 can be repeated to create more training examples. This repetition populates the Signal Processor dataset 2889 produced in S1510. The algorithm 1500 advances to S1555.

[0183] In S1555, the Signal Processor machine-learning algorithm 2891 is trained 2890 on the Signal Processor dataset 2889 populated in S1550, such that the Signal Processor machine-learning algorithm 2891 can produce the instruction set 135 based at least in part on the plurality of digital features 125. For example, Signal Processor machine-learning algorithm 2891 can be a neural network trained using the back-propagation method and the Signal Processor dataset 2889. In implementations in which S1525 is performed, the Signal Processor machine-learning algorithm 2891 can be trained to produce the digital output signal 610, based at least in part on the plurality of digital features 125. In implementations in which S1530 is performed, the Signal Processor machine-learning algorithm 2891 can be trained to produce the instruction set 135, based at least in part on the external digital input signal 410. The algorithm 1500 advances to S1560.

[0184] In S1560, the Signal Processor machine-learning algorithm 2891 is installed in the machine-learning unit 130, and the machine-learning signal processor 100 can operate by producing the instruction set 135, using the Signal Processor machine-learning algorithm 2891 , based on the plurality of digital features 125. In the example where the Signal Processor machine-learning algorithm 2891 is a neural network, the installed Signal Processor machine-learning algorithm 2891 is the neural network 210.

[0185] In implementations in which S1525 is performed, the machine-learning signal processor 100 can operate by producing the digital output signal 610, using the Signal Processor machine-learning algorithm 2891 , based on the plurality of digital features 125. In implementations in which S1530 is performed, the machine-learning signal processor 100 can operate by producing the instruction set 135, using the Signal Processor machine-learning algorithm 2891 , based on the external digital input signal 410.

[0186] The algorithm 1500 advances to S1565 and concludes.

[0187] 4.2 Calibrating a Three-Stage Machine-Learning Unit

[0188] A three-stage machine-learning unit can be produced using the sub-processes described in calibrating the one-stage machine-learning unit. The ADC machine-learning model 310 can be produced by generating the ADC dataset 2840 described in S1410 and in algorithm 1600. The ADC machine-learning algorithm 310 can then be produced by training on that ADC dataset 2840. An example is a neural network, trained via back-propagation, such that the output is a digital signal and the input is a plurality of digital features. The process 330 can be supplied by the user, and can be any arbitrary signal processing technique that can be applied to a digital signal. This user-defined process 330 can be executed in software, digital circuitry, or with another machine-learning algorithm. The DAC machine-learning algorithm 350 is produced as described in S1415 and in algorithm 1700.

[0189] Once the ADC machine-learning algorithm 310, the process 330, and the DAC machine-learning algorithm 350 have been produced, they can be installed in the machine-learning signal processor 100 to operate in the three-stage configuration. The machine-learning unit 130 operates by converting the plurality of digital features 125 into the digital signal 320 with the ADC machine-learning algorithm 310. The process 330 produces the modified digital signal 340, based at least in part on the digital signal 320. The DAC machine-learning algorithm 350 produces the instruction set 135, based at least in part on the modified digital signal 340. This configuration allows for the user or manufacturer to change the process 330 without recalibration of the ADC machine-learning algorithm 310 or the DAC machine-learning algorithm 350. 4.3 Calibrating a Two-Stage Machine-Learning Unit

[0190] Both the one-stage and three-stage calibration procedures use knowledge of the underlying analog circuitry contained in the machine-learning signal processor 100. These procedures use analog signals fed into and read out of the machine-learning signal processor 100 in a controlled environment. This results in an ADC dataset 2840 and a DAC dataset 2880 that capture the operations of the underlying analog circuitry contained in the machine-learning signal processor 100.

[0191] The information in the ADC and DAC datasets 2840, 2880 may be a trade secret that the manufacturer of the device does not publically share. The manufacturer may decide to produce one-stage machine-learning units 130 for popular signal processing techniques, or offer a bespoke service where a customer tells the manufacturer their desired signal processing technique, and calibration is performed by the manufacturer. Thus, the ADC and DAC datasets 2840, 2880 can be kept secret from the customer.

[0192] The manufacturer can also calibrate the three-stage machine-learning unit 130, and provide the customer the ADC and DAC machine-learning algorithms 310, 350. Since the ADC and DAC datasets 2840, 2880 cannot be backcalculated from either the ADC machine-learning algorithm 310 and DAC machine-learning algorithm 350, the manufacturer can release these algorithms publicly while keeping the ADC and DAC datasets 2840, 2880 trade secrets.

[0193] As an intermediate option that requires no knowledge of the ADC and DAC datasets 2840, 2880, but can improve performance and provide flexibility, is a two-stage machine-learning unit 130. This calibration procedure requires the ADC machine-learning algorithm 310, the processor 330, and the DAC machine-learning algorithm 350.

[0194] The core idea is that the digital signal 320, produced by the first ADC machine-learning unit 310 and modified by the process 330, is a standard signal representing an analog input signal to the device. For example, the digital signal 320 can represent the Shannon-Nyquist samples of the analog input signal 105. As a result, an ‘artificial’ digital signal can be produced using a signal generator process. An example signal generator process is a random number generator. The random numbers produced from the random number generator are then the Shannon-Nyquist sample values representing a wideband analog input signal. The processor 330 can then modify this ‘artificial’ digital signal, and the DAC machine-learning algorithm 350 can produce an instruction set based at least in part on the modified ‘artificial’ digital signal. A first training example is produced, comprising an input vector, comprising the original ‘artificial’ digital signal, and an output vector, comprising the resulting instruction set. This first training example is stored, and this process can be repeated a large number of times, populating the dataset.

[0195] A combined user-process / DAC machine-learning algorithm is then trained on this dataset, to produce an instruction set 135 based at least in part on a digital signal 320, wherein the resulting first analog output 155 created by the instruction set 135 represents the process 330 applied to the digital signal 320. Thus, the two stages of the machine-learning unit 130 are the ADC machine-learning algorithm 310 and the combined user-defined / DAC machine-learning algorithm.

[0196] This process requires no knowledge or operation of the analog circuitry contained in the machine-learning signal processor 100, and can be performed even if the manufacturer withholds the ADC and DAC datasets 2840, 2880. This two-stage machine-learning unit can have higher performance with regards to speed and power than the three-stage machine-learning unit, while having more flexibility than the one-stage machine-learning unit.

[0197] Examples

[0198] In Example AA1 , a machine-learning-enabled signal processor includes a signal routing unit that receives a first analog input signal and produces a plurality of analog channels, each based at least in part on the first analog input signal; an array of analog-to-digital converters that produces a plurality of digital features, each based at least in part on a respective channel from the plurality of analog channels; a machine learning unit configured to produce an instruction set, based at least in part on a machine-learning algorithm and the plurality of digital features; an array of digital-to-analog converters that produces a plurality of analog features, each based at least in part on a respective instruction from the instruction set; and a combining unit that produces a first analog output signal, based at least in part on the plurality of analog features.

[0199] Example AA2 is the machine-learning-enabled signal processor of Example AA1, wherein the machine-learning unit includes a digital neural network that receives the plurality of digital features as input and produces the instruction set as output.

[0200] Example AA3 is the machine-learning-enabled signal processor of Example AA1 or Example AA2, wherein the machine-learning algorithm includes: a first machine-learning algorithm configured to produce a digital signal that represents the first analog input signal, based at least in part on the plurality of digital features; a process that produces a modified digital signal, based at least in part on the digital signal; and a second machine-learning algorithm configured to produce the instruction set, based at least in part on the modified digital signal. Example AA4 is the machine-learning-enabled signal processor of any of Examples AA1-AA3, wherein the machine-learning unit receives a digital input signal and is configured to produce the instruction set, based at least in part on the digital input signal.

[0201] Example AA5 is the machine-learning-enabled signal processor of Example AA4, wherein the external digital input signal contains information about the environmental conditions affecting at least one of the components in the machine-learning-enabled signal processor.

[0202] Example AA6 is the machine-learning-enabled signal processor of any of Examples AA1-AA5, wherein the machine-learning unit produces an digital output signal, based at least in part on the plurality of digital features.

[0203] Example AA7 is the machine-learning-enabled signal processor of any of Examples AA1-AA6, wherein the signal routing unit receives a second analog input signal and produces the plurality of analog channels based at least in part on the second analog input signal.

[0204] Example AA8 is the machine-learning-enabled signal processor of any of Examples AA1-AA7, wherein the combining unit produces a second analog output signal, based at least in part on the plurality of analog features.

[0205] In Example AM 1 , a method to be implemented by a machine-learning-enabled signal processor includes receiving a first analog input signal at a signal routing unit; producing, with the signal routing unit, a plurality of analog channels, each based at least in part on the first analog input signal; producing, with an array of analog-to-digital converters, a plurality of digital features, each based at least in part on a respective channel from the plurality of analog channels; producing, with a machine-learning unit, an instruction set, based at least in part on the plurality of digital features; producing, with an array of digital-to-analog converters, a plurality of analog features, each based at least in part on a respective instruction from the instruction set; and producing, with a combining unit, a first analog output signal based at least in part on the plurality of analog features.

[0206] Example AM2 is the method of Example AM1 , wherein producing the instruction set includes receiving the plurality of digital features at a neural network’s input and producing the instruction set at the network’s output.

[0207] Example AM3 is the method of Example AM1 or Example AM2, wherein producing the instruction set includes producing, with a ADC machine-learning algorithm, a digital signal representing the first analog input signal, based at least in part on the plurality of digital features; producing, with a process, a modified digital signal, based at least in part on the digital signal; and producing, with a DAC machine-learning algorithm, the instruction set, based at least in part on the modified digital signal. Example AM4 is the method of any of Examples AM1-AM3, further comprising: receiving, at the machine-learning unit, an external digital input signal; and producing, with the machine-learning unit, the instruction set, based at least in part on the external digital input signal.

[0208] Example AM5 is the method of Example AM4, wherein the external digital input signal contains information about the environmental conditions affecting at least one of the components in the machine-learning-enabled signal processor.

[0209] Example AM6 is the method of any of Examples AM1-AM5, further comprising: producing, with the machine-learning unit, an external digital output signal, based at least in part on the plurality of digital features.

[0210] Example AM7 is the method of any of Examples AM1-AM6, further comprising: receiving, at the signal routing unit, a second analog input signal; and producing, with the signal routing unit, the plurality of analog channels, each based at least in part on the second analog input signal.

[0211] Example AM8 is the method of any of Examples AM1-AM7, further comprising: producing, with the combining unit, a second analog output signal, based at least in part on the plurality of analog features.

[0212] In Example BM1 , a method includes producing a ADC dataset of ADC training examples, each ADC example comprising a training plurality of digital features and a training digital signal; producing a DAC machine-learning algorithm that receives a digital signal and produces an instruction set, based at least in part on the digital signal; reading out a respective training plurality of digital features from a first ADC example in the ADC dataset; reading out a respective training digital signal from the first ADC example in the ADC dataset; producing, with a process, a training modified digital signal based at least in part on the respective training digital signal; producing, with the DAC machine-learning algorithm, a training modified instruction set based at least in part on the training modified digital signal; producing a first Signal Processor training example, based at least on the respective training plurality of digital features and the training modified instruction set; storing the first Signal Processor training example in the Signal Processor dataset; training a Signal Processor machine-learning algorithm, based at least in part on the Signal Processor dataset, to produce an instruction set based at least in part on a plurality of digital features; and producing an instruction set, with the Signal Processor machine-learning algorithm, based at least in part on a plurality of digital features. Example BM2 is the method of Example BM1 , further comprising: producing, with a digital output signal generator process, a training digital output signal based at least in part on the respective training digital signal; producing the first Signal Processor training example, based at least on the training digital output signal; training the Signal Processor machine-learning algorithm, based at least in part on the Signal Processor dataset, to produce both an instruction set and a digital output signal based at least in part on a plurality of digital features; and producing both an instruction set and a digital output signal, with the Signal Processor machine-learning algorithm, based at least in part on a plurality of digital features.

[0213] Example BM3 is the method of Example BM1 or Example BM2, further comprising: producing, with a digital input signal generator process, a training external digital input signal; producing, with the process, the training modified digital signal, based at least in part on the training external digital input signal; producing the first Signal Processor training example, based at least on the training external digital input signal; training the Signal Processor machine-learning algorithm, based at least in part on the Signal Processor dataset, to produce an instruction set based at least in part on a digital input signal; and producing an instruction set, with the Signal Processor machine-learning algorithm, based at least in part on a digital input signal.

[0214] Example BM4 is the method of Example BM3, wherein producing, with a digital input signal generator process, the training external digital input signal includes generating a random number.

[0215] Example BM5 is the method of any of Examples BM1-BM4, wherein producing a ADC dataset of ADC examples, each example comprising a training plurality of digital features and a training digital signal, further comprises: producing, with a digital signal generator process, a first training digital signal; producing, with a first digital-to-analog converter, a first training analog signal representing the first training digital signal; producing, with a signal routing unit of a machine-learning enabled signal processor, a training plurality of analog channels, based at least in part on the first training analog signal; producing, with an array of analog-to-digital comparators of the machine-learning signal processor, a training plurality of digital features, each based at least in part on a respective channel from the training plurality of analog channels; producing a first ADC example, based at least in part on the first training digital signal and the training plurality of digital features; and storing the first ADC example in the ADC dataset.

[0216] Example BM6 is the method of Example BM5, wherein producing, with a digital signal generator process, a first training digital signal includes generating a random number. Example BM7 is the method of any of Examples BM1-BM6, wherein producing a DAC machine-learning algorithm, that receives a digital input signal and produces an instruction set, further comprises: producing, with an instruction set generator process, a training instruction set; producing, with an array of digital-to-analog converters of the machine-learning enabled signal processor, a training plurality of analog features, each based at least in part on a respective instruction from the training instruction set; producing, with a combining unit of the machine-learning enabled signal processor, a first training analog output signal, based at least in part on the training plurality of analog features; producing, with a first analog-to-digital converter, a first DAC training digital signal, based at least in part on the first training analog signal; producing, with a test process, a test result, based at least in part on the first DAC training digital signal; producing a first DAC example, based at least in part on both the training instruction set and the first DAC training digital signal; storing, if the test result is positive, the first DAC example in the DAC dataset; and producing a DAC machine-learning algorithm, wherein the DAC machine-learning algorithm is trained, based at least in part on the DAC dataset, to produce an instruction set based at least in part on a digital signal.

[0217] Example BM8 is the method of Example BM7, wherein producing, with an instruction set generator process, a training instruction set includes generating a random number.

Claims

CLAIMSI claim:

1. A machine-learning-enabled signal processor, comprising: a signal routing unit that receives a first analog input signal and produces a plurality of analog channels, each based at least in part on the first analog input signal; an array of analog-to-digital converters that produces a plurality of digital features, each based at least in part on a respective channel from the plurality of analog channels; a machine learning unit configured to produce an instruction set, based at least in part on a machine-learning algorithm and the plurality of digital features; an array of digital-to-analog converters that produces a plurality of analog features, each based at least in part on a respective instruction from the instruction set; and a combining unit that produces a first analog output signal, based at least in part on the plurality of analog features.

2. The machine-learning-enabled signal processor of claim 1 , wherein the machine-learning unit includes a digital neural network that receives the plurality of digital features as input and produces the instruction set as output.

3. The machine-learning-enabled signal processor of claim 1 or claim 2, wherein the machine-learning algorithm includes: a first machine-learning algorithm configured to produce a digital signal that represents the first analog input signal, based at least in part on the plurality of digital features; a process that produces a modified digital signal, based at least in part on the digital signal; and a second machine-learning algorithm configured to produce the instruction set, based at least in part on the modified digital signal.

4. The machine-learning-enabled signal processor of any of claims 1-3, wherein the machine-learning unit receives a digital input signal and is configured to produce the instruction set, based at least in part on the digital input signal.

5. The machine-learning-enabled signal processor of claim 4, wherein the external digital input signal contains information about the environmental conditions affecting at least one of the components in the machine-learning-enabled signal processor.

6. The machine-learning-enabled signal processor of any of claims 1-5, wherein the machine-learning unit produces an digital output signal, based at least in part on the plurality of digital features.

7. The machine-learning-enabled signal processor of any of claims 1-6, wherein the signal routing unit receives a second analog input signal and produces the plurality of analog channels based at least in part on the second analog input signal.

8. The machine-learning-enabled signal processor of any of claims 1-7, wherein the combining unit produces a second analog output signal, based at least in part on the plurality of analog features.

9. A method to be implemented by a machine-learning-enabled signal processor, the method comprising: receiving a first analog input signal at a signal routing unit; producing, with the signal routing unit, a plurality of analog channels, each based at least in part on the first analog input signal; producing, with an array of analog-to-digital converters, a plurality of digital features, each based at least in part on a respective channel from the plurality of analog channels; producing, with a machine-learning unit, an instruction set, based at least in part on the plurality of digital features; producing, with an array of digital-to-analog converters, a plurality of analog features, each based at least in part on a respective instruction from the instruction set; and producing, with a combining unit, a first analog output signal based at least in part on the plurality of analog features.

10. The method of Claim 9, wherein producing the instruction set includes receiving the plurality of digital features at a neural network’s input and producing the instruction set at the network’s output.

11. The method of Claim 9 or Claim 10, wherein producing the instruction set includes producing, with a ADC machine-learning algorithm, a digital signal representing the first analog input signal, based at least in part on the plurality of digital features; producing, with a process, a modified digital signal, based at least in part on the digital signal; and producing, with a DAC machine-learning algorithm, the instruction set, based at least in part on the modified digital signal.

12. The method of any of Claims 9-11 , further comprising: receiving, at the machine-learning unit, an external digital input signal; and producing, with the machine-learning unit, the instruction set, based at least in part on the external digital input signal.

13. The method of Claim 12, wherein the external digital input signal contains information about the environmental conditions affecting at least one of the components in the machine-learning-enabled signal processor.

14. The method of any of Claims 9-13, further comprising: producing, with the machine-learning unit, an external digital output signal, based at least in part on the plurality of digital features.

15. The method of any of Claims 9-14, further comprising: receiving, at the signal routing unit, a second analog input signal; and producing, with the signal routing unit, the plurality of analog channels, each based at least in part on the second analog input signal.

16. The method of any of Claims 9-15, further comprising: producing, with the combining unit, a second analog output signal, based at least in part on the plurality of analog features.

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