Display panel and display apparatus

Abstract

Disclosed are a display panel and a display apparatus. The display panel comprises a first substrate, in which at least a light-shielding layer, a first gate electrode, and a first source-drain electrode are provided, wherein the light-shielding layer comprises a first light-shielding trace and a second light-shielding trace that intersect each other to form a grid; the orthographic projection of the first gate electrode is located within the orthographic projection of the first light-shielding trace; and at least part of the orthographic projection of the first source-drain electrode is located within the orthographic projection of the second light-shielding trace.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311516187.6 filed on November 13, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Virtual Reality (VR) displays currently have two main structures: LTPS (Low Temperature Poly-Silicon)-VR panels and LTPO (Low Temperature Polycrystalline Oxide)-VR panels. Because VR displays require high resolution (>1000 PPI) to enhance immersion and realism, VR panels require a very high PPI and extremely small pixel size to meet current VR requirements. However, due to the structural limitations of their high PPI, LTPS-VR and LTPO-VR panels have a lower in-plane aperture ratio than conventional products, resulting in lower brightness. Currently, this brightness is compensated by increasing the backlight brightness, but high backlight brightness can cause channel leakage current to deteriorate, affecting product display quality. SUMMARY OF THE INVENTION

[0004] The present application provides a display panel and a display device, which can solve the problem of poor anti-crosstalk capability of existing display panels.

[0005] In a first aspect, the present application provides a display panel comprising a display area and a border area disposed on at least one side of the display area. The display panel further comprises a first substrate and a second substrate disposed opposite each other, the first substrate comprising a base substrate and a plurality of thin film transistors spaced apart on the base substrate, the plurality of thin film transistors comprising a first thin film transistor disposed in the display area, the first thin film transistor comprising a first gate and a first source and drain, the first source and drain being insulated and spaced apart from each other above the first gate on a side of the first substrate facing away from the base substrate in a thickness direction of the first substrate;

[0006] The display panel further includes:

[0007] a light shielding layer, disposed between the base substrate and the first gate, the light shielding layer comprising a first light shielding trace and a second light shielding trace disposed in the display area;

[0008] a color resist layer disposed in the first substrate, the color resist layer being disposed on a side of the first source and drain electrodes facing away from the first gate electrode in the thickness direction;

[0009] The orthographic projection of the first light-shielding trace on the substrate and the orthographic projection of the second light-shielding trace on the substrate intersect with each other to form a grid;

[0010] The orthographic projection of the first gate on the base substrate is located within the orthographic projection of the first light-shielding trace on the base substrate, or the orthographic projection of the first gate on the base substrate is located within the orthographic projection of the second light-shielding trace on the base substrate;

[0011] At least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the first light-shielding trace on the substrate, or at least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the second light-shielding trace on the substrate.

[0012] In a second aspect, the present application further provides a display device, comprising the display panel as described in the first aspect. Beneficial effects

[0013] Compared with the prior art, the present application provides a display panel and a display device having the display panel, wherein the display panel is provided with a light-shielding layer in a first substrate, the light-shielding layer includes a first light-shielding trace and a second light-shielding trace arranged in a display area, the orthographic projection of the first light-shielding trace on the base substrate and the orthographic projection of the second light-shielding trace on the base substrate intersect with each other to form a grid, and the grid structure in which the first light-shielding trace and the second light-shielding trace intersect with each other forms a barrier to the light from the backlight directed toward the first gate and the first source and drain, thereby reducing the reflected light intensity of the first source and drain and the first gate, avoiding the photoinduced leakage current phenomenon caused by the reflected light, improving the anti-crosstalk capability, and improving the display quality of the display panel, and in addition, a color resist layer is provided on the side of the first source and drain away from the first gate, thereby effectively solving the problems of uneven luminescence and color deviation of the first gate and the first source and drain. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 a is a schematic diagram of a first structure of a display panel provided in an embodiment of the present application.

[0015] FIG1 b is a schematic diagram of a second structure of a display panel provided in an embodiment of the present application.

[0016] FIG2 a is a schematic diagram of a third structure of a display panel provided in an embodiment of the present application.

[0017] FIG2 b is a schematic diagram of a fourth structure of a display panel provided in an embodiment of the present application.

[0018] FIG3 is a schematic diagram of the combined structure of a base substrate and a buffer layer in a display panel provided by an embodiment of the present application.

[0019] FIG4 is a schematic diagram of the combined structure of a base substrate, a buffer layer, and a light shielding layer in a display panel provided by an embodiment of the present application.

[0020] FIG5 is a schematic diagram showing the distribution structure of the light shielding layer in the display area and the frame area of ​​the display panel provided by an embodiment of the present application.

[0021] FIG6 is a schematic diagram of the distribution structure of the light-blocking layer in the display area and the frame area of ​​the display panel provided by an embodiment of the present application.

[0022] Description of reference numerals:

[0023] 1. Display panel, 11. Display area, 12. Frame area;

[0024] 10. First substrate, 110. Base substrate, 111. Buffer layer, 1111. Accommodating groove, 112. Barrier layer, 1131. First gate insulating layer, 1132. Second gate insulating layer, 1141. First interlayer insulating layer, 1142. Second interlayer insulating layer, 115. Color resist layer, 1151. Red photoresist unit, 1152. Green photoresist unit, 1153. Blue photoresist unit, 1161. First planarization layer, 1162. Second planarization layer, 117. Pixel electrode layer, 1171. Pixel electrode, 118. Passivation layer, 119. Common electrode layer, 1191. Common electrode;

[0025] 120, light-shielding layer, 121, first light-shielding trace, 122, second light-shielding trace, 123, third light-shielding trace;

[0026] 131. First thin film transistor, 1311. First active layer, 1311a. First channel portion, 1311b. First conductor portion, 1312. First gate electrode, 1313. First source electrode, 1314. First drain electrode, 132. Second thin film transistor, 1321. Second active layer, 1321a. Second channel portion, 1321b. Second conductor portion, 1322. Second gate electrode, 1323. Second source electrode, 1324. Second drain electrode.

[0027] 140, light blocking layer, 141, first light blocking trace, 142, second light blocking trace, 143, third light blocking trace;

[0028] 20. Second substrate, 21. Support pillar, 22. Encapsulation layer;

[0029] X, thickness direction. Modes for Carrying Out the Invention

[0030] The following detailed description of the embodiments of the present application is made in conjunction with the accompanying drawings to fully introduce the technical content of the present application to those skilled in the art, to illustrate that the present application can be implemented, to make the technical content disclosed in the present application clearer, and to make it easier for those skilled in the art to understand how to implement the present application. However, the present application can be embodied in many different forms of embodiments, and the scope of protection of the present application is not limited to the embodiments mentioned herein. The description of the embodiments below is not intended to limit the scope of the present application.

[0031] The directional terms mentioned in this application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate this application, and are not used to limit the scope of protection of this application.

[0032] In the drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for the sake of ease of understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and this application does not limit the size and thickness of each component.

[0033] In some embodiments of the present application, a display device is provided, including a display panel 1 .

[0034] In some embodiments of the present application, a display panel 1 is provided. Display panel 1 is a liquid crystal display panel, and display panel 1 is used as the display panel in a VR display. Referring to Figures 1a, 1b, and 3 through 6, display panel 1 includes a first substrate 10 and a second substrate 20 disposed opposite each other. A liquid crystal layer (not shown) is disposed between first substrate 10 and second substrate 20. The liquid crystal layer comprises a plurality of liquid crystal molecules. Display panel 1 includes a display area 11 and a border area 12. Border area 12 is disposed on at least one side of display area 11.

[0035] In some embodiments of the present application, referring to FIG. 1 a and FIG. 1 b , the first substrate 10 includes: a base substrate 110 , a light shielding layer 120 and a thin film transistor.

[0036] Referring to Figures 1a and 1b , the first substrate 10 is an array substrate, and the second substrate 20 is a color filter (CF) substrate. The base substrate 110 has a thickness direction X. The first substrate 10 further includes a buffer layer 111, a barrier layer 112, an insulating layer, a color resist layer 115, and a planarization layer stacked along the thickness direction X on the surface of the base substrate 110. Specifically, in the embodiment shown in Figures 1a and 1b , the insulating layer includes a first gate insulating layer 1131 and a first interlayer insulating layer 1141 stacked along the thickness direction X, and the planarization layer includes a first planarization layer 1161. The barrier layer 112 provides a barrier to external moisture, preventing moisture from entering the thin film transistor. The color resist layer 115 includes a red photoresist unit 1151, a green photoresist unit 1152, and a blue photoresist unit (not shown).

[0037] 1a and 1b , the thin film transistor includes a first thin film transistor 131, which is disposed in the display area 11. The first thin film transistor 131 includes a first active layer 1311, a first gate electrode 1312, and a first source and drain electrode. The first active layer 1311 is disposed on a side of the barrier layer 112 facing away from the buffer layer 111 in the thickness direction X. A first gate insulating layer 1131 covers the first active layer 1311. The first active layer 1311 includes a first channel portion 1311a and two conductor portions 1311b, one on either side of the first channel portion 1311a. "Located on either side of the first channel portion 1311a" refers to two sides parallel to the surface of the substrate 110. The first gate electrode 1312 is insulated and spaced apart above the side of the first active layer 1311 facing away from the substrate 110 in the thickness direction X. Specifically, the first gate 1312 is arranged on the side of the first gate insulating layer 1131 that is away from the base substrate 110 in the thickness direction X. The first gate 1312 is insulated from the first active layer 1311 by the first gate insulating layer 1131 and arranged at intervals. The first interlayer insulating layer 1141 covers the first gate 1312. The first source and drain include a first source 1313 and a first drain 1314 that are arranged in the same layer and at intervals. The first source and drain are arranged on the side of the first interlayer insulating layer 1141 that is away from the first gate insulating layer 1131 in the thickness direction X. The color resist layer 115 covers the first source and drain.

[0038] Among them, the orthographic projection of the first gate 1312 on the base substrate 110 and the orthographic projection of the first source and drain on the base substrate 110 intersect with each other to form a grid shape, and a through hole is opened on the first interlayer insulating layer 1141, which passes through the first interlayer insulating layer 1141 and the first gate insulating layer 1131 in sequence along the thickness direction X. The through hole exposes the first conductor portion 1311b, and the first source 1313 is connected to one first conductor portion 1311b through a through hole, and the first drain 1314 is connected to another first conductor portion 1311b through another through hole.

[0039] In the embodiment shown in FIG1a and FIG1b , the first active layer 1311 in the first thin film transistor 131 is low temperature poly-silicon (LTPS), the first thin film transistor 131 is a low temperature poly-silicon thin film transistor, and the display panel 1 is an LTPS-VR display panel.

[0040] Referring to Figures 1a and 1b, a light-shielding layer 120 is disposed between the base substrate 110 and the thin-film transistor. Specifically, the light-shielding layer 120 is disposed in the buffer layer 111 and includes a first light-shielding trace 121 and a second light-shielding trace 122. Both the first light-shielding trace 121 and the second light-shielding trace 122 are disposed in the display area 11. Referring to Figure 5, the first light-shielding trace 121 and the second light-shielding trace 122 intersect to form a grid. Specifically, the orthographic projections of the first light-shielding trace 121 and the second light-shielding trace 122 on the base substrate 110 intersect to form a grid.

[0041] In some embodiments, referring to Figures 1a and 5, a plurality of first thin film transistors 131 can be set in the display area 11, and one first thin film transistor 131 corresponds in quantity to one first light-shielding trace 121 and two second light-shielding traces 122. Specifically, the orthographic projection of the first gate 1312 on the base substrate 110 falls within the orthographic projection of the first light-shielding trace 121 on the base substrate 110, the orthographic projection of the first source 1313 in the first source and drain electrodes on the base substrate 110 falls within the orthographic projection of one second light-shielding trace 122 on the base substrate 110, and the orthographic projection of the first drain 1314 on the base substrate 110 falls within the orthographic projection of another second light-shielding trace 122 on the base substrate 110.

[0042] In some embodiments, referring to Figure 1b, the orthographic projection of the first gate 1312 on the base substrate 110 falls within the orthographic projection of the first light-shielding trace 121 on the base substrate 110, and the orthographic projection of the first source and drain on the base substrate 110 is located within the orthographic projection of the first light-shielding trace 121 on the base substrate 110.

[0043] In some embodiments, the orthographic projection of the first gate 1312 on the base substrate 110 falls within the orthographic projection of the second light-shielding trace 122 on the base substrate 110 , and the orthographic projection of the first source and drain on the base substrate 110 is located within the orthographic projection of the first light-shielding trace 121 on the base substrate 110 .

[0044] Generally, LTPS-VR display panels and LTPO-VR display panels are limited by the high PPI (resolution) structural design, and the in-plane aperture ratio is lower than that of conventional products, resulting in low brightness. At this stage, brightness compensation is carried out by increasing the backlight brightness, but the high backlight brightness causes the channel leakage current to deteriorate, resulting in poor crosstalk resistance of VR products.

[0045] Furthermore, due to the extremely small pixel size of VR display panels (a single pixel is approximately 5 μm), the alignment and lamination of the second substrate 20 to the first substrate 10 requires much higher precision than conventional products, making it very susceptible to color shift and uneven illumination caused by misalignment. This problem can be addressed through lamination precision optimization and a COA (CF on Array) structure, but lamination precision is limited by equipment capabilities, leaving limited room for improvement. Furthermore, the black matrix (BM) on the array side of the COA structure is typically made of materials such as an organic BM layer, a metal low-reflectivity stacked BM, or a low-reflectivity oxide (BMO). While this can significantly improve color shift, a certain failure rate still exists.

[0046] The display panel 1 provided in the embodiment of the present application, through the grid structure of the first light-shielding traces 121 and the second light-shielding traces 122, blocks the light from the backlight in the upward direction (X direction) that directly hits the lower surface of the first gate 1312 and the lower surface of the first source and drain, reduces the reflected light intensity of the first gate 1312 and the first source and drain, avoids the phenomenon of leakage current caused by reflected light, improves the anti-crosstalk capability, and enhances the display quality of the display panel.

[0047] Furthermore, the display panel 1 provided in the embodiments of the present application incorporates a color-resistance layer 115 within the first substrate 10, forming a COA (CF on Array) structural design. Referring to Figures 1a and 1b and Figures 2a and 2b, the color-resistance layer 115 is disposed on the side of the first source and drain electrodes facing away from the first gate electrode 1312 in the thickness direction X, and the color-resistance layer 115 covers the first source and drain electrodes. The combination of the color-resistance layer 115 and the light-shielding layer 120 can improve color shift and uneven light emission in the display panel 1.

[0048] In some embodiments, the light shielding layer 120 is made of a metal oxide, or alternatively, the light shielding layer 120 is made of a stacked metal layer and a non-metallic dielectric layer. Specifically, the metal oxide is a high-temperature-resistant, low-reflectivity metal oxide, thereby enabling the first light shielding traces 121 and the second light shielding traces 122 in the light shielding layer 120 to have a low reflectivity. This prevents light-induced leakage current caused by backlight and light reflected from the upper metal layer being reflected from the surface of the light shielding layer 120 to the first channel portion 1311a of the first active layer 1311, thereby improving crosstalk resistance and enhancing the display quality of the display panel.

[0049] In some embodiments, referring to Figures 1a and 1b, in the first active layer 1311, the orthographic projections of the two first conductor portions 1311b on the base substrate 110 and the orthographic projection of the first channel portion 1311a on the base substrate 110 are both located within the orthographic projection of the first light-shielding trace 121 on the base substrate 110.

[0050] In some embodiments, in the first active layer 1311 , the orthographic projections of the two first conductor portions 1311 b and the orthographic projection of the first channel portion 1311 a on the base substrate 110 are both located within the orthographic projection of the second light-shielding trace 122 on the base substrate 110 .

[0051] In some embodiments, only the orthographic projection of the first channel portion 1311 a on the base substrate 110 is located within the orthographic projection of the first light-shielding trace 121 on the base substrate 110 .

[0052] In some embodiments, only the orthographic projection of the first channel portion 1311 a on the base substrate 110 is located within the orthographic projection of the second light-shielding trace 122 on the base substrate 110 .

[0053] In some embodiments, referring to Figures 1a, 1b, and 6, the display panel 1 further includes a light-blocking layer 140. The light-blocking layer 140 is disposed on a side of the thin-film transistor facing away from the base substrate 110 in the thickness direction X, and the light-blocking layer 140 includes a first light-blocking trace 141 and a second light-blocking trace 142. Referring to Figure 6, the first light-blocking trace 141 and the second light-blocking trace 142 are disposed in the display area 11. Specifically, referring to Figures 1a, 1b, and 2a and 2b, the display panel 1 further includes a pixel electrode layer 117, a passivation layer 118, and a common electrode layer 119. The pixel electrode layer 117 is disposed in the display area 11. The pixel electrode layer 117 includes a plurality of pixel electrodes 1171 arranged at intervals, and the pixel electrode layer 117 is disposed on a side of the first planarization layer 1161 facing away from the color resist layer 115 in the thickness direction X. The passivation layer 118 is disposed on a side of the pixel electrode layer 117 facing away from the first planarization layer 1161 in the thickness direction X. The common electrode layer 119 is disposed on the side of the passivation layer 118 facing away from the pixel electrode layer 117 in the thickness direction X. The common electrode layer 119 includes a plurality of spaced common electrodes 1191. A through hole is defined on the side of the first planarization layer 1161 facing away from the color resist layer 115 in the thickness direction X, penetrating the first planarization layer 1161 and the color resist layer 115. The pixel electrode 1171 is connected to the first drain electrode 1314 through the through hole. The passivation layer 118 and the common electrode 1191 are stacked and filled in the through hole. The through hole is also filled with a second planarization layer 1162, which extends along the thickness direction X. The end surface of the second planarization layer 1162 facing away from the first drain electrode 1314 in the thickness direction X is flush with the side of the common electrode 1191 facing away from the passivation layer 118. The first light-blocking trace 141 is arranged on the side of the common electrode 1191 away from the passivation layer 118. The first light-blocking trace 141 and the first light-shielding trace 121 are arranged opposite to each other along the thickness direction X. The second light-blocking trace 142 and the second light-shielding trace 122 are arranged opposite to each other along the thickness direction X. The orthographic projection of the first light-blocking trace 141 on the base substrate 110 and the orthographic projection of the second light-blocking trace 142 on the base substrate 110 intersect with each other to form a grid.

[0054] In some embodiments, referring to Figures 1a and 1b and Figures 2a and 2b, the orthographic projection of the first gate 1312 on the base substrate 110 is located within the orthographic projection of the first light-blocking trace 141 on the base substrate 110, and the orthographic projection of the first source and drain on the base substrate 110 is located within the orthographic projection of the first light-blocking trace 141 on the base substrate 110.

[0055] In some embodiments, the orthographic projection of the first gate 1312 on the base substrate 110 is located within the orthographic projection of the second light-blocking trace 142 on the base substrate 110, and the orthographic projection of the first source and drain on the base substrate 110 is located within the orthographic projection of the second light-blocking trace 142 on the base substrate 110.

[0056] In some embodiments, one first thin film transistor 131 corresponds in number to one first light-blocking trace 141 and two second light-blocking traces 142. Specifically, the orthographic projection of the first gate electrode 1312 on the base substrate 110 falls within the orthographic projection of the first light-blocking trace 141 on the base substrate 110, the orthographic projection of the first source electrode 1313 of the first source and drain electrodes on the base substrate 110 falls within the orthographic projection of one second light-blocking trace 142 on the base substrate 110, and the orthographic projection of the first drain electrode 1314 on the base substrate 110 falls within the orthographic projection of another second light-blocking trace 142 on the base substrate 110.

[0057] The display panel 1 provided in the embodiment of the present application has a color resist layer 115 arranged in the first substrate 10 to form a COA (CF On Array) structure, and a light shielding layer 120 and a light blocking layer 140 are simultaneously arranged in the first substrate 10. The light shielding layer 120 blocks the light emitted upward by the backlight, and can form a reflection of the light emitted by the backlight by the upper metal layer (such as the first gate 1312 and the first source and drain). The first light blocking line 141 and the second light blocking line 142 in the light blocking layer 140 cross to form a grid structure to block the upper surface of the first source and drain and the first gate 1312, forming a COA+double light shielding (light shielding layer 120+light blocking layer 140) structural design, which can effectively solve the problems of uneven light leakage and color deviation of metal. The light blocking layer 140 and the light shielding layer 120 are aligned to effectively avoid color deviation caused by lamination deviation, thereby improving the display quality of the display panel 1.

[0058] In some embodiments of the present application, referring to FIG. 2 a and FIG. 2 b , a base substrate 110 includes a base substrate 110, a buffer layer 111, a barrier layer 112, an insulating layer, a color resist layer 115, a first planarization layer 1161, a pixel electrode layer 117, a passivation layer 118, and a common electrode layer 119 stacked along a thickness direction X. The insulating layer includes a first gate insulating layer 1131, a first interlayer insulating layer 1141, a second gate insulating layer 1132, and a second interlayer insulating layer 1142 stacked along the thickness direction X. The color resist layer 115 includes a blue photoresist unit 1153, a red photoresist unit 1151, and a green photoresist unit 1152 arranged in sequence.

[0059] The thin film transistors include a first thin film transistor 131 and a second thin film transistor 132 that are spaced apart. The first thin film transistor 131 is a driving thin film transistor, and the second thin film transistor 132 is a switching thin film transistor.

[0060] 2a and 2b , the first active layer 1311 in the first thin-film transistor 131 is a low-temperature polycrystalline oxide (LTPO) active layer. The first thin-film transistor 131 is disposed in the display area 11, and the first gate electrode 1312 in the first thin-film transistor 131 is disposed below the first active layer 1311 in the thickness direction X. Specifically, the first gate electrode 1312 is disposed on a side of the first gate insulating layer 1131 facing away from the barrier layer 112 in the thickness direction X. The first active layer 1311 is disposed on a side of the first interlayer insulating layer 1141 facing away from the first gate insulating layer 1131 in the thickness direction X. The first source and drain electrodes are disposed on a side of the second interlayer insulating layer 1142 facing away from the second gate insulating layer 1132 in the thickness direction X.

[0061] Referring to Figures 2a and 2b , the second thin-film transistor 132 is disposed in the border region 12 and includes a second active layer 1321, a second gate electrode 1322, and a second source and drain electrode. The second active layer 1321 is disposed on the side of the barrier layer 112 facing away from the buffer layer 111 in the thickness direction X. The first gate insulating layer 1131 covers the second active layer 1321. The second active layer 1321 is a low-temperature polycrystalline silicon (LTPS) active layer and includes a second channel portion 1321a and a second conductor portion 1321b. There are two second conductor portions 1321b, one on either side of the second channel portion 1321a. "Located on either side of the second channel portion 1321a" refers to two sides parallel to the surface of the base substrate 110. The second gate electrode 1322 is insulated and spaced apart above the side of the second active layer 1321 facing away from the base substrate 110 in the thickness direction X. Specifically, the second gate 1322 is disposed on a side of the first gate insulating layer 1131 facing away from the substrate 110 in the thickness direction X. The second gate 1322 is insulated from the second active layer 1321 by the first gate insulating layer 1131 and spaced apart from each other. The first interlayer insulating layer 1141 covers the second gate 1322. The second source and drain electrodes include a second source electrode 1323 and a second drain electrode 1324 spaced apart from each other. The second source and drain electrodes are disposed on a side of the second gate insulating layer 1132 facing away from the first interlayer insulating layer 1141 in the thickness direction X. The second interlayer insulating layer 1142 covers the first source and drain electrodes. Among them, a through hole is opened on the second gate insulation layer 1132, which passes through the second gate insulation layer 1132, the first interlayer insulation layer 1141 and the first gate insulation layer 1131 in sequence along the thickness direction X, and the through hole exposes the second conductor part 1321b. The second source 1323 is connected to one second conductor part 1321b through a through hole, and the second drain 1324 is connected to another second conductor part 1321b through another through hole.

[0062] In some embodiments of the present application, the light-shielding layer 120 includes a third light-shielding trace 123, which is disposed in the frame region 12. The third light-shielding trace 123 is disposed opposite the second active layer 1321 along the thickness direction X. In the embodiments shown in Figures 2a and 2b, the orthographic projections of the two second conductor portions 1321b in the second active layer 1321 on the projection plane and the orthographic projection of the second channel portion 1321a on the base substrate 110 are both located within the orthographic projection of the third light-shielding trace 123 on the base substrate 110, at least a portion of the orthographic projection of the second gate 1322 on the base substrate 110 is located within the orthographic projection of the third light-shielding trace 123 on the projection plane, and at least a portion of the orthographic projection of the second source and drain on the base substrate 110 falls within the orthographic projection of the third light-shielding trace 123 on the base substrate 110. A third light-shielding trace 123 is provided in the border area 12 to shield the second source and drain electrodes and the second gate electrode 1322 of the second thin-film transistor 132 in the border area 12 , thereby effectively solving the problems of uneven light leakage and color deviation of metal in the border area 12 and improving the display quality of the display panel 1 .

[0063] In some embodiments of the present application, the light-blocking layer 140 further includes a third light-blocking trace 143, which is disposed in the border area 12, and at least a portion of the orthographic projection of the second source and drain electrodes on the substrate 110 is located within the orthographic projection of the third light-blocking trace 143 on the substrate 110, and at least a portion of the orthographic projection of the second gate electrode 1322 on the substrate 110 is located within the orthographic projection of the third light-blocking trace 143 on the substrate 110. Referring to Figure 6, the orthographic projection of the border area 12 on the substrate 110 is located within the orthographic projection of the third light-blocking trace 143 on the substrate 110. Providing the third light-blocking trace 143 in the border area 12 can achieve shielding of the second source and drain electrodes in the second thin-film transistor 132 located in the border area 12 and the upper surface of the second gate electrode 1322, which can effectively solve the problems of uneven light leakage and color deviation of metal light in the border area 12, and improve the display quality of the display panel 1.

[0064] In addition, referring to Figures 1a and 1b and Figures 2a and 2b, the display panel 1 further includes a support column 21 and an encapsulation layer 22. The support column 21 is provided in the display area 11, and the support column 21 extends along the thickness direction X. One end of the support column 21 abuts against a side of the light-blocking layer 140 facing the second substrate 20 in the thickness direction X, and the other end of the support column 21 abuts against a side of the second substrate 20 facing the first substrate 10. The encapsulation layer 22 is provided in the frame area 12, and one end of the encapsulation layer 22 abuts against the third light-blocking trace 143 in the thickness direction X, and the other end of the encapsulation layer 22 abuts against a side of the second substrate 20 facing the first substrate 10 in the thickness direction X to form an encapsulation.

[0065] In some embodiments of the present application, the light blocking layer 140 is made of metal oxide.

[0066] In some embodiments of the present application, the light blocking layer 140 includes a metal layer and a non-metal dielectric layer stacked together.

[0067] In some embodiments of the present application, the metal oxide is a high-temperature resistant and low-reflectivity metal oxide, and the metal oxide includes one of molybdenum oxide (MoO3), copper oxide (CuO), silver oxide (Ag2O), tungsten oxide (WO3) and titanium oxide (TiO2).

[0068] In some embodiments of the present application, the metal in the metal layer includes one of molybdenum (Mo), copper (Cu), silver (Ag), tungsten (W), and titanium (Ti).

[0069] In some embodiments of the present application, the non-metallic medium in the non-metallic medium layer includes silicon oxide (SiN x ), silicon oxide (SiO x ) and one of indium tin oxide (ITO).

[0070] In some embodiments of the present application, referring to FIG3 , a receiving groove 1111 is formed on the buffer layer 111. Referring to FIG4 , the light shielding layer 120 is received in the receiving groove 1111. The provision of the receiving groove 1111 allows the light shielding layer 120 to be embedded in the receiving groove 1111, thereby ensuring that the side of the light shielding layer 120 facing away from the base substrate 110 in the thickness direction X is flush with the side of the light shielding layer 120 facing away from the base substrate 110 in the thickness direction X, thereby ensuring the overall flatness of the display panel 1 and the display quality.

[0071] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, comprising a display area and a frame area arranged on at least one side of the display area, the display panel further comprising a first substrate and a second substrate arranged opposite to each other, the first substrate comprising a base substrate and a plurality of thin film transistors arranged on the base substrate at intervals, the plurality of thin film transistors comprising a first thin film transistor arranged in the display area, the first thin film transistor comprising a first gate and a first source and drain, the first source and drain being insulated and arranged at intervals above a side of the first gate away from the base substrate in a thickness direction of the first substrate; The display panel further includes: A light shielding layer is disposed between the base substrate and the first gate, and the light shielding layer includes a first light shielding wiring and a second light shielding wiring disposed in the display area; A color resist layer is disposed in the first substrate, and the color resist layer is disposed on a side of the first source and drain electrode that is away from the first gate electrode in the thickness direction; Wherein, the orthographic projection of the first light-shielding wiring on the substrate and the orthographic projection of the second light-shielding wiring on the substrate cross each other to form a grid shape; The orthographic projection of the first gate on the base substrate is located within the orthographic projection of the first light-shielding trace on the base substrate, or the orthographic projection of the first gate on the base substrate is located within the orthographic projection of the second light-shielding trace on the base substrate; At least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the first light-shielding trace on the substrate, or at least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the second light-shielding trace on the substrate.

2. The display panel according to claim 1, wherein: The first thin film transistor further includes a first active layer; Along the thickness direction, the first active layer is arranged between the first gate layer and the light shielding layer, or, along the thickness direction, the first active layer is arranged between the first source and drain and the first gate; Wherein, at least a portion of the orthographic projection of the first active layer on the base substrate falls within the orthographic projection of the first light-shielding trace on the base substrate.

3. The display panel according to claim 2, wherein: The first substrate further comprises a buffer layer, a barrier layer and an insulating layer stacked on the base substrate along the thickness direction, the color-resist layer is arranged on a side of the first source and drain electrode away from the insulating layer in the thickness direction; the first light-shielding trace and the second light-shielding trace are respectively arranged on a side of the buffer layer away from the base substrate in the thickness direction, and the barrier layer covers the first light-shielding trace and the second light-shielding trace; The first gate is arranged in the insulating layer, the first source and drain are arranged on a side of the insulating layer away from the blocking layer in the thickness direction, and the color resist layer covers the first source and drain; The first active layer is arranged on a side of the barrier layer away from the buffer layer in the thickness direction, and the insulating layer covers the first active layer, or the first active layer is arranged in the insulating layer.

4. The display panel according to claim 3, wherein: The display panel further includes a light blocking layer, the light blocking layer is arranged on a side of the first substrate facing the second substrate, and the light blocking layer includes a first light blocking wiring and a second light blocking wiring arranged in the display area; The orthographic projection of the first light-blocking wiring on the base substrate and the orthographic projection of the second light-blocking wiring on the base substrate intersect with each other to form a grid shape; The orthographic projection of the first gate on the base substrate is located within the orthographic projection of the first light-blocking wiring on the base substrate, or the orthographic projection of the first gate on the base substrate is located within the orthographic projection of the second light-blocking wiring on the base substrate; At least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the first light-blocking trace on the substrate, or at least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the second light-blocking trace on the substrate.

5. The display panel according to claim 4, wherein: The display panel further comprises a planarization layer and a passivation layer stacked along the thickness direction and arranged on a side of the color resist layer away from the insulating layer; The display panel further comprises a common electrode layer, the common electrode layer is arranged on a side of the passivation layer away from the planar layer in the thickness direction, and the common electrode layer comprises a plurality of common electrodes arranged at intervals; The light-blocking layer is disposed on a side of the passivation layer away from the flat layer in the thickness direction. Along the thickness direction, at least one of the first light-blocking wiring and the second light-blocking wiring is disposed on a side of the common electrode away from the passivation layer.

6. The display panel according to claim 4, wherein: The thin film transistor further comprises a second thin film transistor disposed in the border region, the second thin film transistor comprising a second gate electrode and a second source and drain electrode, the second source and drain electrode being insulated and spaced apart and disposed above a side of the second gate electrode away from the substrate in the thickness direction; The light shielding layer further includes a third light shielding wiring, the third light shielding wiring is arranged in the frame area, the third light shielding wiring is arranged on a side of the buffer layer away from the base substrate in the thickness direction, and the barrier layer covers the third light shielding wiring; Wherein, the orthographic projection of the second gate on the base substrate falls within the orthographic projection of the third light-shielding trace on the base substrate; At least a portion of the orthographic projection of the second source and drain on the base substrate falls within the orthographic projection of the third light-shielding trace on the base substrate.

7. The display panel according to claim 4, wherein: The thin film transistor further comprises a second thin film transistor disposed in the border region, the second thin film transistor comprising a second gate electrode and a second source and drain electrode, the second source and drain electrode being insulated and spaced apart and disposed above a side of the second gate electrode away from the substrate in the thickness direction; The light shielding layer further includes a third light shielding wiring, the third light shielding wiring is arranged in the frame area, the third light shielding wiring is arranged on a side of the buffer layer away from the base substrate in the thickness direction, and the barrier layer covers the third light shielding wiring; Wherein, the orthographic projection of the second gate on the base substrate falls within the orthographic projection of the third light-shielding trace on the base substrate; Alternatively, at least a portion of the orthographic projection of the second source and drain on the base substrate falls within the orthographic projection of the third light-shielding trace on the base substrate.

8. The display panel according to claim 6 or 7, wherein: The light-blocking layer further includes a third light-blocking wiring, and the third light-blocking wiring is arranged in the frame area; At least part of the orthographic projection of the second gate on the base substrate falls within the orthographic projection of the third light-blocking trace on the base substrate; At least a portion of the orthographic projection of the second source and drain on the base substrate falls within the orthographic projection of the third light-blocking trace on the base substrate.

9. The display panel according to claim 8, wherein: The third light-blocking wiring surrounds the display area along a circumferential direction of the display area.

10. The display panel according to claim 6, wherein: The buffer layer is provided with a receiving groove, and the light shielding layer is arranged in the receiving groove.

11. The display panel according to claim 1, wherein: The material of the light shielding layer includes metal oxide, or the light shielding layer includes a metal layer and a non-metallic dielectric layer stacked.

12. The display panel according to claim 4, wherein: The material of the light-blocking layer includes metal oxide, or the light-blocking layer includes a metal layer and a non-metallic dielectric layer stacked in layers.

13. The display panel according to claim 11 or 12, wherein: The material of the metal oxide includes any one of molybdenum oxide, copper oxide, silver oxide, tungsten oxide and titanium oxide, the material of the metal layer includes any one of molybdenum, copper, silver, tungsten and titanium, and the non-metallic dielectric layer includes any one of silicon nitride, silicon oxide and indium tin oxide.

14. A display device, comprising a display panel, the display panel comprising a display area and a frame area arranged on at least one side of the display area, the display panel further comprising a first substrate and a second substrate arranged opposite to each other, the first substrate comprising a base substrate and a plurality of thin film transistors arranged on the base substrate at intervals, the plurality of thin film transistors comprising a first thin film transistor arranged in the display area, the first thin film transistor comprising a first gate and a first source and drain, the first source and drain being insulated and arranged at intervals above a side of the first gate facing away from the base substrate in a thickness direction of the first substrate; The display panel further includes: A light shielding layer is disposed between the base substrate and the first gate, and the light shielding layer includes a first light shielding wiring and a second light shielding wiring disposed in the display area; A color resist layer is disposed in the first substrate, and the color resist layer is disposed on a side of the first source and drain electrode that is away from the first gate electrode in the thickness direction; Wherein, the orthographic projection of the first light-shielding wiring on the substrate and the orthographic projection of the second light-shielding wiring on the substrate cross each other to form a grid shape; The orthographic projection of the first gate on the base substrate is located within the orthographic projection of the first light-shielding trace on the base substrate, or the orthographic projection of the first gate on the base substrate is located within the orthographic projection of the second light-shielding trace on the base substrate; At least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the first light-shielding trace on the substrate, or at least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the second light-shielding trace on the substrate.

15. The display device according to claim 14, wherein: The first thin film transistor further includes a first active layer; Along the thickness direction, the first active layer is arranged between the first gate layer and the light shielding layer, or, along the thickness direction, the first active layer is arranged between the first source and drain and the first gate; Wherein, at least a portion of the orthographic projection of the first active layer on the base substrate falls within the orthographic projection of the first light-shielding trace on the base substrate.

16. The display device according to claim 15, wherein: The first substrate further comprises a buffer layer, a barrier layer and an insulating layer stacked on the base substrate along the thickness direction, the color-resist layer is arranged on a side of the first source and drain electrode away from the insulating layer in the thickness direction; the first light-shielding trace and the second light-shielding trace are respectively arranged on a side of the buffer layer away from the base substrate in the thickness direction, and the barrier layer covers the first light-shielding trace and the second light-shielding trace; The first gate is arranged in the insulating layer, the first source and drain are arranged on a side of the insulating layer away from the blocking layer in the thickness direction, and the color resist layer covers the first source and drain; The first active layer is arranged on a side of the barrier layer away from the buffer layer in the thickness direction, and the insulating layer covers the first active layer, or the first active layer is arranged in the insulating layer.

17. The display device according to claim 16, wherein: The display panel further includes a light blocking layer, the light blocking layer is arranged on a side of the first substrate facing the second substrate, and the light blocking layer includes a first light blocking wiring and a second light blocking wiring arranged in the display area; The orthographic projection of the first light-blocking wiring on the base substrate and the orthographic projection of the second light-blocking wiring on the base substrate intersect with each other to form a grid shape; The orthographic projection of the first gate on the base substrate is located within the orthographic projection of the first light-blocking wiring on the base substrate, or the orthographic projection of the first gate on the base substrate is located within the orthographic projection of the second light-blocking wiring on the base substrate; At least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the first light-blocking trace on the substrate, or at least part of the orthographic projection of the first source and drain on the substrate is located within the orthographic projection of the second light-blocking trace on the substrate.

18. The display device according to claim 17, wherein: The thin film transistor further comprises a second thin film transistor disposed in the border region, the second thin film transistor comprising a second gate electrode and a second source and drain electrode, the second source and drain electrode being insulated and spaced apart and disposed above a side of the second gate electrode away from the substrate in the thickness direction; The light shielding layer further includes a third light shielding wiring, the third light shielding wiring is arranged in the frame area, the third light shielding wiring is arranged on a side of the buffer layer away from the base substrate in the thickness direction, and the barrier layer covers the third light shielding wiring; Wherein, the orthographic projection of the second gate on the base substrate falls within the orthographic projection of the third light-shielding trace on the base substrate; At least a portion of the orthographic projection of the second source and drain on the base substrate falls within the orthographic projection of the third light-shielding trace on the base substrate.

19. The display device according to claim 18, wherein: The light-blocking layer further includes a third light-blocking wiring, and the third light-blocking wiring is arranged in the frame area; At least part of the orthographic projection of the second gate on the base substrate falls within the orthographic projection of the third light-blocking trace on the base substrate; At least a portion of the orthographic projection of the second source and drain on the base substrate falls within the orthographic projection of the third light-blocking trace on the base substrate.

20. The display device according to claim 18, wherein: The buffer layer is provided with a receiving groove, and the light shielding layer is arranged in the receiving groove.

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