Array substrate and driving method therefor, display panel, and display device

Abstract

An array substrate, comprising: a base substrate (101); a plurality of pixel electrodes (102) arranged in an array on the base substrate; a plurality of gate lines (103) extending in a first direction (X) at gaps among the pixel electrodes (102), wherein each gate line (103) comprises a bent portion (1031) protruding towards the side where an adjacent pixel electrode (102) is located, two gate lines (103) are provided at a gap between two pixel electrodes (102) arranged in a second direction (Y), the bent portions (1031) of the two gate lines (103) are opposite to each other to form an accommodating space (AS), and the second direction (Y) intersects with the first direction (X); a plurality of data lines (104) extending in the second direction (Y) at the gaps among the pixel electrodes (102), the orthographic projection of each data line (104) on the base substrate (101) penetrating the orthographic projection of the corresponding accommodating space (AS); and a plurality of transistors (105) located at a gap between two adjacent pixel electrodes (102) arranged in the second direction (Y), the orthographic projections of the transistors (105) on the base substrate (101) overlapping the orthographic projections of the gate lines (103), wherein first electrodes (s) of the transistors (105) are coupled to the data lines (104), and the orthographic projections of the first electrodes (s) of the transistors (105) on the base substrate (101) are partially located within the orthographic projection of the accommodating space (AS). Further provided are a driving method for the array substrate, a display panel and a display device.

Description

Array substrate, driving method thereof, display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on November 13, 2023, with application number 202311501538.6 and invention name "Array substrate, driving method thereof, display panel and display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, a display panel, and a display device. Background Art

[0004] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0005] Summary of the Invention

[0006] The present disclosure provides an array substrate, a driving method thereof, a display panel, and a display device. The specific solutions are as follows:

[0007] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0008] substrate;

[0009] A plurality of pixel electrodes are arranged in an array on the base substrate;

[0010] a plurality of gate lines extending along a first direction at the gaps between the pixel electrodes, the gate lines including a bent portion protruding toward the side where the adjacent pixel electrode is located, two gate lines being provided at the gaps between two adjacent pixel electrodes arranged along a second direction, the bent portions of the two gate lines being opposite to each other to form an accommodation space, and the second direction intersecting the first direction;

[0011] a plurality of data lines extending along the second direction at the gaps between the pixel electrodes, wherein the orthographic projections of the data lines on the base substrate pass through the orthographic projections of the accommodating spaces on the base substrate;

[0012] A plurality of transistors are located in a gap between two adjacent pixel electrodes arranged along the second direction, wherein the orthographic projections of the transistors on the base substrate overlap with the orthographic projections of the gate lines on the base substrate; the first electrodes of the transistors are coupled to the data lines, and a portion of the orthographic projections of the first electrodes of the transistors on the base substrate is located within the orthographic projection of the accommodating space on the base substrate.

[0013] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes at least one bridge line, the orthographic projection of the data line on the base substrate and the orthographic projection of the gate line on the base substrate have multiple overlapping areas, at least one of the data lines is missing in at least one of the overlapping areas, and the bridge line is connected to the data line in the accommodating space and the data line between two adjacent pixel electrodes arranged along the first direction.

[0014] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, at least one of the first electrode, the second electrode, and the active layer of at least one of the transistors is short-circuited with the gate line, and the first electrode of the at least one transistor is disconnected within the accommodating space.

[0015] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, within the area where the same accommodating space is located, the data line is coupled to the first poles of the two transistors, and the coupling positions of the first poles of the two transistors and the data line are separated on both sides of the data line and staggered with each other in the second direction.

[0016] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a common voltage line and a plurality of compensation lines, wherein the plurality of compensation lines are coupled between the second poles of at least part of the transistors and at least part of the pixel electrodes, and the orthographic projections of the plurality of compensation lines on the base substrate at least partially overlap with the orthographic projections of the common voltage lines on the base substrate.

[0017] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the base substrate includes a plurality of red sub-pixel regions, a plurality of green sub-pixel regions, and a plurality of blue sub-pixel regions, and the plurality of pixel electrodes are located in the plurality of red sub-pixel regions, the plurality of green sub-pixel regions, and the plurality of blue sub-pixel regions;

[0018] The plurality of compensation lines are coupled to the pixel electrodes in the plurality of red sub-pixel regions and the plurality of green sub-pixel regions.

[0019] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of connecting lines coupled between the second electrode of the transistor and the pixel electrode, and the compensation line is integrally provided with at least part of the connecting lines.

[0020] In some embodiments, in the array substrate provided by an embodiment of the present disclosure, the connection line includes a first sub-connection line extending along the first direction, and the first sub-connection line is coupled between the second electrode of the transistor and the pixel electrode;

[0021] The compensation line is located on an extension line of at least one end of the first sub-connection line, and the compensation line and the first sub-connection line are integrally provided.

[0022] In some embodiments, in the above-mentioned array substrate provided in an embodiment of the present disclosure, the connecting line also includes a second sub-connecting line extending along the second direction, the second sub-connecting line is coupled between the first sub-connecting line and the pixel electrode, and the extension line of the second sub-connecting line passes through the central area of ​​the pixel electrode.

[0023] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the common voltage line includes a first sub-common voltage line extending along the first direction, and an extension line of the first sub-common voltage line passes through a central area of ​​the pixel electrode.

[0024] In some embodiments, in the above-mentioned array substrate provided by the embodiment of the present disclosure, the common voltage line also includes a hollow structure extending along the second direction, and the orthographic projection of the hollow structure on the base substrate covers the orthographic projection of the data line between adjacent pixel electrodes on the base substrate.

[0025] On the other hand, an embodiment of the present disclosure provides a display panel, including the above-mentioned array substrate provided by an embodiment of the present disclosure.

[0026] In some embodiments, the display panel provided in the embodiments of the present disclosure further includes an opposite substrate disposed opposite to the array substrate, wherein the opposite substrate includes a common electrode.

[0027] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, the opposing substrate further includes a plurality of red color resists, a plurality of green color resists, and a plurality of blue color resists located on the side of the common electrode away from the array substrate; wherein, in the vertical direction of the base substrate: the size of the blue color resist is larger than the size of the red color resist and the size of the green color resist, and the size of the red color resist is approximately the same as the size of the green color resist.

[0028] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present disclosure.

[0029] On the other hand, an embodiment of the present disclosure further provides a driving method for the above array substrate, wherein the nth (n is a positive integer) gate line and the (n+j)th gate line form a gate line group, j is greater than or equal to 2, and the same data line corresponding to the gate line group is connected to sub-pixels of the same color, and the driving method includes:

[0030] The gate line groups are sequentially driven, and the gate lines of the same gate line group are synchronously driven, and the driving durations of two adjacent gate line groups are partially the same; wherein,

[0031] During the driving process of the current gate line group, data signals are input to the data lines, and the input of data signals is stopped after the driving of the current gate line group is completed.

[0032] On the other hand, an embodiment of the present disclosure further provides a driving method for the above-mentioned array substrate, wherein four adjacent gate lines form a gate line group, the same data line corresponding to the odd-numbered gate lines is connected to sub-pixels of the same color, and the same data line corresponding to the even-numbered gate lines is connected to sub-pixels of the same color, and the driving method includes:

[0033] The gate line groups are driven sequentially, and the first gate line, the third gate line, the second gate line, and the fourth gate line are driven in the same gate line group in the order of the first gate line, the third gate line, the second gate line, and the fourth gate line; the driving durations of two adjacent gate lines are partially the same; wherein,

[0034] Before the driving of the first gate line is completed and during the driving of the third gate line, the first data signal is started to be input to the data line, and the input of the first data signal is stopped after the driving of the third gate line is completed; and before the driving of the second gate line is completed and during the driving of the fourth gate line, the second data signal is started to be input to the data line, and the input of the second data signal is stopped after the driving of the fourth gate line is completed, and the input time of the first data signal and the input time of the second data signal are staggered. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic diagram of a pixel arrangement of a dual-gate product provided by an embodiment of the present disclosure;

[0036] FIG2 is a schematic diagram of another structure of an array substrate provided in an embodiment of the present disclosure;

[0037] FIG3 is a schematic diagram of the enlarged structure of the Z region in FIG2 ;

[0038] FIG4 is a schematic diagram of the cross-sectional structure along line I-II in FIG3 ;

[0039] FIG5 is a schematic structural diagram of the layer where the gate lines are located in FIG2 ;

[0040] FIG6 is a schematic structural diagram of the active layer in FIG2 ;

[0041] FIG7 is a schematic structural diagram of the layer where the data line is located in FIG2;

[0042] FIG8 is a schematic structural diagram of the layer where the vias are located in FIG2 ;

[0043] FIG9 is a schematic structural diagram of the layer where the pixel electrode is located in FIG2 ;

[0044] FIG10 is a schematic structural diagram of a repair data line provided by an embodiment of the present disclosure;

[0045] FIG11 is a schematic diagram of the cross-sectional structure along line III-IV in FIG10 ;

[0046] FIG12 is a schematic structural diagram of a first electrode of a disconnect transistor provided in an embodiment of the present disclosure;

[0047] FIG13 is a light effect simulation diagram of a sub-pixel region provided by an embodiment of the present disclosure;

[0048] FIG14 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0049] FIG15 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0050] FIG16 is a working timing diagram of an array substrate provided by an embodiment of the present disclosure;

[0051] FIG17 is a schematic structural diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0052] FIG18 is another working timing diagram of the array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that, to further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that in the accompanying drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Example embodiments are described in this disclosure with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their sizes and shapes are not intended to depict the precise shapes of the regions or reflect true scale. They are intended solely to illustrate the present disclosure. The same or similar reference numerals throughout the text represent the same or similar elements or elements having the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0054] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0055] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0056] Competition in the display industry is increasingly fierce, and cost reduction is becoming increasingly important. Compared to conventional solutions that use one data line to drive a column of sub-pixels, dual-gate products use a single data line to drive multiple columns of sub-pixels simultaneously. This reduces the number of data lines, the total number of driver ICs, and significantly lowers material costs. Dual-gate products are particularly suitable for medium- and large-sized products such as automotive displays and TVs.

[0057] Figure 1 shows a schematic diagram of the pixel arrangement of a dual-gate product provided by an embodiment of the present disclosure. As can be seen from Figure 1, the dual-gate product includes data lines (e.g., D1, D2, D3, etc.), transistors (TFTs), and gate lines (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.), and the data lines (e.g., D1, D2, D3, etc.) and transistors (TFTs) all have overlapping areas with the gate lines (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.). In some embodiments, the source / drain of the transistor (TFT) and the data line (e.g., D1, D2, D3, etc.) are arranged in the same layer and the same material, the gate of the transistor (TFT) and the gate line (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.) are arranged in the same layer and the same material, and an insulating layer is provided between the layer where the data line (e.g., D1, D2, D3, etc.) is located and the layer where the gate line (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.) is located; however, there is an insulating layer between the data line (e.g., D1, D2, D3, etc.) and the gate line (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.) are located. 3. In the process of G4, G5, G6, G7, G8, etc., conductive particles may remain due to incomplete development and etching. The conductive particles pierce the insulating layer, which may cause overlapping data lines (such as D1, D2, D3, etc.) to short-circuit with gate lines (such as G1, G2, G3, G4, G5, G6, G7, G8, etc.), or cause overlapping transistors (TFTs) to short-circuit with gate lines (such as G1, G2, G3, G4, G5, G6, G7, G8, etc.), causing the product to malfunction and affecting the product yield.

[0058] In order to solve the above technical problems existing in the related art, an embodiment of the present disclosure provides an array substrate, as shown in FIG. 2 to FIG. 9 , comprising:

[0059] Base substrate 101, optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.;

[0060] A plurality of pixel electrodes 102 are arranged in an array on the base substrate 101; optionally, the pixel electrodes 102 are made of the same material, such as a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium zinc oxide (GZO);

[0061] A plurality of gate lines 103 extend along a first direction X at the gaps between the pixel electrodes 102, where the first direction X is a row direction or a column direction. The present disclosure takes the first direction X as the row direction as an example for illustration. The gate lines 103 include a bent portion 1031 protruding toward the side where the adjacent pixel electrodes 102 are located. Two gate lines 103 are provided in the gaps between two adjacent pixel electrodes 102 arranged along the second direction Y. The bent portions 1031 of the two gate lines 103 are oppositely arranged to form an accommodating space AS. The second direction Y intersects with the first direction X. The present disclosure takes the second direction Y as the column direction as an example for illustration. Optionally, the material of the gate lines 103 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate lines 103 may have a single-layer structure or a stacked-layer structure. For example, the gate lines 103 may have a single-layer structure composed of a copper metal layer.

[0062] A plurality of data lines 104 extend along the second direction Y at the gaps between the pixel electrodes 102; the orthographic projections of the data lines 104 on the base substrate 101 extend through the orthographic projections of the accommodating spaces AS on the base substrate 101; optionally, the material of the data lines 104 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the data lines 104 may have a single-layer structure or a stacked-layer structure. For example, the data lines 103 may have a stacked-layer structure consisting of a titanium metal layer / an aluminum metal layer / a titanium metal layer;

[0063] A plurality of transistors 105 are located in the gap between two adjacent pixel electrodes 102 arranged along the second direction Y. The orthographic projection of the transistor 105 on the substrate 101 overlaps with the orthographic projection of the gate line 103 on the substrate 101. For example, a portion of the gate line 103 serves as the gate g of the transistor 105. The orthographic projection of the active layer a of the transistor 105 on the substrate 101 is located within the orthographic projection of the gate line 103 on the substrate 101. The orthographic projection of the first electrode s of the transistor 105 on the substrate 101 overlaps with the orthographic projection of the gate line 103 on the substrate 101. Cross, the orthographic projection of the second electrode d of the transistor 105 on the substrate 101 intersects with the orthographic projection of the gate line 103 on the substrate 101. Optionally, the first electrode s is the source and the second electrode d is the drain, or the first electrode s is the drain and the second electrode d is the source. The material of the active layer a can be amorphous silicon a-Si, polycrystalline silicon Poly, indium gallium zinc oxide IGZO, etc. The transistor 105 can be a bottom-gate transistor as shown in Figure 4, or a top-gate transistor or a double-gate transistor. The transistor 105 can be a P-type transistor or an N-type transistor, which is not limited here. In some embodiments, the first electrode d of the transistor 105 is coupled to the data line 104 (for example, the first electrode d and the data line 104 are integrally arranged), and a part of the orthographic projection of the first electrode d of the transistor 105 on the substrate 101 is located within the orthographic projection of the accommodating space AS on the substrate 101.

[0064] In the array substrate provided in the embodiment of the present disclosure, since the bent portions 1031 of the two gate lines 103 are arranged opposite each other at the same gap extending along the first direction X to form a larger accommodation space AS, when a data line 104 and the gate line 103 are short-circuited, the data line 104 at the short-circuited position can be removed (e.g., by laser cutting), and holes are drilled (e.g., by laser drilling) within the larger accommodation space AS and in a larger area between two adjacent pixel electrodes 102 arranged along the first direction X. Then, a conductive material is sprayed between the two holes to form a bridge line 106, so that the data line 104 that is disconnected due to being cut at the short-circuited position is connected via the bridge line 106, thereby ensuring smooth flow of data signals. Based on this, as shown in Figures 10 and 11, the array substrate may further include at least one bridge line 106, at least one data line 104 is missing in at least one overlapping region with the gate line 103, and the bridge line 106 is connected to the data line 104 within the accommodating space AS and the data line 104 between two adjacent pixel electrodes 102 arranged along the first direction X. In this way, the short circuit problem between the gate line 103 and the data line 104 can be solved, thereby improving product yield.

[0065] Furthermore, if the first electrode s and / or the second electrode d of the transistor 105 is short-circuited with the gate line 103, the first electrode s can be cut off within the larger accommodation space AS, ensuring that the scanning signal of the gate line 103 is not interfered with. Alternatively, the present disclosure uses the pixel electrode 102 coupled to the transistor 105 with the cut-off first electrode s as a dark spot. Since the number of dark spots is small, it has little impact on the display effect. This solves the problem of the first electrode s and / or the second electrode d of the transistor 105 being short-circuited with the gate line 103, thereby improving the product yield. In addition, as can be seen from Figures 3 and 4, the orthographic projection of the active layer a of the transistor 105 on the base substrate 101 is located within the orthographic projection of the gate line 103 on the base substrate 101. Therefore, the active layer a may also be shorted to the gate line 103 due to residual conductive particles. In this case, the first electrode s can also be cut off within the larger accommodation space AS to ensure that the scanning signal of the gate line 103 is not interfered with. In some embodiments, the pixel electrode 102 coupled to the transistor 105 with the cut-off first electrode s can be treated as a dark spot. Because the dark spot is small, it has little impact on the display effect. This solves the problem of the active layer a of the transistor 105 being shorted to the gate line 103 and improves the product yield. Based on this, as shown in Figure 12, in the above-mentioned array substrate provided by the embodiment of the present disclosure, at least one of the first electrode s, the second electrode d, and the active layer a of at least one transistor 105 may be shorted to the gate line 103, and the first electrode s of the transistor 105 may be disconnected within the accommodation space AS.

[0066] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG3 , within the region where the same accommodation space AS is located, the data line 104 is coupled to the first electrodes s of two transistors 105. The coupling positions of the first electrodes s of the two transistors 105 to the data line 104 are located on either side of the data line 104 and staggered in the second direction Y. If the coupling positions of the first electrodes s of the two transistors 105 to the data line 104 are collinear in the first direction X (e.g., line L shown in FIG3 ), the right transistor 105 needs to be moved upward accordingly. As a result, the width of the row gap needs to be increased, which affects the pixel aperture ratio. In the present disclosure, staggering the coupling positions of the first electrodes s of the two transistors 105 to the data line 104 in the second direction Y allows the orthographic projections of the two transistors 105 in the second direction Y to overlap, thereby effectively utilizing the row gap and improving the pixel aperture ratio.

[0067] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 5 and 7, further includes a common voltage line 107 and a plurality of compensation lines 108, wherein the plurality of compensation lines 108 are coupled between the second electrodes d of at least a portion of the transistors 105 and at least a portion of the pixel electrodes 102, and the orthographic projections of the plurality of compensation lines 108 on the base substrate 101 at least partially overlap with the orthographic projections of the common voltage line 107 on the base substrate 101. Optionally, the orthographic projections of the compensation lines 108 on the base substrate 101 are located within the orthographic projections of the common voltage line 107 on the base substrate 101, so that a compensation capacitor is formed between the compensation lines 108 and the common voltage lines 107, thereby ensuring that the signal pull-down levels (feed-through) of different sub-pixels are consistent, thereby improving flickering.

[0068] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 7 and 9, the base substrate 101 includes multiple red sub-pixel areas R, multiple green sub-pixel areas G and multiple blue sub-pixel areas B, and multiple pixel electrodes 102 are located in the multiple red sub-pixel areas R, the multiple green sub-pixel areas G and the multiple blue sub-pixel areas B; multiple compensation lines 108 are coupled to the pixel electrodes 102 in the multiple red sub-pixel areas R and the multiple green sub-pixel areas G.

[0069] The counter substrate (also known as the color filter substrate CF) includes multiple red color resists corresponding to multiple red sub-pixel regions R, multiple green color resists corresponding to multiple green sub-pixel regions G, and multiple blue color resists corresponding to multiple blue sub-pixel regions, as well as a common electrode located on the side of the multiple red, green, and blue color resists facing the array substrate. Because the thickness of the red and green color resists is similar (for example, exactly the same or within a ±5% error range due to factors such as manufacturing and measurement), and the blue color resist is thicker than the red color resist, the cell gap in the blue sub-pixel region B is smaller, and the capacitance between the pixel electrode 102 and the common electrode in the blue sub-pixel region B is larger. As a result, the signal pull-down degree of the pixel electrode 102 in the blue sub-pixel region B is greater than that of the pixel electrodes 102 in the red and green sub-pixel regions G. When adjacent sub-pixels are driven by alternating positive (+) and negative (-) signal loading, image flickering may occur. The present disclosure sets compensation lines 108 coupled to pixel electrodes 102 in multiple red sub-pixel regions R and multiple green sub-pixel regions G. The compensation capacitor formed by the compensation line 108 and the common voltage line 107 can be used to compensate the pixel electrode 102, ensuring that the signal pull-down degree of the pixel electrode 102 in the blue sub-pixel region B after compensation is similar to the signal pull-down degree of the pixel electrode 102 in the red sub-pixel region B and the green sub-pixel region G, thereby improving or even avoiding poor screen flickering.

[0070] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 7 to 9, may further include a plurality of connecting lines 109, which are coupled between the second pole d of the transistor 105 and the pixel electrode 102. Optionally, the connecting line 109 is integrally arranged with the second pole d of the transistor 105, and is coupled to the pixel electrode 102 through a first via h1 penetrating the first insulating layer; and in order to simplify the manufacturing process, in the present disclosure, a plurality of compensation lines 108 are integrally arranged with at least part of the connecting lines 109. Exemplarily, in the present disclosure, a plurality of compensation lines 108 are integrally arranged with a plurality of connecting lines 109 of a plurality of red sub-pixel areas B and a plurality of green sub-pixel areas G, so as to compensate for a plurality of pixel electrodes 102 of a plurality of red sub-pixel areas B and a plurality of green sub-pixel areas G through compensation capacitors formed by a plurality of compensation lines 108 and a common voltage line 107.

[0071] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 2, 5, 7 and 9, the connection line 109 includes a first sub-connection line 1091 extending along the first direction X, and the first sub-connection line 1091 is coupled between the second pole d of the transistor 105 and the pixel electrode 102. Optionally, the first sub-connection line 1091 is integrally arranged with the second pole d of the transistor 105, and the orthographic projection of the first sub-connection line 1091 on the base substrate 101 is located within the orthographic projection of the common voltage line 107 on the base substrate 101; to avoid affecting the aperture ratio, the compensation line 109 can be arranged on an extension line of at least one end of the first sub-connection line 1091. The present disclosure takes the compensation line 109 being located on the extension lines of both ends of the first sub-connection line 1091 as an example for illustration; optionally, the compensation line 109 is integrally arranged with the first sub-connection line 1091.

[0072] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figures 2, 7, and 9, the connecting line 109 further includes a second sub-connecting line 1092 extending along the second direction Y. The second sub-connecting line 1092 is coupled between the first sub-connecting line 1091 and the pixel electrode 102, and the extension of the second sub-connecting line 1092 passes through the central region of the pixel electrode 102. As shown in Figure 13, the central region of the pixel electrode 102 has dark stripes caused by disordered liquid crystal alignment. By routing the extension of the second sub-connecting line 1092 through the central region of the pixel electrode 102, the second sub-connecting line 1092 can be positioned within the dark stripe region, thereby avoiding affecting the transmittance of the pixel electrode 102. Optionally, as shown in Figures 2, 5, 7 to 9, the second sub-connection line 1092 is integrally arranged with the first sub-connection line 1091, and the second sub-connection line 1092 is coupled to the pixel electrode 102 through the first via hole h1; at the first via hole h1, the second sub-connection line 1092 is a widened block structure, and the common voltage line 107 (specifically the first sub-common voltage line 1071) is also a widened block structure, forming a storage capacitor between the two.

[0073] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 5, and 9, the common voltage line 107 includes a first sub-common voltage line 1071 extending along a first direction X, and the extension of the first sub-common voltage line 1071 passes through the central region of the pixel electrode 102. Because the central region of the pixel electrode 102 has dark stripes due to disordered liquid crystal alignment (as shown in Figure 13), the present disclosure positions the first sub-common voltage line 1071 in the dark stripe region by extending the extension of the first sub-common voltage line 1071 through the central region of the pixel electrode 102, thereby avoiding affecting the transmittance of the pixel electrode 102.

[0074] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 2, 5 and 7, the common voltage line 107 can be set in the same layer and the same material as the gate line 103, and the common voltage line 107 can also include a hollow structure HS extending along the second direction Y, and the orthographic projection of the hollow structure HS on the base substrate 101 covers the orthographic projection of the data line 104 between adjacent pixel electrodes 102 on the base substrate 101, so as to reduce the overlapping area between the common voltage line 107 and the data line 104, thereby reducing the parasitic capacitance between the common voltage line 107 and the data line 104, and reducing the probability of short circuit between the common voltage line 107 and the data line 104. Continuing to refer to Figures 2, 5, 7 to 9, it can be seen that the common voltage lines 107 of adjacent rows are disconnected at the gate line 103 and are electrically connected through the jumper 110; optionally, the jumper 110 is provided in the same layer and material as the pixel electrode 102, and the jumper 110 is coupled to the common voltage line 107 through the second via h2 of the first insulating layer 111 and the second insulating layer 112.

[0075] In some embodiments, the material of the first insulating layer 111 may be an inorganic insulating material and / or an organic insulating material. Inorganic insulating materials include, but are not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride. Organic insulating materials include, but are not limited to, at least one of polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and novolac epoxy acrylic resin. The material of the second insulating layer 112 may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0076] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, as shown in FIG14 , comprising the array substrate 001 provided in the embodiment of the present disclosure, and an opposing substrate 002 disposed opposite the array substrate 001. Optionally, the opposing substrate 002 includes a common electrode 201, which can be disposed on the entire surface of the display area AA. In some embodiments, the opposing substrate 002 further includes a plurality of red color resists 203, a plurality of green color resists (not shown in the figure), and a plurality of blue color resists (not shown in the figure) located between the substrate 202 and the layer where the common electrode 201 is located. Two adjacent color resists can be separated from each other by a black matrix 204; wherein, in the vertical direction of the base substrate 101: the size of the blue color resist is larger than the size of the red color resist, and the size of the green color resist, and the size of the red color resist is approximately the same as the size of the green color resist.

[0077] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, "approximately the same" may be completely equivalent, or there may be some deviations (for example, a deviation of ±5%). Therefore, as long as the "approximately the same" relationship between related features meets the error allowance, it falls within the scope of protection of the present disclosure.

[0078] In some embodiments, as shown in FIG14 , in the display panel provided by the embodiment of the present disclosure, a liquid crystal layer 003 may be further provided between the array substrate 001 and the counter substrate 002, a first alignment layer may be provided on the side of the array substrate 001 facing the counter substrate 002, a first polarizer may be provided on the side of the array substrate 001 away from the counter substrate 002, a second alignment layer may be provided on the side of the counter substrate 002 away from the array substrate 001, and a second polarizer may be provided on the side of the counter substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer. Other essential components of the display panel are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0079] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in FIG15 , comprising the above-mentioned display panel PNL provided in the embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct-type backlight module or an edge-entry backlight module. Optionally, the edge-entry backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightening film stacked on the light-emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices (QLEDs), micro light-emitting devices (such as Mini LEDs, Micro LEDs), etc.

[0080] Among them, submillimeter-scale or even micron-scale micro-light-emitting devices are self-luminous devices, just like organic light-emitting devices (OLEDs). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting devices emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting devices that emit light based on organic matter. And when micro-light-emitting devices are used as backlight sources, they can achieve more precise dynamic backlight effects. While effectively improving the brightness and contrast of the screen, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0081] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0082] In some embodiments, as shown in Figure 1, two gate lines in the same row gap (e.g., G2 and G3, G4 and G5, G6 and G7) corresponding to the same data line (e.g., D1, D2, or D3) connect to sub-pixels of different colors. When the product is driven using a DLG drive method, cross-color problems will occur. Therefore, it is difficult to use DLG drive to improve the refresh rate. As a result, the refresh rate of ultra-high-resolution dual-gate products is relatively low, unable to meet the market demand for ultra-high refresh rates.

[0083] In order to solve the above technical problems existing in the related art, the embodiment of the present disclosure further provides a DLG driving method for the above array substrate, wherein the nth (n is a positive integer) gate line and the (n+j)th gate line are formed into a gate line group, j is greater than or equal to 2, and the same data line corresponding to the gate line group is connected to the sub-pixels of the same color. The DLG driving method includes:

[0084] During one frame display time, each gate line group is driven sequentially, and the gate lines of the same gate line group are driven synchronously, and the driving duration of two adjacent gate line groups is the same; wherein,

[0085] During the driving process of the current gate line group, data signals are input to the data lines, and the input of data signals is stopped after the driving of the current gate line group is completed.

[0086] In the above-mentioned driving method, since the same data line corresponding to the same gate line group is connected to the sub-pixels of the same color, when the DLG driving method is used to synchronously drive the gate lines of the same gate line group, there will be no cross-color problem. Compared with the method of driving the gate lines one by one within a frame display time, the present disclosure can shorten the total time of the gate line driving, thereby facilitating the improvement of the refresh rate, and is suitable for fast refresh of ultra-high-resolution dual-gate products.

[0087] The following takes j equal to 2 as an example to describe in detail the DLG driving method provided by the embodiment of the present disclosure. As shown in Figures 1, 16 and 17, the first gate line GL1 connected by the first clock signal CLK1 through the first-level shift register unit GOA1, and the third gate line GL3 connected by the third clock signal CLK3 through the third-level shift register unit GOA3 are the first gate line group, the second gate line GL2 connected by the second clock signal CLK2 through the second-level shift register unit GOA2, and the fourth gate line GL4 connected by the fourth clock signal CLK4 through the fourth-level shift register unit GOA4 are the second gate line group, the fifth gate line GL5 connected by the fifth clock signal CLK5 through the fifth-level shift register unit GOA5, and the seventh gate line GL7 connected by the seventh clock signal CLK7 through the seventh-level shift register unit GOA7 are the third gate line group, the sixth gate line GL6 connected by the sixth clock signal CLK6 through the sixth-level shift register unit GOA6, and the eighth gate line GL8 connected by the eighth clock signal CLK8 through the eighth-level shift register unit GOA8 are the fourth gate line group.

[0088] In some embodiments, G1 shown in FIG16 represents a first scanning signal loaded on the first gate line GL1, G2 represents a second scanning signal loaded on the second gate line GL2, G3 represents a third scanning signal loaded on the third gate line GL3, G4 represents a fourth scanning signal loaded on the fourth gate line GL4, G5 represents a fifth scanning signal loaded on the fifth gate line GL5, G5 represents a sixth scanning signal loaded on the sixth gate line GL6, G7 represents a seventh scanning signal loaded on the seventh gate line GL7, G8 represents an eighth scanning signal loaded on the eighth gate line GL8, DA represents a data signal loaded on a data line (e.g., the first data line DL1, the second data line DL2, the third data line DL3, etc. shown in FIG1 ), and H represents the driving time of a row of sub-pixels. Optionally, a high level among the scanning signals G1 to G6 can be used as a gate-on signal to control the conduction of the transistor (TFT) in the sub-pixel.

[0089] In Figures 1, 16 and 17, the first scanning signal G1 is first loaded onto the first gate line GL1 in the first gate line group, and the third scanning signal G3 is synchronously loaded onto the third gate line GL3, so that the transistors (TFTs) corresponding to the first gate line GL1 and the third gate line GL3, respectively, are synchronously turned on under the high level of the scanning signals G1 and G3; and during the high level loading process of the scanning signals G1 and G3, the data signal DA is started to be input to the data lines (for example, the first data line DL1, the second data line DL2, the third data line DL3, etc.), and the input of the data signal DA is stopped after the scanning signals G1 and G3 are changed from high level to low level, so that the sub-pixels corresponding to the first gate line GL1 and the third gate line GL3 are written with the data signal DA. As can be seen from Figure 1, the sub-pixels connected to the first gate line GL1 and the third gate line GL3 through the same data line corresponding to the transistor TFT (for example, the first data line DL1, the second data line DL2 or the third data line DL3, etc.) have the same color. Therefore, synchronously driving the first gate line GL1 and the third gate line GL3 will not cause the problem of cross-color.

[0090] Based on the same driving method, the synchronous driving of the second gate line GL2 and the fourth gate line GL4 in the second gate line group, the synchronous driving of the fifth gate line GL5 and the seventh gate line GL7 in the third gate line group, and the synchronous driving of the sixth gate line GL6 and the eighth gate line GL8 in the fourth gate line group can be completed in sequence; and during the driving process of the current gate line group, the data signal is input to the data line until the input of the data signal is stopped after the current gate line group is driven. The implementation method of the remaining sub-pixels is similarly deduced until the sub-pixels in the entire display panel are completely charged with data signals, which will not be described in detail here.

[0091] In addition, referring to Figures 1, 16 and 17, it can be seen that the driving durations of two adjacent gate line groups are partially the same. For example, the high-level loading durations of the first scanning signal G1 of the first gate line GL1 in the first gate line group and the third scanning signal G3 of the third gate line GL3 partially overlap with the high-level loading durations of the second scanning signal G2 of the second gate line GL2 in the second gate line group and the fourth scanning signal G4 of the fourth gate line GL4. During the overlapping duration, the data signals provided to the sub-pixels corresponding to the first gate line GL1 and the third gate line GL3 can be written into the sub-pixels corresponding to the second gate line GL2 and the fourth gate line GL4 to pre-charge the sub-pixels corresponding to the second gate line GL2 and the fourth gate line GL4, thereby improving the charging rates of the sub-pixels corresponding to the second gate line GL2 and the fourth gate line GL4.

[0092] It should be noted that FIG17 has two frame start signals, STV0 and STV1. Because the frame start signal may be lost during the use of the product, the two frame start signals STV0 and STV1 are used to achieve double insurance and ensure the normal startup of the gate drive circuit.

[0093] On the other hand, in order to improve the refresh rate, the embodiments of the present disclosure further provide another HSR driving method for the above array substrate. For example, four adjacent gate lines are formed into a gate line group, and the same data line corresponding to the odd-numbered gate lines is connected to the sub-pixels of the same color, and the same data line corresponding to the even-numbered gate lines is connected to the sub-pixels of the same color. The HSR driving method includes:

[0094] During one frame display time, each gate line group is driven sequentially, and the first gate line, the third gate line, the second gate line, and the fourth gate line in the same gate line group are driven sequentially; the driving duration of two adjacent gate lines is partially the same; wherein,

[0095] Before the first gate line is driven and during the third gate line driving process, the first data signal starts to be input to the data line, and the input of the first data signal is stopped after the third gate line is driven; and before the second gate line is driven and during the fourth gate line driving process, the second data signal starts to be input to the data line, and the input of the second data signal is stopped after the fourth gate line is driven, and the input time of the first data signal and the input time of the second data signal are staggered.

[0096] In the above-mentioned HSR driving method, since the same data line corresponding to the first gate line and the third gate line is connected to the sub-pixels of the same color, and the same data line corresponding to the second gate line and the fourth gate line is connected to the sub-pixels of the same color, the HSR driving method is used to sequentially drive the first gate line, the third gate line, the second gate line, and the fourth gate line of the same gate line group, and the first data signal is synchronously input to the sub-pixels of the same color corresponding to the first gate line and the third gate line, and the second data signal is synchronously input to the sub-pixels of the same color corresponding to the second gate line and the fourth gate line. In this way, only the charging time of the sub-pixel corresponding to the first gate line is short and the charging time of the sub-pixel corresponding to the third gate line is long, and the charging time of the sub-pixel corresponding to the second gate line is short and the charging time of the sub-pixel corresponding to the fourth gate line is long. That is, there is only a difference in charging rate, and there will be no cross-color problem. Moreover, compared with a driving method in which the time for loading data signals on sub-pixels corresponding to different gate lines is staggered, the present disclosure can shorten the total loading time of data signals within one frame, thereby improving the refresh rate, and is suitable for fast refresh of ultra-high-resolution dual-gate products.

[0097] The following describes the driving method provided by the embodiment of the present disclosure in detail, taking two gate line groups as an example. As shown in Figures 1 and 18, the first gate line GL1, the second gate line GL2, the third gate line GL3, and the fourth gate line GL4 constitute the first gate line group, and the fifth gate line GL5, the sixth gate line GL6, the third gate line GL7, and the eighth gate line GL8 constitute the second gate line group. CLK1 represents the first clock signal provided to the first-level shift register unit GOA1 connected to the first gate line GL1, CLK2 represents the second clock signal provided to the second-level shift register unit GOA2 connected to the second gate line GL2, CLK3 represents the third clock signal provided to the third-level shift register unit GOA3 connected to the third gate line GL3, CLK4 represents the fourth clock signal provided to the fourth-level shift register unit GOA4 connected to the fourth gate line GL4, CLK5 represents the fifth clock signal provided to the fifth-level shift register unit GOA5 connected to the fifth gate line GL5, CLK6 represents the sixth clock signal provided to the sixth-level shift register unit GOA6 connected to the sixth gate line GL6, CLK7 represents the seventh clock signal provided to the seventh-level shift register unit GOA7 connected to the seventh gate line GL7, and CLK8 represents the eighth clock signal provided to the eighth-level shift register unit GOA8 connected to the eighth gate line GL8. G1 represents the first scan signal loaded on the first gate line GL1, G2 represents the second scan signal loaded on the second gate line GL2, G3 represents the third scan signal loaded on the third gate line GL3, G4 represents the fourth scan signal loaded on the fourth gate line GL4, G5 represents the fifth scan signal loaded on the fifth gate line GL5, G5 represents the sixth scan signal loaded on the sixth gate line GL6, G7 represents the seventh scan signal loaded on the seventh gate line GL7, G8 represents the eighth scan signal loaded on the eighth gate line GL8, DA1 represents the first data signal loaded on the data line (e.g., the first data line DL1, the second data line DL2, the third data line DL3, etc. shown in FIG1), DA2 represents the second data signal loaded on the data line (e.g., the first data line DL1, the second data line DL2, the third data line DL3, etc. shown in FIG1), and H represents the driving time of a row of sub-pixels. Optionally, the high level of the scan signals G1 to G6 can be used as a gate-on signal to control the conduction of the transistor (TFT) in the sub-pixel.

[0098] In FIG18 , first, the first gate line GL1 in the first gate line group is loaded with the first scanning signal G1, the third gate line GL3 is loaded with the third scanning signal G3, the second gate line GL2 is loaded with the second scanning signal G2, and the fourth gate line GL4 is loaded with the fourth scanning signal G4, so that the transistors (TFTs) connected to the first gate line GL1, the third gate line GL3, the second gate line GL2, and the fourth gate line GL4, respectively, are turned on in sequence under the high level of the corresponding scanning signals G1, G3, G2, and G4; and before the first scanning signal G1 changes from a high level to a low level, and while the third scanning signal G3 remains at a high level, the data line (for example, the first data line DL1) is turned on. 1. The first data signal DA1 is input to the second data line DL2, the third data line DL3, etc., until the third scanning signal G3 changes from a high level to a low level, then the input of the first data signal DA1 is stopped; and before the second scanning signal G2 changes from a high level to a low level, and while the fourth scanning signal G4 remains at a high level, the second data signal DA2 is started to be input to the data lines (for example, the first data line DL1, the second data line DL2, the third data line DL3, etc.), until the fourth scanning signal G4 changes from a high level to a low level, then the input of the second data signal DA2 is stopped, and the input time of the first data signal DA1 and the input time of the second data signal DA2 are staggered. In combination with Figure 1, it can be seen that the sub-pixels connected to the same data line (for example, the first data line DL1, the second data line DL2 or the third data line DL3, etc.) corresponding to the first gate line GL1 and the third gate line GL3 through the transistor TFT have the same color. Therefore, synchronously providing the first data signal DA1 to the sub-pixels connected to the same data line (for example, the first data line DL1) corresponding to the first gate line GL1 and the third gate line GL3 will not cause the problem of cross-color. In addition, the sub-pixels connected to the same data line (for example, the first data line DL1) corresponding to the second gate line GL2 and the fourth gate line GL4 through the transistor TFT have the same color. Therefore, synchronously providing the second data signal DA2 to the sub-pixels connected to the same data line (for example, the first data line DL1, the second data line DL2 or the third data line DL3, etc.) corresponding to the first gate line GL1 and the third gate line GL3 will not cause the problem of cross-color.

[0099] Based on the same driving method, the fifth gate line GL5, the seventh gate line GL7, the sixth gate line GL6, and the eighth gate line GL8 in the second gate line group can be driven in sequence subsequently; and before the driving of the fifth gate line GL5 is completed and during the driving of the seventh gate line GL7, the third data signal is started to be input to the data line (for example, the first data line DL1, the second data line DL2, the third data line DL3, etc.), and the input of the third data signal is stopped after the driving of the seventh gate line GL7 is completed; and before the driving of the sixth gate line GL6 is completed and during the driving of the eighth gate line GL8, the fourth data signal is started to be input to the data line (for example, the first data line DL1, the second data line DL2, the third data line DL3, etc.), and the input of the fourth data signal is stopped after the driving of the eighth gate line GL8 is completed, and the input time of the third data signal is staggered with the input time of the fourth data signal; the implementation methods of the remaining sub-pixels are analogous until the sub-pixels in the entire display panel are completely charged with data signals, which will not be repeated here.

[0100] In addition, referring to Figures 1 and 18 , it can be seen that the driving durations of two adjacent gate lines are partially the same. For example, the high-level loading durations of the first scanning signal G1 of the first gate line GL1 and the second scanning signal G3 of the second gate line GL2 partially overlap, and within the overlapping duration, the first data signal DA1 provided to the sub-pixel corresponding to the first gate line GL1 can be written into the sub-pixel corresponding to the second gate line GL2 to pre-charge the sub-pixel corresponding to the second gate line GL2, thereby improving the charging rate of the second gate line GL2 and the corresponding sub-pixel.

[0101] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0102] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate substrate; A plurality of pixel electrodes are arranged in an array on the base substrate; A plurality of gate lines extending along a first direction at the gap between the pixel electrodes, the gate lines comprising a bent portion protruding toward the side where the adjacent pixel electrode is located, two gate lines are provided at the gap between two adjacent pixel electrodes arranged along a second direction, the bent portions of the two gate lines are arranged opposite to each other to form an accommodation space, and the second direction intersects with the first direction; A plurality of data lines extending along the second direction at the gaps between the pixel electrodes, wherein the orthographic projections of the data lines on the base substrate penetrate the orthographic projections of the accommodation spaces on the base substrate; A plurality of transistors are located in the gap between two adjacent pixel electrodes arranged along the second direction, and the orthographic projection of the transistor on the substrate overlaps with the orthographic projection of the gate line on the substrate; the first electrode of the transistor is coupled to the data line, and a part of the orthographic projection of the first electrode of the transistor on the substrate is located within the orthographic projection of the accommodating space on the substrate.

2. The array substrate according to claim 1, wherein: It also includes at least one bridge wire, the orthographic projection of the data line on the substrate and the orthographic projection of the gate line on the substrate have multiple overlapping areas, at least one of the data lines is missing in at least one of the overlapping areas, and the bridge wire is connected to the data line in the accommodating space and the data line between two adjacent pixel electrodes arranged along the first direction.

3. The array substrate according to claim 1 or 2, wherein: At least one of the first electrode, the second electrode, and the active layer of at least one of the transistors is short-circuited with the gate line, and the first electrode of at least one of the transistors is disconnected in the accommodating space.

4. The array substrate according to any one of claims 1 to 3, wherein: In the same area where the accommodating space is located, the data line is coupled to the first electrodes of the two transistors, and the coupling positions of the first electrodes of the two transistors and the data line are separated on both sides of the data line and staggered with each other in the second direction.

5. The array substrate according to any one of claims 1 to 4, wherein: It also includes a common voltage line and a plurality of compensation lines, wherein the plurality of compensation lines are coupled between the second poles of at least part of the transistors and at least part of the pixel electrodes, and the orthographic projections of the plurality of compensation lines on the substrate at least partially overlap with the orthographic projections of the common voltage lines on the substrate.

6. The array substrate according to claim 5, wherein: The base substrate comprises a plurality of red sub-pixel regions, a plurality of green sub-pixel regions and a plurality of blue sub-pixel regions, and the plurality of pixel electrodes are located in the plurality of red sub-pixel regions, the plurality of green sub-pixel regions and the plurality of blue sub-pixel regions; The plurality of compensation lines are coupled to the plurality of red sub-pixel regions and the pixel electrodes in the plurality of green sub-pixel regions.

7. The array substrate according to claim 5 or 6, wherein: It also includes a plurality of connection lines, wherein the connection lines are coupled between the second electrode of the transistor and the pixel electrode, and the compensation line is integrally arranged with at least part of the connection lines.

8. The array substrate according to claim 7, wherein: The connection line comprises a first sub-connection line extending along the first direction, and the first sub-connection line is coupled between the second electrode of the transistor and the pixel electrode; The compensation line is located on an extension line of at least one end of the first sub-connection line, and the compensation line is integrally arranged with the first sub-connection line.

9. The array substrate according to claim 8, wherein: The connection line further includes a second sub-connection line extending along the second direction, the second sub-connection line is coupled between the first sub-connection line and the pixel electrode, and an extension line of the second sub-connection line passes through a central area of ​​the pixel electrode.

10. The array substrate according to any one of claims 5 to 9, wherein: The common voltage line includes a first sub-common voltage line extending along the first direction, and an extended line of the first sub-common voltage line passes through a central area of ​​the pixel electrode.

11. The array substrate according to any one of claims 5 to 10, wherein: The common voltage line further includes a hollow structure extending along the second direction, and the orthographic projection of the hollow structure on the base substrate covers the orthographic projection of the data line between adjacent pixel electrodes on the base substrate.

12. A display panel, wherein: It comprises the array substrate as claimed in any one of claims 1 to 11.

13. The display panel according to claim 12, wherein: The invention also includes an opposite substrate arranged opposite to the array substrate, and the opposite substrate includes a common electrode.

14. The display panel according to claim 13, wherein: The opposing substrate also includes a plurality of red color resists, a plurality of green color resists and a plurality of blue color resists located on a side of the common electrode away from the array substrate; wherein, in the vertical direction of the base substrate: the size of the blue color resist is larger than the size of the red color resist and the size of the green color resist, and the size of the red color resist is approximately the same as the size of the green color resist.

15. A display device, wherein: It comprises the display panel as claimed in any one of claims 12 to 14.

16. A method for driving an array substrate according to any one of claims 1 to 11, wherein: The nth (n is a positive integer) gate line and the (n+j)th gate line are a gate line group, j is greater than or equal to 2, and the same data line corresponding to the gate line group is connected to sub-pixels of the same color, and the driving method includes: The gate line groups are sequentially driven, and the gate lines of the same gate line group are synchronously driven, and the driving time lengths of two adjacent gate line groups are partially the same; wherein, During the driving process of the current gate line group, data signals are input to the data lines, and the input of data signals is stopped after the driving of the current gate line group is completed.

17. A method for driving an array substrate according to any one of claims 1 to 11, wherein: Four adjacent gate lines are formed into a gate line group, the same data line corresponding to the odd-numbered gate lines is connected to sub-pixels of the same color, and the same data line corresponding to the even-numbered gate lines is connected to sub-pixels of the same color, and the driving method includes: The gate line groups are sequentially driven, and the first gate line, the third gate line, the second gate line, and the fourth gate line are sequentially driven in the same gate line group; the driving time lengths of two adjacent gate lines are partially the same; wherein, Before the first gate line driving is completed and during the third gate line driving process, the first data signal is input to the data line, and the first data signal is stopped after the third gate line driving is completed. input of a data signal; and before the second gate line is driven, and during the fourth gate line driving process, starting to input the second data signal to the data line, until the fourth gate line is driven, then stopping the input of the second data signal, and the input time of the first data signal and the input time of the second data signal are staggered.

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