Pixel circuit and driving method therefor, display panel and display apparatus

Abstract

Provided are a pixel circuit and a driving method therefor, a display panel and a display apparatus, which belong to the technical field of display. A data writing circuit can control the connection and disconnection between a data line and a first node under the control of a gate driving signal; a first light-emission control circuit can control the connection and disconnection between a driving power source line and a second node under the control of a first light-emission control signal; a reset circuit can control the connection and disconnection between an initial power source line and a third node under the control of a reset signal; and a compensation circuit can control the connection and disconnection between a compensation power source line and the first node under the control of a compensation signal and adjust the potential of the first node. Therefore, by means of flexibly setting signals, a driving signal transmitted by a driving circuit to a light-emitting element is independent of both a signal provided by a driving power source line and a threshold voltage of a driving transistor in the driving circuit. Thus, the influence of a voltage drop on the driving power source line and the characteristic drift of the transistor on the driving signal can be avoided, thereby ensuring that the light-emitting element is reliably driven to emit light, such that a display effect is better.

Description

Pixel circuit and driving method thereof, display panel, and display device

[0001] This disclosure claims priority to Chinese patent application number 202311541715.3, filed on November 17, 2023, entitled “Pixel circuit and driving method thereof, display panel, and display device,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0003] Organic light-emitting diode (OLED) display panels are widely used in various display products due to their advantages such as self-luminescence, high contrast, wide color gamut and wide operating temperature range.

[0004] In related art, an OLED display panel generally includes multiple pixels. Each pixel includes a pixel circuit and a light-emitting element. The pixel circuit is coupled to multiple drive signal lines (e.g., gate lines, data lines, and drive power lines) and the light-emitting element, and drives the light-emitting element to emit light based on the drive signals provided by the multiple drive signal lines.

[0005] However, due to the influence of the voltage drop on the driving signal line and the characteristic drift of the transistor in the pixel circuit, the pixel circuit in the related art cannot reliably drive the light-emitting element to emit light, and the display effect of the display panel is poor.

[0006] Summary of the Invention

[0007] The present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device. The technical solution is as follows:

[0008] In one aspect, a pixel circuit is provided for use in a display panel; the pixel circuit includes:

[0009] a data writing circuit, coupled to the gate line, the data line and the first node respectively, and configured to control the connection and disconnection between the data line and the first node in response to a gate driving signal provided by the gate line;

[0010] a first light-emitting control circuit, coupled to a first light-emitting control line, a driving power line, and a second node, respectively, and configured to control the connection and disconnection between the driving power line and the second node in response to a first light-emitting control signal provided by the first light-emitting control line;

[0011] a reset circuit, coupled to a reset line, an initial power line, and a third node, respectively, and configured to control the connection and disconnection between the initial power line and the third node in response to a reset signal provided by the reset line, wherein the third node is configured to be coupled to the light-emitting element;

[0012] a driving circuit coupled to the first node, the second node, and the third node, respectively, and configured to transmit a driving signal to the third node based on the potential of the first node and the potential of the second node, so as to drive the light-emitting element to emit light;

[0013] a compensation circuit, coupled to at least one compensation line, a compensation power line, the driving power line, and the first node, respectively, and configured to control the connection and disconnection between the compensation power line and the first node in response to a compensation signal provided by the at least one compensation line, and to adjust the potential of the first node;

[0014] The compensation power line is introduced through both sides of the display panel to transmit the compensation power signal to the pixel circuit in both directions.

[0015] Optionally, the compensation circuit includes:

[0016] a switch sub-circuit, coupled to the at least one compensation line, the compensation power line, and the first node, respectively, and configured to control the connection and disconnection between the compensation power line and the first node in response to a compensation signal provided by the at least one compensation line;

[0017] a first regulating subcircuit, coupled to the driving power line and the first node respectively, and configured to regulate the potential of the first node;

[0018] Furthermore, the first regulating sub-circuit is indirectly coupled to the driving power line through the first light-emitting control circuit; or the first regulating sub-circuit is directly coupled to the driving power line.

[0019] Optionally, the switch sub-circuit is coupled to two compensation lines, namely, a first compensation line and a second compensation line; the switch sub-circuit includes:

[0020] a first switch unit, coupled to the first compensation line, the compensation power line, and a fourth node, respectively, and configured to control the connection and disconnection of the compensation power line and the fourth node in response to a compensation signal provided by the first compensation line;

[0021] a second switch unit, coupled to the second compensation line, the fourth node, and the first node, respectively, and configured to control the connection and disconnection of the fourth node and the first node in response to a compensation signal provided by the second compensation line;

[0022] The first regulating subcircuit is coupled to the second node to be indirectly coupled to the driving power line through the first light emitting control circuit, and the first regulating subcircuit is also coupled to the fourth node to be coupled to the first node through the second switch unit.

[0023] Optionally, the first switch unit includes: a first transistor; the second switch unit includes: a second transistor; the first regulating subcircuit includes: a first capacitor;

[0024] The gate of the first transistor is coupled to the first compensation line, the first electrode of the first transistor is coupled to the compensation power line, and the second electrode of the first transistor is coupled to the fourth node;

[0025] A gate of the second transistor is coupled to the second compensation line, a first electrode of the second transistor is coupled to the fourth node, and a second electrode of the second transistor is coupled to the first node;

[0026] A first terminal of the first capacitor is coupled to the fourth node, and a second terminal of the first capacitor is coupled to the second node.

[0027] Optionally, the gate line is shared with the reset line.

[0028] Optionally, the regulating subcircuit is indirectly coupled to the driving power line through the first light emitting control circuit; and the compensation circuit further includes:

[0029] The second regulating subcircuit is coupled to the reset line, the driving power line and the second node respectively, and is used to control the connection and disconnection of the driving power line and the second node in response to the reset signal provided by the reset line to adjust the potential of the second node.

[0030] Optionally, the second regulating subcircuit includes: a third transistor and a second capacitor;

[0031] The gate of the third transistor is coupled to the reset line, the first electrode of the third transistor is coupled to the first end of the second capacitor, the second electrode of the third transistor is coupled to the second node, and the second end of the second capacitor is coupled to the driving power line.

[0032] Optionally, the transistor in the pixel circuit includes: a P-type transistor.

[0033] Optionally, the switch subcircuit is coupled to a compensation line, and the regulation subcircuit is directly coupled to the driving power line;

[0034] The compensation circuit further includes: a third regulating subcircuit, coupled to the first node and the fifth node respectively, and configured to regulate the potential of the first node and the potential of the fifth node;

[0035] The pixel circuit also includes: a second light-emitting control circuit, which is coupled to the second light-emitting control line, the fifth node and the third node respectively, and is used to control the connection and disconnection of the fifth node and the third node in response to a second light-emitting control signal provided by the second light-emitting control line; and the driving circuit is coupled to the fifth node to be indirectly coupled to the third node through the second light-emitting control circuit.

[0036] Optionally, the switch subcircuit includes: a fourth transistor; the first regulation subcircuit includes: a third capacitor; the third regulation subcircuit includes: a fourth capacitor; the second light emitting control circuit includes: a fifth transistor;

[0037] The gate of the fourth transistor is coupled to the compensation line, the first electrode of the fourth transistor is coupled to the compensation power line, and the second electrode of the fourth transistor is coupled to the first node;

[0038] The gate of the fifth transistor is coupled to the second light emitting control line, the first electrode of the fifth transistor is coupled to the fifth node, and the second electrode of the fifth transistor is coupled to the third node;

[0039] A first end of the third capacitor is coupled to the driving power line, and a second end of the third capacitor is coupled to the first node;

[0040] A first terminal of the fourth capacitor is coupled to the first node, and a second terminal of the fourth capacitor is coupled to the fifth node.

[0041] Optionally, the transistor in the pixel circuit includes: an N-type transistor.

[0042] Optionally, the initial power line is introduced through both sides of the display panel;

[0043] Furthermore, the compensation power line is shared with the initial power line.

[0044] Optionally, the data writing circuit includes: a sixth transistor; the first light emitting control circuit includes: a seventh transistor; the reset circuit includes: an eighth transistor; the driving circuit includes: a ninth transistor;

[0045] The gate of the sixth transistor is coupled to the gate line, the first electrode of the sixth transistor is coupled to the data line, and the second electrode of the sixth transistor is coupled to the first node;

[0046] The gate of the seventh transistor is coupled to the first light emitting control line, the first electrode of the seventh transistor is coupled to the driving power line, and the second electrode of the seventh transistor is coupled to the second node;

[0047] The gate of the eighth transistor is coupled to the reset line, the first electrode of the eighth transistor is coupled to the initial power line, and the second electrode of the eighth transistor is coupled to the third node;

[0048] A gate of the ninth transistor is coupled to the first node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the third node.

[0049] In another aspect, a method for driving a pixel circuit is provided, which is applied to the pixel circuit described in the first aspect above; the method comprises:

[0050] In the first stage, the reset circuit controls the initial power line to be connected to the third node, so that the initial power line transmits an initial power signal to the third node;

[0051] In the second stage, the compensation circuit controls the compensation power line to be conductive with the first node in response to the compensation signal provided by the at least one compensation line, and adjusts the potential of the first node so that the compensation power line transmits the compensation power signal to the first node;

[0052] In the third stage, the data writing circuit controls the data line to be connected to the first node in response to the gate driving signal provided by the gate line, so that the data line transmits the data signal to the first node;

[0053] In the fourth stage, the first light-emitting control circuit controls the driving power line to be conductive with the second node in response to the first light-emitting control signal provided by the first light-emitting control line, so that the driving power line transmits the driving power signal to the second node; and the driving circuit transmits the driving signal to the third node based on the potential of the first node and the potential of the second node, so as to drive the light-emitting element coupled to the third node to emit light.

[0054] The compensation power line is introduced through both sides of the display panel to transmit the compensation power signal to the pixel circuit in both directions.

[0055] In yet another aspect, a display panel is provided, comprising: a substrate, and a plurality of pixels located on the substrate;

[0056] The pixel includes: a light-emitting element, and the pixel circuit as described in the above aspect; the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0057] In another aspect, a display device is provided, comprising: a power supply component, and the display panel as described in the above-mentioned further aspect;

[0058] The power supply component is coupled to the display panel and is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] FIG1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0061] FIG2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0062] FIG3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0063] FIG4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0064] FIG5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0065] FIG6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0066] FIG7 is a circuit structure diagram of a pixel circuit, taking the structure shown in FIG3 as an example;

[0067] FIG8 is a circuit structure diagram of another pixel circuit, taking the structure shown in FIG4 as an example;

[0068] FIG9 is a circuit structure diagram of another pixel circuit, taking the structure shown in FIG5 as an example;

[0069] FIG10 is a circuit structure diagram of another pixel circuit, taking the structure shown in FIG6 as an example;

[0070] FIG11 is a flow chart of a driving method for a pixel circuit provided in an embodiment of the present disclosure;

[0071] FIG12 is a timing diagram showing an operation of a pixel circuit, taking the structure shown in FIG7 as an example;

[0072] FIG13 is a timing diagram showing an operation of a pixel circuit, taking the structure shown in FIG8 as an example;

[0073] FIG14 is an operation timing diagram of another pixel circuit, taking the structure shown in FIG9 as an example;

[0074] FIG15 is an operation timing diagram of another pixel circuit, taking the structure shown in FIG10 as an example;

[0075] FIG16 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0076] FIG17 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0078] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. The source is referred to as the first electrode and the drain as the second electrode, or the drain is referred to as the first electrode and the source as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Furthermore, the switching transistors used in the embodiments of the present disclosure may include either a P-type transistor or an N-type transistor, or a combination thereof. A P-type transistor is turned on when the gate voltage is low and turned off when the gate voltage is high, while an N-type transistor is turned on when the gate voltage is high and turned off when the gate voltage is low. Furthermore, multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two different states and do not represent that the first potential or the second potential has a specific value.

[0079] Figure 1 is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure, which is applied to a display panel. That is, the display panel may include the pixel circuit shown in Figure 1. As shown in Figure 1, the pixel circuit includes: a data writing circuit 01, a first light-emitting control circuit 02, a reset circuit 03, a driving circuit 04, and a compensation circuit 05.

[0080] 1 , the data writing circuit 01 is coupled to the gate line G1 , the data line D1 and the first node N1 , and is configured to control the connection between the data line D1 and the first node N1 in response to a gate driving signal provided by the gate line G1 .

[0081] For example, the data write circuit 01 can control the data line D1 to be connected to the first node N1 when the potential of the gate drive signal provided by the gate line G1 is a first potential. At this time, the data signal provided by the data line D1 is transmitted to the first node N1. Furthermore, the data write circuit 01 can control the data line D1 to be disconnected from the first node N1 when the potential of the gate drive signal provided by the gate line G1 is a second potential.

[0082] Optionally, in the disclosed embodiment, the first potential may be an effective potential, and the second potential may be an ineffective potential. Furthermore, in one embodiment, the first potential may be a low potential relative to the second potential, and in this embodiment, the transistor in the pixel circuit includes a P-type transistor that is turned on at a low potential. In another embodiment, the first potential may be a high potential relative to the second potential, and in this embodiment, the transistor in the pixel circuit includes an N-type transistor that is turned on at a high potential.

[0083] Continuing to refer to Figure 1, it can be seen that the first light-emitting control circuit 02 is coupled to the first light-emitting control line EMA, the driving power line VDD and the second node N2 respectively, and is used to control the on and off of the driving power line VDD and the second node N2 in response to the first light-emitting control signal provided by the first light-emitting control line EMA.

[0084] For example, the first light-emitting control circuit 02 can control the driving power line VDD to be connected to the second node N2 when the potential of the first light-emitting control signal provided by the first light-emitting control line EMA is a first potential. In this case, the driving power signal provided by the driving power line VDD can be transmitted to the second node N2. Furthermore, the first light-emitting control circuit 02 can control the driving power line VDD to be disconnected from the second node N2 when the potential of the first light-emitting control signal provided by the first light-emitting control line EMA is a second potential.

[0085] Continuing with FIG1 , it can be seen that the reset circuit 03 is coupled to the reset line GW, the initial power line Var, and a third node N3, respectively, and is configured to control the connection and disconnection between the initial power line Var and the third node N3 in response to a reset signal provided by the reset line GW. The third node N3 is coupled to the light-emitting element L1.

[0086] For example, the reset circuit 03 can control the initial power line Var to be electrically connected to the third node N3 when the potential of the reset signal provided by the reset line GW is a first potential. In this case, the initial power signal provided by the initial power line Var can be transmitted to the third node N3. Furthermore, the reset circuit 03 can control the initial power line Var to be disconnected from the third node N3 when the potential of the reset signal provided by the reset line GW is a second potential.

[0087] Alternatively, referring to FIG1 , the third node N3 may be coupled to the first electrode of the light-emitting element L1, and the second electrode of the light-emitting element L1 may be coupled to the pull-down power supply line VSS. Of the first and second electrodes of the light-emitting element L1, one may be an anode, and the other may be a cathode. For example, FIG1 illustrates the first electrode of the light-emitting element L1 as an anode, and the second electrode as a cathode. The coupled pixel circuit and light-emitting element may be referred to as a pixel.

[0088] Continuing to refer to Figure 1, it can be seen that the driving circuit 04 is coupled to the first node N1, the second node N2 and the third node N3 respectively, and is used to transmit a driving signal to the third node N3 (i.e., the light-emitting element L1) based on the potential of the first node N1 and the potential of the second node N2 to drive the light-emitting element L1 to emit light.

[0089] For example, the light emitting element L1 may emit light under the action of a voltage difference between a driving signal (eg, driving current) transmitted by the driving circuit 04 and a pull-down power signal provided by the pull-down power line VSS.

[0090] Continuing to refer to Figure 1, it can be seen that the compensation circuit 05 is coupled to at least one compensation line GB, the compensation power line VB, the driving power line VDD and the first node N1 respectively, and is used to control the connection and disconnection of the compensation power line VB and the first node N1 in response to the compensation signal provided by at least one compensation line GB, and is used to adjust the potential of the first node N1.

[0091] For example, the compensation circuit 05 can control the compensation power line VB to be electrically connected to the first node N1 when the potential of the compensation signal provided by at least one compensation line GB is at a first potential. In this case, the compensation power signal provided by the compensation power line VB can be transmitted to the first node N1. Furthermore, the compensation circuit 05 can control the compensation power line VB to be decoupled from the first node N1 when the potential of the compensation signal provided by at least one compensation line GB is at a second potential. Furthermore, the compensation circuit 05 can also adjust the potential of the first node N1 through coupling.

[0092] On this basis, by coordinating the operation of other circuits and flexibly configuring various signals, the drive signal transmitted by the driver circuit 04 to the light-emitting element L1 based on the potential of the first node N1 can be related to the compensation power signal provided by the compensation power line VB and the data signal provided by the data line D1, and is independent of the threshold voltage Vth of the driver transistor in the driver circuit 04 or the drive power signal provided by the drive power line VDD. This prevents not only the difference in voltage drops (IR drops) at different locations on the drive power line VDD that could result in an inability to reliably drive the light-emitting element, but also the characteristic drift (here, threshold voltage drift) of the driver transistor that could result in an inability to reliably drive the light-emitting element. In other words, dual compensation for the drive power signal and threshold voltage can be achieved, ensuring reliable drive of the light-emitting element and improving display uniformity across the display panel.

[0093] It should be noted that, in the embodiment of the present disclosure, the compensation power line VB can be introduced through both sides of the display panel to transmit the compensation power signal bidirectionally to the pixel circuit. In combination with the above embodiment, the compensation power signal is specifically transmitted bidirectionally to the compensation circuit 05 in the pixel circuit. By bidirectional introduction, it can be distinguished from the unidirectional introduction of the driving power line VDD in the related art, or the reference power line Vref coupled to the reset circuit / compensation circuit, to ensure that pixels at different positions in the same row receive the same size of compensation power signal, that is, there is no voltage drop problem similar to the driving power line VDD / reference power line Vref. In other words, although the driving signal transmitted to the light-emitting element L1 by the driving circuit 04 provided in the embodiment of the present disclosure is related to the compensation power signal, the compensation circuit 05 does not realize compensation for the compensation power signal provided by the compensation power line VB, but because the compensation power line VB is introduced bidirectionally, it can still ensure good display uniformity.

[0094] In summary, the embodiments of the present disclosure provide a pixel circuit. A data write circuit can control the connection and disconnection between a data line and a first node under the control of a gate drive signal provided by a gate line; a first light-emitting control circuit can control the connection and disconnection between a driving power line and a second node under the control of a first light-emitting control signal provided by a first light-emitting control line; a reset circuit can control the connection and disconnection between an initial power line and a third node under the control of a reset signal provided by a reset line; and a compensation circuit can control the connection and disconnection between a compensation power line and the first node under the control of a compensation signal provided by a compensation line, while simultaneously adjusting the potential of the first node. Thus, by flexibly setting each signal, the drive signal transmitted by the drive circuit to the light-emitting element based on the potential of the first node is independent of the drive power signal provided by the drive power line and the threshold voltage of the drive transistor in the drive circuit, thereby achieving compensation for the drive power signal and the threshold voltage. Furthermore, the influence of the voltage drop on the drive power line and the characteristic drift of the drive transistor on the drive signal transmitted to the light-emitting element can be avoided, ensuring that the drive circuit reliably drives the light-emitting element to emit light, thereby achieving a better display effect of the display panel.

[0095] Optionally, FIG2 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG2 , in the pixel circuit described in the embodiment of the present disclosure, the compensation circuit 05 may include: a switch subcircuit 051 and a first adjustment subcircuit 052 .

[0096] 2 , it can be seen that the switch sub-circuit 051 can be coupled to at least one compensation line GB, the compensation power line VB and the first node N1, respectively, and can be used to control the on / off connection between the compensation power line VB and the first node N1 in response to a compensation signal provided by at least one compensation line GB.

[0097] For example, the switch sub-circuit 051 can control the compensation power line VB to be conductively coupled to the first node N1 when the potential of the compensation signal provided by the at least one compensation line GB is a first potential, so that the compensation power signal provided by the compensation power line VB can be transmitted to the first node N1. Furthermore, the switch sub-circuit 051 can control the compensation power line VB to be decoupled from the first node N1 when the potential of the compensation signal provided by the at least one compensation line GB is a second potential.

[0098] 2 , it can be seen that the first regulating sub-circuit 052 can be coupled to the driving power line VDD and the first node N1 respectively, and can be used to regulate the potential of the first node N1.

[0099] For example, the first regulating sub-circuit 052 can regulate the potential of the first node N1 through coupling.

[0100] Optionally, the first regulating sub-circuit 052 may be indirectly coupled to the driving power line VDD through the first light emitting control circuit 02. Alternatively, the first regulating sub-circuit 052 may be directly coupled to the driving power line VDD.

[0101] First, taking the indirect coupling of the first regulating sub-circuit 052 to the driving power line VDD via the first light emitting control circuit 02 as an example, the following embodiment provides a design method for a pixel circuit.

[0102] 1. As an optional implementation:

[0103] Referring to the schematic structural diagram of another pixel circuit shown in FIG3 , it can be seen that, while the first regulating sub-circuit 052 is indirectly coupled to the driving power line VDD via the first light-emitting control circuit 02, the switching sub-circuit 051 can be coupled to two compensation lines GB, namely, the first compensation line GB1 and the second compensation line GB2. Accordingly, the switching sub-circuit 051 can include a first switching unit 0511 and a second switching unit 0512.

[0104] 3 , the first switch unit 0511 can be coupled to the first compensation line GB1, the compensation power line VB and the fourth node N4, respectively, and can be used to control the on / off connection between the compensation power line VB and the fourth node N4 in response to the compensation signal provided by the first compensation line GB1.

[0105] For example, when the potential of the compensation signal provided by the first compensation line GB1 is a first potential, the first switch unit 0511 can control the compensation power line VB to be conductive with the fourth node N4, so that the compensation power signal provided by the compensation power line VB can be transmitted to the fourth node N4. Furthermore, when the potential of the compensation signal provided by the first compensation line GB1 is a second potential, the first switch unit 0511 can control the compensation power line VB to be decoupled from the fourth node N4.

[0106] Continuing to refer to Figure 3, it can be seen that the second switch unit 0512 can be coupled to the second compensation line GB2, the fourth node N4 and the first node N1 respectively, and can be used to control the connection and disconnection of the fourth node N4 and the first node N1 in response to the compensation signal provided by the second compensation line GB2.

[0107] For example, when the potential of the compensation signal provided by the second compensation line GB2 is the first potential, the second switch unit 0512 can control the fourth node N4 to be conductive with the first node N1, so that the signal transmitted to the fourth node N4 can be further transmitted to the first node N1. Furthermore, when the potential of the compensation signal provided by the second compensation line GB2 is the second potential, the second switch unit 0512 can control the fourth node N4 to be decoupled from the first node N1.

[0108] 3 , it can be seen that the first regulating sub-circuit 052 can be coupled to the second node N2 to be indirectly coupled to the driving power line VDD via the first light-emitting control circuit 02. Furthermore, the first regulating sub-circuit 052 can also be coupled to the fourth node N4 to be indirectly coupled to the first node N1 via the second switch unit 0512.

[0109] Optionally, for the structure shown in FIG3 , in some embodiments, the gate line G1 and the reset line GW can be shared. That is, the data write circuit 01 and the reset circuit 03 can be coupled to the same signal line (e.g., the reset line GW), and the on / off control between the two coupled parts can be controlled by the signal provided by the same signal line. This simplifies wiring, saves costs, reduces the number of signals required to be connected, reduces power consumption, and facilitates the narrow-frame design of the display panel.

[0110] 2. As another optional implementation:

[0111] Based on FIG. 3 , referring to FIG. 4 which shows a structural diagram of another pixel circuit, it can be seen that the compensation circuit 05 described in the embodiment of the present disclosure may further include: a second regulating subcircuit 053 .

[0112] The second regulating sub-circuit 053 can be coupled to the reset line GW, the driving power line VDD and the second node N2 respectively, and can be used to control the connection and disconnection of the driving power line VDD and the second node N2 in response to the reset signal provided by the reset line GW to adjust the potential of the second node N2.

[0113] For example, the second regulating sub-circuit 053 can control the driving power line VDD to be conductive with the second node N2 when the potential of the reset signal provided by the reset line GW is a first potential, and regulate the potential of the second node N2 through coupling. Furthermore, the second regulating sub-circuit 053 can control the driving power line VDD to be decoupled from the second node N2 when the potential of the reset signal provided by the reset line GW is a second potential.

[0114] 3. As another optional implementation:

[0115] Referring to the structural schematic diagram of another pixel circuit shown in FIG5 , it can be seen that, given that the compensation circuit 05 includes the second regulating sub-circuit 053 shown in FIG4 , and the first regulating sub-circuit 052 is indirectly coupled to the driving power line VDD via the first light-emitting control circuit 02 , the switch sub-circuit 051 can be coupled to a single compensation line. In other words, referring to FIG5 , the switch sub-circuit 051 does not need to be divided into two switching units; it can be coupled to only one compensation line (here, the first compensation line GB1 described in the above embodiment is used as an example). Accordingly, it can also be seen that there is no fourth node N4 to which the two switching units are coupled, and the first regulating sub-circuit 052 can be directly coupled to the first node N1.

[0116] Next, taking the example that the first regulating sub-circuit 052 can be directly coupled to the driving power line VDD, the following embodiment provides a design method for the pixel circuit.

[0117] Referring to the structural schematic diagram of another pixel circuit shown in Figure 6, it can be seen that on the basis of the first regulation sub-circuit 052 being directly coupled to the driving power line VDD, the switch sub-circuit 051 can be coupled to a compensation line (here taking the first compensation line GB1 recorded in the above embodiment as an example), and the compensation circuit 05 can also include: a third regulation sub-circuit 054.

[0118] 6 , it can be seen that the third regulating sub-circuit 054 can be coupled to the first node N1 and the fifth node N5 respectively, and can be used to regulate the potential of the first node N1 and the potential of the fifth node N5.

[0119] For example, the third regulating sub-circuit 054 can regulate the potential of the first node N1 and the potential of the fifth node N5 through coupling.

[0120] Continuing to refer to FIG. 6 , it can be seen that the pixel circuit may further include: a second light emitting control circuit 06 .

[0121] The second light emitting control circuit 06 can be coupled to the second light emitting control line EMB, the fifth node N5 and the third node N3 respectively, and can be used to control the connection and disconnection of the fifth node N5 and the third node N3 in response to the second light emitting control signal provided by the second light emitting control line EMB.

[0122] For example, the second light-emitting control circuit 06 can control the fifth node N5 to be conductive with the third node N3 when the potential of the second light-emitting control signal provided by the second light-emitting control line EMB is a first potential, so that the signal transmitted to the fifth node N5 is further transmitted to the third node N3. Furthermore, the second light-emitting control circuit 06 can control the fifth node N5 to be decoupled from the third node N3 when the potential of the second light-emitting control signal provided by the second light-emitting control line EMB is a second potential.

[0123] On this basis, it can be seen from FIG6 that the driving circuit 04 can be coupled to the fifth node N5 to be indirectly coupled to the third node N3 through the second light emitting control circuit 06 .

[0124] Of course, in some other embodiments, any pixel circuit shown in FIG. 3 to FIG. 5 may also include the second light emitting control circuit 06 as shown in FIG. 6 .

[0125] Optionally, in some embodiments, the initial power line Var coupled to the reset circuit 03 can also be routed through both sides of the display panel. Furthermore, as can be seen from Figures 2 to 6 , the compensation power line VB can be shared with the initial power line Var. That is, the reset circuit 03 and the compensation circuit 05 can share the same signal line. This further simplifies wiring, reduces costs, and facilitates the design of a narrow-frame display panel.

[0126] Alternatively, taking the structure shown in FIG3 as an example, FIG7 shows a circuit structure diagram of a pixel circuit. Taking the structure shown in FIG4 as an example, FIG8 shows a circuit structure diagram of another pixel circuit. Taking the structure shown in FIG5 as an example, FIG9 shows a circuit structure diagram of yet another pixel circuit. Taking the structure shown in FIG6 as an example, FIG10 shows a circuit structure diagram of yet another pixel circuit.

[0127] (1) Referring to FIG. 7 and FIG. 8 , it can be seen that, based on the division of the switch subcircuit 051 into two switch units, the first switch unit 0511 may include: a first transistor T1. The second switch unit 0512 may include: a second transistor T2. The first regulating subcircuit 052 may include: a first capacitor C1.

[0128] The gate of the first transistor T1 can be coupled to the first compensation line GB1, the first electrode of the first transistor T1 can be coupled to the compensation power line VB (ie, the initial power line Var), and the second electrode of the first transistor T1 can be coupled to the fourth node N4.

[0129] A gate electrode of the second transistor T2 may be coupled to the second compensation line GB2 , a first electrode of the second transistor T2 may be coupled to the fourth node N4 , and a second electrode of the second transistor T2 may be coupled to the first node N1 .

[0130] A first end (ie, a first plate) of the first capacitor C1 may be coupled to the fourth node N4 , and a second end (ie, a second plate) of the first capacitor C1 may be coupled to the second node N2 .

[0131] (2) Referring to FIG. 8 and FIG. 9 , it can be seen that the second regulating sub-circuit 053 may include: a third transistor T3 and a second capacitor C2.

[0132] Among them, the gate of the third transistor T3 can be coupled to the reset line GW, the first electrode of the third transistor T3 can be coupled to the first end of the second capacitor C2, the second electrode of the third transistor T3 can be coupled to the second node N2, and the second end of the second capacitor C2 can be coupled to the driving power line VDD.

[0133] (3) Based on the structure shown in FIG5 , i.e., the switch sub-circuit 051 does not need to be divided into two switch units, there is no fourth node N4 coupled between the two switch units, and the first regulating sub-circuit 052 is directly coupled to the first node N1, it can be seen from the corresponding circuit structure diagram shown in FIG9 that the switch sub-circuit 051 can include a first transistor T1 as shown in FIG7 and FIG8 . Furthermore, the first end of the first capacitor C1 can be directly coupled to the first node N1.

[0134] (4) Based on the structure shown in FIG6 , i.e., the structure in which the first regulating subcircuit 052 is directly coupled to the driving power line VDD and the switch subcircuit 051 is coupled to a compensation line GB1, referring to the corresponding circuit structure diagram shown in FIG10 , it can be seen that the switch subcircuit 051 may include a fourth transistor T4. The first regulating subcircuit 052 includes a third capacitor C3. The third regulating subcircuit 054 may include a fourth capacitor C4. The second light-emitting control circuit 06 may include a fifth transistor T5.

[0135] The gate of the fourth transistor T4 can be coupled to the compensation line GB1, the first electrode of the fourth transistor T4 can be coupled to the compensation power line VB (ie, the initial power line Var), and the second electrode of the fourth transistor T4 can be coupled to the first node N1.

[0136] A gate electrode of the fifth transistor T5 may be coupled to the second light emitting control line EMB, a first electrode of the fifth transistor T5 may be coupled to the fifth node N5, and a second electrode of the fifth transistor T5 may be coupled to the third node N3.

[0137] A first terminal of the third capacitor C3 may be coupled to the driving power line VDD, and a second terminal of the third capacitor C3 may be coupled to the first node N1.

[0138] A first terminal of the fourth capacitor C4 may be coupled to the first node N1 , and a second terminal of the fourth capacitor C4 may be coupled to the fifth node N5 .

[0139] Furthermore, referring to Figures 7 to 10 , it can be seen that in any of the above implementations, the data writing circuit 01 can include a sixth transistor T6. The first light-emitting control circuit 02 can include a seventh transistor T7. The reset circuit 03 can include an eighth transistor T8. The driving circuit 04 can include a ninth transistor T9, which is also the driving transistor described in the above embodiments.

[0140] A gate of the sixth transistor T6 may be coupled to the gate line G1 , a first electrode of the sixth transistor T6 may be coupled to the data line D1 , and a second electrode of the sixth transistor T6 may be coupled to the first node N1 .

[0141] A gate of the seventh transistor T7 may be coupled to the first light emitting control line EMA, a first electrode of the seventh transistor T7 may be coupled to the driving power line VDD, and a second electrode of the seventh transistor T7 may be coupled to the second node N2.

[0142] A gate electrode of the eighth transistor T8 may be coupled to the reset line GW, a first electrode of the eighth transistor T8 may be coupled to the initial power line Var, and a second electrode of the eighth transistor T8 may be coupled to the third node N3.

[0143] A gate of the ninth transistor T9 may be coupled to the first node N1 , a first electrode of the ninth transistor T9 may be coupled to the second node N2 , and a second electrode of the ninth transistor T9 may be coupled to the third node N3 .

[0144] Furthermore, it should be noted that, for the structure shown in FIG. 10 , the second electrode of the ninth transistor T9 may be coupled to the fifth node N5 , so as to be indirectly coupled to the third node N3 through the fifth transistor T5 .

[0145] Optionally, for the pixel circuit designs shown in FIG. 3 to FIG. 5 , ie, FIG. 7 to FIG. 9 , the transistors in the pixel circuits may include: P-type transistors.

[0146] Optionally, for the pixel circuit design shown in FIG. 6 , that is, FIG. 10 , the transistors in the pixel circuit may include: N-type transistors.

[0147] For example, the material of the P-type transistor may include: low temperature polysilicon (LTPS) material. The material of the N-type transistor may include: oxide (Oxide) material. The materials here may all refer to the materials of the active layer in the transistor. In addition, the pixel circuit may also be coupled to the display driver circuit to receive the drive signal transmitted by the display driver circuit. For example, the display driver circuit may be a gate driver on array (GOA) circuit, and the pixel circuit may be coupled to the GOA circuit through the gate line G1 to receive the gate drive signal provided by the GOA circuit, and the display driver circuit also includes a plurality of transistors. For a pixel circuit including an N-type transistor, the transistor in the coupled display driver circuit may be a transistor made of LTPS material. Accordingly, a display product including a P-type transistor pixel circuit may also be referred to as an LTPS display product. A display product including an N-type transistor pixel circuit may also be referred to as an LTPS+Oxide display product, that is, an LTPO display product. Of course, the above is only a schematic illustration.

[0148] Based on the above embodiments, it can be seen that the circuit shown in Figure 7 can be called a pixel circuit of the LTPS 6T1C structure (i.e., including 6 transistors and 1 capacitor); the circuit shown in Figure 8 can be called a pixel circuit of the LTPS 7T2C structure; the circuit shown in Figure 9 can be called a pixel circuit of the LTPS 6T2C structure; and the circuit shown in Figure 10 can be called a pixel circuit of the LTPO+6T2C structure. Of course, the above are only schematic illustrations. For example, in some other embodiments, the circuit shown in Figure 7 can also include the above-mentioned fifth transistor T5, and be changed to a pixel circuit of the LTPS 7T1C structure.

[0149] Based on the above-mentioned embodiments, it can be seen that the pixel circuit structure provided by the embodiments of the present disclosure is simple, and can effectively reduce the voltage drop on the power line, and also improve the capacitor charging speed, thereby improving the processing speed of the pixel circuit, avoiding the impact of threshold voltage drift or voltage drop on the luminous brightness of the light-emitting element, and achieving better display uniformity and better display effect. While the circuit structure is simple, the design capacity of the display area can also be increased, making it easier to design high-density pixels. It has a good advantage for large-size products.

[0150] In summary, the embodiments of the present disclosure provide a pixel circuit. A data write circuit can control the connection and disconnection between a data line and a first node under the control of a gate drive signal provided by a gate line; a first light-emitting control circuit can control the connection and disconnection between a driving power line and a second node under the control of a first light-emitting control signal provided by a first light-emitting control line; a reset circuit can control the connection and disconnection between an initial power line and a third node under the control of a reset signal provided by a reset line; and a compensation circuit can control the connection and disconnection between a compensation power line and the first node under the control of a compensation signal provided by a compensation line, while simultaneously adjusting the potential of the first node. Thus, by flexibly setting each signal, the drive signal transmitted by the drive circuit to the light-emitting element based on the potential of the first node is independent of the drive power signal provided by the drive power line and the threshold voltage of the drive transistor in the drive circuit, thereby achieving compensation for the drive power signal and the threshold voltage. Furthermore, the influence of the voltage drop on the drive power line and the characteristic drift of the drive transistor on the drive signal transmitted to the light-emitting element can be avoided, ensuring that the drive circuit reliably drives the light-emitting element to emit light, thereby achieving a better display effect of the display panel.

[0151] FIG11 is a flow chart of a method for driving a pixel circuit according to an embodiment of the present disclosure, which can be applied to the pixel circuits shown in any one of FIG1 to FIG10 . As shown in FIG11 , the method includes:

[0152] Step 1101, in the first stage, the reset circuit controls the initial power line to be connected to the third node, so that the initial power line transmits the initial power signal to the third node.

[0153] Step 1102, second stage: the compensation circuit controls the compensation power line to be connected to the first node in response to the compensation signal provided by at least one compensation line, and adjusts the potential of the first node so that the compensation power line transmits the compensation power signal to the first node.

[0154] Step 1103 , the third stage: the data writing circuit controls the data line to be connected to the first node in response to the gate driving signal provided by the gate line, so that the data line transmits the data signal to the first node.

[0155] Step 1104, the fourth stage, the first light-emitting control circuit controls the driving power line to be connected to the second node in response to the first light-emitting control signal provided by the first light-emitting control line, so that the driving power line transmits the driving power signal to the second node; the driving circuit transmits the driving signal to the third node based on the potential of the first node and the potential of the second node to drive the light-emitting element coupled to the third node to emit light.

[0156] The compensation power supply line may be introduced through both sides of the display panel to transmit the compensation power supply signal to the pixel circuit in both directions.

[0157] As an optional implementation:

[0158] Taking the pixel circuit structure shown in FIG7 as an example, FIG12 shows a working timing diagram of a pixel circuit provided by an embodiment of the present disclosure. In conjunction with FIG12, the working principle of the pixel circuit is described as follows:

[0159] (1) In the first phase t01, the potential of the gate drive signal provided by the gate line G1, the potential of the light-emitting control signal provided by the first light-emitting control line EMA, and the potential of the compensation signal provided by the first compensation line GB1 can all be low potentials (effective potentials). Since the reset line GW is shared with the gate line G1, the potential of the reset signal provided by the reset line GW can also be low potential; while the potential of the compensation signal provided by the second compensation line GB2 can be high potential (ineffective potential). Accordingly, the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be turned on; and the second transistor T2 can be turned off.

[0160] On this basis, the initial power signal provided by the initial power line Var can be transmitted to the third node N3 via the turned-on eighth transistor T8. Because the compensation power line VB shares the same voltage as the initial power line Var, the initial power signal can also be transmitted as a compensation power signal to the fourth node N4 via the turned-on first transistor T1. The data signal provided by the data line D1 can be transmitted to the first node N1 via the turned-on sixth transistor T6. And, the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via the turned-on seventh transistor T7. Assuming the potential of the initial power signal is Var0, the potential of the data signal is Vdata, and the potential of the driving power signal is VDD0, it can be seen that in the first phase t01, the potential VN3 of the third node N3 and the potential VN4 of the fourth node N4 can both satisfy: VN3 = VN4 = Var0; the potential VN1 of the first node N1 can satisfy: VN1 = Vdata; and the potential VN2 of the second node N2 can satisfy: VN2 = VDD0, causing the ninth transistor T9 to be turned off. Turning on the eighth transistor T8 can prevent the leakage current of the ninth transistor T9 from causing the light emitting element L1 to emit light prematurely. The first stage t01 can also be called an initialization stage.

[0161] (2) In the second phase t02, the potential of the gate drive signal provided by the gate line G1 and the potential of the compensation signal provided by the first compensation line GB1 can both be low. Since the reset line GW is shared with the gate line G1, the potential of the reset signal provided by the reset line GW can also be low. The potential of the light-emitting control signal provided by the first light-emitting control line EMA and the potential of the compensation signal provided by the second compensation line GB2 can both be high. Accordingly, the first transistor T1, the sixth transistor T6, and the eighth transistor T8 can all be turned on; while the second transistor T2 and the seventh transistor T7 can both be turned off.

[0162] On this basis, the initial power signal provided by the initial power line Var can still be transmitted to the third node N3 through the turned-on eighth transistor T8, and can still be transmitted to the fourth node N4 through the turned-on first transistor T1; and the data signal provided by the data line D1 can still be transmitted to the first node N1 through the turned-on sixth transistor T6. And at this time, for the ninth transistor T9, the gate-source voltage difference Vgs is less than the threshold voltage Vth, that is, Vgs<Vth, so the ninth transistor T9 is turned on, and the second end (i.e., the second plate) of the first capacitor C1 coupled to the second node N2 is discharged, and the current can flow to the eighth transistor T8. When Vgs = Vdata - VN2 = Vth, that is, VN2 = Vdata - Vth, the discharge can be cut off. In this way, the data signal is written into the second node N2. In addition, similar to the first stage t01, by turning on the eighth transistor T8, the leakage current of the ninth transistor T9 can also be prevented from causing the light-emitting element L1 to emit light in advance, which can be regarded as adding a black frame, and can play a certain role in improving the short-term afterimage. The second stage t02 can also be called the compensation stage.

[0163] (3) In the third stage t03, the potential of the light-emitting control signal provided by the first light-emitting control line EMA and the potential of the compensation signal provided by the second compensation line GB2 can both be low potentials; while the potential of the gate driving signal provided by the gate line G1 and the potential of the compensation signal provided by the first compensation line GB1 can both be high potentials, and because the reset line GW shares the gate line G1, the potential of the reset signal provided by the reset line GW can also be high. Correspondingly, the second transistor T2 and the seventh transistor T7 can both be turned on; while the first transistor T1, the sixth transistor T6 and the eighth transistor T8 can all be turned off.

[0164] On this basis, the signal transmitted to the fourth node N4 can be transmitted to the first node N1 via the turned-on second transistor T2; and the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via the turned-on seventh transistor T7. That is, in the third phase t03, the potential VN2 of the second node N2 can satisfy: VN2 = VDD0. Furthermore, relative to the second phase t02, the potential change ΔVN2 of the second node N2 can satisfy: ΔVN2 = VDD0 - (Vdata - Vth). Under the coupling effect of the first capacitor C1, the first capacitor C1 is coupled to the first end of the fourth node N4 (i.e., the first plate of the first capacitor C1). That is, the potential VN4 of the fourth node N4 can satisfy: VN4 = Var0 + VDD0 - Vdata + Vth. At this time, for the ninth transistor T9, its Vgs - Vth = Var0 - Vdata < 0. The ninth transistor T9 can remain turned on, transmitting the driving signal to the light-emitting element L1, thereby driving the light-emitting element L1 to emit light. The driving signal may refer to a driving current I, and I satisfies: I = (1 / 2) μ * Cox * (W / L) * (Var0 - Vdata) 2 The third stage t03 may also be called a light-emitting stage.

[0165] Where W / L refers to the width-to-length ratio of the ninth transistor T9, μ refers to the hole mobility of the ninth transistor T9, and Cox refers to the gate capacitance of the ninth transistor T9. These values ​​are all fixed, and the same applies to the following embodiments, so they are not further described. It can be seen that the drive current ultimately transmitted to the light-emitting element L1 is independent of the drive power signal provided by the drive power line VDD and the threshold voltage Vth of the ninth transistor T9. This achieves reliable compensation for the voltage drop on the drive power line VDD and the characteristic drift of the ninth transistor T9, improving the long-range uniformity of the current and ensuring a better display effect of the display panel.

[0166] Optionally, as can be seen from FIG. 12 , in the third phase t03 , the potential of the light-emission control signal provided by the first light-emission control line EMA can be set to a lower potential in advance relative to the potential of the compensation signal provided by the second compensation line GB2 , causing the seventh transistor T7 to turn on earlier than the second transistor T2 , resulting in a margin between the turn-on times. In this manner, the coupling voltage can be first written to the fourth node N4 via the coupling effect of the first capacitor C1 , and then the second transistor T2 can be turned on to further write the coupling voltage to the first node N1 .

[0167] It should be noted that, as can be seen from FIG12 , for the structure shown in FIG7 , the third stage corresponding to FIG11 can be executed simultaneously with the first stage / second stage, so it can be shortened to three stages.

[0168] Furthermore, it should be noted that for the structure shown in FIG7 , if the initial power line Var coupled to the first transistor T1 is replaced with the reference power line Vref, the first stage t01 to the third stage t03 shown in FIG12 can also be performed. Accordingly, it can be inferred that the driving current I transmitted to the light-emitting element L1 can satisfy the following: I = (1 / 2) μ * Cox * (W / L) * (Vref0 - Vdata) 2 Vref0 refers to the potential of the reference power signal provided by the reference power line Vref. Therefore, it can be determined that by replacing the signal line, compensation for the driving power signal provided by the driving power line VDD and the threshold voltage Vth of the ninth transistor T9 can also be achieved. However, the wiring method of the reference power line Vref and the driving power line VDD is generally the same, which results in a poor compensation effect.

[0169] As another optional implementation:

[0170] Taking the structure shown in FIG8 as an example, FIG13 shows an operation timing diagram of another pixel circuit provided by an embodiment of the present disclosure. In conjunction with FIG13, the operation principle of the pixel circuit is described as follows:

[0171] (1) In the first phase t01, the potential of the gate drive signal provided by the gate line G1, the potential of the compensation signal provided by the second compensation line GB2, the potential of the first light-emitting control signal provided by the first light-emitting control line EMA, and the potential of the reset signal provided by the reset line GW can all be low potentials (effective potentials); while the potential of the compensation signal provided by the first compensation line GB1 can be high potential (ineffective potential). Accordingly, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be turned on; and the first transistor T1 can be turned off.

[0172] On this basis, the data signal provided by the data line D1 can be transmitted to the first node N1 via the enabled sixth transistor T6; the initial power signal provided by the initial power line Var can be transmitted to the third node N3 via the enabled eighth transistor T8; the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via both the enabled seventh transistor T7 and the enabled third transistor T3; and the signal transmitted to the first node N1 can be transmitted to the fourth node N4 via the enabled second transistor T2, thereby charging the first capacitor C1 and the second capacitor C2. That is, in the first phase t01, the potential VN1 of the first node N1 and the potential VN4 of the fourth node N4 can both satisfy: VN1 = VN4 = Vdata; the potential VN2 of the second node N2 can satisfy: VN2 = VDD0; and the potential VN3 of the third node N3 can satisfy: VN3 = Var0. The ninth transistor T9 is in the off state. Similar to the above-mentioned alternative implementation, turning on the eighth transistor T8 can prevent leakage current of the ninth transistor T9 from causing the light-emitting element L1 to emit prematurely. The first phase t01 may also be called an initialization phase.

[0173] (2) In the second phase t02, the potential of the gate drive signal provided by the gate line G1, the potential of the compensation signal provided by the second compensation line GB2, and the potential of the reset signal provided by the reset line GW can all be low; while the potential of the compensation signal provided by the first compensation line GB1 and the potential of the first light-emitting control signal provided by the first light-emitting control line EMA can all be high. Accordingly, the second transistor T2, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 can all be turned on; while the first transistor T1 and the seventh transistor T7 can both be turned off.

[0174] On this basis, the data signal provided by the data line D1 can still be transmitted to the first node N1 through the turned-on sixth transistor T6; the initial power signal provided by the initial power line Var can still be transmitted to the third node N3 through the turned-on eighth transistor T8; the driving power signal provided by the driving power line VDD can still be transmitted to the second node N2 through the turned-on third transistor T3; and the signal transmitted to the first node N1 can still be transmitted to the fourth node N4 through the turned-on second transistor T2. At this time, for the ninth transistor T9, the gate-source voltage difference Vgs is less than the threshold voltage Vth, that is, Vgs<Vth, and the ninth transistor T9 is turned on. The potential of the second node N2 can be discharged to: VN2 = Vdata - Vth, so that the ninth transistor T9 is turned off, and the current can flow to the eighth transistor T8. In this way, the writing of the data signal and the threshold voltage Vth of the ninth transistor T9 is achieved. In addition, similar to the first stage t01, by turning on the eighth transistor T8, the leakage current of the ninth transistor T9 can also be prevented from causing the light-emitting element L1 to emit light in advance, which can be regarded as adding a black screen frame and can play a certain role in improving the short-time afterimage. The second stage t02 can also be called the compensation stage.

[0175] (3) In the third stage t03, the potential of the compensation signal provided by the first compensation line GB1 and the potential of the reset signal provided by the reset line GW can be low potentials; while the potential of the gate driving signal provided by the gate line G1, the potential of the compensation signal provided by the second compensation line GB2, and the potential of the light-emitting control signal provided by the first light-emitting control line EMA can all be high potentials. Correspondingly, the first transistor T1, the third transistor T3, and the eighth transistor T8 can all be turned on; while the second transistor T2, the sixth transistor T6, and the seventh transistor T7 can all be turned off.

[0176] On this basis, the driving power signal provided by the driving power line VDD can still be transmitted to the second node N2 via the turned-on third transistor T3; the initial power signal provided by the initial power line Var can still be transmitted to the third node N3 via the turned-on eighth transistor T8; and because the compensation power line VB shares the initial power line Var, the initial power signal can also be transmitted as the compensation power signal to the fourth node N4 via the turned-on first transistor T1. That is, in the third phase t03, the potential VN4 of the fourth node N4 can satisfy: VN4 = Var0. Furthermore, relative to the second phase t02, under the coupling effect of the first capacitor C1, the potential VN2 of the second node N2 can jump to: VN2 = (Vdata - Vth) + (Var0 - Vdata) * C10 / (C10 + C20). Where C10 refers to the capacitance of the first capacitor C1, and C20 refers to the capacitance of the second capacitor C2. This completes the writing of the initial power signal, and the ninth transistor T9 can now be turned off. The third stage t03 may also be referred to as a Var0 writing stage.

[0177] (4) In the fourth stage t04, the potential of the compensation signal provided by the second compensation line GB2 and the potential of the first light-emitting control signal provided by the first light-emitting control line EMA can both be low; while the potential of the gate drive signal provided by the gate line G1, the potential of the compensation signal provided by the first compensation line GB1, and the potential of the reset signal provided by the reset line GW can all be high. Accordingly, the second transistor T2 and the seventh transistor T7 can both be turned on; while the first transistor T1, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 can all be turned off.

[0178] On this basis, the signal transmitted to the fourth node N4 can be transmitted to the first node N1 via the turned-on second transistor T2, and the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via the turned-on seventh transistor T7. That is, in the fourth phase t04, the potential VN2 of the second node N2 can satisfy: VN2 = VDD0. Furthermore, with respect to the second stage t02, under the coupling action of the first capacitor C1 and the second capacitor C2, the potential change △VN2 of the second node N2 can satisfy: △VN2 = VDD0-(Vdata-Vth)+(Var0-Vdata)*C10 / (C10+C20), and according to the potential change △VN2 of the second node N2 being equal to the potential change △VN4 of the fourth node N4 (i.e., △VN4 = △VN2), it can be obtained that: VN4-Var0 = VDD0-(Vdata-Vth)+(Var0-Vdata)*C10 / (C10+C20), and further it can be concluded that the potential VN4 of the fourth node N4 satisfies: VN4 = (Var0-Vdata)+(VDD0+Vth)-(Var0-Vdata)*C10 / (C10+C20). Because the second transistor T2 is turned on, the potential VN1 of the first node N1 can satisfy: VN1 = (Var0 - Vdata) + (VDD0 + Vth) - (Var0 - Vdata) * C10 / (C10 + C20). At this time, for the ninth transistor T9, its Vgs - Vth = (Var0 - Vdata) * C10 / (C10 + C20) < 0, and the ninth transistor T9 remains on, transmitting the driving signal (i.e., the driving current I) to the light-emitting element L1 to drive the light-emitting element L1 to emit light. And I can satisfy: I = (1 / 2) μ * Cox * (W / L) * [(Var0 - Vdata) * C10 / (C10 + C20)] 2 The fourth stage t04 may also be referred to as a light-emitting stage.

[0179] As can be seen, the driving current ultimately transmitted to the light-emitting element L1 is independent of the driving power signal provided by the driving power line VDD or the threshold voltage Vth of the ninth transistor T9. This reliably compensates for the voltage drop on the driving power line VDD and the characteristic drift of the ninth transistor T9, improving the long-range current uniformity and ensuring a better display quality for the display panel.

[0180] Optionally, in combination with Figure 13, it can be seen that in the fourth stage t04, the potential of the compensation signal provided by the second compensation line GB2 can be set to a low potential in advance relative to the potential of the light-emitting control signal provided by the first light-emitting control line EMA, so that the second transistor T2 is turned on earlier than the seventh transistor T7.

[0181] As can be seen from FIG13 , for the structure shown in FIG8 , the third stage corresponding to FIG11 can be executed simultaneously with the first stage / second stage, except that there is an additional stage of writing Var0 .

[0182] As another optional implementation:

[0183] Taking the structure shown in FIG9 as an example, FIG14 shows another working timing diagram of a pixel circuit provided by an embodiment of the present disclosure. In conjunction with FIG14, the working principle of the pixel circuit is described as follows:

[0184] (1) In the first phase t01, the potential of the compensation signal provided by the first compensation line GB1, the potential of the first light-emitting control signal provided by the first light-emitting control line EMA, and the potential of the reset signal provided by the reset line GW can all be low potentials (i.e., effective potentials); while the potential of the gate drive signal provided by the gate line G1 can be high potentials (i.e., ineffective potentials). Accordingly, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 can all be turned on; and the sixth transistor T6 can be turned off.

[0185] On this basis, the initial power signal provided by the initial power line Var can be transmitted to the third node N3 via the turned-on eighth transistor T8. Because the compensation power line VB shares the initial power line Var, the initial power signal can also be transmitted as a compensation power signal to the first node N1 via the turned-on first transistor T1. Furthermore, the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via the turned-on seventh transistor T7 and the turned-on third transistor T3. That is, in the first phase t01, the potential VN1 of the first node N1 and the potential VN3 of the third node N3 can both satisfy: VN1 = VN3 = Var0; and the potential VN2 of the second node N2 can satisfy: VN2 = VDD0. The first phase t01 can also be referred to as the initialization phase.

[0186] (2) In the second phase t02, the potential of the compensation signal provided by the first compensation line GB1 and the potential of the reset signal provided by the reset line GW can both be low. The potential of the gate drive signal provided by the gate line G1 and the potential of the first light-emitting control signal provided by the first light-emitting control line EMA are high. Accordingly, the first transistor T1, the third transistor T3, and the eighth transistor T8 can all be turned on; while the sixth transistor T6 and the seventh transistor T7 can be turned off.

[0187] On this basis, the initial power signal provided by the initial power line Var can still be transmitted to the first node N1 through the turned-on first transistor T1 and still be transmitted to the third node N3 through the turned-on eighth transistor T8; and the drive power signal provided by the drive power line VDD can still be transmitted to the second node N2 through the turned-on third transistor T3. At this time, for the ninth transistor T9, the gate-source voltage difference Vgs is less than its threshold voltage Vth, that is, Vgs<Vth, so the ninth transistor T9 is turned on. The potential of the second node N2 can be discharged to: VN2 = Var0 - Vth, causing the ninth transistor T9 to turn off, and the current can flow to the eighth transistor T8. In this way, the writing of the data signal and the threshold voltage Vth of the ninth transistor T9 is achieved. In addition, similar to the first stage t01, by turning on the eighth transistor T8, it is also possible to prevent the leakage current of the ninth transistor T9 from causing the light-emitting element L1 to emit light in advance. The second stage t02 can also be called the compensation stage.

[0188] (3) In the third stage t03, the potential of the gate driving signal provided by the gate line G1 and the potential of the reset signal provided by the reset line GW can both be at a low potential; while the potential of the compensation signal provided by the first compensation line GB1 and the potential of the first light emission control signal provided by the first light emission control line EMA can both be at a high potential. Accordingly, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 can all be turned on; while the first transistor T1 and the seventh transistor T7 can both be turned off.

[0189] On this basis, the initial power signal provided by the initial power line Var can still be transmitted to the third node N3 through the turned-on eighth transistor T8 and still be transmitted to the fourth node N4 through the turned-on first transistor T1; and the data signal provided by the data line D1 can be transmitted to the first node N1 through the turned-on sixth transistor T6. That is, in the third stage t03, the potential VN1 of the first node N1 can satisfy: VN1 = Vdata. Furthermore, relative to the second stage t02, under the coupling effect of the first capacitor C1 and the second capacitor C2, according to the fact that the potential change amount △VN1 of the first node N1 is equal to the potential change amount △VN2 of the second node N2 (that is, △VN1 = △VN2), it can be obtained that: (Vdata - Var0)*C10 = [VN2 - (Var0 - Vth)]*(C10 + C20), and then it can be concluded that the potential VN2 of the second node N2 satisfies: VN2 = (Var0 - Vth) + (Vdata - Var0)*C10 / (C10 + C20). Thus, the writing of the data signal is completed, and at this time the ninth transistor T9 can be turned off. The third stage t03 can also be called the Vdata writing stage.

[0190] Optionally, as can be seen from FIG. 14 , in the third phase t03 , the potential of the compensation signal provided by the first compensation line GB1 can be initially set to a high potential, and then the potential of the gate drive signal provided by the gate line G1 can be set to a low potential, so that the sixth transistor T6 is turned on after the first transistor T1 is turned off. This prevents crosstalk between signals and ensures better driving stability.

[0191] (4) In the fourth stage t04, the potential of the first light-emitting control signal provided by the first light-emitting control line EMA can be low; while the potential of the gate drive signal provided by the gate line G1, the potential of the reset signal provided by the reset line GW, and the potential of the compensation signal provided by the first compensation line GB1 can all be high. Accordingly, only the seventh transistor T7 can be turned on; while the first transistor T1, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 can all be turned off.

[0192] On this basis, the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via the turned-on seventh transistor T7. That is, in the fourth stage t04, the potential VN2 of the second node N2 can satisfy: VN2 = VDD0. Furthermore, relative to the third stage t03, under the coupling effect of the first capacitor C1 and the second capacitor C2, according to ΔVN1 = ΔVN2, it can be obtained that: VN1 - Vdata = VDD0 - [(Var0 - Vth) + (Vdata - Var0) * C10 / (C10 + C20)]. Furthermore, it can be concluded that the potential VN1 of the first node N1 satisfies: VN1 = (Vdata - Var0) + (VDD0 + Vth) - [(Vdata - Var0) * C10 / (C10 + C20)]. At this time, for the ninth transistor T9, its Vgs - Vth = (Vdata - Var0) * C10 / (C10 + C20). By controlling the values ​​of Vdata and Var0, Vgs-Vth < 0 can be achieved, thereby keeping the ninth transistor T9 turned on and transmitting a driving signal (i.e., a driving current I) to the light-emitting element L1 to drive the light-emitting element L1 to emit light. Furthermore, the driving current I can satisfy the following equation: I = (1 / 2)μ*Cox*(W / L)*[(Vdata-Var0)*C10 / (C10+C20)] 2 The fourth stage t04 may also be referred to as a light-emitting stage.

[0193] As can be seen, the driving current ultimately transmitted to the light-emitting element L1 is independent of the driving power signal provided by the driving power line VDD or the threshold voltage Vth of the ninth transistor T9. This reliably compensates for the voltage drop on the driving power line VDD and the characteristic drift of the ninth transistor T9, improving the long-range current uniformity and ensuring a good display quality for the display panel.

[0194] Optionally, as can be seen in conjunction with FIG. 14 , in the fourth phase t04, the potential of the reset signal provided by the reset line GW can be first set to a high potential, and then the potential of the light-emission control signal provided by the first light-emission control line EMA can be set to a low potential, so that the seventh transistor T7 is turned on after the third transistor T3 is turned off. In this way, crosstalk between signals can be avoided, ensuring better driving stability.

[0195] As another optional implementation:

[0196] Taking the structure shown in FIG10 as an example, FIG15 shows a working timing diagram of another pixel circuit provided by an embodiment of the present disclosure. In conjunction with FIG15, the working principle of the pixel circuit is described as follows:

[0197] (1) In the first phase t01, the potential of the gate drive signal provided by the gate line G1, the potential of the second light-emitting control signal provided by the second light-emitting control line EMB, and the potential of the reset signal provided by the reset line GW can all be high potentials (i.e., effective potentials); while the potential of the compensation signal provided by the compensation line GB1 and the potential of the first light-emitting control signal provided by the first light-emitting control line EMA can all be low potentials (i.e., ineffective potentials). Accordingly, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 can all be turned on; and the fourth transistor T4 and the seventh transistor T7 can all be turned off.

[0198] On this basis, the data signal provided by data line D1 can be transmitted to first node N1 via the enabled sixth transistor T6; the initial power signal provided by initial power line Var can be transmitted to third node N3 via the enabled eighth transistor T8, then to fifth node N5 via the enabled fifth transistor T5, and finally to second node N2 via the ninth transistor T9; and the third capacitor C3 and fourth capacitor C4 are charged. That is, in the first phase t01, the potential VN1 of first node N1 can satisfy: VN1 = Vdata; the potentials VN2 of second node N2, VN3 of third node N3, and VN5 of fifth node N5 can all satisfy: VN2 = VN3 = VN5 = Var0. The first phase t01 can also be referred to as the initialization phase.

[0199] (2) In the second phase t02, the potential of the gate drive signal provided by the gate line G1, the potential of the first light-emitting control signal provided by the first light-emitting control line EMA, and the potential of the reset signal provided by the reset line GW can all be high potentials; while the potential of the compensation signal provided by the compensation line GB1 and the potential of the second light-emitting control signal provided by the second light-emitting control line EMB can all be low potentials. Accordingly, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be turned on; and the fourth transistor T4 and the fifth transistor T5 can all be turned off.

[0200] On this basis, the data signal provided by the data line D1 can still be transmitted to the first node N1 via the turned-on sixth transistor T6; the initial power signal provided by the initial power line Var can still be transmitted to the third node N3 via the turned-on eighth transistor T8; and the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via the turned-on seventh transistor T7. The discharge current from the second node N2 can charge the fourth capacitor C4. At this time, for the ninth transistor T9, its Vgs-Vth can satisfy: Vgs-Vth = Vdata-Var0-Vth > 0. The potential of the second node N2 discharges to VN5 = Vdata-Vth, causing the ninth transistor T9 to turn off. In this way, the data signal and the threshold voltage Vth of the ninth transistor T9 are written. In addition, as in the first stage t01, turning on the eighth transistor T8 can also prevent the leakage current of the ninth transistor T9 from causing the light-emitting element L1 to emit light prematurely. The second stage t02 can also be called the compensation stage.

[0201] Alternatively, as can be seen from FIG. 15 , in the second phase t02, the potential of the second light-emitting control signal provided by the second light-emitting control line EMB can be initially set to a low potential, and then the potential of the light-emitting control signal provided by the first light-emitting control line EMA can be set to a high potential, so that the seventh transistor T7 is turned on after the fifth transistor T5 is turned off. In this way, the discharge current of the second node N2 can be prevented from flowing to the eighth transistor T8.

[0202] (3) In the third phase t03, the potential of the compensation signal provided by the compensation line GB1 and the potential of the reset signal provided by the reset line GW can both be high; while the potential of the gate drive signal provided by the gate line G1, the potential of the first light-emitting control signal provided by the first light-emitting control line EMA, and the potential of the second light-emitting control signal provided by the second light-emitting control line EMB can all be low. Accordingly, the fourth transistor T4 and the eighth transistor T8 can both be turned on; while the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be turned off.

[0203] On this basis, the initial power signal provided by the initial power line Var can still be transmitted to the third node N3 via the turned-on eighth transistor T8. Since the compensation power line VB shares the initial power line Var, the initial power signal can also be transmitted to the first node N1 via the turned-on fourth transistor T4 as the compensation power signal. That is, in the third phase t03, the potential VN1 of the first node N1 can satisfy: VN1 = Var0. Furthermore, relative to the second phase t02, under the coupling effect of the first capacitor C1 and the second capacitor C2, the potential change ΔVN1 of the first node N1 is equal to the potential change ΔVN5 of the fifth node N5 (i.e., ΔVN1 = ΔVN5), and thus: (Vdata - Var0) * (C30 + C40) = [VN5 - (Vdata - Vth)] * C40. It can be concluded that the potential VN5 of the fifth node N5 can satisfy: VN5 = (Vdata - Vth) + (Var0 - Vdata) * (C30 + C40) / C40. C30 can refer to the capacitance of the third capacitor C3; C40 can refer to the capacitance of the fourth capacitor C40. At this time, for the ninth transistor T9, its Vgs-Vth can satisfy: Vgs-Vth = (Vata - Var0) * C30 / C40 > 0, and the ninth transistor T9 is turned on. The third stage t03 can also be called the Vdata write stage.

[0204] Optionally, referring to FIG15 , it can be seen that in the third stage t03, the potential of the gate drive signal provided by the gate line G1 can be first set to a low potential, and then the potential of the compensation signal provided by the compensation line GB1 can be set to a high potential, so that the fourth transistor T4 is turned on again after the sixth transistor T6 is turned off. In this way, crosstalk between signals can be avoided, ensuring better driving stability. In addition, in the third stage t03, because different columns of pixels receive different data signals, the drive signals transmitted to the third node N3 are also different. Therefore, by controlling the eighth transistor T8 to turn on, the third nodes N3 of different light-emitting elements can be reset, ensuring the voltage consistency of different light-emitting elements before emitting light, playing the role of anode initialization, that is, ensuring that the voltage of different light-emitting elements before lighting remains consistent, thereby ensuring better display uniformity.

[0205] (4) In the fourth stage t04, the potential of the first light-emitting control signal provided by the first light-emitting control line EMA and the potential of the second light-emitting control signal provided by the second light-emitting control line EMB can both be high; while the potential of the compensation signal provided by the compensation line GB1, the potential of the reset signal provided by the reset line GW, and the potential of the gate drive signal provided by the gate line G1 can all be low. Accordingly, the fifth transistor T5 and the seventh transistor T7 can both be turned on; while the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 can all be turned off.

[0206] On this basis, the driving power signal provided by the driving power line VDD can be transmitted to the second node N2 via the turned-on seventh transistor T7; and the signal transmitted to the fifth node N5 can be further transmitted to the third node N3. At this time, for the ninth transistor T9, its Vgs-Vth = (Vdata-Var0)*C30 / C40. The ninth transistor T9 is turned on and transmits the driving signal (i.e., driving current I) to the light-emitting element L1 to drive the light-emitting element L1 to emit light. In addition, the driving current I can satisfy: I = (1 / 2)μ*Cox*(W / L)*[(Vdata-Var0)*C30 / C40] 2 The fourth stage t04 may also be referred to as a light-emitting stage.

[0207] As can be seen, the driving current ultimately transmitted to the light-emitting element L1 is independent of the driving power signal provided by the driving power line VDD or the threshold voltage Vth of the ninth transistor T9. This reliably compensates for the voltage drop on the driving power line VDD and the characteristic drift of the ninth transistor T9, improving the long-range current uniformity and ensuring a better display quality for the display panel.

[0208] Since the driving method can have substantially the same technical effects as the pixel circuit described in the previous embodiment, the technical effects of the driving method will not be repeatedly described here for the purpose of brevity.

[0209] FIG16 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG16 , the display panel includes: a substrate 10 and a plurality of pixels P1 located on the substrate 10 .

[0210] The pixel P1 includes a light emitting element L1 and a pixel circuit 00 as shown in any one of Figures 1 to 10. The pixel circuit 00 is coupled to the light emitting element L1 and is used to drive the light emitting element L1 to emit light.

[0211] Since the display panel can have substantially the same technical effects as the pixel circuit described in the previous embodiment, the technical effects of the display panel will not be repeatedly described here for the purpose of brevity.

[0212] FIG17 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG17 , the display device includes: a power supply component J1 and a display panel 100 as shown in FIG16 .

[0213] The power supply component J1 is coupled to the display panel 100 and is used to supply power to the display panel 100 .

[0214] Optionally, the display device may be an OLED display device or an active-matrix organic light-emitting diode (AMOLED) display device, etc. OLED display technology has been widely recognized by the market due to its advantages such as high resolution and high contrast.

[0215] Optionally, the display device may also include: any product or component with a display function, such as a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0216] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0217] It should be noted that the terms used in the examples of this disclosure are only used to explain the examples and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this disclosure should have the common meanings understood by people with ordinary skills in the field to which this disclosure belongs.

[0218] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0219] When we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may be present. In addition, "connected" or "coupled" as used herein may include wireless connection or wireless coupling.

[0220] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0221] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0222] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0223] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A pixel circuit used in a display panel; The pixel circuit comprises: A data writing circuit is coupled to the gate line, the data line and the first node respectively, and is used to control the connection and disconnection of the data line and the first node in response to a gate driving signal provided by the gate line; A first light-emitting control circuit is coupled to a first light-emitting control line, a driving power line and a second node respectively, and is used to control the connection and disconnection of the driving power line and the second node in response to a first light-emitting control signal provided by the first light-emitting control line; A reset circuit is coupled to a reset line, an initial power line and a third node respectively, and is used to control the connection and disconnection of the initial power line and the third node in response to a reset signal provided by the reset line, wherein the third node is used to couple to a light emitting element; a driving circuit, coupled to the first node, the second node and the third node respectively, and configured to transmit a driving signal to the third node based on the potential of the first node and the potential of the second node, so as to drive the light emitting element to emit light; a compensation circuit, coupled to at least one compensation line, a compensation power line, the driving power line and the first node respectively, and used to control the connection and disconnection of the compensation power line and the first node in response to a compensation signal provided by the at least one compensation line, and used to adjust the potential of the first node; The compensation power line is introduced through both sides of the display panel to transmit the compensation power signal to the pixel circuit in both directions.

2. The pixel circuit according to claim 1, wherein: The compensation circuit comprises: a switch subcircuit, coupled to the at least one compensation line, the compensation power line and the first node respectively, and used to control the connection and disconnection of the initial power line and the first node in response to a compensation signal provided by the at least one compensation line; a first regulating subcircuit, coupled to the driving power line and the first node respectively, and used for regulating the potential of the first node; Furthermore, the first regulating subcircuit is indirectly coupled to the driving power line through the first light emitting control circuit; or, the first regulating subcircuit is directly coupled to the driving power line.

3. The pixel circuit according to claim 2, wherein: The switch subcircuit is coupled to two compensation lines, namely, a first compensation line and a second compensation line; the switch subcircuit comprises: a first switch unit, coupled to the first compensation line, the compensation power line and the fourth node respectively, and used to control the on-off of the compensation power line and the fourth node in response to a compensation signal provided by the first compensation line; a second switch unit, coupled to the second compensation line, the fourth node and the first node respectively, and used to control the connection and disconnection of the fourth node and the first node in response to a compensation signal provided by the second compensation line; The first regulating subcircuit is coupled to the second node to be indirectly coupled to the driving power line through the first light emitting control circuit, and the first regulating subcircuit is also coupled to the fourth node to be coupled to the first node through the second switch unit.

4. The pixel circuit according to claim 3, wherein: The first switch unit includes: a first transistor; the second switch unit includes: a second transistor; the first regulating subcircuit includes: a first capacitor; The gate of the first transistor is coupled to the first compensation line, the first electrode of the first transistor is coupled to the compensation power line, and the second electrode of the first transistor is coupled to the fourth node; A gate of the second transistor is coupled to the second compensation line, a first electrode of the second transistor is coupled to the fourth node, and a second electrode of the second transistor is coupled to the first node; A first terminal of the first capacitor is coupled to the fourth node, and a second terminal of the first capacitor is coupled to the second node.

5. The pixel circuit according to claim 3, wherein: The gate line is shared with the reset line.

6. The pixel circuit according to any one of claims 2 to 5, wherein: The regulating subcircuit is indirectly coupled to the driving power line through the first light emitting control circuit; the compensation circuit further includes: The second regulating subcircuit is coupled to the reset line, the driving power line and the second node respectively, and is used to control the connection and disconnection of the driving power line and the second node in response to a reset signal provided by the reset line to adjust the potential of the second node.

7. The pixel circuit according to claim 6, wherein: The second regulating subcircuit includes: a third transistor and a second capacitor; The gate of the third transistor is coupled to the reset line, the first electrode of the third transistor is coupled to the first end of the second capacitor, the second electrode of the third transistor is coupled to the second node, and the second end of the second capacitor is coupled to the driving power line.

8. The pixel circuit according to any one of claims 3 to 7, wherein: The transistors in the pixel circuit include: P-type transistors.

9. The pixel circuit according to claim 2, wherein: The switch subcircuit is coupled to a compensation line, and the adjustment subcircuit is directly coupled to the drive power line; The compensation circuit further includes: a third regulating subcircuit, coupled to the first node and the fifth node respectively, and used to regulate the potential of the first node and the potential of the fifth node; The pixel circuit also includes: a second light-emitting control circuit, which is coupled to the second light-emitting control line, the fifth node and the third node respectively, and is used to control the connection and disconnection of the fifth node and the third node in response to a second light-emitting control signal provided by the second light-emitting control line; and the driving circuit is coupled to the fifth node to be indirectly coupled to the third node through the second light-emitting control circuit.

10. The pixel circuit according to claim 9, wherein: The switch subcircuit includes: a fourth transistor; the first regulating subcircuit includes: a third capacitor; the third regulating subcircuit includes: a fourth capacitor; the second light emitting control circuit includes: a fifth transistor; The gate of the fourth transistor is coupled to the compensation line, the first electrode of the fourth transistor is coupled to the compensation power line, and the second electrode of the fourth transistor is coupled to the first node; The gate of the fifth transistor is coupled to the second light emitting control line, the first electrode of the fifth transistor is coupled to the fifth node, and the second electrode of the fifth transistor is coupled to the third node; A first end of the third capacitor is coupled to the driving power line, and a second end of the third capacitor is coupled to the first node; A first terminal of the fourth capacitor is coupled to the first node, and a second terminal of the fourth capacitor is coupled to the fifth node.

11. The pixel circuit according to claim 9, wherein: The transistors in the pixel circuit include: N-type transistors.

12. The pixel circuit according to any one of claims 1 to 11, wherein: The initial power line is introduced through both sides of the display panel; Furthermore, the compensation power line is shared with the initial power line.

13. The pixel circuit according to any one of claims 1 to 12, wherein: The data writing circuit includes: a sixth transistor; the first light emitting control circuit includes: a seventh transistor; the reset circuit includes: an eighth transistor; the driving circuit includes: a ninth transistor; A gate electrode of the sixth transistor is coupled to the gate line, a first electrode of the sixth transistor is coupled to the data line, and a second electrode of the sixth transistor is coupled to the first node; The gate of the seventh transistor is coupled to the first light emitting control line, the first electrode of the seventh transistor is coupled to the driving power line, and the second electrode of the seventh transistor is coupled to the second node; The gate of the eighth transistor is coupled to the reset line, the first electrode of the eighth transistor is coupled to the initial power line, and the second electrode of the eighth transistor is coupled to the third node; A gate of the ninth transistor is coupled to the first node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the third node.

14. A method for driving a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 13; the method comprising: In the first stage, the reset circuit controls the initial power line to be connected to the third node, so that the initial power line transmits an initial power signal to the third node; In the second stage, the compensation circuit controls the compensation power line to be connected to the first node in response to the compensation signal provided by at least one compensation line, and adjusts the potential of the first node so that the compensation power line transmits the compensation power signal to the first node; In the third stage, the data writing circuit controls the data line to be connected to the first node in response to the gate driving signal provided by the gate line, so that the data line transmits the data signal to the first node; In the fourth stage, the first light-emitting control circuit controls the driving power line to be connected to the second node in response to the first light-emitting control signal provided by the first light-emitting control line, so that the driving power line transmits the driving power signal to the second node; The driving circuit is based on the potential of the first node and the potential of the second node. bit, transmitting a driving signal to the third node to drive the light-emitting element coupled to the third node to emit light; The compensation power line is introduced through both sides of the display panel to transmit the compensation power signal to the pixel circuit in both directions.

15. A display panel, comprising: a substrate, and a plurality of pixels located on the substrate; Wherein, the pixel comprises: a light-emitting element, and a pixel circuit as described in any one of claims 1 to 13; the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

16. A display device, comprising: A power supply component, and a display panel as claimed in claim 15; Wherein, the power supply component is coupled to the display panel and is used to supply power to the display panel.

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