Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device. The array substrate comprises: a base (1); a plurality of gate lines (2) extending in a first direction (X); a plurality of data lines (3) extending in a second direction (Y); and a plurality of sub-pixel electrodes (4), wherein at least one of the plurality of sub-pixel electrodes (4) comprises a first sub-pixel electrode group (PA) and a second sub-pixel electrode group (PB); the first sub-pixel electrode group (PA) and the second sub-pixel electrode group (PB) each comprise two sub-pixel electrode portions (P0) arranged in a third direction (Z) and electrically connected; and in the same sub-pixel electrode (4), the brightness of the first sub-pixel electrode group (Pa) is greater than the brightness of the second sub-pixel electrode group (Pb), the two sub-pixel electrode portions (P0) of the first sub-pixel electrode group (Pa) are located on the same side of the two sub-pixel electrode portions (P0) of the second sub-pixel electrode group (PB), and the third direction (Z) intersects the first direction (X) and the second direction (Y).

Description

Array substrate, display panel, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on November 17, 2023, with application number 202311535807.0 and invention name "Array substrate, display panel and display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0004] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0005] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0006] Summary of the Invention

[0007] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0008] substrate;

[0009] A plurality of gate lines are located on one side of the substrate, and the plurality of gate lines extend along a first direction;

[0010] a plurality of data lines, located on the same side of the substrate as the plurality of gate lines, the plurality of data lines extending along a second direction;

[0011] A plurality of sub-pixel electrodes, at least one of the plurality of sub-pixel electrodes includes: a first sub-pixel electrode group, and a second sub-pixel electrode group; the first sub-pixel electrode group and the second sub-pixel electrode group each include: two sub-pixel electrode portions arranged along the third direction and electrically connected; in the same sub-pixel electrode, the brightness of the first sub-pixel electrode group is greater than the brightness of the second sub-pixel electrode group, and the two sub-pixel electrode portions of the first sub-pixel electrode group are located on the same side of the two second sub-pixel electrode portions of the second sub-pixel electrode group, and the third direction intersects with the first direction and the second direction.

[0012] In a possible implementation manner, the two sub-pixel electrode portions of the first sub-pixel electrode group are respectively: a first sub-pixel electrode portion and a second sub-pixel electrode portion; the two sub-pixel electrode portions of the second sub-pixel electrode group are respectively: a third sub-pixel electrode portion and a fourth sub-pixel electrode portion;

[0013] The second sub-pixel electrode portion is adjacent to the third sub-pixel electrode and is arranged along the first direction.

[0014] In a possible implementation manner, the first sub-pixel electrode portion is adjacent to the third sub-pixel electrode portion and is arranged along the second direction.

[0015] In a possible implementation manner, the fourth sub-pixel electrode portion is adjacent to the second sub-pixel electrode portion and is arranged along the second direction.

[0016] In a possible embodiment, in the sub-pixel electrode, the first sub-pixel electrode portion, the second sub-pixel electrode portion, and the third sub-pixel electrode portion are located on one side of the gate line to which the sub-pixel electrode is electrically connected, and the fourth sub-pixel electrode portion is located on the other side of the gate line to which the sub-pixel electrode is electrically connected.

[0017] In a possible implementation, the array substrate further includes: a first pixel connecting portion and a second pixel connecting portion;

[0018] In the same sub-pixel electrode, the first sub-pixel electrode portion and the second sub-pixel electrode portion are electrically connected via the first pixel connecting portion, and the third sub-pixel electrode portion and the fourth sub-pixel electrode portion are electrically connected via the second pixel connecting portion.

[0019] In a possible implementation manner, the first pixel connection portion extends along the third direction and electrically connects two opposite corners of the first sub-pixel electrode portion and the second sub-pixel electrode portion.

[0020] In one possible embodiment, the second pixel connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion, and a third sub-connection portion extending along the third direction and connecting the first sub-connection portion and the second sub-connection portion; wherein the extension line of the second sub-connection portion is located on a side of the extension line of the first sub-connection portion close to the second sub-pixel electrode portion.

[0021] In a possible implementation, the array substrate further includes: a pixel driving circuit electrically connected to the sub-pixel electrodes in a one-to-one correspondence, and a first trace extending along the second direction; the pixel driving circuit includes: a first transistor, a second transistor, and a third transistor;

[0022] The gate of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second sub-pixel electrode portion;

[0023] The gate of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is reused as the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode portion;

[0024] The gate of the third transistor is electrically connected to the gate line, the first electrode of the third transistor multiplexes the second electrode of the second transistor, and the second electrode of the third transistor multiplexes a portion of the first wiring.

[0025] In a possible implementation, the array substrate further includes: a first pixel bonding portion electrically connected to the second sub-pixel electrode portion, and a second pixel bonding portion electrically connected to the fourth sub-pixel electrode portion;

[0026] The orthographic projection of the first pixel overlap portion on the substrate overlaps with the orthographic projection of the second electrode of the first transistor on the substrate, and the second sub-pixel electrode portion is electrically connected to the second electrode of the first transistor through the first pixel overlap portion;

[0027] The orthographic projection of the second pixel overlap portion on the substrate has an overlapping area with the orthographic projection of the second electrode of the second transistor on the substrate, and the fourth sub-pixel electrode portion is electrically connected to the second electrode of the second transistor through the second pixel overlap portion.

[0028] In a possible implementation manner, the second pixel connecting portion includes: a first sub-connecting portion, and a second sub-connecting portion connecting the first sub-connecting portion and the fourth sub-pixel electrode;

[0029] There is a gap between the first sub-bridge portion and the fourth sub-pixel electrode.

[0030] In a possible implementation, the first pixel overlapping portion has two first sides extending along the second direction; the second pixel overlapping portion has two second sides extending along the second direction;

[0031] The orthographic projection of one of the first sides on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; and the orthographic projection of one of the second sides on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

[0032] In one possible implementation, the second electrode of the first transistor includes: a first main portion extending along the first direction, and a first branch portion extending from one end of the first main portion along the second direction; an orthographic projection of the first main portion on the substrate and an orthographic projection of the first pixel overlap portion on the substrate having an overlapping area; and an orthographic projection of the first branch portion on the substrate and an orthographic projection of the gate line on the substrate having an overlapping area.

[0033] The second electrode of the second transistor includes: a second main portion extending along the first direction, and a second branch portion extending from one end of the first main portion along the first direction; the orthographic projection of the second main portion on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping portion on the substrate; the orthographic projection of the second branch portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

[0034] In a possible implementation manner, the first routing line includes: a plurality of first routing line main portions extending along the second direction, and a first routing line bending portion connecting two adjacent first routing line main portions;

[0035] The orthographic projection of the main portion of the first routing line on the substrate has an overlapping area with the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the orthographic projection of the substrate; the orthographic projection of the first routing bend portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate, and bends toward one side of the third transistor.

[0036] In a possible implementation, the array substrate further includes: a plurality of first common routing groups extending along the second direction; the common routing groups include: a first sub-common routing located on one side of the gate line, and a second sub-common routing located on the other side of the gate line;

[0037] The first sub-common routing line includes: a first sub-common routing line main portion, and a first sub-common routing line convex portion extending from the first sub-common routing line main portion toward one side of the gate line; the second sub-common routing line includes: a second sub-common routing line main portion, and a second sub-common routing line convex portion extending from the second sub-common routing line main portion toward one side of the gate line;

[0038] The orthographic projection of the first sub-common routing protrusion on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping portion on the substrate; the orthographic projection of the second sub-common routing protrusion on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping portion on the substrate.

[0039] The present disclosure also provides a display panel, which includes the array substrate provided in the present disclosure and an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

[0040] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic diagram of the sub-pixel distribution of 1P4D;

[0042] FIG2 is a schematic diagram showing the principle of dark lines appearing in conventional SUVA pixel design;

[0043] FIG3A is a schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0044] FIG3B is a schematic diagram of a single film layer of the gate line layer in FIG3A ;

[0045] FIG3C is a schematic diagram of a single film layer of the data line layer in FIG3A ;

[0046] FIG3D is a schematic diagram of a single film layer of the active layer in FIG3A;

[0047] FIG3E is a schematic diagram of a single film layer of the first insulating layer in FIG3A ;

[0048] FIG3F is a schematic diagram of a single film of the first electrode layer in FIG3A ;

[0049] FIG3G is a schematic diagram of a single film layer of the second insulating layer in FIG3A ;

[0050] FIG3H is a schematic diagram of a single film layer of the pixel electrode layer in FIG3A ;

[0051] FIG3I is an enlarged schematic diagram of the dotted box S in FIG3A ;

[0052] FIG4 is a schematic diagram of the connection of sub-pixel electrodes provided by an embodiment of the present disclosure;

[0053] FIG5 is an equivalent schematic diagram of a sub-pixel electrode circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0056] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0057] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0058] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0059] Compared to the UV2A pixel design, ultra-fine photo alignment (SUVA) is an upgraded version of UV2A. Figures 1 and 2 show this. Figure 1 shows a 1P4D (four domains per subpixel) SUVA pixel design. While the SUVA pixel design effectively reduces pixel dark lines compared to the UV2A pixel design, as shown in Figure 2, dark lines still exist in the area between liquid crystal regions 1 and 2 (LC regions 1-2), affecting the panel's color shift. Therefore, a multi-domain approach is necessary to further improve color shift.

[0060] In view of this, referring to Figures 3A-3I and Figure 4, Figure 3A is a schematic top view of an array substrate provided in an embodiment of the present disclosure, Figure 3B is a schematic diagram of a single film layer of the gate line layer in Figure 3A, Figure 3C is a schematic diagram of a single film layer of the data line layer in Figure 3A, Figure 3D is a schematic diagram of a single film layer of the active layer in Figure 3A, Figure 3E is a schematic diagram of a single film layer of the first insulating layer in Figure 3A, Figure 3F is a schematic diagram of a single film layer of the first electrode layer in Figure 3A, Figure 3G is a schematic diagram of a single film layer of the second insulating layer in Figure 3A, Figure 3H is a schematic diagram of a single film layer of the pixel electrode layer in Figure 3A, Figure 3I is an enlarged schematic diagram of the dotted box S in Figure 3A, and Figure 4 is a schematic diagram of the connection of a sub-pixel electrode provided in an embodiment of the present disclosure. An embodiment of the present invention provides an array substrate, which includes:

[0061] Substrate 1;

[0062] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0063] A plurality of data lines 3 are located on the same side of the substrate 1 as the plurality of gate lines 2 , and the plurality of data lines 3 extend in a second direction Y;

[0064] A plurality of sub-pixel electrodes 4, at least one sub-pixel electrode 4 among the plurality of sub-pixel electrodes 4 includes: a first sub-pixel electrode group PA, and a second sub-pixel electrode group PB; the first sub-pixel electrode group PA and the second sub-pixel electrode group PB both include: two sub-pixel electrode portions P0 arranged along a third direction Z and electrically connected; in the same sub-pixel electrode 4, the brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB, and the two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are located on the same side of the two second sub-pixel electrode portions P0 of the second sub-pixel electrode group PB extending in the third direction Z, and the third direction Z intersects with the first direction X and the second direction Y. As shown in Figure 3A, H represents the brighter sub-pixel electrode portion P0 in a sub-pixel electrode 4, and L represents the darker sub-pixel electrode portion P0. It should be noted that brighter here means that more backlight is transmitted, and darker means that less backlight is transmitted, that is, when different sub-pixel electrode portions P0 are applied with different voltages, the voltage difference formed with the common electrode of the opposite substrate is different. The larger the pressure difference, the stronger the ability to drive the liquid crystal to rotate, the more backlight is transmitted, and the brighter the sub-pixel electrode portion P0. Conversely, the smaller the pressure difference, the weaker the ability to drive the liquid crystal to rotate, the less backlight is transmitted, and the darker the sub-pixel electrode portion P0.

[0065] In the embodiment of the present disclosure, the sub-pixel electrode 4 includes: a first sub-pixel electrode group PA, and a second sub-pixel electrode group PB. The brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB, and the two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are located on the same side of the two second sub-pixel electrode portions P0 of the second sub-pixel electrode group PB extending in the third direction Z. When a sub-pixel electrode 4 is made to include two brighter sub-pixel electrode portions P0 and two darker sub-pixel electrode portions P0, the wiring can be simplified, the wiring complexity of the array substrate can be reduced, and the defective rate of the array substrate can be reduced, which is also conducive to achieving multi-domain and improving color deviation. Moreover, the centers of the two brighter sub-pixel electrode portions P0 and the two darker sub-pixel electrode portions P0 form a diamond shape, so that the array substrate is cross-distributed with light and dark in the first direction X and the second direction Y, which can also improve the problem of horizontal and vertical dark stripes.

[0066] In a possible implementation, the angle formed by the third direction Z and the first direction X may be 30° to 60°, and specifically, for example, may be 45°.

[0067] Specifically, the array substrate may also include a pixel driving circuit corresponding one-to-one to each sub-pixel electrode 4. The brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB. It can be understood that under the drive of the pixel driving circuit, the brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB.

[0068] In a possible embodiment, the array substrate may include a plurality of sub-pixel electrode portion rows extending along a first direction X and arranged along a second direction Y, and two sub-pixel electrode portion rows may be distributed between two adjacent gate lines 2, wherein the four sub-pixel electrode portions P0 of a sub-pixel electrode 4 may be distributed in three sub-pixel electrode portion rows.

[0069] In a possible embodiment, as shown in Figure 3A, the sub-pixel electrode portion P0 may be provided with a slit F, and each sub-pixel electrode portion P0 may further include a first sub-portion P01 arranged along the second direction Y, and a second sub-portion P02, and the extension directions of the slits F of the first sub-portion P01 and the second sub-portion P02 in the same sub-pixel electrode portion P0 are different.

[0070] In a possible embodiment, in combination with what is shown in FIG3A , in the same sub-pixel electrode portion row, the extension direction of the slit F of the two first sub-portions P01 adjacent in the first direction X is the same, and the extension direction of the slit F of the two second sub-portions P02 adjacent in the first direction X is the same; in the two sub-pixel electrode portion rows between two adjacent gate lines 2, the extension direction of the slit F of the first sub-portion P01 in one sub-pixel electrode portion row is the same as the extension direction of the slit F of the second sub-portion P02 in the other sub-pixel electrode portion row; and the extension direction of the slit F of the second sub-portion P02 in one sub-pixel electrode portion row is the same as the extension direction of the slit F of the first sub-portion P01 in the other sub-pixel electrode portion row.

[0071] In a possible embodiment, with reference to FIG3A , in one row of sub-pixel electrode portions, the angle formed by the extension direction of the slit F in the first sub-portion P01 and the first direction X may be in the range of 130° to 160°, specifically, for example, 145°, and the angle formed by the extension direction of the slit F in the second sub-portion P02 and the first direction X may be in the range of 30° to 60°, specifically, for example, 45°; in another row of sub-pixel electrode portions, the angle formed by the extension direction of the slit F in the first sub-portion P01 and the first direction X may be in the range of 30° to 60°, specifically, for example, 45°, and the angle formed by the extension direction of the slit F in the second sub-portion P02 and the first direction X may be in the range of 130° to 160°, specifically, for example, 145°.

[0072] In a possible embodiment, in combination with Figures 3A and 3H, the two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are respectively: a first sub-pixel electrode portion P1, and a second sub-pixel electrode portion P2; the two sub-pixel electrode portions P0 of the second sub-pixel electrode group PB are respectively: a third sub-pixel electrode portion P3, and a fourth sub-pixel electrode portion P4; the second sub-pixel electrode portion P2 is adjacent to the third sub-pixel electrode P3, and are arranged along the first direction X.

[0073] In a possible implementation, as shown in FIG. 3A and FIG. 3H , the first sub-pixel electrode portion P1 is adjacent to the third sub-pixel electrode portion P3 and is arranged along the second direction Y.

[0074] In a possible implementation, as shown in combination with FIG. 3A and FIG. 3H , the fourth sub-pixel electrode portion P4 is adjacent to the second sub-pixel electrode portion P2 and is arranged along the second direction Y.

[0075] In a possible embodiment, in combination with Figures 3A and 3H, in the sub-pixel electrode 4, the first sub-pixel electrode portion P1, the second sub-pixel electrode portion P2, and the third sub-pixel electrode portion P3 are located on one side of the gate line 2 to which the sub-pixel electrode 4 is electrically connected, and the fourth sub-pixel electrode portion P4 is located on the other side of the gate line 2 to which the sub-pixel electrode 4 is electrically connected.

[0076] It can be understood that the sub-pixel electrode 4 is electrically connected to the source or drain of the transistor, and the gate of the transistor is electrically connected to the gate line 2 .

[0077] In a possible embodiment, in combination with what is shown in FIG3H , the array substrate further includes: a first pixel connection portion 41, and a second pixel connection portion 42; in the same sub-pixel electrode 4, the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 are electrically connected via the first pixel connection portion 41, and the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 are electrically connected via the second pixel connection portion 42.

[0078] In the embodiment of the present disclosure, the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 are electrically connected through the first pixel connecting portion 41, and the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 are electrically connected through the second pixel connecting portion 42. The first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 can be connected nearby, and the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 can be connected nearby, thereby simplifying the wiring of the array substrate.

[0079] In one possible embodiment, as shown in FIG3H , the first pixel connection portion 41 extends along the third direction Z and electrically connects two opposing corners of the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2. This allows the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 to be connected close together, simplifying the wiring of the array substrate.

[0080] In one possible embodiment, as shown in FIG3H , the second pixel connection portion 42 includes a first sub-connection portion 421 extending along the second direction Y, a second sub-connection portion 422, and a third sub-connection portion 423 extending along the third direction Z and connecting the first sub-connection portion 421 and the second sub-connection portion 422. The extension of the second sub-connection portion 422 is located on a side of the extension of the first sub-connection portion 421 that is closer to the second sub-pixel electrode portion P2. This allows the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 to be connected in close proximity, simplifying the wiring of the array substrate.

[0081] In one possible implementation, with reference to FIG. 3A to FIG. 3I and FIG. 5 , where FIG. 5 is an equivalent circuit diagram corresponding to a sub-pixel, the array substrate further includes: a pixel driving circuit electrically connected to the sub-pixel electrodes in a one-to-one correspondence, and a first trace 5 extending along the second direction Y; the pixel driving circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3; specifically, the pixel driving circuit may further include a first capacitor C1 and a second capacitor C2;

[0082] The gate of the first transistor T1 is electrically connected to the gate line 2, the first electrode TA of the first transistor T1 is electrically connected to the data line 3, and the second electrode TB of the first transistor T1 is electrically connected to the second sub-pixel electrode portion P2; specifically, the second electrode TB of the first transistor T1 can be electrically connected to the second sub-pixel electrode portion P2 through the first via K1 and the third via K3;

[0083] The gate of the second transistor T2 is electrically connected to the gate line 2, the first electrode TA of the second transistor T2 reuses the first electrode TA of the first transistor T1, and the second electrode TB of the second transistor T2 is electrically connected to the fourth sub-pixel electrode portion P4; specifically, the second electrode TB of the second transistor T2 can be electrically connected to the fourth sub-pixel electrode portion P4 through the second via K2 and the fourth via K4;

[0084] The gate of the third transistor T3 is electrically connected to the gate line 2 . The first electrode TA of the third transistor T3 multiplexes the second electrode TB of the second transistor T2 . The second electrode TB of the third transistor T3 multiplexes part of the first wiring 5 .

[0085] Specifically, the array substrate also includes a first liquid crystal capacitor Cpx1 and a second liquid crystal capacitor Cpx2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode group PA and the common electrode layer of the opposite substrate, and the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode group PB and the common electrode layer of the opposite substrate. The first capacitor C1 can be formed by the first sub-pixel electrode group PA and the first sub-common wiring 61, and the second capacitor C2 can be formed by the second sub-pixel electrode group PB and the second sub-common wiring 62.

[0086] In an embodiment of the present invention, the first sub-pixel electrode group PA can be electrically connected to the gate line 1 and the data line 3 through the first transistor T1, the second sub-pixel electrode group PB can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the second electrode of the third transistor T3 is electrically connected to the first wiring 5. The storage capacitance in the second capacitor C2 corresponding to the second sub-pixel electrode group PB can be released to the first wiring 5 through the third transistor T3, thereby making the brightness of the first sub-pixel electrode group PA greater than the brightness of the second sub-pixel electrode group PB, so that different light and dark pixels are provided in the same sub-pixel electrode 4, and realizing an 8-domain display effect.

[0087] In a possible implementation, as shown in FIG3H , the array substrate further includes: a first pixel bonding portion 43 electrically connected to the second sub-pixel electrode portion P2 , and a second pixel bonding portion 44 electrically connected to the fourth sub-pixel electrode portion P4 ;

[0088] The orthographic projection of the first pixel overlap portion 43 on the substrate 1 overlaps with the orthographic projection of the second electrode TB of the first transistor T1 on the substrate 1 . The second sub-pixel electrode portion P2 is electrically connected to the second electrode TB of the first transistor T1 through the first pixel overlap portion 43 .

[0089] The orthographic projection of the second pixel overlap portion 44 on the substrate 1 overlaps with the orthographic projection of the second electrode TB of the second transistor T2 on the substrate 1 . The fourth sub-pixel electrode portion T4 is electrically connected to the second electrode TB of the second transistor T2 through the second pixel overlap portion 44 .

[0090] In one possible embodiment, as shown in FIG3H , the second pixel overlap portion 44 includes: a first sub-overlap portion 441, and a second sub-overlap portion 442 connecting the first sub-overlap portion 441 and the fourth sub-pixel electrode P4; wherein there is a gap between the first sub-overlap portion 441 and the fourth sub-pixel electrode P4.

[0091] In one possible embodiment, as shown in Figure 3H, the first pixel overlapping portion 43 has two first edges w1 extending along the second direction Y; the second pixel overlapping portion 44 has two second edges w2 extending along the second direction Y; the orthographic projection of one of the first edges w1 on the substrate 1 overlaps with the orthographic projection of the second pixel overlapping portion 44 on the substrate 1; and the orthographic projection of one of the second edges w2 on the substrate 1 overlaps with the orthographic projection of the first pixel overlapping portion 43 on the substrate 1.

[0092] In a possible embodiment, the orthographic projections of the two first sides w1 on the substrate 1 may coincide with the orthographic projections of the two second sides w2 on the substrate 1 , that is, the first pixel overlap portion 43 and the fourth sub-pixel electrode portion P4 are aligned in the second direction Y.

[0093] In one possible embodiment, as shown in FIG3C , the second electrode TB of the first transistor T1 includes: a first main portion TB11 extending along a first direction X, and a first branch portion TB12 extending from one end of the first main portion TB11 along a second direction Y; an orthographic projection of the first main portion TB11 on the substrate 1 overlaps with an orthographic projection of the first pixel overlapping portion 43 on the substrate 1; and an orthographic projection of the first branch portion TB12 on the substrate 1 overlaps with an orthographic projection of the gate line 2 on the substrate 1.

[0094] The second electrode TB of the second transistor T2 includes: a second main portion TB21 extending along the first direction X, and a second branch portion TB22 extending from one end of the second main portion TB21 along the first direction X; the orthographic projection of the second main portion TB22 on the substrate 1 overlaps with the orthographic projection of the second pixel overlapping portion 44 on the substrate 1; and the orthographic projection of the second branch portion TB22 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1.

[0095] In a possible embodiment, as shown in FIG3A , FIG3H , and FIG3I , the first trace 5 includes: a plurality of first trace main portions 51 extending along the second direction Y, and a first trace bending portion 52 connecting two adjacent first trace main portions 51 ;

[0096] The orthographic projection of the first main routing portion 51 on substrate 1 overlaps with the gap between the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 on substrate 1. The orthographic projection of the first routing bend 52 on substrate 1 overlaps with the orthographic projection of the gate line 2 on substrate 1 and bends toward one side of the third transistor T3. In the disclosed embodiment, the first routing 5 also includes a first routing bend 52, which faces one side of the third transistor T3. In this way, the first routing bend 52 can be reused as the second electrode TB of the third transistor T3 to avoid a large distance between the first electrode TA and the second electrode TB of the third transistor T3 in the first direction X, which would affect the performance of the third transistor T3.

[0097] In a possible embodiment, as shown in FIG3B , the array substrate further includes: a plurality of first common routing groups 6 extending along the second direction Y; the common routing group 6 includes: a first sub-common routing 61 located on one side of the gate line 2, and a second sub-common routing 62 located on the other side of the gate line 6;

[0098] The first sub-common routing line 61 includes: a first sub-common routing line main portion 611, and a first sub-common routing line protrusion 612 extending from the first sub-common routing line main portion 611 toward the gate line 2 side; the second sub-common routing line 62 includes: a second sub-common routing line main portion 621, and a second sub-common routing line protrusion 622 extending from the second sub-common routing line main portion 621 toward the gate line 2 side;

[0099] The orthographic projection of the first sub-common routing protrusion 612 on the substrate 1 has an overlapping area with the orthographic projection of the first pixel overlapping portion 43 on the substrate 1, thereby forming a first capacitor C1; the orthographic projection of the second sub-common routing protrusion 622 on the substrate 1 has an overlapping area with the orthographic projection of the second pixel overlapping portion 44 on the substrate 1, thereby forming a second capacitor C2.

[0100] In a possible embodiment, as shown in Figures 3A to 3H , the array substrate may be provided with, in sequence, a gate line layer as shown in Figure 3B , a data line layer as shown in Figure 3C , an active layer as shown in Figure 3D , a first insulating layer 91 as shown in Figure 3E , a first electrode layer as shown in Figure 3F , a second insulating layer 92 as shown in Figure 3G , and a pixel electrode layer as shown in Figure 3H , on one side of the substrate 1;

[0101] The active layer may include an active pattern 7 corresponding to the transistor;

[0102] The first insulating layer 91 may have a first via hole K1 and a second via hole K2; the first insulating layer 91 may be a first passivation layer or an organic layer;

[0103] The first electrode layer may include a first hollow L1, a second hollow L2, a third hollow L3 and a fourth hollow L4, wherein the first hollow L1 may correspond to the same two sub-pixel electrode portions P0 in the first direction X; the orthographic projection of the second hollow L2 on the substrate 1 and the orthographic projection of the first via K1 on the substrate 1, so that the second sub-pixel electrode portion P2 is conductively connected to the second electrode TB of the first transistor T1 through the second hollow portion L2; the orthographic projection of the third hollow L3 on the substrate 1 and the orthographic projection of the second via K2 on the substrate 1, so that the four sub-pixel electrode portions P4 are conductively connected to the second electrode TB of the second transistor T2 through the third hollow L3; the orthographic projection of the fourth hollow L4 on the substrate 1 may have an overlapping area with the orthographic projection of the gate line 2 on the substrate 1 to reduce the overlapping capacitance with the gate line 2; specifically, the first electrode layer may be a transparent electrode layer, and the material of the first electrode layer may be the same as that of the pixel electrode layer;

[0104] The second insulating layer 92 may have a third via hole K3 and a fourth via hole K4; the second insulating layer 92 may be a second passivation layer;

[0105] In the embodiment of the present disclosure, the array substrate is further provided with a first electrode layer having a first hollow L1. The orthographic projection of the first electrode layer on the substrate 1 can cover at least a portion of the orthographic projection of the data line 3 on the substrate 1, and can cover at least a portion of the orthographic projection of the gate line 2 on the substrate 1, thereby shielding the coupling capacitance between the sub-pixel electrode 4 and the data line 3, and the coupling capacitance between the sub-pixel electrode 4 and the gate line 2, thereby improving the transmittance of the display panel.

[0106] Based on the same inventive concept, the array substrate provided in the embodiment of the present disclosure further includes an opposite substrate arranged opposite to the array substrate, and the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

[0107] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, which includes a display panel as provided in an embodiment of the present disclosure. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be repeated.

[0108] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0109] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0110] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate lines are located on one side of the substrate, and the plurality of gate lines extend along a first direction; a plurality of data lines, located on the same side of the substrate as the plurality of gate lines, the plurality of data lines extending along a second direction; A plurality of sub-pixel electrodes, at least one of the plurality of sub-pixel electrodes comprises: a first sub-pixel electrode group, and a second sub-pixel electrode group; the first sub-pixel electrode group and the second sub-pixel electrode group both comprise: two sub-pixel electrode portions arranged along the third direction and electrically connected; in the same sub-pixel electrode, the brightness of the first sub-pixel electrode group is greater than the brightness of the second sub-pixel electrode group, and the two sub-pixel electrode portions of the first sub-pixel electrode group are located on the same side of the two second sub-pixel electrode portions of the second sub-pixel electrode group, and the third direction intersects with the first direction and the second direction.

2. The array substrate according to claim 1, wherein: The two sub-pixel electrode portions of the first sub-pixel electrode group are respectively: a first sub-pixel electrode portion and a second sub-pixel electrode portion; the two sub-pixel electrode portions of the second sub-pixel electrode group are respectively: a third sub-pixel electrode portion and a fourth sub-pixel electrode portion; The second sub-pixel electrode portion is adjacent to the third sub-pixel electrode and is arranged along the first direction.

3. The array substrate according to claim 2, wherein: The first sub-pixel electrode portion is adjacent to the third sub-pixel electrode portion and is arranged along the second direction.

4. The array substrate according to claim 3, wherein: The fourth sub-pixel electrode portion is adjacent to the second sub-pixel electrode portion and is arranged along the second direction.

5. The array substrate according to claim 4, wherein: In the sub-pixel electrode, the first sub-pixel electrode portion, the second sub-pixel electrode portion, and the third sub-pixel electrode portion are located on one side of the gate line electrically connected to the sub-pixel electrode, and the fourth sub-pixel electrode portion is located on the other side of the gate line electrically connected to the sub-pixel electrode.

6. The array substrate according to claim 4 or 5, wherein: The array substrate further includes: a first pixel connecting portion and a second pixel connecting portion; In the same sub-pixel electrode, the first sub-pixel electrode portion and the second sub-pixel electrode portion are electrically connected via the first pixel connecting portion, and the third sub-pixel electrode portion and the fourth sub-pixel electrode portion are electrically connected via the second pixel connecting portion.

7. The array substrate according to claim 6, wherein: The first pixel connection portion extends along the third direction and electrically connects two opposite corners of the first sub-pixel electrode portion and the second sub-pixel electrode portion.

8. The array substrate according to claim 6 or 7, wherein: The second pixel connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion, and a third sub-connection portion extending along the third direction and connecting the first sub-connection portion and the second sub-connection portion; wherein an extension line of the second sub-connection portion is located on a side of the extension line of the first sub-connection portion close to the second sub-pixel electrode portion.

9. The array substrate according to any one of claims 5 to 8, wherein: The array substrate further comprises: a pixel driving circuit electrically connected to the sub-pixel electrodes in a one-to-one correspondence, and a first wiring extending along the second direction; the pixel driving circuit comprises: a first transistor, a second transistor, and a third transistor; The gate of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second sub-pixel electrode portion; The gate of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is reused as the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode portion; The gate of the third transistor is electrically connected to the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor, and the second electrode of the third transistor reuses part of the first wiring.

10. The array substrate according to claim 9, wherein: The array substrate further includes: a first pixel bonding portion electrically connected to the second sub-pixel electrode portion, and a second pixel bonding portion electrically connected to the fourth sub-pixel electrode portion; The orthographic projection of the first pixel overlap portion on the substrate has an overlapping area with the orthographic projection of the second electrode of the first transistor on the substrate, and the second sub-pixel electrode portion is electrically connected to the second electrode of the first transistor through the first pixel overlap portion; The orthographic projection of the second pixel overlap portion on the substrate has an overlapping area with the orthographic projection of the second electrode of the second transistor on the substrate, and the fourth sub-pixel electrode portion is electrically connected to the second electrode of the second transistor through the second pixel overlap portion.

11. The array substrate according to claim 10, wherein: The second pixel overlap portion includes: a first sub-overlap portion, and a second sub-overlap portion connecting the first sub-overlap portion and the fourth sub-pixel electrode; There is a gap between the first sub-bridge portion and the fourth sub-pixel electrode.

12. The array substrate according to claim 10 or 11, wherein: The first pixel overlapping portion has two first sides extending along the second direction; the second pixel overlapping portion has two second sides extending along the second direction; One of the orthographic projections of the first side on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; one of the orthographic projections of the second side on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

13. The array substrate according to any one of claims 10 to 12, wherein: The second electrode of the first transistor comprises: a first main portion extending along the first direction, and a first branch portion extending from one end of the first main portion along the second direction; an orthographic projection of the first main portion on the substrate and an orthographic projection of the first pixel overlap portion on the substrate have an overlapping area; an orthographic projection of the first branch portion on the substrate and an orthographic projection of the gate line on the substrate have an overlapping area; The second electrode of the second transistor comprises: a second main portion extending along the first direction, and a second branch portion extending from one end of the first main portion along the first direction; an orthographic projection of the second main portion on the substrate and an orthographic projection of the second pixel overlap portion on the substrate have an overlapping area; The orthographic projection of the second branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

14. The array substrate according to any one of claims 9 to 13, wherein: The first routing line comprises: a plurality of first routing line main portions extending along the second direction, and a first routing line bending portion connecting two adjacent first routing line main portions; The orthographic projection of the main portion of the first routing line on the substrate has an overlapping area with the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion on the orthographic projection of the substrate; the orthographic projection of the first routing bend portion on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate, and bends toward one side of the third transistor.

15. The array substrate according to any one of claims 10 to 14, wherein: The array substrate further comprises: a plurality of first common routing groups extending along the second direction; the common routing groups comprise: a first sub-common routing located on one side of the gate line, and a second sub-common routing located on the other side of the gate line; The first sub-common routing line includes: a first sub-common routing line main part, and a first sub-common routing line convex part extending from the first sub-common routing line main part toward one side of the gate line; the second sub-common routing line includes: a second sub-common routing line main part, and a second sub-common routing line convex part extending from the second sub-common routing line main part toward one side of the gate line; The orthographic projection of the first sub-common routing protrusion on the substrate has an overlapping area with the orthographic projection of the first pixel overlapping portion on the substrate; the orthographic projection of the second sub-common routing protrusion on the substrate has an overlapping area with the orthographic projection of the second pixel overlapping portion on the substrate.

16. A display panel, wherein: It comprises the array substrate as claimed in any one of claims 1 to 15, and further comprises an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

17. A display device, wherein: Comprising the display panel as claimed in claim 16.

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