Display chip and manufacturing method

Abstract

The present application invention belongs to the technical field of semiconductors. Disclosed are a display chip and a manufacturing method. The display chip comprises: a chip structure, which comprises a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer that are arranged in sequence, wherein one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other one is a p-type semiconductor layer, and the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers.

Description

Display chip and manufacturing method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese application with application number 202311506815.2 and application date November 13, 2023, and claims its priority. The disclosed content of the Chinese application is hereby introduced as a whole into this application. Technical Field

[0003] The present application relates to the field of semiconductor technology, and in particular to a display chip and a manufacturing method thereof. Background Art

[0004] At present, the film material in display devices such as micro light-emitting diodes (Micro-LEDs) is gallium-polar material. The growth temperature of the gallium-polar film layer is low, resulting in a high threading dislocation density. The quantum confined Stark effect caused by the strong polarization electric field in the quantum well leads to low luminous efficiency of the display device.

[0005] Summary of the Invention

[0006] In a first aspect, the present application provides a display chip, comprising:

[0007] The chip structure comprises a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer arranged in sequence; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer;

[0008] Wherein, the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers.

[0009] According to one embodiment of the present application, the chip structure further includes a fourth undoped semiconductor layer, a first barrier layer, a first superlattice layer, and a second superlattice layer sequentially arranged between the first semiconductor layer and the quantum well light-emitting layer;

[0010] The fourth undoped semiconductor layer, the first barrier layer, the first superlattice layer and the second superlattice layer are all nitrogen-polar film layers.

[0011] According to one embodiment of the present application, the fourth undoped semiconductor layer includes a u-GaN layer, the first barrier layer includes a GaN layer, and the first superlattice layer includes a u-In layer. a Ga 1-a N / u-GaN superlattice layer, 0.01≤a≤0.05; the second superlattice layer includes u-In b Ga 1-b N / n-GaN superlattice layer, 0.05≤b≤0.1.

[0012] According to one embodiment of the present application, the first semiconductor layer includes a heavily doped semiconductor layer and a lightly doped semiconductor layer located between the heavily doped semiconductor layer and the quantum well light emitting layer;

[0013] The heavily doped semiconductor layer and the lightly doped semiconductor layer are both nitrogen polar film layers.

[0014] According to one embodiment of the present application, the heavily doped semiconductor layer includes an n-GaN heavily doped layer or an n-Al c Ga 1- c N / n-GaN superlattice layer, 0.02≤c≤0.15; the lightly doped semiconductor layer includes an n-GaN lightly doped layer or an n-Al g Ga 1-g N / n-GaN superlattice layer, 0.02≤g≤0.08.

[0015] According to one embodiment of the present application, the quantum well light-emitting layer includes a fifth undoped semiconductor layer, a first potential well layer, a first cap layer, a second barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer and a third barrier layer, which are sequentially arranged between the first semiconductor layer and the second semiconductor layer;

[0016] The fifth undoped semiconductor layer, the first potential well layer, the first capping layer, the second barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second capping layer and the third barrier layer are all nitrogen polar film layers.

[0017] According to one embodiment of the present application, the fifth undoped semiconductor layer and the sixth undoped semiconductor layer both include u-GaN layers, the first cap layer and the second cap layer both include GaN layers; the first potential well layer includes u-In x Ga 1-x N layer, 0.1≤x≤0.15; the second barrier layer includes a GaN layer or u-In y Ga 1-y N layer, 0.01≤y≤0.03; the second potential well layer includes u-In z Ga 1-z N layer, 0.35≤z≤0.4; the third barrier layer includes u-Al d Ga 1-d N layers, 0.3≤d≤0.35.

[0018] According to one embodiment of the present application, the second semiconductor layer includes an electron blocking layer, a hole injection layer, and an ohmic contact layer sequentially arranged on a side of the quantum well light-emitting layer away from the first semiconductor layer;

[0019] The electron blocking layer, the hole injection layer and the ohmic contact layer are all nitrogen polar film layers.

[0020] According to one embodiment of the present application, the electron blocking layer includes a p-AlGaN polarization induction layer or a p-Al e Ga 1- e N / p-GaN superlattice layer, 0.15≤e≤0.25; the hole injection layer includes a p-GaN layer; the ohmic contact layer includes a p-In f Ga 1-f N / p-GaN superlattice layer, 0.1≤f≤0.2.

[0021] According to one embodiment of the present application, the chip structure further includes a first transparent conductive layer, a first reflective layer, and a bonding layer sequentially located on a side of the second semiconductor layer away from the quantum well light-emitting layer.

[0022] According to one embodiment of the present application, the chip structure further includes a protective layer located between the quantum well light-emitting layer and the second semiconductor layer.

[0023] According to one embodiment of the present application, the quantum well light-emitting layer includes a red light quantum well light-emitting layer.

[0024] According to one embodiment of the present application, the display chip further includes a substrate; the substrate is bonded to a side of the chip structure facing away from the first semiconductor layer.

[0025] According to one embodiment of the present application, the display chip further includes a passivation layer and a second reflective layer;

[0026] The passivation layer is located on a side of the chip structure facing away from the substrate and covers a sidewall of the chip structure, and the second reflective layer covers the passivation layer.

[0027] According to one embodiment of the present application, the display chip further includes a second transparent conductive layer located on a side of the second reflective layer facing away from the substrate, and the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer.

[0028] According to an embodiment of the present application, the display chip further includes a third reflective layer located on a peripheral side of the chip structure, and a microlens located on a side of the second transparent conductive layer away from the chip structure.

[0029] In a second aspect, the present application provides a method for manufacturing a display chip, comprising:

[0030] forming a base;

[0031] A chip structure is formed on one side of the substrate; the chip structure includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer sequentially arranged on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen-polar film layers;

[0032] The substrate is removed.

[0033] According to one embodiment of the present application, the base includes a substrate, a buffer layer, and an undoped semiconductor composite layer;

[0034] The forming of the substrate comprises:

[0035] providing a substrate;

[0036] forming a buffer layer on one side of the substrate;

[0037] forming a non-doped semiconductor composite layer on a side of the buffer layer facing away from the substrate; and the chip structure is located on a side of the non-doped semiconductor composite layer facing away from the buffer layer.

[0038] Wherein, the buffer layer and the non-doped semiconductor composite layer are both nitrogen-polar film layers.

[0039] According to one embodiment of the present application, the non-doped semiconductor composite layer includes a plurality of stacked non-doped semiconductor layers and at least one insertion layer, and there is one insertion layer between any two adjacent non-doped semiconductor layers;

[0040] The non-doped semiconductor layer and the insertion layer are both nitrogen-polar film layers.

[0041] According to one embodiment of the present application, the plurality of undoped semiconductor layers include a first undoped semiconductor layer, a second undoped semiconductor layer, and a third undoped semiconductor layer, and the at least one insertion layer includes a first insertion layer and a second insertion layer; the first undoped semiconductor layer, the first insertion layer, the second undoped semiconductor layer, the second insertion layer, and the third undoped semiconductor layer are sequentially arranged between the buffer layer and the first semiconductor layer;

[0042] The first non-doped semiconductor layer, the second non-doped semiconductor layer and the third non-doped semiconductor layer all include u-GaN layers, and the first insertion layer includes porous SiN x layer, and the second insertion layer includes an AlN layer.

[0043] According to one embodiment of the present application, removing the substrate includes:

[0044] removing the substrate;

[0045] The buffer layer and the undoped semiconductor composite layer are removed.

[0046] According to one embodiment of the present application, before removing the substrate, the method further includes:

[0047] The side of the chip structure facing away from the base is bonded to a substrate.

[0048] According to one embodiment of the present application, after removing the substrate, the method further includes:

[0049] forming a passivation layer on a side of the chip structure facing away from the substrate, wherein the passivation layer covers a sidewall of the chip structure;

[0050] A second reflective layer is formed on the surface of the passivation layer.

[0051] According to one embodiment of the present application, the method further includes:

[0052] forming a second transparent conductive layer on a side of the second reflective layer facing away from the substrate, wherein the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer;

[0053] A microlens is formed on a side of the second transparent conductive layer facing away from the substrate.

[0054] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0056] FIG1 is a schematic flow chart of a method for manufacturing a display chip according to an embodiment of the present application;

[0057] FIG2 is a schematic diagram of a structure of a display chip during the manufacturing process according to an embodiment of the present application;

[0058] FIG3 is a second structural diagram of the display chip during the manufacturing process provided by an embodiment of the present application;

[0059] FIG4 is a third structural diagram of the display chip during the manufacturing process provided by an embodiment of the present application;

[0060] FIG5 is a fourth structural diagram of the display chip during the manufacturing process provided by an embodiment of the present application;

[0061] FIG6 is a fifth structural diagram of the display chip during the manufacturing process provided by an embodiment of the present application;

[0062] FIG7 is a sixth structural diagram of the display chip during the manufacturing process provided by an embodiment of the present application;

[0063] FIG8 is a seventh structural diagram of the display chip during the manufacturing process provided by an embodiment of the present application;

[0064] FIG9 is an eighth structural diagram of the display chip during the manufacturing process according to an embodiment of the present application;

[0065] FIG10 is a ninth structural diagram of a display chip during the manufacturing process according to an embodiment of the present application;

[0066] FIG11 is a tenth structural diagram of the display chip during the manufacturing process provided by an embodiment of the present application;

[0067] FIG12 is an eleventh structural diagram of the display chip during the manufacturing process according to an embodiment of the present application;

[0068] FIG13 is a twelfth structural diagram of the display chip during the manufacturing process according to an embodiment of the present application;

[0069] FIG14 is a schematic diagram of the structure of a display chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0071] The display chip and manufacturing method provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0072] FIG1 is a flow chart of a method for manufacturing a display chip according to an embodiment of the present application, wherein the display chip may be a Micro-LED display chip.

[0073] As shown in FIG1 , the method for manufacturing a display chip provided in an embodiment of the present application includes step 110 , step 120 , and step 130 .

[0074] Step 110: forming a substrate.

[0075] In some embodiments, as shown in FIG2 , the base 10 may include a substrate 1, a buffer layer 2, and an undoped semiconductor composite layer 3. Forming the base in step 110 includes: providing a substrate 1; forming a buffer layer 2 on one side of the substrate 1; and forming an undoped semiconductor composite layer 3 on a side of the buffer layer 2 facing away from the substrate 1. The buffer layer 2 and the undoped semiconductor composite layer 3 are both nitrogen-polar film layers.

[0076] The substrate 1 may include a sapphire substrate with a certain bevel angle, etc. The buffer layer 2 may include an undoped GaN (u-GaN) layer, and the thickness of the buffer layer 2 may be 15 nm to 35 nm. The undoped semiconductor composite layer 3 may be a film layer with a low dislocation density.

[0077] For example, using an MOCVD (metal organic chemical vapor deposition) system, a hydrogen atmosphere is first provided to substrate 1 at a temperature of 1080°C to 1100°C for 300 to 400 seconds. Maintaining the hydrogen atmosphere, the reaction chamber temperature is lowered to 1020°C to 1060°C, and then ammonia gas is introduced to nitride the surface of substrate 1.

[0078] Next, a low-temperature buffer layer 2 is grown on one side of substrate 1. The atmosphere is switched from hydrogen to nitrogen, with ammonia still introduced, and the reaction chamber temperature is lowered to 550°C to 580°C. Maintaining the nitrogen atmosphere, the reaction chamber temperature is raised to 1060°C to 1080°C, and the buffer layer 2 is annealed for 500 to 600 seconds.

[0079] It should be noted that the buffer layer 2 may also be formed by other processes, which are not specifically limited here.

[0080] An undoped semiconductor composite layer 3 is formed on the side of the buffer layer 2 facing away from the substrate 1. In some embodiments, the undoped semiconductor composite layer 3 comprises a plurality of stacked undoped semiconductor layers and at least one insertion layer, with one insertion layer located between any two adjacent undoped semiconductor layers. Both the undoped semiconductor layers and the insertion layer are nitrogen-polar films. The insertion layer can reduce the threading dislocation density within the undoped semiconductor layer, thereby improving the internal quantum efficiency of the chip.

[0081] In some embodiments, as shown in FIG2 , the plurality of undoped semiconductor layers include a first undoped semiconductor layer 31, a second undoped semiconductor layer 33, and a third undoped semiconductor layer 35, and the at least one insertion layer includes a first insertion layer 32 and a second insertion layer 34. The first undoped semiconductor layer 31, the first insertion layer 32, the second undoped semiconductor layer 33, the second insertion layer 34, and the third undoped semiconductor layer 35 are sequentially disposed on a side of the buffer layer 2 facing away from the substrate 1.

[0082] The first undoped semiconductor layer 31 may include a u-GaN layer, and the thickness of the first undoped semiconductor layer 31 may be 300 nm to 500 nm. The first insertion layer 32 may include a porous SiNx layer. The main functions of the first insertion layer 32 are: first, it reduces the defect density and impurity ion concentration of the u-GaN layer; second, it reduces the background electron concentration of the nitrogen-polar u-GaN layer, thereby increasing mobility and improving luminescence performance.

[0083] The second undoped semiconductor layer 33 may include a u-GaN layer, and the thickness of the second undoped semiconductor layer 33 may be 1 μm to 1.2 μm. The second insertion layer 34 may include an AlN layer, and the thickness of the second insertion layer 34 may be 5 nm to 30 nm. The third undoped semiconductor layer 35 may include a u-GaN layer, and the thickness of the third undoped semiconductor layer 35 may be 1.5 μm to 2.5 μm. The overall thickness of the undoped semiconductor composite layer 3 may be 3 μm to 4 μm.

[0084] For example, after growing the buffer layer 2, the atmosphere is switched from nitrogen to hydrogen, the reaction chamber temperature is raised to 1080°C to 1100°C, and a first undoped semiconductor layer 31 is grown on the side of the buffer layer 2 facing away from the substrate 1. Only ammonia (NH3) and silane (SiH4) are introduced, and a first insertion layer 32 is grown on the side of the first undoped semiconductor layer 31 facing away from the buffer layer 2.

[0085] Then, under a hydrogen atmosphere and a reaction chamber temperature of 1080° C. to 1100° C., a second non-doped semiconductor layer 33 is grown on the side of the first insertion layer 32 facing away from the first non-doped semiconductor layer 31. Then, the reaction chamber temperature is lowered to 900° C. to 1000° C., and a low-temperature second insertion layer 34 is grown on the side of the second non-doped semiconductor layer 33 facing away from the first insertion layer 32. Then, under a hydrogen atmosphere and a reaction chamber temperature of 1080° C. to 1100° C., a third non-doped semiconductor layer 35 is grown on the side of the second insertion layer 34 facing away from the second non-doped semiconductor layer 33.

[0086] It should be noted that the undoped semiconductor composite layer 3 may also be formed by other processes, which are not specifically limited here.

[0087] Step 120: forming a chip structure on one side of the substrate; the chip structure includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer sequentially arranged on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen-polar film layers.

[0088] As shown in Figures 3 to 7 , the chip structure 20 includes a first semiconductor layer 4, a quantum well light-emitting layer 5, and a second semiconductor layer 6. Forming the chip structure on one side of the substrate in step 120 includes: forming the first semiconductor layer 4 on one side of the substrate 10; forming the quantum well light-emitting layer 5 on a side of the first semiconductor layer 4 facing away from the substrate 10; and forming the second semiconductor layer 6 on a side of the quantum well light-emitting layer 5 facing away from the first semiconductor layer 4.

[0089] The first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer. Alternatively, the first semiconductor layer 4 is a p-type semiconductor layer, and the second semiconductor layer 6 is an n-type semiconductor layer. In some embodiments, the chip structure 20 is a nitrogen-polarity InGaN-based chip structure, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer.

[0090] In some embodiments, as shown in FIG3 , the first semiconductor layer 4 includes a heavily doped semiconductor layer 41 and a lightly doped semiconductor layer 42. The heavily doped semiconductor layer 41 is located on one side of the substrate 10, for example, the heavily doped semiconductor layer 41 is located on the side of the undoped semiconductor composite layer 3 facing away from the substrate 1, and the lightly doped semiconductor layer 42 is located on the side of the heavily doped semiconductor layer 41 facing away from the substrate 10. Both the heavily doped semiconductor layer 41 and the lightly doped semiconductor layer 42 are nitrogen-polarity film layers.

[0091] The heavily doped semiconductor layer 41 may include an n-GaN heavily doped layer, and the electron concentration of the heavily doped semiconductor layer 41 is 1×10 18 cm -3 ~2×10 19 cm -3 The heavily doped semiconductor layer 41 has a thickness of 0.5 μm to 1.5 μm.

[0092] For example, the reaction chamber temperature is 1080°C to 1100°C, silane is introduced, and a delta doping method is used to separate the process of introducing silane from the growth process of the heavily doped semiconductor layer 41, so as to periodically grow a non-doped semiconductor layer. The n-type doping of the non-doped semiconductor layer is achieved by relying on the diffusion of Si atoms during the growth process to obtain the heavily doped semiconductor layer 41. The non-doped semiconductor layer may include a GaN layer, and the heavily doped semiconductor layer 41 may include an n-GaN layer. The periodic thickness of the non-doped semiconductor layer may be 10nm to 30nm, and the flow rate of silane may be 2nmol / min to 80nmol / min, which can achieve an electron concentration of 1×10 18 cm -3 ~2×10 19 cm -3 The heavily doped semiconductor layer 41 has a thickness of 0.5 μm to 1.5 μm.

[0093] It should be noted that silane is usually selected as the n-type dopant of the GaN layer, but uniform silane doping leads to a decrease in the mobility of Ga atoms and easily forms V-type defects. Therefore, this embodiment adopts a δ doping method to avoid V-type defects.

[0094] The heavily doped semiconductor layer 41 may also include n-Al c Ga 1-c N / n-GaN superlattice layer, 0.02≤c≤0.15, electron concentration is 1×10 18 cm -3 ~2×10 19 cm -3 Among them, n-Al c Ga 1-c The Al content in N is about 2% to 15%, and the thickness can be 2nm to 3nm. The thickness of n-GaN can be 2.5nm to 15nm. c Ga 1-c The N / n-GaN superlattice layer can alleviate the extension of dislocations and regulate stress.

[0095] The lightly doped semiconductor layer 42 may include an n-GaN lightly doped layer, and the electron concentration of the lightly doped semiconductor layer 42 is 1×10 17 cm -3 ~5×10 17 cm -3 The thickness of the lightly doped semiconductor layer 42 is 0.2 μm to 0.5 μm.

[0096] For example, the reaction chamber temperature is 1080°C to 1100°C, silane is introduced, and a delta doping method is used to periodically grow an undoped semiconductor layer, and n-type ions are doped into the undoped semiconductor layer to obtain a lightly doped semiconductor layer 42. The undoped semiconductor layer includes a GaN layer, and the lightly doped semiconductor layer 42 includes an n-GaN layer. The periodic thickness of the undoped semiconductor layer is 10nm to 30nm, and the flow rate of silane is 0.1nmol / min to 1.5nmol / min. The electron concentration of the lightly doped semiconductor layer 42 can be 1×10 17 cm -3 ~5×10 17 cm -3 The thickness of the lightly doped semiconductor layer 42 is 0.2 μm to 0.5 μm.

[0097] The lightly doped semiconductor layer 42 may also include n-Al g Ga 1-g N / n-GaN superlattice layer, 0.02≤g≤0.08, electron concentration is 1×10 17 cm -3 ~5×10 17cm -3 Among them, n-Al g Ga 1-g The Al component in N is about 2% to 8%, the thickness is 2nm to 3nm, and the thickness of n-GaN is 2.5nm to 15nm.

[0098] In some embodiments, as shown in FIG4 , forming the chip structure in step 120 further includes sequentially forming a fourth undoped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73, and a second superlattice layer 74 on a side of the first semiconductor layer 4 facing away from the substrate 10, with the quantum well light-emitting layer 5 being located on a side of the second superlattice layer 74 facing away from the first superlattice layer 73. The fourth undoped semiconductor layer 71, the first barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 are all nitrogen-polar film layers.

[0099] The fourth non-doped semiconductor layer 71 may include a u-GaN layer, and the thickness of the fourth non-doped semiconductor layer 71 may be 10 nm to 30 nm. The first barrier layer 72 may include a GaN layer, and the thickness of the first barrier layer 72 may be 10 nm to 30 nm. The first superlattice layer 73 may include at least one period (e.g., 1 to 3 periods) of u-In a Ga 1-a N / u-GaN superlattice layer, 0.01≤a≤0.05. Among them, u-In a Ga 1-a The thickness of N can be 2nm to 3nm, the In composition is 1% to 5%, and the thickness of u-GaN can be 2.5nm to 15nm. The second superlattice layer 74 can include at least one period (such as 1 to 3 periods) of u-In b Ga 1-b N / n-GaN superlattice layer, 0.05≤b≤0.1. Among them, the electron concentration of n-GaN can be 1×10 17 cm -3 ~5×10 17 cm -3 , u-In b Ga 1-b The thickness of N can be 2 nm to 3 nm, the In composition can be 5% to 10%, and the thickness of n-GaN can be 2.5 nm to 15 nm.

[0100] For example, after growing the lightly doped semiconductor layer 42, the reaction chamber temperature is lowered to 900°C to 1000°C, and a fourth undoped semiconductor layer 71 is grown on the side of the lightly doped semiconductor layer 42 facing away from the heavily doped semiconductor layer 41. The fourth undoped semiconductor layer 71 is used to repair damage caused by hydrogen etching during the cooling process.

[0101] Then, the nitrogen atmosphere is switched and the reaction chamber temperature is lowered to 800°C to 900°C. A first barrier layer 72 is grown on the side of the fourth undoped semiconductor layer 71 facing away from the lightly doped semiconductor layer 42. A first superlattice layer 73 is then grown on the side of the first barrier layer 72 facing away from the fourth undoped semiconductor layer 71. A second superlattice layer 74 is then grown on the side of the first superlattice layer 73 facing away from the first barrier layer 72.

[0102] Then, as shown in FIG. 5 , a quantum well light emitting layer 5 is formed on the side of the second superlattice layer 74 facing away from the first superlattice layer 73 .

[0103] In some embodiments, the quantum well light emitting layer 5 includes a red light quantum well light emitting layer. This embodiment uses a nitrogen polar film layer to alleviate the drop effect of the chip under large current injection and improve the red light effect.

[0104] In some embodiments, the quantum well light-emitting layer 5 includes at least one periodic structure (e.g., 2 to 3 periodic structures), each periodic structure including a fifth undoped semiconductor layer, a first potential well layer, a first capping layer, a second barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second capping layer, and a third barrier layer, sequentially disposed between the first semiconductor layer 4 and the second semiconductor layer 6. The fifth undoped semiconductor layer, the first potential well layer, the first capping layer, the second barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second capping layer, and the third barrier layer are all nitrogen-polar film layers.

[0105] The fifth non-doped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the fifth non-doped semiconductor layer may be 2nm to 3nm. The first potential well layer may include u-In x Ga 1-x N layer, 0.1≤x≤0.15, the thickness of the first potential well layer can be 2.5nm to 3.5nm. The first cap layer can include a GaN layer, and the thickness of the first cap layer can be 2nm to 3nm. The second barrier layer can include a GaN layer or u-In y Ga 1-y N layer, 0.01≤y≤0.03, the thickness of the second barrier layer can be 10nm to 15nm. The sixth non-doped semiconductor layer can include a low-temperature u-GaN layer, and the thickness of the sixth non-doped semiconductor layer can be 2nm to 3nm. The second potential well layer can include u-In z Ga 1-z N layer, 0.35≤z≤0.4, the thickness of the second potential well layer can be 2.5nm~3.5nm. The second cap layer can include a GaN layer, and the thickness of the second cap layer can be 2nm~3nm. The third barrier layer can include u-Al d Ga 1-dN layer, 0.3≤d≤0.35, the thickness of the third barrier layer can be 10nm~15nm.

[0106] In some embodiments, as shown in FIG6 , forming the chip structure in step 120 further includes forming a protective layer 75 on the side of the quantum well light-emitting layer 5 facing away from the first semiconductor layer 4 . The protective layer 75 is a nitrogen-polar film layer. The protective layer 75 may include a u-GaN layer, and the thickness of the protective layer 75 may be 20 nm to 50 nm.

[0107] For example, in a nitrogen atmosphere, the protection layer 75 is grown on the side of the quantum well light emitting layer 5 facing away from the first semiconductor layer 4 .

[0108] Then, as shown in FIG. 6 , a second semiconductor layer 6 is formed on the side of the protective layer 75 away from the quantum well light emitting layer 5 .

[0109] In some embodiments, the second semiconductor layer 6 includes an electron blocking layer 61, a hole injection layer 62, and an ohmic contact layer 63, which are sequentially formed on the side of the quantum well light-emitting layer 5 facing away from the first semiconductor layer 4. The electron blocking layer 61, the hole injection layer 62, and the ohmic contact layer 63 are all nitrogen-polar film layers.

[0110] The electron blocking layer 61 may include a p-AlGaN polarization induction layer. The thickness of the p-AlGaN polarization induction layer may be 50 nm to 60 nm. The Al component may be linearly increased from 0% to 20% or 30%. The theoretical hole concentration of the film layer is 2×10 18 cm -3 ~2.5×10 18 cm -3 The electron blocking layer 61 may also include p-Al e Ga 1-e N / p-GaN superlattice layer, 0.15≤e≤0.25, the hole concentration can be 1.5×10 18 cm -3 ~2.5×10 18 cm -3 , p-Al e Ga 1-e The Al content in N is about 15% to 25%, and the p-Al e Ga 1-e The thickness of N can be 2 nm to 3 nm, and the thickness of p-GaN can be 5 nm to 15 nm.

[0111] The hole injection layer 62 may include a p-GaN layer, and the thickness of the hole injection layer 62 may be 100 nm to 140 nm. The ohmic contact layer 63 may include at least one period (eg, 2 to 4 periods) of p-In f Ga 1-fN / p-GaN superlattice layer, 0.1≤f≤0.2. Among them, p-In f Ga 1-f The In content in N is about 10% to 20%, and the p-In f Ga 1-f The thickness of N can be 2 nm to 3 nm, and the thickness of p-GaN can be 5 nm to 15 nm.

[0112] For example, the hydrogen atmosphere is switched to grow the electron blocking layer 61 on the side of the protective layer 75 facing away from the quantum well light-emitting layer 5. Then, the hole injection layer 62 is deposited on the side of the electron blocking layer 61 facing away from the protective layer 75. The ohmic contact layer 63 is deposited on the side of the hole injection layer 62 facing away from the electron blocking layer 61.

[0113] It should be noted that the second semiconductor layer 6 may also be formed by using other processes, which are not specifically limited here.

[0114] In some embodiments, as shown in FIG7 , forming the chip structure in step 120 further includes sequentially forming a first transparent conductive layer 76, a first reflective layer 77, and a bonding layer 78 on a side of the second semiconductor layer 6 facing away from the quantum well light-emitting layer 5. The first reflective layer 77 is used to enhance the light extraction efficiency of the display chip.

[0115] The first transparent conductive layer 76 may include an ITO (indium tin oxide) layer. The first reflective layer 77 may include a metal reflective layer, such as at least one of Ag and Al. The bonding layer 78 may include a metal layer, such as at least one of Cr, Pt, Ni, Ti, Ni, and Ag.

[0116] For example, electron beam evaporation or PVD (Physical Vapor Deposition) is used to deposit the first transparent conductive layer 76 on the side of the ohmic contact layer 63 away from the hole injection layer 62, and an annealing process is combined to improve the transmittance of the first transparent conductive layer 76 and reduce the material resistance.

[0117] Then, a first reflective layer 77 is deposited on the side of the first transparent conductive layer 76 facing away from the ohmic contact layer 63 by electron beam evaporation or PVD. Then, a bonding layer 78 is deposited on the side of the first reflective layer 77 facing away from the first transparent conductive layer 76 by electron beam evaporation or PVD.

[0118] It should be noted that the first transparent conductive layer 76 and the first reflective layer 77 may also be formed by using other processes, which are not specifically limited here.

[0119] Along the c-axis growth direction, GaN materials have two polarities, namely gallium polarity and nitrogen polarity. Compared with gallium polarity, the incorporation efficiency of In in nitrogen-polarity InGaN materials is higher. The main reason is that the In atoms in the nitrogen-polarity InGaN material can form stronger In-N bonds with the surface N atoms. Moreover, there are 4 In-N bonds around each In atom on the surface of the nitrogen-polarity InGaN material, which makes the desorption efficiency of In in the nitrogen-polarity InGaN material lower, which is conducive to the incorporation of In. Therefore, under the same In component, the nitrogen-polarity InGaN material can have a higher growth temperature, which is conducive to improving the crystal quality of the potential well layer material in the quantum well and improving the internal quantum efficiency of the chip structure.

[0120] Furthermore, nitrogen-polar materials have a polarization direction opposite to gallium-polar materials, which can lower the barrier to carrier injection into the chip's quantum wells while also raising the barrier to carrier overflow. Therefore, nitrogen-polar InGaN-based chips have higher carrier injection efficiency while also suppressing carrier overflow, alleviating the chip's Droop effect at high currents (high current densities) to a certain extent and improving the display chip's luminous efficiency.

[0121] In some embodiments, the method for manufacturing the display chip further includes:

[0122] The substrate is bonded to the side of the chip structure facing away from the base.

[0123] As shown in Fig. 8, the chip structure 20 is bonded to the substrate 30 via a bonding layer 78. The substrate 30 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane.

[0124] Step 130: Remove the substrate.

[0125] The base 10 may include a substrate 1, a buffer layer 2, and a non-doped semiconductor composite layer 3. Removing the base in the display chip in step 130 includes: removing the substrate 1; removing the buffer layer 2 and the non-doped semiconductor composite layer 3.

[0126] For example, as shown in Figure 9, the laser lift-off technology is used to remove the substrate 1. The selected pulse laser wavelengths may be 355 nm, 266 nm, and 248 nm.

[0127] Then, as shown in Figure 10, the buffer layer 2 and the undoped semiconductor layer composite layer 3 are etched using an ICP-RIE (inductively coupled plasma-reactive ion etching) process until the heavily doped semiconductor layer 41 is exposed. The surface of the heavily doped semiconductor layer 41 is then mechanically polished. As shown in Figure 11, the chip structure 20 is etched using photolithography and ICP-RIE processes to meet different pixel size requirements.

[0128] In some embodiments, as shown in FIG11 , the method for manufacturing the display chip further includes: forming a passivation layer 81 on the side of the chip structure 20 facing away from the substrate 30, with the passivation layer 81 covering the sidewalls of the chip structure 20; and forming a second reflective layer 82 on the surface of the passivation layer 81. The passivation layer 81 is located on the side of the heavily doped semiconductor layer 41 facing away from the substrate 30 and on the sidewalls of the chip structure 20, and the second reflective layer 82 is located on the surface of the passivation layer 81. The second reflective layer 82 can further enhance the light extraction efficiency of the chip.

[0129] The passivation layer 81 may include SiO2, SiN x and Al2O3, the thickness of the passivation layer 81 can be 10nm-40nm, the second reflective layer 82 can include a DBR (Distributed Bragg Reflection) layer, and the DBR layer can include TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0130] For example, wet etching (such as 25% TMAH solution) is used to repair the sidewalls of the chip structure 20, and then an ALD device is used to deposit the passivation layer 81. Then, a second reflective layer 82 is deposited using PVD, electron beam evaporation or ALD equipment.

[0131] For another example, a PE-ALD device is used to plasma-treat the sidewalls of the chip structure 20. The gas may include O2, Ar, H2, NH3, N2, etc. to deposit the passivation layer 81. Then, a second reflective layer 82 is deposited using PVD, electron beam evaporation, or ALD.

[0132] For another example, a protective layer is deposited on the chip structure 20 using a PECVD process through photolithography. The thickness of the protective layer is 10 nm to 40 nm. A PE-ALD device is used to plasma-treat the sidewalls of the chip structure 20 using gases such as O2, Ar, H2, NH3, and N2 to deposit a passivation layer 81. Then, a second reflective layer 82 is deposited using PVD, electron beam evaporation, or ALD.

[0133] In some embodiments, as shown in FIG12 , the method for manufacturing the display chip further includes: forming a first isolation layer 83 on the peripheral side of the chip structure 20. The first isolation layer 83 may include SiO2 and SiN x At least one of .

[0134] For example, an ICP-RIE process is used to etch isolation grooves around the chip structure 20. Then, a first isolation layer 83 is formed in the grooves using a photolithography process and PECVD equipment. The photoresist is removed using an acetone solution, ultrasonically cleaned using ethanol and deionized water, and dried with nitrogen.

[0135] It should be noted that the first isolation layer 83 may also be formed by using other processes, which are not specifically limited here.

[0136] In some embodiments, as shown in FIG13 , the method for manufacturing the display chip further includes: forming a second transparent conductive layer 84 on a side of the second reflective layer 82 facing away from the substrate 30, with the second transparent conductive layer 84 penetrating the second reflective layer 82 and the passivation layer 81 to connect to the first semiconductor layer 4. As shown in FIG13 , the second transparent conductive layer 84 is located on a side of the second reflective layer 82 facing away from the substrate 30 and on a side of the first isolation layer 83 facing away from the substrate 30, and the second transparent conductive layer 84 penetrating the second reflective layer 82 and the passivation layer 81 to connect to the heavily doped semiconductor layer 41 in the first semiconductor layer 4.

[0137] The second transparent conductive layer 84 may include an ITO layer, and the thickness of the second transparent conductive layer 84 may be 100 nm to 400 nm.

[0138] For example, photolithography and ICP-RIE etching processes are used to etch the second reflective layer 82 and the passivation layer 81 on the side of the heavily doped semiconductor layer 41 facing away from the substrate 30 to expose the heavily doped semiconductor layer 41. The second transparent semiconductor layer 84 is deposited using electron beam evaporation or PVD, and an annealing process is performed to increase the transmittance of the second transparent semiconductor layer 84 and reduce the material resistance.

[0139] In some embodiments, as shown in FIG14 , the method for manufacturing the display chip further includes forming an n-type ohmic contact electrode and a third reflective layer 85 on the peripheral side of the chip structure 20, with the n-type ohmic contact electrode and the third reflective layer 85 being located on the side of the second transparent semiconductor layer 84 facing away from the substrate 30. The third reflective layer 85 can reduce optical crosstalk between pixels and reduce the light divergence angle, thereby improving light extraction efficiency.

[0140] The n-type ohmic contact electrode includes a metal layer, such as Ti / Al / Ti / Au, etc. The third reflective layer may include a metal layer, such as at least one of Ag and Al, etc.

[0141] For example, the n-type ohmic contact electrode is fabricated using photolithography and electron beam evaporation. The third reflective layer is deposited using electron beam evaporation or PVD. It should be noted that the n-type ohmic contact electrode and the third reflective layer 85 may also be fabricated using other processes, which are not specifically limited herein.

[0142] In some embodiments, as shown in FIG14 , the method for manufacturing the display chip further includes: forming a second isolation layer 86 on the peripheral side of the chip structure 20; and forming a micro-lens 85 (micro-lens) on the side of the second transparent conductive layer 84 facing away from the substrate 30. The second isolation layer 86 covers the second transparent semiconductor layer 84, the n-type ohmic contact electrode and the third reflective layer 85, and the surface of the second isolation layer 86 facing away from the substrate 30 can be flush with the surface of the second transparent conductive layer 84 facing away from the substrate 30. The first isolation layer 83 and the second isolation layer 86 are used to achieve electrical insulation between pixel mesas. The second isolation layer 86 may include SiO2 and SiN x At least one of the above. The micro lens 85 corresponds to the position of the chip structure 20 and is used to increase the light collection of the chip. The micro lens 85 may include SiO2 or the like.

[0143] For example, a photolithography process and a PECVD device are used to deposit the second isolation layer 86. A PECVD device is used to deposit the microlens 87.

[0144] According to the manufacturing method of the display chip provided in the embodiment of the present application, the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the chip carrier injection efficiency, and effectively suppressing the overflow of carriers, alleviating the Droop effect of the chip under large current injection, improving the luminous efficiency of the display chip, and thereby improving the display effect of the display chip.

[0145] Accordingly, an embodiment of the present application further provides a display chip that can be manufactured using the above-mentioned method for manufacturing a display chip, wherein the display chip can be a Micro-LED display chip.

[0146] As shown in Figure 14, the display chip includes a chip structure 20, which includes a first semiconductor layer 4, a quantum well light-emitting layer 5 and a second semiconductor layer 6. The quantum well light-emitting layer 5 is located on one side of the first semiconductor layer 4, and the second semiconductor layer 6 is located on the side of the quantum well light-emitting layer 5 away from the first semiconductor layer 4.

[0147] One of the first semiconductor layer 4 and the second semiconductor layer 6 is an n-type semiconductor layer, and the other is a p-type semiconductor layer, that is, the first semiconductor layer 4 is an n-type semiconductor layer and the second semiconductor layer 6 is a p-type semiconductor layer; or, the first semiconductor layer 4 is a p-type semiconductor layer and the second semiconductor layer 6 is an n-type semiconductor layer.

[0148] The first semiconductor layer 4 , the quantum well light-emitting layer 5 and the second semiconductor layer 6 are all nitrogen-polar film layers.

[0149] In this embodiment, the first semiconductor layer 4, the quantum well light-emitting layer 5 and the second semiconductor layer 6 are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the carrier injection efficiency of the chip, and effectively suppressing the overflow of carriers, thereby alleviating the Droop effect of the chip under large current injection, and improving the luminous efficiency of the display chip.

[0150] In some embodiments, the chip structure 20 is a nitrogen-polarity InGaN-based chip structure, the first semiconductor layer 4 is an n-type semiconductor layer, and the second semiconductor layer 6 is a p-type semiconductor layer.

[0151] In some embodiments, as shown in FIG14 , the first semiconductor layer includes a heavily doped semiconductor layer 41 and a lightly doped semiconductor layer 42. The lightly doped semiconductor layer 42 is located between the heavily doped semiconductor layer 41 and the quantum well light emitting layer 5. Both the heavily doped semiconductor layer 41 and the lightly doped semiconductor layer 42 are nitrogen-polar film layers.

[0152] The heavily doped semiconductor layer 41 may include an n-GaN heavily doped layer, and the electron concentration of the heavily doped semiconductor layer 41 is 1×10 18 cm -3 ~2×10 19 cm -3 The thickness of the heavily doped semiconductor layer 41 is 0.5 μm to 1.5 μm. The heavily doped semiconductor layer 41 may also include n-Al c Ga 1-c N / n-GaN superlattice layer, 0.02≤c≤0.15, electron concentration is 1×10 18 cm -3 ~2×10 19 cm -3 Among them, n-Al c Ga 1-c The Al content in N is about 2% to 15%, and the thickness can be 2nm to 3nm. The thickness of n-GaN can be 2.5nm to 15nm. c Ga 1-c The N / n-GaN superlattice layer can alleviate the extension of dislocations and regulate stress.

[0153] The lightly doped semiconductor layer 42 may include an n-GaN lightly doped layer, and the electron concentration of the lightly doped semiconductor layer 42 is 1×10 17 cm -3 ~5×10 17 cm -3 The thickness of the lightly doped semiconductor layer 42 is 0.2 μm to 0.5 μm. The lightly doped semiconductor layer 42 may also include n-Al g Ga 1-gN / n-GaN superlattice layer, 0.02≤g≤0.08, electron concentration is 1×10 17 cm -3 ~5×10 17 cm -3 Among them, n-Al g Ga 1-g The Al component in N is about 2% to 8%, the thickness is 2nm to 3nm, and the thickness of n-GaN is 2.5nm to 15nm.

[0154] In some embodiments, as shown in FIG14 , the chip structure 20 further includes a fourth undoped semiconductor layer 71, a first barrier layer 72, a first superlattice layer 73, and a second superlattice layer 74 sequentially disposed between the first semiconductor layer 4 and the quantum well light-emitting layer 5. That is, the fourth undoped semiconductor layer 71 is located between the lightly doped semiconductor layer 42 and the quantum well light-emitting layer 5, the first barrier layer 72 is located between the fourth undoped semiconductor layer 71 and the quantum well light-emitting layer 5, the first superlattice layer 73 is located between the first barrier layer 72 and the quantum well light-emitting layer 5, and the second superlattice layer 74 is located between the first superlattice layer 73 and the quantum well light-emitting layer 5. The fourth undoped semiconductor layer 71, the first barrier layer 72, the first superlattice layer 73, and the second superlattice layer 74 are all nitrogen-polar film layers.

[0155] The fourth non-doped semiconductor layer 71 may include a u-GaN layer, and the thickness of the fourth non-doped semiconductor layer 71 may be 10 nm to 30 nm. The first barrier layer 72 may include a GaN layer, and the thickness of the first barrier layer 72 may be 10 nm to 30 nm. The first superlattice layer 73 may include at least one period (e.g., 1 to 3 periods) of u-In a Ga 1-a N / u-GaN superlattice layer, 0.01≤a≤0.05. Among them, u-In a Ga 1-a The thickness of N can be 2nm to 3nm, the In composition can be 1% to 5%, and the thickness of u-GaN can be 2.5nm to 15nm. The second superlattice layer 74 can include at least one period (such as 1 to 3 periods) of u-In. b Ga 1-b N / n-GaN superlattice layer, 0.05≤b≤0.1. Among them, the electron concentration of n-GaN can be 1×10 17 cm -3 ~5×10 17 cm -3 , u-In b Ga 1-b The thickness of N can be 2 nm to 3 nm, the In composition can be 5% to 10%, and the thickness of n-GaN can be 2.5 nm to 15 nm.

[0156] In some embodiments, the quantum well light emitting layer 5 includes a red light quantum well light emitting layer.

[0157] In some embodiments, the quantum well light-emitting layer 5 includes at least one periodic structure (e.g., 2 to 3 periodic structures), each periodic structure including a fifth undoped semiconductor layer, a first potential well layer, a first cap layer, a second barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer, and a third barrier layer, which are sequentially disposed between the first semiconductor layer 4 and the second semiconductor layer 6. The fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer, and the third barrier layer are all nitrogen-polar film layers.

[0158] The fifth non-doped semiconductor layer may include a low-temperature u-GaN layer, and the thickness of the fifth non-doped semiconductor layer may be 2nm to 3nm. The first potential well layer may include u-In x Ga 1-x N layer, 0.1≤x≤0.15, the thickness of the first potential well layer can be 2.5nm to 3.5nm. The first cap layer can include a GaN layer, and the thickness of the first cap layer can be 2nm to 3nm. The second barrier layer can include a GaN layer or u-In y Ga 1-y N layer, 0.01≤y≤0.03, the thickness of the second barrier layer can be 10nm to 15nm. The sixth non-doped semiconductor layer can include a low-temperature u-GaN layer, and the thickness of the sixth non-doped semiconductor layer can be 2nm to 3nm. The second potential well layer can include u-In z Ga 1-z N layer, 0.35≤z≤0.4, the thickness of the second potential well layer can be 2.5nm~3.5nm. The second cap layer can include a GaN layer, and the thickness of the second cap layer can be 2nm~3nm. The third barrier layer can include u-Al d Ga 1-d N layer, 0.3≤d≤0.35, the thickness of the third barrier layer can be 10nm~15nm.

[0159] This embodiment uses a nitrogen-polar film layer, so that the quantum well light-emitting layer can be grown at a high temperature, thereby improving the crystal quality of the barrier layer material in the quantum well light-emitting layer, and reducing the barrier for carrier injection into the quantum well light-emitting layer in the chip. At the same time, it can also increase the barrier for carrier overflow from the quantum well light-emitting layer, that is, improve the carrier injection efficiency, while suppressing the overflow of carriers and alleviating the Droop effect of the chip under large current injection.

[0160] In some embodiments, as shown in FIG14 , the chip structure 20 may further include a protective layer 75 located between the quantum well light-emitting layer 5 and the second semiconductor layer 6 . The protective layer 75 is a nitrogen-polar film layer. The protective layer 75 includes a u-GaN layer and has a thickness of 20 nm to 50 nm.

[0161] In some embodiments, as shown in FIG14 , the second semiconductor layer 6 includes an electron blocking layer 61, a hole injection layer 62, and an ohmic contact layer 63, which are sequentially arranged on the side of the quantum well light-emitting layer 5 facing away from the first semiconductor layer 4. The electron blocking layer 61, the hole injection layer 62, and the ohmic contact layer 63 are all nitrogen-polar film layers.

[0162] The electron blocking layer 61 may include a p-AlGaN polarization induction layer. The thickness of the p-AlGaN polarization induction layer may be 50 nm to 60 nm. The Al component may be linearly increased from 0% to 20% or 30%. The theoretical hole concentration of the film layer is 2×10 18 cm -3 ~2.5×10 18 cm -3 The electron blocking layer 61 may also include p-Al e Ga 1-e N / p-GaN superlattice layer, 0.15≤e≤0.25, the hole concentration can be 1.5×10 18 cm -3 ~2.5×10 18 cm -3 , p-Al e Ga 1-e The Al content in N is about 15% to 25%, and the p-Al e Ga 1-e The thickness of N can be 2 nm to 3 nm, and the thickness of p-GaN can be 5 nm to 15 nm.

[0163] The hole injection layer 62 may include a p-GaN layer, and the thickness of the hole injection layer 62 may be 100 nm to 140 nm. The ohmic contact layer 63 may include at least one period (eg, 2 to 4 periods) of p-In f Ga 1-f N / p-GaN superlattice layer, 0.1≤f≤0.2. p-In f Ga 1-f The In content in N is about 10% to 20%, and the p-In f Ga 1-f The thickness of N can be 2 nm to 3 nm, and the thickness of p-GaN can be 5 nm to 15 nm.

[0164] In some embodiments, the chip structure 20 further includes a first transparent conductive layer 76, a first reflective layer 77, and a bonding layer 78, which are sequentially located on the side of the second semiconductor layer 6 facing away from the quantum well light-emitting layer 5. Specifically, the first transparent conductive layer 76 is located on the side of the ohmic contact layer 63 facing away from the hole injection layer 62, the first reflective layer 77 is located on the side of the first transparent conductive layer 76 facing away from the ohmic contact layer 63, and the bonding layer 78 is located on the side of the first reflective layer 77 facing away from the first transparent conductive layer 76. The first reflective layer 77 is used to enhance the light extraction efficiency of the display chip, and the bonding layer 78 is used to bond the display chip to another substrate.

[0165] The first transparent conductive layer 76 may include an ITO (indium tin oxide) layer. The first reflective layer 77 may include a metal reflective layer, such as at least one of Ag and Al. The bonding layer 78 may include a metal layer, such as at least one of Cr, Pt, Ni, Ti, Ni, and Ag.

[0166] Along the c-axis growth direction, GaN materials have two polarities, namely gallium polarity and nitrogen polarity. Compared with gallium polarity, the incorporation efficiency of In in nitrogen-polarity InGaN materials is higher. The main reason is that the In atoms in the nitrogen-polarity InGaN material can form stronger In-N bonds with the surface N atoms. Moreover, there are 4 In-N bonds around each In atom on the surface of the nitrogen-polarity InGaN material, which makes the desorption efficiency of In in the nitrogen-polarity InGaN material lower, which is conducive to the incorporation of In. Therefore, under the same In component, the nitrogen-polarity InGaN material can have a higher growth temperature, which is conducive to improving the crystal quality of the potential well layer material in the quantum well and improving the internal quantum efficiency of the chip structure.

[0167] Furthermore, nitrogen-polar materials have a polarization direction opposite to gallium-polar materials, which can lower the barrier to carrier injection into the chip's quantum wells while also raising the barrier to carrier overflow. Therefore, the nitrogen-polar InGaN-based chip structure has higher carrier injection efficiency while also suppressing carrier overflow, alleviating the chip's Droop effect at high currents (high current densities) to a certain extent and improving the display chip's luminous efficiency.

[0168] In some embodiments, as shown in FIG14 , the display chip further includes a substrate 30 . The substrate 30 is bonded to a side of the chip structure 20 facing away from the first semiconductor layer 4 .

[0169] In some embodiments, the substrate 30 is located on a side of the bonding layer 78 facing away from the first semiconductor layer 4 , and the substrate 30 is bonded to the chip structure 20 through the bonding layer 78 .

[0170] The substrate 30 may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving backplane.

[0171] In some embodiments, as shown in FIG14 , the display chip further includes a passivation layer 81 and a second reflective layer 82. The passivation layer 81 is located on the side of the chip structure 20 facing away from the substrate 30 and covers the sidewalls of the chip structure 20. That is, the passivation layer 81 is located on the side of the heavily doped semiconductor layer 41 facing away from the substrate 30 and on the sidewalls of the chip structure 20. The second reflective layer 82 covers the passivation layer 81, that is, the second reflective layer 82 is located on the surface of the passivation layer 81.

[0172] The passivation layer 81 may include SiO2, SiN x and Al2O3, the thickness of the passivation layer 81 may be 10nm-40nm, the second reflective layer 82 may include a DBR layer, and the DBR layer may include TiO2 / SiO2 or Ta2O5 / SiO2, etc.

[0173] In some embodiments, the display chip further includes a first isolation layer 83, and the first isolation layer 83 is located on the peripheral side of the chip structure 20. The first isolation layer 83 may include SiO2 and SiN x At least one of .

[0174] In some embodiments, the display chip further includes a second transparent conductive layer 84, which is located on the side of the second reflective layer 82 facing away from the substrate 30 and on the side of the first isolation layer 83 facing away from the substrate 30, and the second transparent conductive layer 84 penetrates the second reflective layer 82 and the passivation layer 81 and is connected to the heavily doped semiconductor layer 41 in the first semiconductor layer 4.

[0175] The second transparent conductive layer 84 may include an ITO layer, and the thickness of the second transparent conductive layer 84 may be 100 nm to 400 nm.

[0176] In some embodiments, the display chip further includes an n-type ohmic contact electrode, which is located around the chip structure 20 and on a side of the second transparent conductive layer 84 facing away from the substrate 30. The n-type ohmic contact electrode includes a metal layer, such as Ti / Al / Ti / Au.

[0177] In some embodiments, as shown in FIG14 , the display chip further includes a third reflective layer 85 . The third reflective layer 85 is located around the chip structure 20 and on the side of the second transparent conductive layer 84 facing away from the substrate 30 . The third reflective layer 85 can reduce inter-pixel optical crosstalk and light divergence angle, and improve chip light extraction efficiency. The third reflective layer 85 can include a metal layer, such as at least one of Ag and Al.

[0178] In some embodiments, the display chip further includes a second isolation layer 86, which is located on the peripheral side of the chip structure 20 and covers the second transparent conductive layer 84 and the third reflective layer 85. The surface of the second isolation layer 86 facing away from the substrate 30 can be flush with the surface of the second transparent conductive layer 84 facing away from the substrate 30. The second isolation layer 86 can include SiO2 and SiN x The first isolation layer 83 and the second isolation layer 86 are used to achieve electrical insulation between pixel mesas.

[0179] In some embodiments, the display chip further includes a microlens 85. The microlens 85 is located on a side of the second transparent conductive layer 84 facing away from the chip structure 20. The microlens 85 corresponds to the position of the chip structure 20. The microlens 85 is used to increase the light collection of the chip. The microlens 85 is made of SiO2 or the like.

[0180] According to the display chip provided in the embodiment of the present application, the first semiconductor layer 4, the quantum well light-emitting layer 5 and the second semiconductor layer 6 are all nitrogen-polar film layers. The nitrogen-polar film layers can be grown at high temperatures, thereby improving the crystal quality of the potential well layer material in the quantum well, improving the carrier injection efficiency of the chip, and effectively suppressing the overflow of carriers, thereby alleviating the Droop effect of the chip under large current injection, improving the luminous efficiency of the display chip, and thereby improving the display effect of the display chip.

[0181] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object may be one or more.

[0182] In the description of this application, “plurality” means two or more.

[0183] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0184] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display chip, characterized in that: include: The chip structure comprises a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer arranged in sequence; One of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; Wherein, the first semiconductor layer, the quantum well light-emitting layer and the second semiconductor layer are all nitrogen-polar film layers.

2. The display chip according to claim 1, characterized in that: The chip structure further includes a fourth non-doped semiconductor layer, a first barrier layer, a first superlattice layer and a second superlattice layer which are sequentially arranged between the first semiconductor layer and the quantum well light-emitting layer; The fourth undoped semiconductor layer, the first barrier layer, the first superlattice layer and the second superlattice layer are all nitrogen-polar film layers.

3. The display chip according to claim 1 or 2, characterized in that: The first semiconductor layer includes a heavily doped semiconductor layer and a lightly doped semiconductor layer located between the heavily doped semiconductor layer and the quantum well light emitting layer; The heavily doped semiconductor layer and the lightly doped semiconductor layer are both nitrogen polar film layers.

4. The display chip according to any one of claims 1 to 3, characterized in that: The quantum well light-emitting layer comprises a fifth undoped semiconductor layer, a first potential well layer, a first cap layer, a second potential barrier layer, a sixth undoped semiconductor layer, a second potential well layer, a second cap layer and a third barrier layer, which are sequentially arranged between the first semiconductor layer and the second semiconductor layer; The fifth undoped semiconductor layer, the first potential well layer, the first cap layer, the second potential barrier layer, the sixth undoped semiconductor layer, the second potential well layer, the second cap layer and the third potential barrier layer are all nitrogen polar film layers.

5. The display chip according to any one of claims 1 to 4, characterized in that: The second semiconductor layer comprises an electron blocking layer, a hole injection layer and an ohmic contact layer which are sequentially arranged on a side of the quantum well light-emitting layer away from the first semiconductor layer; The electron blocking layer, the hole injection layer and the ohmic contact layer are all nitrogen polar film layers.

6. The display chip according to any one of claims 1 to 5, characterized in that: The chip structure further includes a first transparent conductive layer, a first reflective layer and a bonding layer which are sequentially located on a side of the second semiconductor layer away from the quantum well light-emitting layer.

7. The display chip according to any one of claims 1 to 6, characterized in that: The chip structure further includes a protection layer located between the quantum well light-emitting layer and the second semiconductor layer.

8. The display chip according to any one of claims 1 to 7, characterized in that: The display chip further includes a substrate; The substrate is bonded to a side of the chip structure facing away from the first semiconductor layer.

9. The display chip according to claim 8, characterized in that: The display chip further includes a passivation layer and a second reflective layer; The passivation layer is located on a side of the chip structure away from the substrate and covers a side wall of the chip structure, and the second reflective layer covers the passivation layer.

10. The display chip according to claim 9, characterized in that: The display chip further includes a second transparent conductive layer located on a side of the second reflective layer away from the substrate, and the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer.

11. The display chip according to claim 10, characterized in that: The display chip further comprises a third reflective layer located on the peripheral side of the chip structure, and a microlens located on a side of the second transparent conductive layer away from the chip structure.

12. The display chip according to any one of claims 1 to 11, characterized in that: The quantum well light-emitting layer comprises a red light quantum well light-emitting layer.

13. A method for manufacturing a display chip, characterized in that: include: forming a base; A chip structure is formed on one side of the substrate; the chip structure comprises a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer sequentially arranged on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light-emitting layer, and the second semiconductor layer are all nitrogen-polar film layers; The substrate is removed.

14. The method for manufacturing a display chip according to claim 13, characterized in that: The base comprises a substrate, a buffer layer and a non-doped semiconductor composite layer; The forming of the substrate comprises: providing a substrate; forming a buffer layer on one side of the substrate; A non-doped semiconductor composite layer is formed on a side of the buffer layer away from the substrate; the chip structure is located on a side of the non-doped semiconductor composite layer away from the buffer layer; Wherein, the buffer layer and the non-doped semiconductor composite layer are both nitrogen-polar film layers.

15. The method for manufacturing a display chip according to claim 14, characterized in that: The non-doped semiconductor composite layer comprises a plurality of non-doped semiconductor layers and at least one insertion layer which are stacked, and there is one insertion layer between any two adjacent non-doped semiconductor layers; The non-doped semiconductor layer and the insertion layer are both nitrogen-polar film layers.

16. The method for manufacturing a display chip according to claim 15, characterized in that: The plurality of non-doped semiconductor layers include a first non-doped semiconductor layer, a second non-doped semiconductor layer and a third non-doped semiconductor layer, the at least one insertion layer includes a first insertion layer and a second insertion layer; the first non-doped semiconductor layer, the first insertion layer, the second non-doped semiconductor layer, the second insertion layer and the third non-doped semiconductor layer are sequentially arranged between the buffer layer and the first semiconductor layer; The first non-doped semiconductor layer, the second non-doped semiconductor layer and the third non-doped semiconductor layer all include u-GaN layers, and the first insertion layer includes porous SiN x layer, and the second insertion layer includes an AlN layer.

17. The method for manufacturing a display chip according to any one of claims 14 to 16, characterized in that: The removing of the substrate comprises: removing the substrate; The buffer layer and the undoped semiconductor composite layer are removed.

18. The method for manufacturing a display chip according to any one of claims 13 to 17, characterized in that: Before removing the substrate, the method further comprises: The side of the chip structure facing away from the base is bonded to a substrate.

19. The method for manufacturing a display chip according to claim 18, characterized in that: After removing the substrate, the method further comprises: forming a passivation layer on a side of the chip structure facing away from the substrate, wherein the passivation layer covers a side wall of the chip structure; A second reflective layer is formed on the surface of the passivation layer.

20. The method for manufacturing a display chip according to claim 19, characterized in that: The method further comprises: forming a second transparent conductive layer on a side of the second reflective layer away from the substrate, wherein the second transparent conductive layer penetrates the second reflective layer and the passivation layer and is connected to the first semiconductor layer; A microlens is formed on a side of the second transparent conductive layer facing away from the substrate.

Images