High-voltage-withstanding HEMT device and driving method therefor

Abstract

A high-voltage-withstanding HEMT device and a driving method therefor, which relate to the technical field of microelectronics, and can improve the voltage-withstanding performance and current density of the HEMT device. The HEMT device comprises: a multi-layer body material layer (10); sources (20) and a drain (30), wherein the sources (20) and the drain (30) are stacked on the multi-layer body material layer (10); in a first direction (D1), the sources (20) and the drain (30) are located on two sides of the multi-layer body material layer (10), respectively; or the sources (20) and the drain (30) are located on the same side of the multi-layer body material layer (10), and the sources (20) and the drain (30) are located on different mesas (70) respectively; first gates (40), wherein the first gates (40) and the sources (20) are located on the same side of the multi-layer body material layer (10), and the first gates (40) and the sources (20) are arranged adjacent to each other; and a second gate (50), wherein the second gate (50) and the first gates (40) are located on the same side of the multi-layer body material layer (10), and the first gates (40) are located between the second gate (50) and the sources (20), the second gate (50) is embedded inside the multi-layer body material layer (10) from the surface of the multi-layer main material layer (10), the second gate (50) is used for controlling a vertical conductive channel in the first direction (D1), and the first direction (D1) is perpendicular to the multi-layer body material layer (10).

Description

A high-voltage HEMT device and a driving method thereof Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and in particular relates to a high-voltage HEMT device and a driving method thereof. Background Art

[0002] HEMT devices are planar devices, meaning the source and drain are on the same plane. Therefore, the material's voltage withstand capability cannot be fully utilized. To achieve a higher device voltage withstand, the physical distance between the source and drain electrodes must be increased. This increases the chip area, increasing costs while also reducing the yield rate of chip manufacturing. Furthermore, due to limitations in substrate and buffer layer materials, the device's voltage withstand capability is not easily increased to a particularly high level. The advantage of vertical devices is that the source and drain electrodes can be placed on opposite sides of the bulk material, allowing the voltage between the source and drain electrodes to be borne by the bulk material. This improves the device's voltage withstand capability, while also increasing integration and enabling chips with higher current densities.

[0003] Existing GaN-based vertical devices are generally divided into two types, one is a planar gate and the other is a vertical gate. Among them, the planar gate controls the current through a gate parallel to the chip surface. The source and gate of the device are located in the same plane, and the source and drain of the device are located on different planes or on both sides of the device material layer. A current blocking layer covering part of the area is set between the source and drain of the device. At this time, the current flow path is generally from the drain through the body material vertically through the area not covered by the current blocking layer to the area covered by the gate on the chip surface where the source and gate are located, and then moves a distance on the chip surface parallel to the direction of the planar gate to reach the source; the advantage of the planar gate is that the gate manufacturing process is relatively mature and simple, but when it is manufactured on the structure of the HEMT device type, it is necessary to inject or other methods into the area not covered by the gate, that is, not controlled by the gate. A current blocking layer is formed in the material below the two-dimensional carrier gas channel in the control area, or the growth of the current blocking layer is inserted during the epitaxial growth of the device, and then the current blocking layer material in part of the area is removed by etching, and then the growth of subsequent material layers is continued by secondary epitaxy, so as to realize the current path including vertically passing through the area not covered by the current blocking layer and reaching the area covered by the gate on the chip surface and then flowing horizontally to the source. Whether the current blocking layer is realized by ion implantation or by secondary epitaxial process, the related process is difficult and will affect the material quality of the device. At the same time, because there is no inversion channel layer to protect the gate, it is easy to cause gate degradation and form large leakage in a long-term high electric field environment.

[0004] A vertical gate is achieved by etching a hole perpendicular to the chip device surface in different material layers, filling the inner walls of the hole with an insulating layer and then a metal. The gate controls the channel region of the bulk material layer. Applying a gate voltage causes the sidewalls of the material layer in the area covered by the gate to generate an inversion layer, forming a conductive channel. This structure has the advantage of achieving higher integration, but the disadvantage is that it loses the high-frequency response capability of the two-dimensional carrier gas channel of the HEMT device. In addition, due to the need to consider the threshold voltage, the gate insulation layer thickness cannot be too thick. This also makes the vertical bottom gate region susceptible to breakdown and other reliability issues after long-term exposure to the drain electric field. Existing Si-based and SiC-based power devices have many structures to enhance the breakdown protection of the vertical gate, but these structures require a complex combination of ion implantation to form a protection zone at the bottom of the vertical gate, which is difficult to process and is not suitable for HEMT device structures composed of materials such as GaN.

[0005] Therefore, there is an urgent need to provide a high-voltage HEMT device to improve the voltage-withstand characteristics of the HEMT device. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a high-voltage HEMT device and a driving method thereof. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a high withstand voltage HEMT device, comprising:

[0008] multiple layers of subject material;

[0009] A source electrode and a drain electrode, both of which are stacked with the multi-layer main material layer; along the first direction, the source electrode and the drain electrode are respectively located on both sides of the multi-layer main material layer; or, along the first direction, the source electrode and the drain electrode are located on the same side of the multi-layer main material layer, and the source electrode and the drain electrode are respectively located on different mesas;

[0010] A first gate electrode is located on the same side of the multi-layer main material layer as the source electrode and is stacked with the multi-layer main material layer; the first gate electrode is adjacent to the source electrode;

[0011] The second gate and the first gate are located on the same side of the multi-layer main material layer, the second gate is adjacent to the first gate, and the first gate is located between the second gate and the source; the second gate is embedded from the surface of the multi-layer main material layer into the interior of the multi-layer main material layer and extends along the first direction, and the second gate is used to control the vertical conductive channel along the first direction; the first direction is perpendicular to the multi-layer main material layer.

[0012] In a second aspect, the present invention further provides a method for driving a high-voltage HEMT device, comprising:

[0013] A first voltage is applied to the second gate, where the applied first voltage is greater than a first threshold, thereby opening a vertical conductive channel, and the current conduction capability of the vertical conductive channel can be adjusted by adjusting the magnitude of the first voltage. The first gate is controlled by an external drive signal. A second voltage is applied to the first gate. When the applied second voltage reaches a second threshold, the horizontal two-dimensional carrier gas channel under the first gate is controlled to be turned on or off by the first gate. That is, after the second gate opens the vertical conductive channel, the external drive signal applied to the first gate controls the on / off of the high-voltage HEMT device.

[0014] When a positive voltage, zero bias or negative voltage is applied to the second gate, the applied positive voltage, zero bias or negative voltage is less than the first threshold, the vertical channel turn-on condition is not met, and the first gate controls the conduction or shutoff of the two-dimensional carrier gas conduction channel under the action of the external drive signal, but the high-voltage HEMT device as a whole is still in the off state.

[0015] Beneficial effects of the present invention:

[0016] The present invention provides a high-voltage HEMT device and a driving method thereof, wherein a first gate is stacked on the surface of a multi-layer main material layer, and a second gate is embedded from the surface of the multi-layer main material layer into the interior of the multi-layer main material layer and extends in a direction perpendicular to the multi-layer main material layer; a two-dimensional carrier gas channel is provided below the HEMT device covered by the first gate, while no two-dimensional carrier gas channel is provided below the HEMT device covered by the second gate. When a sufficient voltage is applied to the second gate, a vertical conductive channel is formed below the HEMT device covered by the second gate. At this time, the two-dimensional carrier gas channel and the vertical conductive channel form an electrical connection path. By adjusting the voltage applied to the second gate, the vertical conductive channel perpendicular to the direction of the multi-layer main material layer can also be adjusted. Thus, by applying an operating voltage to the second gate before the device operates, a conduction channel in the vertical direction of the device is established in advance. At the same time, the current can be directed into the HEMT device through the second gate in the vertical direction of the device, thereby achieving the purpose of improving the device's withstand voltage by utilizing the multiple host material layers. Then, by applying a control signal to the first gate to control the conduction or shutoff between the source and drain of the HEMT device, the excellent high-frequency response capability and low on-resistance when controlling the conduction and shutoff of the two-dimensional carrier gas by the first gate can be retained. At the same time, through the inversion channel layer connected to the source, the withstand voltage of the device acting on the first gate is mainly borne by the drift region. Thus, while ensuring the withstand voltage performance of the device, the operating frequency of the HEMT device is achieved and the current density of the HEMT device is increased.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a schematic diagram of a high-voltage HEMT device provided by an embodiment of the present invention;

[0019] FIG2 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0020] FIG3 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0021] FIG4 is a top view of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0022] FIG5 is a schematic diagram of a first gate provided by an embodiment of the present invention;

[0023] FIG6 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0024] FIG7 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0025] FIG8 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0026] FIG9 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0027] FIG10 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0028] FIG11 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0029] FIG12 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0030] FIG13 is another top view of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0031] FIG14 is another top view of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0032] FIG15 is another schematic diagram of a high withstand voltage HEMT device provided by an embodiment of the present invention;

[0033] FIG16 is another top view of the high withstand voltage HEMT device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0035] Referring to FIG. 1 and FIG. 2 , FIG. 1 is a schematic diagram of a high-voltage HEMT device provided in an embodiment of the present invention, and FIG. 2 is another schematic diagram of a high-voltage HEMT device provided in an embodiment of the present invention. The high-voltage HEMT device provided in the present invention includes:

[0036] Multi-layer body material layer 10;

[0037] The source electrode 20 and the drain electrode 30 are both stacked with the multi-layer body material layer 10; along the first direction D1, the source electrode 20 and the drain electrode 30 are respectively located on both sides of the multi-layer body material layer 10; or, along the first direction D1, the source electrode 20 and the drain electrode 30 are located on the same side of the multi-layer body material layer 10, and the source electrode 20 and the drain electrode 30 are respectively located on different mesas 70;

[0038] The first gate 40 is located on the same side of the multi-layer main material layer 10 as the source 20 and is stacked with the multi-layer main material layer 10; the first gate 40 and the source 20 are adjacently arranged and can be spaced apart.

[0039] The second gate 50, the second gate 50 and the first gate 40 are located on the same side of the multi-layer main material layer 10, the second gate 50 and the first gate 40 are adjacent to each other and can be arranged at intervals, and the first gate 40 is located between the second gate 50 and the source 20; the second gate 50 is embedded from the surface of the multi-layer main material layer 10 into the interior of the multi-layer main material layer 10 and extends along the first direction D1, the second gate 50 is used to control the vertical conductive channel along the first direction D1; the first direction D1 is perpendicular to the multi-layer main material layer 10.

[0040] Specifically, please continue to refer to Figures 1 and 2. A high-voltage HEMT device provided in this embodiment includes a multi-layer main body material layer 10, a source 20, a drain 30, a first gate 40 and a second gate 50, wherein the source 20 and the drain 30 are both stacked with the multi-layer main body material layer 10. Along the first direction D1, that is, along the direction perpendicular to the multi-layer main body material layer, the source 20 and the drain 30 are respectively located on both sides of the multi-layer main body material layer 10, see Figure 1, or, along the first direction D1, the source 20 and the drain 30 are located on the same side of the multi-layer main body material layer 10, and the source 20 and the drain 30 are respectively located on the same side of the multi-layer main body material layer 10. 2; the first gate 40 and the second gate 50 are both located on the same side of the multilayer main material layer 10, and the first gate 40 and the second gate 50 are located on the same side as the source 20, the first gate 40 is adjacent to the source 20 and can be arranged at intervals, the second gate 50 is adjacent to the first gate 40 and can be arranged at intervals, the first gate 40 is located between the second gate 50 and the source 20; the first gate 40 is only stacked on the surface of the multilayer main material layer 10, and the second gate 50 is embedded in the interior of the multilayer main material layer 10 from the surface of the multilayer main material layer 10, and is vertically spaced. The first gate 40 extends perpendicularly to the direction of the multilayer host material layer 10; optionally, the first gate 40 may be a p-type GaN gate, or a metal gate or a metal groove gate, and the second gate 50 may be a metal; it is understood that the HEMT device covered by the first gate 40 has a two-dimensional carrier gas channel below, and the HEMT device covered by the second gate 50 does not have a two-dimensional carrier gas channel below. When a sufficient voltage is applied to the second gate 50, a vertical conductive channel is formed below the HEMT device covered by the second gate 50. At this time, the two-dimensional carrier gas channel and the vertical conductive channel form an electrical connection path; In this way, by applying an operating voltage to the second gate 50 before the device operates, a conduction channel in the vertical direction of the device is established in advance. Then, by applying a control signal to the first gate 40 to control the conduction or shutoff between the source 20 and the drain 30 of the HEMT device, the excellent high-frequency response capability when controlling the conduction and shutoff of the two-dimensional carrier gas by the first gate 40 can be retained. At the same time, the current can be directed into the interior of the HEMT device through the second gate 50 in the vertical direction of the device, thereby achieving the purpose of improving the withstand voltage of the device by utilizing the multi-layer host material layer 10, and achieving the operating frequency of the HEMT device while ensuring the withstand voltage performance of the device.

[0041] It should be noted that the first gate 40 that controls the on and off of the two-dimensional carrier gas channel can be a normally-on gate, that is, when there is no gate voltage on the first gate 40, the two-dimensional carrier gas channel always remains in the on state, and the two-dimensional carrier gas channel can only be turned off by applying a voltage on the gate; it can also be a normally-off gate, that is, when there is no gate voltage on the first gate 40, the two-dimensional carrier gas channel always remains in the off state, and the two-dimensional carrier gas channel can only be turned on by applying a voltage on the gate.

[0042] The two-dimensional carrier gas can be a two-dimensional electron gas or a two-dimensional hole gas. The two-dimensional electron gas channel in the channel below the normally-on gate needs a negative voltage applied to the gate to turn off, and the two-dimensional electron gas channel in the channel below the normally-off gate needs a positive voltage applied to the gate to turn on. The two-dimensional hole gas channel in the channel below the normally-on gate needs a positive voltage applied to the gate to turn off, and the two-dimensional hole gas channel in the channel below the normally-off gate needs a negative voltage applied to the gate to turn on. When the two-dimensional carrier gas used is a two-dimensional electron gas, the material of the inversion channel layer 12 in the multilayer main material structure is generally p-type doped GaN material. When the two-dimensional carrier gas used is a two-dimensional hole gas, the material of the inversion channel layer 12 in the multilayer main material structure is generally n-type doped GaN material.

[0043] It is understood that the barrier layer 14 is generally made of AlGaN, but may also be other GaN-based materials. The polarization channel layer 13 is generally made of GaN, but may also be other GaN-based materials. When the bandgap of the barrier layer 14 material is greater than the bandgap of the polarization channel layer 13 material, a two-dimensional hole gas is formed on the side of the polarization channel layer 13 near the barrier layer 14. When the bandgap of the barrier layer 14 material is less than the bandgap of the polarization channel layer 13 material, a two-dimensional hole gas is formed on the side of the polarization channel layer 13 near the barrier layer 14.

[0044] Among them, GaN-based materials mainly include GaN, BN and AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) alloy materials.

[0045] It should be noted that the embodiment shown in Figure 1 only schematically shows the positional relationship between the multi-layer main material layer 10, the first gate 40, and the second gate 50, and the source 20 and the drain 30 are located on different sides of the multi-layer main material layer 10, and does not represent their actual size; the embodiment shown in Figure 2 only schematically shows the positional relationship between the multi-layer main material layer 10, the first gate 40, and the second gate 50, and the source 20 and the drain 30 are located on the same side of the multi-layer main material layer 10, on different tables, and does not represent their actual size.

[0046] In an optional embodiment of the present invention, the multilayer main material layer 10 includes a drift layer 11, an inversion channel layer 12, a polarization channel layer 13, and a barrier layer 14 stacked in sequence; the drain 30 is located on the side of the drift layer 11 away from the inversion channel layer 12, and the source 20 is located on the side of the barrier layer 14 away from the polarization channel layer 13; wherein, a two-dimensional carrier gas conduction channel is formed between the polarization channel layer 13 and the barrier layer 14, and the first gate 40 is used to control the two-dimensional carrier gas conduction channel.

[0047] Specifically, referring to Figure 1, the multilayer main material layer 10 in this embodiment includes a stacked drift layer 11, an inversion channel layer 12, a polarization channel layer 13, and a barrier layer 14, wherein the drift layer 11 is an n-type drift layer 11; as shown in Figure 1, a cap layer 15 is provided above the barrier layer 14, the source 20, the first gate 40 and the second gate 50 are all provided above the cap layer 15 and stacked with the cap layer 15, and the drain 30 is located below the drift layer 11.

[0048] In an optional embodiment of the present invention, referring to Figures 3 and 4 , Figure 3 is another schematic diagram of a high-voltage HEMT device provided in an embodiment of the present invention, and Figure 4 is a top view of the high-voltage HEMT device provided in an embodiment of the present invention. An n+ electrode contact layer 16 is disposed below the n-type drift layer 11, and a drain electrode 30 is disposed below the n+ electrode contact layer 16. The n+ electrode contact layer 16 and the drain electrode 30 are stacked. A heavily n-type doped metal contact layer is disposed between the drift layer 11 and the drain electrode 30. Its primary function is to reduce the contact resistance of the metal semiconductor. The drift layer 11 is typically a lightly n-type doped material layer or an unintentionally doped material layer. Its primary function is to bear the voltage of the drain electrode 30 when the device is in the off state. As shown in Figure 4 , a first gate 40 is disposed around a second gate 50, and a source electrode 20 is disposed around the first gate 40. Figure 4 only illustrates the polygonal shape of the electrodes; the electrodes may also be circular or elliptical. The electrode shapes are not limited here and may be determined according to actual needs.

[0049] It should be noted that the multilayer main material layer 10 can be a stacked arrangement of a cap layer 15, a barrier layer 14, a polarization channel layer 13 and a drift layer 11, or a stacked arrangement of a cap layer 15, a barrier layer 14, a polarization channel layer 13, an inversion channel layer 12 and a drift layer 11. The film layers included in the multilayer main material layer 10 are not limited here and can be determined according to actual needs.

[0050] It should be noted that, referring to FIG. 4 , the HEMT device may be composed of a metapack structure in which a first gate 40 surrounds a second gate 50 and a source 20 surrounds the first gate 40 . The metapacks may also be electrically isolated by an insulating table. The concept of the metapack is consistent with that of existing power devices such as IGBTs and vertical power Si MOSFETs and will not be described separately here. It should be noted that, in this embodiment, the multilayer main material layer 10 includes at least one two-dimensional carrier gas channel. When it includes one two-dimensional carrier gas channel, the multilayer main material layer 10 includes a stacked polarization channel layer 13 and a barrier layer 14 to form a two-dimensional carrier gas channel. When it includes multiple two-dimensional carrier gas channels, the multilayer main material layer 10 includes alternately stacked channel layers 13 and barrier layers 14, that is, a polarization channel layer 13 and a barrier layer 14 form a two-dimensional carrier gas channel, and multiple two-dimensional carrier gas channels can be formed; when it includes multiple two-dimensional carrier gas channels, the first gate 40 can control multiple two-dimensional carrier gas channels.

[0051] In an optional embodiment of the present invention, please refer to Figure 5, which is a schematic diagram of the first gate provided in an embodiment of the present invention. The first gate can be any one of a pGaN gate, a metal gate, a metal groove gate 1, a metal groove gate 2 or a pGaN groove gate. Please refer to Figure 5 for its specific structure.

[0052] In an optional embodiment of the present invention, the multi-layer main material layer 10 is grown layer by layer in a same epitaxial growth process.

[0053] Specifically, in this embodiment, the multi-layer main material layer 10 is grown layer by layer in the same epitaxial growth process by epitaxy, which can save process and simplify the manufacturing process.

[0054] In an optional embodiment of the present invention, please refer to Figure 6, which is another schematic diagram of a high-voltage HEMT device provided by an embodiment of the present invention. The second gate 50 includes a first branch 51 and a second branch 52. The first branch 51 is stacked with the multi-layer main material layer 10, and the second branch 52 extends from the surface of the multi-layer main material layer 10 to the drift layer 11. An insulating layer 60 is provided on the contact surface between the second branch 52 and the multi-layer main material layer 10.

[0055] Specifically, please continue to refer to Figures 1 and 3, and in combination with Figure 6, in this embodiment, the second gate 50 includes two parts, namely a first branch 51 and a second branch 52. The first branch 51 is arranged above the cap layer 15, and the second branch 52 extends from the upper surface of the cap layer 15 to the drift layer 11; it can be understood that the side of the second branch 52 and the contact surface with the cap layer 15, the barrier layer 14, the polarization channel layer 13, the inversion channel layer 12 and the drift layer 11 are all provided with an insulating layer 60.

[0056] In this embodiment, please continue to refer to Figure 6. The first gate 40 controls the two-dimensional carrier gas channel formed between the barrier layer 14 and the polarization channel layer 13, and the second gate 50 controls the channel in the vertical direction through the barrier layer 14, the polarization channel layer 13 or the barrier layer 14, the polarization channel layer 13, the inversion channel layer 12 to the drift layer 11. When a forward voltage is applied to the second gate 50, electrons accumulate on the sidewalls of the second branch 52. Furthermore, when the voltage applied to the second gate 50 is large enough, the sidewalls of the second gate 50 close to the polarization channel layer 13 and the inversion channel layer 12 on one side of the polarization channel layer 13 and the inversion channel layer begin to form electron accumulation, and finally form a conduction channel. As shown in Figure 6, the horizontal arrows represent the two-dimensional carrier gas channel formed below the HEMT device covered by the first gate 40, and the vertical arrows represent the two-dimensional carrier gas channel formed below the HEMT device covered by the first gate 40. When a sufficient voltage is applied to the second gate 50, electrons accumulate on the sidewalls of the second branch 52. When voltage is applied, a vertical conductive channel is formed beneath the HEMT device covered by the second gate 50. The two-dimensional carrier gas formed between the barrier layer 14 and the polarization channel layer 13 forms an electrical connection with the drift layer 11 through the channel formed by the second gate 50. The side of the drift layer 11 away from the polarization channel layer 13 and / or the inversion channel layer 12 is connected to the drain 30 of the HEMT device. Whether a conductive channel exists between the source 20 and drain 30 of the HEMT device is controlled by the state of the first gate 40. When the first gate 40 activates the two-dimensional carrier gas channel, the source 20 and drain 30 of the HEMT device are electrically connected through the two-dimensional carrier gas channel and the conductive channel formed by the second gate 50. The voltage drop from the drain 30 to the source 20 is primarily distributed in the portion where the second gate 50 extends deep into the drift layer 11 or in the portion where the inversion channel layer 12 and the second gate 50 extend deep into the drift layer 11.

[0057] In this embodiment, an operating voltage is applied to the second gate 50 before the device operates to pre-establish a conductive channel in the vertical direction of the HEMT device. The first gate 40 and a control signal applied thereto are then used to control the conduction or disconnection between the source 20 and drain 30 of the HEMT device. This not only preserves the excellent high-frequency response capability of the first gate 40 when controlling the conduction and disconnection of the two-dimensional carrier gas, thereby increasing the device's operating frequency while maintaining HEMT device performance, but also allows the second gate 50, located vertically, to direct current into the device interior, thereby achieving the goal of improving the HEMT device's withstand voltage by utilizing the materials of the multi-layered host material layer 10. Because the voltage applied to the second gate 50 is not limited by the driving voltage, an appropriate voltage can be applied as required to reduce the on-resistance of the vertical channel, thereby ensuring that the HEMT device structure of the present invention does not increase the overall on-resistance. Furthermore, the insulating layer 60 disposed outside the second branch 52 of the second gate 50 can also be made of a thicker insulating material (the thickness of the insulating layer 60 is not limited herein), which can effectively withstand the voltage of the drain 30 during the HEMT device's off period. When the HEMT device is not operating, no voltage is applied to the second gate 50. This prevents significant electric field stress from being generated between the second gate 50 and the first gate 40 due to the voltage difference. This avoids reliability issues such as dynamic resistance drift or current collapse caused by the voltage on the drain 30 in conventional HEMT devices. Furthermore, field plates can be added to the first gate 40 and / or the source 20 to further mitigate the impact of the voltage applied by the second gate 50 on the first gate 40. The first gate 40 field plate and the source 20 field plate are common structures in HEMT device fabrication and will not be described separately here.

[0058] In an optional embodiment of the present invention, please refer to Figure 7, which is another schematic diagram of a high-voltage HEMT device provided by an embodiment of the present invention, further comprising: at least one diffusion layer 17, the diffusion layer 17 being located in the drift layer 11, the diffusion layer 17 being located on a side of the second branch 52 facing away from the first branch 51, and the diffusion layer 17 being in contact with the insulating layer 60 outside the second branch 52.

[0059] Specifically, referring to FIG. 7 , in this embodiment, to further enhance HEMT device performance, a diffusion layer 17 is further provided in the HEMT device layer structure. Diffusion layer 17 is a heavily n-type doped diffusion layer 17. Diffusion layer 17 is located within the drift layer 11 and below the polarization channel layer 13 or the polarization channel layer 13 and the inversion channel layer 12. The insulating layer 60 outside the second branch 52 of the second gate 50 contacts the heavily n-type doped diffusion layer 17. It is understood that there is no inversion channel layer 12 below the diffusion layer 17. Carriers entering the drift layer 11 through the channel generated by the second gate 50 are further evenly distributed in the diffusion layer 17, which is more conducive to even current distribution in the HEMT device.

[0060] It should be noted that the embodiment shown in FIG. 7 only schematically illustrates the provision of one diffusion layer 17 and does not represent its actual size.

[0061] In an optional embodiment of the present invention, please refer to Figure 8, which is another schematic diagram of a high-voltage HEMT device provided by an embodiment of the present invention. The second gate 50 includes a first branch 51 and a second branch 52. The first branch 51 is located above the multi-layer main material layer 10, and an insulating layer is provided between the first branch 51 and the multi-layer main material layer. The second branch 52 extends from the surface of the multi-layer main material layer 10 to the inversion channel layer 12, and an insulating layer 60 is provided on the contact surface between the second branch 52 and the multi-layer main material layer 10.

[0062] In an optional embodiment of the present invention, an n-type region 19 is provided between the drift layer and the second branch. Along the first direction D1, a portion of the n-type region 19 passes through the inversion channel layer. One side of the n-type region 19 contacts the insulating layer outside the second branch, and the other side of the n-type region 19 contacts the drift layer.

[0063] Specifically, please continue to refer to Figure 8. In this embodiment, the second branch 52 of the second gate 50 extends to the inversion channel layer 12, and ions are implanted between the insulating layer 60 and the diffusion layer 17 on the outer side of the bottom of the second branch 52, that is, an n-type region 19 is formed between the two. It can be understood that in order to better disperse the electric field applied by the drain 30 of the HEMT device to the bottom of the second gate 50, the bottom of the second gate 50 is designed to be within the inversion channel layer 12. After etching the vertical channel when manufacturing the second gate 50, ions are implanted into the bottom of the channel to modify the inversion channel layer 12 at the bottom of the channel. The inversion channel layer 12 becomes the n-type region 19 (the inversion channel layer 12 becomes the N-type region 19). The n-type region 19 is in direct contact with the drift layer 11. At this time, after the insulating layer 60 and the gate metal of the second gate 50 are formed, a JFET structure in which the inversion channel layer surrounds the n-type material is formed at the bottom of the second gate 50. The inversion channel layer well wraps the front edge of the bottom of the second gate 50. At the same time, when the HEMT device is turned off, the voltage of the drain 30 acts on the n-type material surrounded by the inversion channel layer, forming a reverse pn junction with the inversion channel layer, further protecting the bottom of the second gate 50.

[0064] In this embodiment, after etching the multi-layer main material layer 10 to form a hole for the second gate 50, n-type GaN material is epitaxially grown for a second time, and then a portion of the n-type GaN material is etched away to retain the n-type GaN material at the bottom of the hole. Then, an insulating layer and a metal are deposited in the hole region to form the second gate. At this time, the n-type region at the bottom of the second gate is the retained n-type GaN material at the bottom of the hole.

[0065] In an optional embodiment of the present invention, referring to Figures 9 and 10, Figure 9 is another schematic diagram of a high-voltage HEMT device provided in an embodiment of the present invention, and Figure 10 is another schematic diagram of a high-voltage HEMT device provided in an embodiment of the present invention, the diffusion layer 17 includes multiple layers, all of which are located in the drift layer, and adjacent diffusion layers 17 are arranged at intervals. Among the multiple diffusion layers 17, the diffusion layer 17 adjacent to the second branch contacts the insulating layer outside the second branch. Alternatively, among the multiple diffusion layers 17, an n-type region 19 is provided between the diffusion layer 17 adjacent to the second branch and the second branch.

[0066] Specifically, please continue to refer to Figures 9 and 10. In this embodiment, the diffusion layer 17 can be a single layer of material or a stack of multiple parallel n-type heavily doped material layers. The multiple parallel n-type heavily doped material layers can better diffuse the current evenly and reduce the on-resistance of the device. When the n-type heavily doped diffusion layer 17 is a stack of multiple parallel n-type heavily doped material layers, the bottom of the second gate 50 needs to reach the diffusion layer 17 closest to the inversion channel layer 12 or the drift layer 11 above the diffusion layer 17, or the bottom of the second gate 50 is converted into an n-type material by the above-mentioned ion implantation in the inversion channel layer 12, and the n-type material is connected to the diffusion layer 17 closest to the inversion channel layer 12 or the drift layer 11 above the diffusion layer 17.

[0067] It should be noted that the embodiments shown in FIG. 9 and FIG. 10 only schematically illustrate the provision of three diffusion layers 17 . The number of diffusion layers 17 may also be other numbers, and the present invention is not limited thereto.

[0068] In an optional embodiment of the present invention, please refer to Figure 11, which is another schematic diagram of a high-voltage HEMT device provided by an embodiment of the present invention. The inversion channel layer 12 includes multiple layers, and adjacent inversion channel layers 12 are arranged at intervals; the second branch 52 extends through the multiple layers of inversion channel layers 12 to the drift layer 11; or, the second branch 52 extends through at least a portion of the inversion channel layer 12 to the inversion channel layer 12 adjacent to the drift layer 11.

[0069] Specifically, please continue to refer to Figure 11. In this embodiment, the inversion channel layer 12 can be a single layer of material or a stack of multiple parallel inversion channel layers. The stacking of multiple inversion channel layers further reduces the leakage of the device, improves the voltage resistance of the device, and enhances the reliability of the device. When the inversion channel layer 12 is a stacked structure of multiple parallel inversion channel layers, the bottom of the second gate 50 needs to pass through the last inversion channel layer 12 closest to the diffusion layer 17 and penetrate into the diffusion layer 17 or the drift layer 11, or the bottom of the second gate 50 is in the last inversion channel layer 12 closest to the diffusion layer 17, and the inversion channel layer 12 material covered by the bottom of the second gate 50 is converted into n-type material through the above-mentioned ion implantation method.

[0070] In an optional embodiment of the present invention, referring to FIG. 1 , the source electrode 20 is connected to the two-dimensional carrier gas channel and to the inversion channel layer 12 .

[0071] Specifically, please continue to refer to Figure 1. In this embodiment, in addition to forming an ohmic contact with the two-dimensional carrier gas channel, the source 20 electrode metal also forms an ohmic contact with the inversion channel layer 12. The source 20 electrode forms an ohmic contact with the two-dimensional carrier gas channel to reduce the contact resistance of the source 20, and forms an ohmic contact with the inversion channel layer 12 to provide the inversion channel layer 12 with a bias voltage from the source 20 to avoid the inversion channel layer 12 potential floating, which is more conducive to the conduction of the vertical channel and the shielding of the drain 30 voltage on the first gate 40. One way is to expose the inversion channel layer 12 material by mesa etching, and the source 20 metal simultaneously forms an ohmic contact with the two-dimensional carrier gas and the inversion channel layer 12 in a manner across the mesa.

[0072] In an optional embodiment of the present invention, the drift layer 11 is an n-type drift layer, and the n-type doping concentration in the n-type drift layer 11 remains unchanged.

[0073] In an optional embodiment of the present invention, the drift layer 11 is an n-type drift layer, and the n-type doping concentration in the n-type drift layer 11 changes gradually or continuously, that is, in the direction from the source 20 to the drain 30, the n-type doping concentration of the n-type drift layer 11 can be gradually increasing or decreasing.

[0074] In an optional embodiment of the present invention, the inversion channel layer 12, the diffusion layer 17 and the drift layer 11 include periodic stacks of semiconductor materials with different band gap widths; the inversion channel layer 12, the diffusion layer 17 and the drift layer 11 include at least one semiconductor material.

[0075] Specifically, in this embodiment, the inversion channel layer 12, the n-type heavily doped diffusion layer 17, and the drift layer 11 can be a single semiconductor material, or a periodic stack of multiple semiconductor materials with different bandgap widths. For example, they can be GaN materials, or two or more of GaN, AlGaN, InGaN, InAlGaN, etc. can be overlapped. The periodic stacking of semiconductor materials with different bandgap widths introduces multiple carrier barriers in the direction of voltage resistance of the multilayered main material layer 10 of the HEMT device, which helps further improve the withstand voltage and reduce leakage current. In particular, when the insulating layer 60 of the second gate 50 degrades, it can help reduce leakage current, thereby extending the service life of the device.

[0076] In an optional embodiment of the present invention, please refer to Figure 12, which is another schematic diagram of a high-voltage HEMT device provided by an embodiment of the present invention. In combination with Figure 1, along the first direction D1, the source 20 and the drain 30 are arranged on both sides of the multilayer main material, and the drain 30 is a surface state structure.

[0077] Specifically, please continue to refer to Figure 12 and Figure 1. In this embodiment, along the direction perpendicular to the multilayer main material, the source 20 and the drain 30 are located on both sides of the multilayer main material layer 10, and the drain 30 is arranged on one side of the drift layer 11 and is a planar structure.

[0078] It should be noted that the embodiment shown in FIG12 only schematically illustrates a position diagram of the first gate, the second gate and the source when the source and the drain are located on different sides.

[0079] In an optional embodiment of the present invention, referring to FIG. 13 and FIG. 14 , in combination with FIG. 2 , FIG. 13 is another top view of the high-voltage HEMT device provided in an embodiment of the present invention, and FIG. 14 is another top view of the high-voltage HEMT device provided in an embodiment of the present invention. Along a first direction D1, the source 20 and the drain 30 are disposed on the same side of the multilayer body material. The drain 30 is disposed adjacent to the source 20 and spaced apart. The drain 30 extends from the surface of the multilayer body material layer 10 to contact the n-type region 19.

[0080] Specifically, please continue to refer to Figures 13 and 14, and in combination with Figure 2, in this embodiment, the source 20 and the first gate 40 are on the same side but on different mesas 70, the mesas 70 between the source 20 and the drain 30 are isolated by an insulating medium, and the electric field distribution between the drain 30 and the first gate 40 will be shared by the source 20 and the second gate 50. Furthermore, in the structure with the inversion channel layer 12, it will be further shared by the inversion channel layer 12 that is in direct contact with the source 20, thereby forming good protection for the first gate 40 and ensuring the long-term reliability and stability of the first gate 40.

[0081] It should be noted that the short arrows in Figure 14 indicate that the current flows along the current channel in the first direction controlled by the first gate, that is, the two-dimensional carrier gas channel, and the long arrows indicate that the current flows along the current channel of the second gate, that is, the second direction, and then flows through the diffusion layer in a direction parallel to the first direction to the current channel between the drain.

[0082] In an optional embodiment of the present invention, please refer to Figures 15 and 16. Figure 15 is another schematic diagram of a high-voltage HEMT device provided in an embodiment of the present invention, and Figure 16 is another top view of the high-voltage HEMT device provided in an embodiment of the present invention. Figure 15 shows another embodiment in which the source 20 and the drain 30 are arranged on the same side of the multilayer host material along the first direction D1, and Figure 16 is a corresponding top view thereof.

[0083] In an optional embodiment of the present invention, using GaN as an example, the fabrication method for the high-voltage HEMT device proposed in this application is to grow a relatively thick drift layer 11 on a substrate. During the growth of the drift layer 11, several n-type heavily doped diffusion layers 17 are interposed. Then, an inversion channel layer 12 is grown on top of the drift layer 11, followed by a polarization channel layer 13. Alternatively, the polarization channel layer 13 is grown directly, a barrier layer 14 is grown on top of the polarization channel layer 13, and then a cap layer 15 is grown. If a pGaN gate is used, a p-type GaN layer needs to be grown. A deep hole is then etched in the material layer until it passes through all of the inversion channel layers 12 or stops in the inversion channel layer 12 farthest from the polarization channel layer 13. If the hole stops in the inversion channel layer 12 farthest from the polarization channel layer 13, a mask is used to shield the surface of the material layer outside the deep hole. Si is then implanted into the bottom of the deep hole by ion implantation, and annealing is performed to convert the inversion channel layer 12 at the bottom of the deep hole to n-type. The deep holes are then filled with insulating material.

[0084] In the case where the source 20 and drain 30 are located on both sides of the device body material, the mesa is etched until the inversion channel layer is exposed, and the source 20 metal is made in the exposed inversion channel layer area and the surface area of ​​the device material layer adjacent to the mesa to form an ohmic contact. The first gate 40 is made, including pGaN etching or groove etching and gate metal deposition. The metal of the second gate 50 needs to be filled on the insulating material in the deep hole. The hole space can be reserved when the insulating material is filled, or a hole can be completely filled and then a hole can be etched inside the insulating material. The metal of the second gate 50 can be filled separately or deposited simultaneously with the metal of the first gate 40. If the substrate at this time is a GaN homogeneous substrate, metal can be deposited on the side of the device material layer away from the source 20 and the first gate 40 after thinning the back side of the substrate to form the drain 30. If the substrate at this time is a heterogeneous substrate such as a Si or sapphire substrate, metal can be deposited on the side of the device material layer away from the source 20 and the first gate 40 to form the drain 30 after removing the substrate or etching the substrate material on the back side of the substrate until the drift layer 11 material is exposed.

[0085] In the case where the source 20 and drain 30 are located on the same side of the device body but on different mesas, the fabrication methods for the source 20, first gate 40, and second gate 50 are essentially the same. A mesa is etched on the side of the source 20 away from the first gate 40 until the diffusion layer 17 furthest from the polarization channel layer 13 is exposed. An insulating material is deposited to protect the mesa on the side near the source 20. Insulating material is then etched on the exposed surface of the diffusion layer 17 furthest from the polarization channel layer 13 to create a window for metal deposition. The drain 30 metal is then deposited and diffused to form an ohmic contact, completing the fabrication of the drain 30.

[0086] Based on the same inventive concept, the present invention further provides a method for driving a high-voltage HEMT device, which is used to drive the high-voltage HEMT device provided by the above embodiment of the present invention. For the embodiments of the high-voltage HEMT device, please refer to the above, and the repeated parts will not be repeated here. The driving method includes:

[0087] A first positive voltage is applied to the second gate 50, where the applied first positive voltage is greater than a first threshold, thereby opening the vertical conductive channel. The current conduction capability of the vertical conductive channel can be adjusted by adjusting the magnitude of the first positive voltage. The first gate 40 is controlled by an external drive signal. A second voltage is applied to the first gate 40. When the applied second voltage reaches a second threshold, the horizontal two-dimensional carrier gas channel under the first gate 40 is controlled to be turned on or off by the first gate 40. That is, after the second gate 50 opens the vertical conductive channel, the external drive signal applied to the first gate 40 controls the on / off of the high-voltage HEMT device.

[0088] When a positive voltage, a zero bias voltage, or a negative voltage is applied to the second gate 50, the applied positive voltage, zero bias voltage, or negative voltage is less than the first threshold value, the vertical channel turn-on condition is not met, and the first gate 40 controls the conduction or shutoff of the two-dimensional carrier gas conductive channel under the action of the external drive signal, but the high-voltage HEMT device as a whole is still in the off state.

[0089] Specifically, this embodiment provides a method for driving a high-voltage HEMT device. A two-dimensional carrier gas channel is provided below the HEMT device covered by the first gate 40, while no two-dimensional carrier gas channel is provided below the HEMT device covered by the second gate 50. When a sufficient voltage is applied to the second gate 50, a conductive channel is formed below the HEMT device covered by the second gate 50. At this point, the two-dimensional carrier gas channel and the conductive channel form an electrical connection. Thus, by applying an operating voltage to the second gate 50 before the device operates, a conductive channel in the device's vertical direction is established in advance. Then, by applying a control signal to the first gate 40 to control the conduction or disconnection between the source 20 and drain 30 of the HEMT device, the excellent high-frequency response capability of the first gate 40 when controlling the conduction and disconnection of the two-dimensional carrier gas can be retained. This improves the operating frequency of the HEMT device while maintaining its performance. Furthermore, the second gate 50 in the vertical direction of the device can be used to direct current into the HEMT device, thereby achieving the purpose of improving the device's withstand voltage by utilizing the multi-layer host material layer 10.

[0090] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high withstand voltage HEMT device, characterized in that: include: Multiple body material layers; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are stacked with the multi-layer main material layer; Along the first direction, the source electrode and the drain electrode are respectively located on both sides of the multi-layer main material layer; or, along the first direction, the source electrode and the drain electrode are located on the same side of the multi-layer main material layer, and the source electrode and the drain electrode are respectively located on different mesas; A first gate electrode, wherein the first gate electrode and the source electrode are located on the same side of the multi-layer main material layer and are stacked with the multi-layer main material layer; the first gate electrode and the source electrode are adjacently arranged; a second gate, wherein the second gate and the first gate are located on the same side of the multi-layer main material layer, the second gate is disposed adjacent to the first gate, and the first gate is located between the second gate and the source electrode; the second gate is embedded from the surface of the multi-layer main material layer into the interior of the multi-layer main material layer and extends along the first direction, and the second gate is used to control a vertical conductive channel along the first direction; The first direction is perpendicular to the multiple layers of host material.

2. The high withstand voltage HEMT device according to claim 1, characterized in that: The multilayer main material layer includes a drift layer, an inversion channel layer, a polarization channel layer, and a barrier layer stacked in sequence; the drain is located on the side of the drift layer away from the inversion channel layer, and the source is located on the side of the barrier layer away from the polarization channel layer; wherein a two-dimensional carrier gas conduction channel is formed between the polarization channel layer and the barrier layer, and the first gate is used to control the two-dimensional carrier gas conduction channel.

3. The high withstand voltage HEMT device according to claim 2, characterized in that: The multi-layer main material layer is grown layer by layer in sequence by epitaxy in the same epitaxial process.

4. The high withstand voltage HEMT device according to claim 2, characterized in that: The second gate includes a first branch and a second branch, the first branch is stacked with the multi-layer main material layer, the second branch extends from the surface of the multi-layer main material layer to the drift layer, and an insulating layer is provided on the contact surface between the second branch and the multi-layer main material layer.

5. The high withstand voltage HEMT device according to claim 4, characterized in that: Also includes: At least one diffusion layer is located in the drift layer, and the diffusion layer is located on a side of the second branch facing away from the first branch.

6. The high withstand voltage HEMT device according to claim 2, characterized in that: The second gate includes a first branch and a second branch, the first branch is located above the multi-layer main material layer, and an insulating layer is arranged between the first branch and the multi-layer main material layer, the second branch extends from the surface of the multi-layer main material layer to the inversion channel layer, and an insulating layer is arranged on the contact surface between the second branch and the multi-layer main material layer.

7. The high withstand voltage HEMT device according to claim 6, characterized in that: An n-type region is arranged between the drift layer and the second branch. Along the first direction, a portion of the n-type region passes through the inversion channel layer. One side of the n-type region contacts the insulating layer outside the second branch, and the other side of the n-type region contacts the drift layer.

8. The high withstand voltage HEMT device according to claim 5 or 7, characterized in that: The diffusion layer includes multiple layers, all of which are located in the drift layer, and adjacent diffusion layers are arranged at intervals; among the multiple diffusion layers, the diffusion layer adjacent to the second branch is in contact with the insulating layer outside the second branch; or, among the multiple diffusion layers, an n-type layer is arranged between the diffusion layer adjacent to the second branch and the second branch.

9. The high withstand voltage HEMT device according to claim 4, characterized in that: The inversion channel layer includes multiple layers, and adjacent inversion channel layers are arranged at intervals; the second branch extends through the multiple layers of the inversion channel layer to the drift layer; or, the second branch extends through at least a portion of the inversion channel layer to the inversion channel layer adjacent to the drift layer.

10. The high withstand voltage HEMT device according to claim 2, characterized in that: The source electrode is connected to the two-dimensional carrier gas channel and to the inversion channel layer.

11. The high withstand voltage HEMT device according to claim 1, characterized in that: Along a first direction, the source electrode and the drain electrode are arranged on two sides of the multi-layer main material, and the drain electrode is a planar structure.

12. The high withstand voltage HEMT device according to claim 1, characterized in that: Along the first direction, the source electrode and the drain electrode are arranged on the same side of the multi-layer main material, and the drain electrode is arranged on the diffusion layer exposed after the multi-layer main material layer is etched and contacts the diffusion layer.

13. A method for driving a high withstand voltage HEMT device, for driving the high withstand voltage HEMT device according to any one of claims 1 to 12, characterized in that: include: A first voltage is applied to the second gate, the applied first voltage is greater than a first threshold value, the vertical conductive channel is opened, and the current conduction capacity of the vertical conductive channel can be adjusted by adjusting the magnitude of the first voltage; the first gate is controlled by an external driving signal, a second voltage is applied to the first gate, and when the applied second voltage reaches a second threshold value, the horizontal two-dimensional carrier gas channel under the first gate is controlled to be turned on or off by the first gate, that is, after the second gate opens the vertical conductive channel, the external driving signal applied to the first gate controls the turning on and off of the high withstand voltage HEMT device; When a positive voltage, a zero bias voltage or a negative voltage is applied to the second gate, the applied positive voltage, zero bias voltage or negative voltage is less than the first threshold value, the vertical channel opening condition is not met, and the first gate controls the conduction or shutoff of the two-dimensional carrier gas conduction channel under the action of an external driving signal, but the high withstand voltage HEMT device as a whole is still in the off state.

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