Optical module access method, apparatus and system, electronic device, and nonvolatile readable storage medium

Abstract

The present application discloses an optical module access method, apparatus and system, an electronic device, and a nonvolatile readable storage medium, which are applied to the technical field of computers. The system comprises a central processing unit and an interface function extension structure comprising a plurality of programmable logic controllers, wherein the central processing unit is connected to a port of each programmable logic controller by means of a target bus. The central processing unit delivers an optical module access request to the interface function extension structure by means of the target bus. Each programmable logic controller is separately connected to a plurality of optical modules by means of a plurality of inter-integrated circuit buses, accesses a target optical module on the basis of an optical module address carried by the optical module access request, and performs information feedback to the central processing unit by means of interrupt multiplexing. The present application can solve the problem in the prior art of low efficiency of accessing the optical modules by means of the central processing unit, and realizes low-cost and efficient access to the optical modules.

Description

Optical module access method, device, system, electronic device and non-volatile readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 15, 2023, with application number 202311517868.4 and application name “Optical module access method, device, system, electronic device and readable storage medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to an optical module access method, device, system, electronic device, and non-volatile readable storage medium. Background Art

[0004] With the rapid development of data center services, the demand for data center switches, switch switching capacity, panel port data and port speed are also gradually increasing, which requires frequent access to optical modules.

[0005] Related technologies use the I2C (Inter-Integrated Circuit) interface of the CPU (Central Processing Unit) to access optical modules through a cascade of multiple external I2C expansion chips. However, the CPU's I2C interface is configured only for simple communications and does not handle complex I2C communications. Furthermore, the limited number of I2C interfaces results in low access efficiency for optical modules. Summary of the Invention

[0006] The present application provides an optical module access method, device, system, electronic device and non-volatile readable storage medium, which can achieve efficient access to optical modules.

[0007] To solve the above technical problems, this application provides the following technical solutions:

[0008] On the one hand, the present application provides an optical module access system, including a central processing unit and an interface function expansion structure;

[0009] The interface function expansion structure includes a plurality of programmable logic controllers, and the central processing unit is connected to the ports of each programmable logic controller via a target bus;

[0010] The central processing unit is configured to send the optical module access request to the interface function extension structure through the target bus;

[0011] The interface function expansion structure programmable logic controller is connected to multiple optical modules through multiple integrated circuit interconnection buses, namely I2C buses, and is configured to access the target optical module according to the optical module address carried by the optical module access request, and to provide information feedback to the central processing unit through interrupt multiplexing.

[0012] In a first exemplary embodiment, the programmable logic controller includes a bus slave interface module, an address allocation module, a register processing module, a communication control module, and an interrupt module;

[0013] The address allocation module is connected to the bus slave interface module, the register processing module, and the communication control module respectively; the interrupt module is connected to the central processing unit and the communication control module respectively;

[0014] The bus slave interface module is configured to parse the read and write commands of the target bus and convert the parsed read and write names into read and write commands in the target format; the address allocation module is configured to allocate addresses for the communication control module and the register processing module; the register processing module is configured to perform read and write processing on each register during the optical module access process; the communication control module is configured to control the timing during the optical module access process; the interrupt module is configured to report information to the central processing unit through interrupt multiplexing.

[0015] In a second exemplary embodiment, the communication control module includes a register interface, a byte control module, a bit control module, and a clock frequency division module;

[0016] The register interface is connected to the byte control module, the bit control module, and the clock frequency division module respectively; the byte control module is connected to the bit control module; the clock frequency division module is connected to the bit control module; and the bit control module is externally connected to the I2C bus;

[0017] The register interface is configured to complete the reading and writing of the register and the generation of interrupts during the access process of the optical module; the byte control module is configured to control the start bit command and stop bit command during the access process of the optical module, and split the data bit command and the response bit command; the bit control module is configured to complete the sending timing and receiving timing of each command; the clock division module is configured to divide the high-frequency clock into the target I2C clock signal and send it to the bit control module.

[0018] In a third exemplary embodiment, the byte control module is configured to complete the control of the start bit command and the stop bit command, and the splitting of the data bit command and the response bit command by controlling the state machine to be in different states.

[0019] In a fourth exemplary embodiment, the byte control module is further configured to:

[0020] When the current state of the state machine is not the idle state, if a stop bit command is received, it jumps to the stop bit state;

[0021] If a start bit command is received, it jumps into the start bit state and performs the corresponding byte operation until the target bit is operated, and jumps into the response bit state at the same time; if the response is completed, it jumps into the stop bit state; if the response is not completed, it jumps into the idle state.

[0022] In the fifth exemplary embodiment, the byte control module is configured to enter the read bit state when receiving the optical module information read command, and simultaneously count the total number of read bits; when it is detected that the current total number of read bits reaches the target bit, it jumps to the response bit state.

[0023] In the sixth exemplary embodiment, the byte control module is configured to enter the write bit state when receiving the optical module information write command, and simultaneously count the total number of written bits; when it is detected that the current total number of written bits reaches the target bit, it jumps to the response bit state.

[0024] In a seventh exemplary embodiment, the communication control module includes a plurality of control submodules; each control submodule is connected to the address allocation module and the interruption module respectively;

[0025] The control submodule is configured to access the corresponding optical module according to the optical module address carried in an optical module access request sent by the central processor, and provide information feedback to the central processor via interrupt multiplexing.

[0026] In an eighth exemplary implementation, the target bus is a reduced pin bus, ie, an LPC, and the bus slave interface module is configured to perform IO read and write functions on the reduced pin bus.

[0027] In a ninth exemplary embodiment, the interface function expansion structure is connected to each optical module via an integrated circuit interconnect expansion chip device, i.e., an I2C expansion chip device; two ends of the I2C expansion chip device are respectively connected to the interface function expansion structure and each optical module via an I2C bus;

[0028] The number of expansion channels in the I2C expansion chip device is determined based on the number of programmable logic controllers included in the interface function expansion structure and the total number of control submodules included in the communication control module, and each expansion channel uniquely corresponds to one control submodule.

[0029] In a tenth exemplary embodiment, the interface function extension structure includes a plurality of complex programmable logic devices;

[0030] One end of each complex programmable logic device is connected to the central processing unit through the target bus, and the other end is connected to the I2C expansion chip device through the I2C bus.

[0031] In an eleventh exemplary implementation, the interface function extension structure is further configured to send a bus abnormality signal to the central processing unit when an access abnormality is detected on the I2C bus connected to the destination optical module.

[0032] In a twelfth exemplary implementation, the central processing unit is further configured to send a write command and a stop command to the destination optical module, so that the destination optical module releases the I2C bus.

[0033] In a thirteenth exemplary implementation, the interface function extension structure is further configured to send a write command and a stop command to the destination optical module, so that the destination optical module releases the I2C bus.

[0034] In a fourteenth exemplary implementation, the interface function extension structure is further configured as follows:

[0035] When in an idle state, monitoring whether an interrupt signal exists and reporting the monitored interrupt signal to the central processing unit;

[0036] If an interrupt signal is detected, it jumps to the interrupt state; when in the interrupt state, it determines whether the current interrupt maintenance time exceeds the preset interrupt threshold;

[0037] If it is determined that the current interruption maintenance time exceeds the preset interruption threshold, the state is jumped to the idle state; if it is determined that the current interruption maintenance time does not exceed the preset interruption threshold, the state is jumped to the response state;

[0038] When in the response state, determine whether the current response time exceeds the preset response threshold;

[0039] If it is determined that the current response time exceeds the preset response threshold, the system jumps to the idle state; if it is determined that the current response time does not exceed the preset response threshold, the system jumps to the idle state after the response is completed.

[0040] On the other hand, the present application provides an optical module access method, which is applied to the optical module access system as described in any of the preceding items, comprising:

[0041] Receive optical module access request;

[0042] The target optical module is accessed according to the optical module address carried in the optical module access request, and information is reported in an interrupt multiplexing manner.

[0043] As an exemplary implementation, accessing the target optical module according to the optical module address carried in the optical module access request includes:

[0044] Determine a corresponding target expansion channel in the I2C expansion chip device based on the optical module address, and open the target expansion channel;

[0045] According to the optical module information acquisition protocol format determined by the I2C communication protocol, an optical module information reading command is sent, and after the optical module information reading is completed, the target extension channel is closed.

[0046] As another exemplary embodiment, the opening of the target extension channel includes:

[0047] Send start bit;

[0048] Send an I2C expansion chip device address write command and send a write data command to open the target expansion channel.

[0049] As another exemplary implementation, the sending of the optical module information reading command includes:

[0050] Send start bit;

[0051] Send the optical module address read command and the optical module register read command;

[0052] Send start bit;

[0053] Send the optical module register read command and the optical module data read command.

[0054] As another exemplary implementation, after the optical module information is read, closing the target extension channel includes:

[0055] When the optical module information is read, a stop bit command is sent;

[0056] Send start bit;

[0057] Send an I2C expansion chip device address write command and send a write data 0 command to close the target expansion channel.

[0058] As another exemplary embodiment, accessing the target optical module according to the optical module address carried in the optical module access request includes:

[0059] Determine a corresponding target expansion channel in the I2C expansion chip device based on the optical module address, and open the target expansion channel;

[0060] According to the optical module information acquisition protocol format determined by the I2C communication protocol, an optical module information writing command is sent, and after the optical module information writing is completed, the target expansion channel is closed.

[0061] As another exemplary implementation, the sending of the optical module information write command includes:

[0062] Send start bit;

[0063] Send optical module address read command and optical module register write command;

[0064] Send the optical module data write command.

[0065] In another aspect, the present application provides an optical module access device, which is applied to the optical module access system as described in any of the preceding items, comprising:

[0066] A request receiving module, configured to receive an optical module access request;

[0067] The optical module access module is configured to access the target optical module according to the optical module address carried in the optical module access request, and report information in an interrupt multiplexing manner.

[0068] The present application also provides an electronic device, comprising a processor, wherein the processor is configured to implement the steps of the optical module access method as described in any of the preceding items when executing a computer program stored in a memory.

[0069] Finally, the present application also provides a non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the optical module access method as described in any of the previous items are implemented.

[0070] The advantage of the technical solution provided by the present application is that, based on the original hardware, the optical module management interface is connected to the port of the interface function extension structure through the target bus, and the I2C expansion is realized by using the interface function extension structure. The software and hardware can be flexibly expanded according to the number of ports to achieve efficient optical module access; the overall hardware changes are relatively small, the hardware design topology is simple, and the logic multiplexing is good, which can effectively reduce the logic hardware development cost; the interrupt multiplexing method is used for data reporting, and the software resource occupancy can be reduced from the original 90% to less than 4%. Only minor adjustments are needed to the upper-level driver, which reduces the development complexity and design difficulty, reduces the development risk, and is conducive to improving the reliability of the system and effectively saving costs, thereby achieving low-cost and efficient access to the optical module.

[0071] In addition, the present application also provides corresponding implementation devices, systems, electronic devices and non-volatile readable storage media for the optical module access method, further making the method more practical, and the devices, systems, electronic devices and non-volatile readable storage media have corresponding advantages.

[0072] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0074] FIG1 is a schematic diagram of a structural framework of an optional implementation scheme of an optical module access system provided by the present application;

[0075] FIG2 is a schematic diagram of the structural framework of another optional implementation scheme of the optical module access system provided by the present application;

[0076] FIG3 is a schematic diagram of a structural framework of an optional implementation scheme of a communication control module provided in this application;

[0077] FIG4 is a schematic diagram of a state machine flow chart of a byte control module provided by the present application;

[0078] FIG5 is a schematic diagram of the interrupt multiplexing process of the interrupt module provided by the present application;

[0079] FIG6 is a schematic diagram of the structure of an optical module access system for an exemplary application scenario provided by the present application;

[0080] FIG7 is a flow chart of an optical module access method provided by the present application;

[0081] FIG8 is a structural diagram of an optional embodiment of the optical module access device provided by the present application;

[0082] FIG9 is a structural diagram of an optional implementation of the electronic device provided in this application. DETAILED DESCRIPTION

[0083] In order to make those skilled in the art better understand the technical solution of this application, the present application is further described in detail below in conjunction with the accompanying drawings and optional implementation methods. Obviously, the described embodiments are only part of the embodiments of this application, not all of them.

[0084] Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of this application. The terms "first", "second", "third", "fourth", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations of the two are intended to cover non-exclusive inclusions. The term "exemplary" means "used as an example, embodiment or illustrative". Any embodiment described here as "exemplary" is not necessarily to be interpreted as being superior or better than other embodiments.

[0085] At present, the way for data centers to obtain port status information is to use a baseboard management controller with more I2C ports to manage optical modules or to use the CPU's I2C port to plug in a multi-stage I2C expansion chip to achieve optical module access. However, for clients without BMC (Baseboard Management Controller, baseboard management controller) requirements, optical module management can only be placed on the CPU side, and the CPU's I2C interface is limited and is only set to simple communication, not processing complex I2C communication. Related technologies often use multi-stage I2C expansion chip cascades or use dedicated chips to achieve optical module management, which is not only inefficient but also costly. Based on the original hardware, the present application connects the optical module management interface to the port of the interface function extension structure through the target bus, and utilizes the interface function extension structure to achieve I2C expansion. It is possible to flexibly perform software and hardware expansion according to the number of ports, achieving low-cost and efficient optical module access. Various non-limiting embodiments of the present application are described in detail below. In order to better illustrate the present application, numerous details are provided in the optional implementation below. Those skilled in the art should understand that without these details, the present application can also be implemented. In some other instances, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present application.

[0086] First, please refer to FIG1 , which is a schematic diagram of the structural framework of an optical module access system provided by the present application under an optional embodiment. The present application may include the following contents:

[0087] The optical module access system may include a central processing unit 1 and an interface function extension structure 2, the interface function extension structure 2 includes multiple programmable logic controllers 20, and the central processing unit 1 is connected to the ports of each programmable logic controller through a target bus 3. Among them, the target bus 3 can be any bus that can connect the central processing unit 1 and each programmable logic controller, such as an eSPI (Enhanced Serial Peripheral Interface) bus, an LPC (Low Pin Count Bus), and this application does not impose any restrictions on this. In order to achieve low-cost access to the optical module, the target bus of this embodiment can be a reduced pin bus LPC. The total number of programmable logic controllers 20 included in the interface function extension structure 2 can be determined based on the total number of optical modules in the actual application scenario and the system hardware and software performance. The programmable logic controller 20 can be any hardware that can be programmed. In order to achieve low-cost access to the optical module, the programmable logic controller 20 of this embodiment can be a CPLD (Complex Programmable Logic Device). For example, a programmable logic device based on CMOS (Complementary Metal Oxide Semiconductor) technology and field programmable flash memory technology, such as the XC9536XL-10PCG44C chip (chip model), can be used. Technicians in the relevant field can flexibly select according to actual conditions. One end of each complex programmable logic device is connected to the central processing unit 1 through the target bus 3, and the other end is connected to the I2C expansion chip device through the I2C bus. The I2C expansion chip device can divide the I2C bus into multiple sub-buses, and each sub-bus can support multiple I2C devices. That is, the interface function extension structure 2 can be connected to multiple optical modules through the I2C expansion chip device, thereby achieving access to the optical module.

[0088] In this embodiment, the central processing unit 1 is configured to send an optical module access request to the interface function extension structure 2 via a target bus. The optical module access request includes an optical module information query or acquisition request, and may also include an optical module information write request. The central processing unit 1 receives the optical module access request from the upper-layer software or the client and sends the optical module access request to the interface function extension structure 2 for processing. Each programmable logic controller 20 of the interface function extension structure 2 is connected to multiple optical modules via optical ports via multiple I2C (Inter-Integrated Circuit) buses. The optical ports are interfaces for transmitting optical signals, including but not limited to SFP (Small Form-factor Pluggable) and QSFP (Quad Small Form-factor Pluggable). The optical ports are configured to access the target optical module based on the I2C communication protocol according to the optical module address carried in the optical module access request, and provide information feedback to the central processing unit 1 via interrupt multiplexing. The information feedback may include reporting fault information and processing progress information of the optical module access request to the central processing unit.

[0089] In the technical solution provided in this application, on the basis of the original hardware, the optical module management interface is connected to the port of the interface function extension structure through the target bus, and the interface function extension structure is used to realize I2C expansion. The software and hardware can be flexibly expanded according to the number of ports to achieve efficient optical module access; the overall hardware changes are small, the hardware design topology is simple, and the logic multiplexing is good, which can effectively reduce the logic hardware development cost; the interrupt multiplexing method is used for data reporting, and the software resource occupancy can be reduced from the original 90% to less than 4%. Only minor adjustments are needed to the upper-level driver, which reduces the development complexity and design difficulty, reduces the development risk, and is conducive to improving the reliability of the system and effectively saving costs, thereby achieving low-cost and efficient access to the optical module.

[0090] The above embodiment does not impose any limitation on the internal structure of each programmable logic controller 20 of the interface function extension structure 2. Based on this, the present application also provides an optional implementation, as shown in FIG2 , which may include the following contents:

[0091] In this embodiment, the programmable logic controller 20 includes a bus slave interface module 201, an address allocation module 202, a register processing module 203, a communication control module 204, and an interrupt module 205. The bus slave interface module 201, address allocation module 202, register processing module 203, communication control module 204, and interrupt module 205 are all program modules that implement specific functions within the programmable logic controller 20. Specifically, the bus slave interface module 201, address allocation module 202, register processing module 203, communication control module 204, and interrupt module 205 are a series of computer program instruction segments that can perform specific functions. In terms of data interaction or data flow, one end of the address allocation module 202 is connected to the bus slave interface module 201, and the other end is connected to the register processing module 203 and the communication control module 204, respectively. The interrupt module 205 is also connected to the central processing unit and the communication control module 204, respectively.

[0092] Among them, the bus slave interface module 201 is configured to read and write to the target bus 3. It is configured to parse the read and write commands of the target bus and convert the read and write naming obtained by the parsing into read and write commands in the target format. According to the current read and write requirements, data is exchanged with the corresponding register. That is, the bus slave interface module 201 matches the target bus 3. The target bus 3 is LPC. The bus slave interface module 201 is an LPC slave interface module and is configured to complete the IO read and write functions of the LPC bus. The address allocation module 202 is configured to allocate addresses for the communication control module 204 and the register processing module 203. That is, it allocates addresses to the registers and communication control module 204 involved in the optical module access process. The register processing module 203 is configured to read and write each register in the optical module access process, such as reading and writing the interrupt register, reset register, test register, etc. The communication control module 204 is configured to control the timing in the optical module access process based on the I2C communication protocol, such as completing the start bit, data bit and stop bit timing control specified in the I2C communication protocol. The interrupt module 205 is configured to report information to the central processing unit through interrupt multiplexing, which completes the communication control module 204. If the communication control module 204 has multiple branches that control the timing of the optical module access process based on the I2C communication protocol, it can complete the reporting of the interrupt signal of each branch and the interrupt timeout processing.

[0093] As can be seen from the above, this embodiment completes the entire process from receiving an optical module access request to accessing the optical module through the bus from the interface module, address allocation module, register processing module, communication control module and interrupt module, which are program modules that implement specific functions. It is simple and easy to implement, which is conducive to reducing costs and achieving low-cost access to the optical module.

[0094] The above embodiment is based on the I2C communication protocol to control the timing of the optical module access process and is not limited in any way. Based on the above embodiment, the present application also provides another embodiment, refer to Figure 3, which may include the following content:

[0095] The communication control module 204 may include a register interface, a byte control module, a bit control module, and a clock divider module. The register interface, byte control module, bit control module, and clock divider module are all program modules that implement specific functions within the programmable logic controller 20, that is, the register interface, byte control module, bit control module, and clock divider module are a series of computer program instruction segments that can complete specific functions. In terms of data interaction or data flow, one end of the register interface is connected to the address allocation module, and the other end is connected to the byte control module, bit control module, and clock divider module respectively; the byte control module is connected to the bit control module; the clock divider module is connected to the bit control module to transmit a clock signal to the bit control module; the bit control module is externally connected to the I2C bus, that is, connected to the SCL (Serial Clock line) and SDA (Serial Data) signal line.

[0096] Among them, the register interface is configured to complete the reading and writing of registers and the generation of interrupts involved in the optical module access process. The byte control module is configured to control the start bit command and stop bit command in the optical module access process, and to split the data bit command and the response bit command. The bit control module is configured to complete the sending timing and receiving timing of each command, such as completing the optional sending and receiving timing of the start bit, data bit and stop bit. The clock divider module is configured to divide the high-frequency clock into the target I2C clock signal. The target I2C clock signal is the frequency of the clock signal required by the current I2C communication protocol, such as completing the high-frequency clock to 100KHz, 400KHz, etc. I2C transmission clock generation, and sending it to the bit control module.

[0097] As an optional implementation, the byte control module may be configured to control the start bit command and the stop bit command, and split the data bit command and the response bit command by controlling the state machine to be in different states.

[0098] Exemplarily, the state machine may include an idle state, a start bit state, a stop bit state, and a response bit state. When the current state of the state machine is not the idle state, that is, when the state machine jumps from the idle state to another state, if a stop bit command is received, the state machine jumps to the stop bit state; if a start bit command is received, the state machine jumps to the start bit state and performs the corresponding byte operation until the target bit is operated, and then jumps to the response bit state; if the response is completed, the state machine jumps to the stop bit state and enters the idle state through the stop bit state; if the response is not completed, the state machine directly jumps to the idle state.

[0099] Furthermore, bit operations may include bit read operations and bit write operations. Accordingly, the state machine may also include a read bit state for reading sub-nodes and a write bit state for writing bytes. The byte control module is further configured to enter the read bit state upon receiving an optical module information read command, while simultaneously counting the total number of read bits; and jump to the response bit state upon detecting that the current total number of read bits reaches a target bit. Upon receiving an optical module information write command, the module enters the write bit state while simultaneously counting the total number of written bits; and jump to the response bit state upon detecting that the current total number of written bits reaches a target bit. The target bit is determined based on the number of command bits. As shown in FIG4 , the byte control module completes the 9-bit command splitting of the data bit and the response bit, and the target bit is 8. bit_cnt represents the bit count, meaning that a read byte will execute 8 read bits and then jump to the response bit; a write byte will execute 8 write bits and then jump to the response bit.

[0100] Based on the structure of the communication control module, the process of sending the optical module information reading instruction under the central processing unit to the communication control module is as follows: sending instructions to the byte control module through the register interface, first sending the start bit, then sending the I2C expansion chip device address write command, sending the write data command, and setting the 8-bit (bit) data corresponding channel bit to 1, thereby opening the channel corresponding to the I2C expansion chip device connected to the optical module to be accessed; then, according to the protocol format requirements for obtaining the optical module information, sending the start bit, optical module address read command, optical module register read command, start bit, optical module register read command, data read command, and sending the stop bit command after the reading is completed; finally, sending the start bit, I2C expansion chip device address write command, and write data 0 command to close the channel. The process of sending the optical module information write instruction from the central processing unit to the communication control module is as follows: sending instructions to the byte control module through the register interface, first sending the start bit, then sending the I2C expansion chip device address write command, sending the write data command, and setting the 8-bit data corresponding channel bit to 1, thereby opening the channel corresponding to the I2C expansion chip device connected to the optical module to be accessed; then, according to the protocol format requirements of the optical module information acquisition, sending the start bit, optical module address read command, optical module register write command, write data command, and stop bit command; finally, sending the start bit, I2C expansion chip device address write command, and write data 0 command to close the channel.

[0101] As can be seen from the above, in this embodiment, the communication control module controls the timing during the I2C communication process to achieve access to the optical module.

[0102] To further enhance the practicality of the optical module access system, achieve large-scale I2C port expansion, support access to more optical modules, and thus enable management of a large number of optical modules, based on the above embodiment, the communication control module 204 may include multiple control submodules; each control submodule is connected to the address allocation module 202 and the interrupt module 205. Each control submodule is configured to access the corresponding optical module based on the I2C communication protocol according to the optical module address carried in an optical module access request issued by the central processor, and provide information feedback to the central processor via interrupt multiplexing.

[0103] In this embodiment, the interface function expansion structure may include multiple programmable logic devices, each programmable logic device includes a communication control module, and a communication control module 204 may have multiple branches inside to simultaneously process optical module access requests, so that access to and management of a large number of optical modules can be achieved simultaneously.

[0104] It is understood that the interface function expansion structure 2 and the optical port require a device that divides the I2C bus into multiple sub-buses, each of which is connected to a corresponding optical port, thereby expanding sufficient interfaces on the limited I2C resources. In this embodiment, an I2C expansion chip device can be used to connect the interface function expansion structure 2 and the optical port. The two ends of the I2C expansion chip device are connected to the interface function expansion structure and each optical port via the I2C bus, and then connected to the optical module. The number of expansion channels in the I2C expansion chip device is determined by the number of programmable logic controllers 20 included in the interface function expansion structure 2 and the total number of control submodules included in the communication control module 204, and each expansion channel uniquely corresponds to a control submodule. For example, the I2C expansion chip device can be a set of I2C switch chips, such as a set of Pca954x (model) series chips. The Pca954x has only one control register internally and is a device without subaddresses. When performing I / O access, a write operation to address 0x00 is sufficient. This enables I2C bus routing for devices connected to the Pca954x. The Pca9548 can implement eight switches, adding eight I2C expansion channels. Of course, in some application scenarios, an external I2C expansion chip device can be used to access optical modules without using an external I2C expansion chip device. Instead, a high-capacity CPLD device can be used to replace the I2C expansion chip device to complete I2C expansion of all optical modules. Those skilled in the art can flexibly choose this option based on actual circumstances, and this does not affect the implementation of this embodiment.

[0105] Inevitably, various faults may occur when the system accesses the optical module. To improve the reliability and stability of the system, based on the above embodiment, this application also provides an exemplary fault handling method, which may include the following:

[0106] The interface function extension structure 2 is further configured to send a bus anomaly signal to the central processing unit upon detecting an access anomaly to the I2C bus of the destination optical module connected to the target optical port. Upon a bus anomaly, the central processing unit can directly send a write command and a stop command to the destination optical module connected to the target optical port to cause the destination optical module to release the I2C bus. Of course, after notifying the central processing unit of the bus access anomaly, the interface function extension structure can also send a write command and a stop command to the destination optical module connected to the target optical port to cause the destination optical module to release the I2C bus.

[0107] In this embodiment, when a bus access anomaly is detected, the central processing unit and the interface function extension structure 2 can both send a write command and a stop command to cause the slave device to release the bus, thereby realizing the recovery function after the I2C communication protocol is hung.

[0108] In order to further improve system performance and reduce resource usage caused by round-robin training, based on the above embodiment, the interrupt multiplexing process of the interface function extension structure 2, that is, the data processing process of the interrupt module, may include the following contents:

[0109] When in the idle state, monitor whether there is an interrupt signal and report the interrupt signal to the central processing unit; if an interrupt signal is detected, jump to the interrupt state; when in the interrupt state, determine whether the current interrupt maintenance time exceeds the preset interrupt threshold; if it is determined that the current interrupt maintenance time exceeds the preset interrupt threshold, jump to the idle state; if it is determined that the current interrupt maintenance time does not exceed the preset interrupt threshold, jump to the response state; when in the response state, determine whether the current response time exceeds the preset response threshold; if it is determined that the current response time exceeds the preset response threshold, jump to the idle state; if it is determined that the current response time does not exceed the preset response threshold, jump to the idle state after the response is completed.

[0110] As shown in Figure 5, the interrupt multiplexing process includes three states: idle state, interrupt state, and response state. The idle state completes the interrupt signal detection of the communication control module and each control submodule within it. After detecting the interrupt signal, the state jumps to the interrupt state. When the interrupt state is completed, when an interrupt timeout is detected, it jumps to the idle state. After the interrupt response, the interrupt signal state is cleared and the state jumps to the response state. When the response state is completed, when a timeout is detected, it jumps to the idle state. After the state response is completed, the state jumps to the idle state and the interrupt detection and reporting functions are enabled again.

[0111] In order to make the technical personnel in the relevant field more clearly understand the technical solution of the present application, the present application also provides an exemplary embodiment. The structure of the optical module access system of this embodiment is shown in Figure 6. For example, it can be applied to the access of optical modules in the switch field or the communication field. The programmable logic controller of this embodiment is CPLD, and the target bus is LPC bus, so that the LPC parallel interface bus on the existing hardware is used to implement I2C port expansion, thereby realizing optical module management. This embodiment only needs to connect the LPC bus to the port management CPLD on the basis of the original hardware, and the CPLD logic completes the I2C expansion, and the external I2C expansion chip is used to complete the optical module access. The entire system can be implemented based on the Lattice Machxo3LF 6900C (product model) chip, and the design language adopts Verilog language. This embodiment may include the following contents:

[0112] The optical module access system includes a central processing unit and an interface function expansion structure. The interface function expansion structure includes two CPLDs. The central processing unit is connected to the ports of the first CPLD and the second CPLD via the LPC bus. The first CPLD and the second CPLD provide an I2C bus to connect to a group of Pca9548 chips. The group of Pca9548 chips of the first CPLD includes Pca9548-1, Pca9548-2, Pca9548-3, and Pca9548-4. The group of Pca9548 chips of the second CPLD includes Pca9548-5, Pca9548-6, Pca9548-7, and Pca9548-8. Each Pca9548 It is connected to eight SFP optical module interfaces or four QSFP optical module interfaces. For example, Pca9548-1 is connected to SFP through the I2C bus, Pca9548-2 is connected to SFP through the I2C bus, Pca9548-3 is connected to SFP through the I2C bus, Pca9548-4 is connected to QSFP through the I2C bus, Pca9548-5 is connected to SFP through the I2C bus, Pca9548-6 is connected to SFP through the I2C bus, Pca9548-7 is connected to SFP through the I2C bus, and Pca9548-8 is connected to QSFP through the I2C bus.

[0113] In this embodiment, the central processing unit (CPU) sends an optical module access request to the corresponding CPLD via the LPC bus. The CPLD's LPC receives the optical module access request from an interface. The CPLD may include an address allocation module, a communication control module, a register processing module, and an interrupt module. The communication control module includes four control submodules: the first CPLD includes control submodule 1, control submodule 2, control submodule 3, and control submodule 4; the second CPLD includes control submodule 5, control submodule 6, control submodule 7, and control submodule 8. The address allocation module receives the optical module access request from the interface based on the LPC bus. Based on the control submodules included in the communication control module and the registers involved in the optical module access process, it assigns addresses to each control submodule and register. The communication control module controls the timing of the optical module access process based on the I2C communication protocol. During the entire optical module access process, the register processing module is used to read and write interrupt registers, reset registers, and test registers. The interrupt module monitors the interrupt signal of each control submodule and, through interrupt multiplexing, reports the interrupt to the CPU and handles interrupt timeouts.

[0114] As can be seen from the above, the CPLD in this embodiment connects the optical module management interface to the port management CPLD based on the existing hardware. The port management CPLD implements I2C interface function expansion based on the existing LPC management bus, thereby providing a unified interface for upper-layer software, which then drives the optical module management through LPC. This design is flexible, with minimal hardware changes, good logic reusability, and low development costs. It also facilitates unified software processing and reduces software processing complexity, thereby reducing development difficulty and risk, lowering operating costs, and achieving low-cost and efficient optical module access.

[0115] Based on the above embodiments, the present application further provides an optical module access method that can be applied to any of the previous embodiments. Please refer to Figure 7, which is a flow chart of an optical module access method provided by the present application. The present application may include the following contents:

[0116] S701: Receive an optical module access request.

[0117] S702: Access the target optical module according to the optical module address carried in the optical module access request, and report information through interrupt multiplexing.

[0118] As an exemplary implementation of this embodiment, if the optical module access request is an optical module information read request, the implementation of S701 of the above embodiment of "accessing the target optical module according to the optical module address carried in the optical module access request" may include the following content:

[0119] The corresponding target expansion channel in the I2C expansion chip device is determined based on the optical module address, and the target expansion channel is opened; the optical module information acquisition protocol format determined by the I2C communication protocol is used to send an optical module information reading command, and after the optical module information reading is completed, the target expansion channel is closed.

[0120] Among them, the target extension channel is the path of the optical module for which the optical module access request wants to read data. As an optional implementation of the above embodiment, the target extension channel can be opened by first sending a start bit, then sending an I2C expansion chip device address write command, and then sending a write data command to open the target extension channel.

[0121] After the target expansion channel is opened, the required optical module information can be read. As an optional implementation of the above embodiment, the process of sending the optical module information read command may include: first sending a start bit, then sending an optical module address read command and an optical module register read command; sending a start bit; sending an optical module register read command and an optical module data read command. During the process of reading the optical module information, the completion of the read operation is detected in real time. When the optical module information reading is completed, a stop bit command is sent. When the optical module information reading is completed, in order to avoid affecting subsequent access to the optical module, the target expansion channel must be closed. As an optional implementation of the above embodiment, the target expansion channel can be closed by first sending a start bit; then sending an I2C expansion chip device address write command, and then sending a write data 0 command, thereby closing the target expansion channel.

[0122] As another exemplary implementation of this embodiment, if the optical module access request is a request to write optical module information, the implementation of S701 of the above embodiment of "accessing the target optical module according to the optical module address carried in the optical module access request" may include the following:

[0123] The corresponding target expansion channel in the I2C expansion chip device is determined based on the optical module address, and the target expansion channel is opened; the optical module information acquisition protocol format determined by the I2C communication protocol is used, an optical module information write command is sent, and after the optical module information writing is completed, the target expansion channel is closed.

[0124] Among them, the target extension channel is the path of the optical module to which the optical module access request is to write data. As an optional implementation of the above embodiment, the target extension channel can be opened by first sending a start bit, then sending an I2C expansion chip device address write command, and then sending a write data command to open the target extension channel.

[0125] After the target expansion channel is opened, the required optical module information can be written into the optical module. As an optional implementation of the above embodiment, the process of sending the optical module information write command may include: first sending a start bit, then sending an optical module address read command and an optical module register write command; sending an optical module data write command, and during the process of writing information to the optical module, real-time detection of whether the data write operation is complete. When the optical module information has been written, a stop bit command is sent. When all optical module data has been written, in order to avoid affecting subsequent access to the optical module, the target expansion channel must be closed. As an optional implementation of the above embodiment, the target expansion channel can be closed by: first sending a start bit; then sending an I2C expansion chip device address write command, and then sending a write data 0 command, thereby closing the target expansion channel.

[0126] The implementation process of the optical module access method in this embodiment can be implemented according to the contents recorded in the above system embodiment. Its optional implementation process can refer to the relevant description of the above system embodiment, which will not be repeated here.

[0127] As can be seen from the above, this embodiment achieves low-cost and efficient access to the optical module. It should be noted that there is no strict order of execution between the steps in this application. As long as they comply with the logical order, these steps can be executed simultaneously or in a certain preset order. Figure 7 is only a schematic method and does not mean that this is the only execution order.

[0128] The present application also provides a corresponding device for the optical module access method, which further makes the method more practical. Among them, the device can be described from the perspective of functional modules and hardware. The optical module access device provided by the present application is introduced below. The device is used to implement the optical module access method provided by the present application. In this embodiment, the optical module access device may include or be divided into one or more program modules, and the one or more program modules are stored in a non-volatile readable storage medium and executed by one or more processors to complete the optical module access method disclosed in Example 1. The program module referred to in this application refers to a series of computer program instruction segments that can complete specific functions, which is more suitable for describing the execution process of the optical module access device in a non-volatile readable storage medium than the program itself. The following description will introduce the functions of each program module in this embodiment. The optical module access device described below and the optical module access method described above can be referenced to each other.

[0129] From the perspective of functional modules, see FIG8 , which is a structural diagram of an optical module access device provided by the present application under an optional implementation manner, applied to the optical module access system described in any of the previous embodiments, and the device may include:

[0130] The request receiving module 801 is configured to receive an optical module access request;

[0131] The optical module access module 802 is configured to access the target optical module according to the optical module address carried in the optical module access request, and report information in an interrupt multiplexing manner.

[0132] For example, in some implementations of this embodiment, the optical module access module 802 may also be configured as follows:

[0133] The corresponding target expansion channel in the I2C expansion chip device is determined based on the optical module address, and the target expansion channel is opened; the optical module information acquisition protocol format determined by the I2C communication protocol is used to send an optical module information reading command, and after the optical module information reading is completed, the target expansion channel is closed.

[0134] As an optional implementation of the above embodiment, the optical module access module 802 may be further configured to: send a start bit; send an I2C expansion chip device address write command, and send a write data command to open a target expansion channel.

[0135] As another optional implementation of the above embodiment, the above optical module access module 802 can be further configured to: send a start bit; send an optical module address read command and an optical module register read command; send a start bit; send an optical module register read command and an optical module data read command.

[0136] As another optional implementation of the above embodiment, the above optical module access module 802 can be further configured to: when the optical module information is read, send a stop bit command; send a start bit; send an I2C expansion chip device address write command, and send a write data 0 command to close the target expansion channel.

[0137] For example, in some other implementations of this embodiment, the optical module access module 802 may be further configured to:

[0138] The corresponding target expansion channel in the I2C expansion chip device is determined based on the optical module address, and the target expansion channel is opened; the optical module information acquisition protocol format determined by the I2C communication protocol is used, an optical module information write command is sent, and after the optical module information writing is completed, the target expansion channel is closed.

[0139] As an optional implementation of the above embodiment, the above optical module access module 802 can be further configured to: send a start bit; send an optical module address read command and an optical module register write command; and send an optical module data write command.

[0140] The functions of the functional modules of the optical module access device of the present application can be optionally implemented according to the method in the above method embodiment. The optional implementation process can refer to the relevant description of the above method embodiment and will not be repeated here.

[0141] As can be seen from the above, this embodiment can achieve low-cost and efficient access to the optical module.

[0142] The optical module access device mentioned above is described from the perspective of a functional module. Furthermore, this application also provides an electronic device, which is described from a hardware perspective. Figure 9 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application under one embodiment. As shown in Figure 9, the electronic device includes a memory 90, which is configured to store a computer program; and a processor 91, which is configured to implement the steps of the optical module access method mentioned in any of the above embodiments when executing the computer program.

[0143] The processor 91 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 91 may also be a controller, microcontroller, microprocessor, or other data processing chip. The processor 91 may be implemented in at least one hardware form: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). The processor 91 may also include a main processor and a coprocessor. The main processor is a processor configured to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor configured to process data in the standby state. In some embodiments, the processor 91 may be integrated with a GPU (Graphics Processing Unit), which is configured to render and draw the content required to be displayed on the display screen. In some embodiments, the processor 91 may also include an AI (Artificial Intelligence) processor, which is configured to handle computing operations related to machine learning.

[0144] The memory 90 may include one or more computer non-volatile readable storage media, which may be non-transitory. The memory 90 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the memory 90 may be an internal storage unit of an electronic device, such as a hard disk of a server. In other embodiments, the memory 90 may also be an external storage device of an electronic device, such as a plug-in hard disk equipped on a server, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card, etc. Furthermore, the memory 90 may also include both an internal storage unit of an electronic device and an external storage device. The memory 90 may be configured not only to store application software installed in the electronic device and various types of data, such as the code of the program in the process of executing the optical module access method, but may also be configured to temporarily store data that has been output or is to be output. In this embodiment, the memory 90 is at least configured to store the following computer program 901, wherein, after the computer program is loaded and executed by the processor 91, it can implement the relevant steps of the optical module access method disclosed in any of the aforementioned embodiments. In addition, the resources stored in memory 90 may also include an operating system 902 and data 903, which may be stored in a temporary or permanent manner. Operating system 902 may include Windows, Unix, Linux, etc. Data 903 may include, but is not limited to, data corresponding to the optical module access result.

[0145] In some embodiments, the electronic device may further include a display screen 92, an input / output interface 93, a communication interface 94 or a network interface, a power supply 95, and a communication bus 96. The display screen 92 and the input / output interface 93, such as a keyboard, are user interfaces. Optional user interfaces may also include standard wired interfaces, wireless interfaces, and the like. In some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touchscreen, and the like. The display may also be appropriately referred to as a display screen or display unit, and is configured to display information processed in the electronic device and to display a visual user interface. The communication interface 94 may optionally include a wired interface and / or a wireless interface, such as a Wi-Fi interface or a Bluetooth interface, and is typically configured to establish a communication connection between the electronic device and other electronic devices. The communication bus 96 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. This bus may be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, FIG9 shows only one thick line, but this does not mean that there is only one bus or one type of bus.

[0146] Those skilled in the art will appreciate that the structure shown in FIG. 9 does not limit the electronic device and may include more or fewer components than shown in the figure, for example, may also include a sensor 97 for implementing various functions.

[0147] The functions of each functional module of the electronic device of the present application can be optionally implemented according to the method in the above method embodiment. The optional implementation process can refer to the relevant description of the above method embodiment and will not be repeated here.

[0148] As can be seen from the above, this embodiment can achieve low-cost and efficient access to the optical module.

[0149] It is understandable that if the optical module access method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer non-volatile readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the relevant technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a non-volatile readable storage medium to execute all or part of the steps of the various embodiments of the present application. The aforementioned non-volatile readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various non-volatile readable storage media that can store program code.

[0150] Based on this, the present application also provides a non-volatile readable storage medium storing a computer program. When the computer program is executed by a processor, the steps of the optical module access method in any of the above embodiments are performed.

[0151] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. References to the same or similar parts between the various embodiments are sufficient. The hardware disclosed in the embodiments, including devices and electronic devices, is described briefly because it corresponds to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0152] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0153] The above is a detailed introduction to an optical module access method, device, system, electronic device and non-volatile readable storage medium provided by the present application. Optional examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. An optical module access system, characterized in that: Including central processing unit and interface function expansion structure; The interface function expansion structure includes a plurality of programmable logic controllers, and the central processing unit is connected to the ports of each programmable logic controller via a target bus; The central processor is configured to send the optical module access request to the interface function extension structure through the target bus; The programmable logic controller of the interface function expansion structure is connected to multiple optical modules through multiple integrated circuit interconnection buses, and is configured to access the target optical module according to the optical module address carried by the optical module access request, and provide information feedback to the central processor through interrupt multiplexing.

2. The optical module access system according to claim 1, characterized in that: The programmable logic controller includes a bus slave interface module, an address allocation module, a register processing module, a communication control module and an interrupt module; The address allocation module is connected to the bus slave interface module, the register processing module, and the communication control module respectively; the interrupt module is connected to the central processing unit and the communication control module respectively; The bus slave interface module is configured to parse the read and write commands of the target bus and convert the parsed read and write commands into read and write commands in the target format; the address allocation module is configured to allocate addresses for the communication control module and the register processing module; the register processing module is configured to perform read and write processing on each register in the process of accessing the optical module; the communication control module is configured to control the timing in the process of accessing the optical module; the interrupt module is configured to report information to the central processing unit through interrupt multiplexing.

3. The optical module access system according to claim 2, characterized in that: The communication control module includes a register interface, a byte control module, a bit control module and a clock frequency division module; The register interface is connected to the byte control module, the bit control module, and the clock frequency division module respectively; the byte control module is connected to the bit control module; the clock frequency division module is connected to the bit control module; the bit control module is externally connected to the integrated circuit interconnection bus; The register interface is configured to complete the reading and writing of registers and the generation of interrupts during the access process of the optical module; The byte control module is configured to control the start bit command and the stop bit command during the access process of the optical module, and to split the data bit command and the response bit command; the bit control module is configured to complete the sending timing and receiving timing of each command; the clock division module is configured to divide the high-frequency clock into the target integrated circuit interconnection clock signal, and send it to the bit control module.

4. The optical module access system according to claim 3, characterized in that: The byte control module is configured to complete the control of the start bit command and the stop bit command, and the separation of the data bit command and the response bit command by controlling the state machine to be in different states.

5. The optical module access system according to claim 4, characterized in that: The byte control module is also configured to: When the current state of the state machine is not an idle state, if a stop bit command is received, it jumps to a stop bit state; If a start bit command is received, it jumps into the start bit state and performs corresponding byte operations until the target bit is operated, and jumps into the response bit state at the same time; if the response is completed, it jumps into the stop bit state; if the response is not completed, it jumps into the idle state.

6. The optical module access system according to claim 5, characterized in that: The byte control module is configured to enter a read bit state when receiving an optical module information read command and simultaneously count the total number of read bits; and jump to a response bit state when detecting that the current total number of read bits reaches the target bit.

7. The optical module access system according to claim 5, characterized in that: The byte control module is configured to enter a write bit state when receiving an optical module information write command and simultaneously count the total number of written bits; and jump to a response bit state when detecting that the current total number of written bits reaches the target bit.

8. The optical module access system according to claim 2, characterized in that: The communication control module includes a plurality of control submodules; each control submodule is respectively connected to the address allocation module and the interruption module; The control submodule is configured to access the corresponding optical module according to the optical module address carried in an optical module access request sent by the central processor, and to provide information feedback to the central processor in an interrupt multiplexing manner.

9. The optical module access system according to claim 2, characterized in that: The target bus is a reduced pin bus; the bus slave interface module is configured to complete the IO read and write functions of the reduced pin bus.

10. The optical module access system according to claim 1, characterized in that: The interface function expansion structure is connected to each optical module through an integrated circuit interconnection expansion chip device; two ends of the integrated circuit interconnection expansion chip device are respectively connected to the interface function expansion structure and each optical module through an integrated circuit interconnection bus; The number of expansion channels in the integrated circuit interconnection expansion chip device is determined based on the number of programmable logic controllers included in the interface function expansion structure and the total number of control submodules included in the communication control module, and each expansion channel uniquely corresponds to one control submodule.

11. The optical module access system according to claim 10, characterized in that: The interface function expansion structure includes a plurality of complex programmable logic devices; One end of each complex programmable logic device is connected to the central processing unit through the target bus, and the other end is connected to the integrated circuit interconnection expansion chip device through the integrated circuit interconnection bus.

12. The optical module access system according to claim 1, characterized in that: The interface function extension structure is also configured to send a bus abnormality signal to the central processor when an access abnormality is detected in the integrated circuit interconnect bus connected to the destination optical module.

13. The optical module access system according to claim 12, characterized in that: The central processor is also configured to send a write command and a stop command to the destination optical module, so that the destination optical module releases the integrated circuit interconnect bus.

14. The optical module access system according to claim 12, characterized in that: The interface function extension structure is also configured to send a write command and a stop command to the destination optical module so that the destination optical module releases the integrated circuit interconnect bus.

15. The optical module access system according to any one of claims 1 to 14, characterized in that: The interface function extension structure is also configured as follows: When in an idle state, monitoring whether there is an interrupt signal, and reporting the monitored interrupt signal to the central processing unit; If an interrupt signal is detected, jump to the interrupt state; When in an interrupt state, determine whether the current interrupt duration exceeds a preset interrupt threshold; If it is determined that the current interruption maintenance time exceeds the preset interruption threshold, jumping to the idle state; If it is determined that the current interruption maintenance time does not exceed the preset interruption threshold, jump to the response state; When in the response state, determine whether the current response time exceeds the preset response threshold; If it is determined that the current response time exceeds the preset response threshold, jump to the idle state; If it is determined that the current response time does not exceed the preset response threshold, then after the response is completed, the system jumps to the idle state.

16. An optical module access method, characterized in that: Applicable to the optical module access system according to any one of claims 1 to 15, comprising: Receive an optical module access request; The target optical module is accessed according to the optical module address carried in the optical module access request, and information is reported in an interrupt multiplexing manner.

17. The optical module access method according to claim 16, characterized in that: The accessing the target optical module according to the optical module address carried in the optical module access request includes: Determine a corresponding target extension channel in the integrated circuit interconnection extension chip device based on the optical module address, and open the target extension channel; According to the optical module information acquisition protocol format determined by the integrated circuit interconnection communication protocol, an optical module information reading command is sent, and after the optical module information reading is completed, the target extension channel is closed.

18. The optical module access method according to claim 17, characterized in that: The step of opening the target extension channel comprises: Send start bit; Send an integrated circuit interconnection extension chip device address write command and send a write data command to open the target extension channel.

19. The optical module access method according to claim 17, characterized in that: The sending of the optical module information reading command comprises: Send start bit; Send the optical module address read command and the optical module register read command; Send start bit; Send the optical module register read command and the optical module data read command.

20. The optical module access method according to claim 17, characterized in that: After the optical module information is read, closing the target extension channel includes: When the optical module information is read, a stop bit command is sent; Send start bit; Send an integrated circuit interconnection extension chip device address write command and send a write data 0 command to close the target extension channel.

21. The optical module access method according to claim 16, characterized in that: The accessing the target optical module according to the optical module address carried in the optical module access request includes: Determine a corresponding target extension channel in the integrated circuit interconnection extension chip device based on the optical module address, and open the target extension channel; According to the optical module information acquisition protocol format determined by the integrated circuit interconnection communication protocol, an optical module information writing command is sent, and after the optical module information writing is completed, the target extension channel is closed.

22. The optical module access method according to claim 21, characterized in that: The sending of the optical module information writing command comprises: Send start bit; Send the optical module address read command and the optical module register write command; Send the optical module data write command.

23. An optical module access device, characterized in that: Applicable to the optical module access system according to any one of claims 1 to 15, comprising: A request receiving module, configured to receive an optical module access request; The optical module access module is configured to access the target optical module according to the optical module address carried in the optical module access request, and report information in an interrupt multiplexing manner.

24. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the processor is configured to implement the steps of the optical module access method according to any one of claims 16 to 22 when executing a computer program stored in the memory.

25. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the optical module access method according to any one of claims 16 to 22 are implemented.

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