Memory device using semiconductor element

Abstract

The present invention has a p-type semiconductor region formed in an n+ layer to which a bit line is connected, and an n-type semiconductor layer connected to a source line, and comprises: a first gate insulating layer and a first gate conductor layer that are in contact with the upper surface of the p-type semiconductor layer, the first gate conductor layer being in contact with the first gate insulating layer and connected to a word line; and a second gate insulating layer and a second gate conductor layer that are in contact with the lower surface of the p-type semiconductor layer, the second gate conductor layer being in contact with the second gate insulating layer and connected to a plate line, wherein the distance from the n+ layer to the first gate conductor layer is shorter than the distance to the second gate conductor layer, and the plate line and the source potential have positive potentials having the same polarity in an erasing operation.

Description

Memory device using semiconductor elements

[0001] The present invention relates to a memory device using a semiconductor element.

[0002] 2. Description of the Related Art In recent years, with the development of LSI (Large Scale Integration) technology, there has been a demand for memory devices that can be equipped with logic circuits using semiconductor elements, with higher integration, higher performance, lower power consumption, and higher functionality.

[0003] Dynamic Random Access Memory (DRAM) is widely used as integrated circuit memory. To improve the density of DRAM memory, an SGT structure extending perpendicular to the upper surface of the semiconductor substrate has been used (see, for example, Patent Document 1 and Non-Patent Document 1). Other DRAM memory cells include those composed of a single MOS transistor without a capacitor (see, for example, Non-Patent Documents 3 to 6). These are commonly referred to as "1T DRAM." For example, a source-drain current in an n-channel MOS transistor generates holes and electrons in the channel by impact ionization, and some or all of the holes are retained in the channel to write logical data "1." Then, the holes are removed from the channel to write logical data "0." However, this structure poses a problem: applying a voltage to a selected cell inputs an unwanted signal to unselected cells, causing the unselected memory cells to malfunction.

[0004] There are also twin-transistor MOS transistor memory elements, in which two MOS transistors are used to form one memory cell in an SOI layer (see, for example, Patent Documents 2 and 3, and Non-Patent Document 7). Furthermore, there are dynamic flash memories (DFMs), which do not have a capacitor and each memory cell is composed of two gate electrodes (see Patent Document 4 and Non-Patent Document 8). In these memory cells, the carrier concentration in the floating body is changed by manipulating the voltages of the four electrodes, creating a conductive or non-conductive state to enable memory operation. Structures in which a body that stores carriers is connected to the bottom of the MOS transistor have also been proposed (see Patent Document 5). Furthermore, there are DRAMs that are three-dimensionally stacked with 1T DRAMs created using a sacrificial layer to achieve higher density (see Patent Documents 6 and 7). However, these memory elements still have concerns about instability of DRAM operation due to the 1T DRAM.

[0005] JP-A-2-188966 US2008 / 0137394 A1US2003 / 0111681 A1US2023 / 11776620 B2US 2023 / 0077140 A1US 2023 / 0106561 A1US 2023 / 0269926 A1

[0006] The snowflake, the snowflake, the snowflake Thank you, sightseeing, sightseeing, The fingers of the fingers, the fingers of the fingers Aesthetics of aesthetics, sights, NO3, 0573578 (1991) The snow, N. Yes, N. Yes, it is. Yes, S. Yes, it is. No, it's THIS, THIS. No, 10 Note, 100%. No, no, No, it's a. I: “FOUR2 LIKE THIS THING YOU CAN SAY The scientist(s)” 011 scientists s The emotional snowflake emotional Thanksgiving, (2011) Thanksgiving、. Whatever, The scientists, 100%, The scientist, I'm sorry, I'm sorry. Psychology、“Emotional attitude i The scientists of the snow snow water” PHYS snowflake is snowflake snow, s. 37, N11, 15001522 (2002) 100, 4. THIS, THIS. Thanksgiving, this is scientists: “The scientists are scientists THIS ACTIVITY LITERATURE THINGS The emotional attitude is the aesthetic feeling,” Emotional emotional, s. 35, 82, 174181 (2012) Thanks, The snowflakes, The snowflakes, Thanksgiving, Whatever, 2013, 10:0 2013, The snowflakes, Thanksgiving, A. 2013, The scientists, What do you think, The scientists,J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama: “Floating Body RAM Technology and its Scalability to 32nm Node and Beyond,” IEEE IEDM (2006).E. Yoshida: “A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” IEEE IEDM (2006).F. Morishita, H. Noda, I. Hayashi, T. Gyohten, M. Oksmoto, T. Ipposhi, S. Maegawa, K. Dosaka, and K. Arimoto: “ Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI,”IEICE Trans. Electron., Vol. E90-c., No.4 pp.765-771 (2007)K.Sakui, N. Harada,” Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT),”Proc. IEEE IMW, pp.72-75(2021)N. Louber et al., ”Stacked Nanosheet Gate-All-Around Transisitor to Enable Scaling Beyond FinFET,”IEEE Symposium on VLSI Technology Digest of Technical Papers,pp. T230-T231 (2017) Hidenori Miyagawa, Haruka Kusai, Riichiro Takaishi, Tomoya Kawai, Yuuichi Kamimuta, Toshiya Murakami, Keiko Ariyoshi, Takanori Asano, Masakazu Goto, Makoto Fujiwara, Yuuichi Mitani, Tomoyuki Obu, Hideaki Aochi, "Metal-Assisted Solid-Phase Crystallization Process" for Vertical Monocrystalline Si Channel in 3D Flash Memory”, pp.650-653, IEDM (2019),

[0007] An object of the present invention is to three-dimensionally stack memory cells to realize a high density memory, and to provide stable memory operation.

[0008] In order to solve the above problems, a memory cell using a semiconductor element according to a first aspect of the present invention is a memory cell comprising: a first semiconductor region extending in a direction perpendicular to a substrate; a second semiconductor region surrounding a part of the periphery of the first semiconductor region and connected thereto; a third semiconductor region surrounding a part of the periphery of the second semiconductor region and connected thereto; a first dielectric film covering a part of the upper surface of the second semiconductor region; a first gate conductor layer in contact with the upper surface of the first dielectric film; a second dielectric film covering a part of the lower surface of the second semiconductor region; and a second gate conductor layer in contact with the second dielectric film and located at a shortest distance from the first semiconductor region that is greater than the shortest distance from the second dielectric film and the first semiconductor region, A source line is connected to the third semiconductor region, a bit line is connected to the second wiring conductor layer, a word line is connected to the first gate conductor layer, and a plate line is connected to the second gate conductor layer; voltages are applied to the source line, bit line, plate line, word line, and control line, respectively, to perform write operations, erase operations, and read operations; and during an erase operation of the memory, a voltage is applied to only one of the source line and the bit line.

[0009] The second invention is characterized in that, in the above-mentioned first invention, the polarity of the voltages applied to the bit line and the word line during read and write operations is the same, and the polarity of the voltage applied to them and the plate line is different.

[0010] A third invention is characterized in that in the first invention, during an erase operation of the memory device, a voltage of the same polarity as that of the plate line is applied to either the source line or the bit line.

[0011] A fourth invention is characterized in that in the first invention, the second insulating layer has a thickness greater than that of the first insulating layer.

[0012] A fifth invention is characterized in that in the first invention, the majority carriers in the first semiconductor region and the third semiconductor region are the same and different from the majority carriers in the second semiconductor region.

[0013] A sixth invention is characterized in that in the first invention, a first metal layer is used instead of the first semiconductor region.

[0014] A seventh invention is characterized in that in the sixth invention, the first semiconductor layer is used around the first metal layer.

[0015] An eighth invention is characterized in that in the first invention, the first metal layer is further provided connected to the inside of the first semiconductor region.

[0016] A ninth invention is characterized in that in the first invention, the periphery of the third semiconductor region is covered with a metal layer.

[0017] A memory device according to a tenth aspect of the present invention is characterized in that a plurality of memory cells of the first aspect of the present invention are laid out on a plane, the second semiconductor layer, the third semiconductor layer, the first dielectric film, the first gate conductor layer, the second dielectric film, and the second gate conductor layer are shared by a plurality of horizontally adjacent memory cells, and further, in the vertical direction, the memory cells are separated by a first insulating layer except for the first semiconductor layer, and the first semiconductor layer is shared with memory cells in the vertical direction, thereby stacking a plurality of memory cells in the vertical direction.

[0018] An eleventh aspect of the present invention is characterized in that the memory cells of the tenth aspect are arranged in a horizontal direction, separated by a second insulator.

[0019] A twelfth aspect of the present invention is characterized in that, in the tenth aspect, the second gate conductor layer is shared by memory cells adjacent in the vertical direction.

[0020] A method for manufacturing a memory device according to a thirteenth aspect of the present invention is characterized by comprising the steps of: forming a stacked structure by alternately depositing a semiconductor layer that will become a second semiconductor layer and a first sacrificial layer or a second sacrificial film layer in a plurality of layers; forming vertical bit line holes that penetrate the stacked structure using a trench process, and introducing impurities into the semiconductor layer using an isotropic doping process that penetrates from the bit line holes; and then filling the bit line holes with a semiconductor or metal layer, removing a selected portion of the deposited insulating layer, and forming a dielectric film and a gate conductor layer.

[0021] A fourteenth aspect of the present invention is characterized in that in the thirteenth aspect, the bit line region is made of either metal or polysilicon.

[0022] A fifteenth aspect of the present invention is characterized in that, in the thirteenth aspect, the first sacrificial film and the second sacrificial film have different etching characteristics.

[0023] A sixteenth invention is characterized in that, in the thirteenth invention, the first sacrificial film and the second semiconductor layer material, or the second sacrificial film and the second semiconductor material, have different etching characteristics.

[0024] The method for manufacturing a semiconductor memory device according to the seventeenth invention is characterized by comprising the steps of alternately depositing three or more sacrificial layers to form a stacked structure, forming vertical bit line holes penetrating the stacked structure using a trench process, and filling the holes with a semiconductor or metal layer, selectively removing one of the layers and then replacing it with a semiconductor layer while simultaneously performing a doping process thereon, and removing a selected portion of the deposited insulating layer to form a dielectric film and a gate conductor layer.

[0025] An eighteenth invention is characterized in that in the seventeenth invention, the plurality of sacrificial film materials have different etching characteristics from one another.

[0026] 1A is a bird's-eye view of a memory device using a semiconductor element according to a first embodiment, and FIG. 1B is a bird's-eye view with an upper film removed of FIG. 1A. A diagram for explaining the accumulation of hole carriers and cell current during a write operation of a memory device using a semiconductor element according to the first embodiment. A diagram for explaining an erase operation of a memory device using a semiconductor element according to the first embodiment. A diagram showing signals input to each terminal and a memory state when operating a memory device using a semiconductor element according to the first embodiment. A bird's-eye view of an additional example of a memory device using a semiconductor element according to the first embodiment and a bird's-eye view with an upper film removed of FIG. 1A. A bird's-eye view of an additional example of a memory device using a semiconductor element according to the first embodiment. A bird's-eye view of an additional example of a memory device using a semiconductor element according to the first embodiment. A diagram for explaining the expanded state of the cell layout of FIG. 1 in a memory device using a semiconductor element according to the first embodiment, and a diagram for explaining coordinates of a cell layout according to a second embodiment. A diagram for explaining the bird's-eye view of FIG. 1A with an upper film removed of FIG. 1A. An additional example of a memory device using a semiconductor element according to the second embodiment. An additional example of a memory device using a semiconductor element according to the second embodiment. An additional example of a memory device using a semiconductor element according to the second embodiment. FIG. 10 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 11 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 12 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 13 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 14 is a diagram for explaining an additional example of a method for manufacturing a memory device according to a third embodiment. FIG. 15 is a diagram for explaining an additional example of a method for manufacturing a memory device according to a third embodiment.

[0027] Hereinafter, the structure, driving method, and behavior of stored carriers of a memory device using semiconductor elements according to an embodiment of the present invention will be described with reference to the drawings.

[0028] (First Embodiment) The cell structure and operation of a memory using a semiconductor element according to a first embodiment of the present invention will be described using FIGS. 1 to 3. The cell structure of a memory using a semiconductor element according to the first embodiment of the present invention will be described using FIGS. 1(a) and 1(b). The write mechanism of a memory cell and the behavior of carriers will be described using FIG. 2. The erase mechanism of a memory cell and the behavior of carriers will be described using FIG. 3. In addition, other embodiments of the present invention will be described using FIGS. 4 and 5.

[0029] FIG. 1A shows the structure of a memory using a semiconductor device according to a first embodiment of the present invention. The memory includes an n+ layer 1, a semiconductor region containing a high concentration of donor impurities (an example of the "first semiconductor region" in the claims). The semiconductor region containing a high concentration of donor impurities is referred to as the "n+ layer." Surrounding a portion of the n+ layer 1 is a p-layer 2 (an example of the "second semiconductor region" in the claims) containing acceptor impurities and having p-type conductivity, which is in contact with the n+ layer 1. A first gate insulating layer 4 (an example of the "first dielectric layer" in the claims) is in contact with the upper surface of the p-layer 2, and a second gate insulating layer 6 (an example of the "second dielectric layer" in the claims) is in contact with the lower surface of the semiconductor layer 2. In addition, a first gate electrode 5 (an example of a "first gate conductor layer" in the claims) is in contact with the first gate insulating layer, and a second gate electrode 7 (an example of a "second gate conductor layer" in the claims) is in contact with the second gate insulating layer 6. The shortest distance L2 between the second gate electrode 7 and the n+ layer 1 is longer than the shortest distance L1 between the first gate electrode 5 and the n+ layer 1. Furthermore, in contact with the p layer 2 and the gate insulating layers 4 and 6, there is a semiconductor n layer 3 having an n-type conductivity containing donor impurities (an example of a "third semiconductor region" in the claims).

[0030] Furthermore, the n layer 3 is connected to a source line SL (an example of a "source line" in the claims) which is a first wiring conductive layer, the n+ layer 1 is connected to a bit line BL (an example of a "bit line" in the claims) which is a second wiring conductive layer, the gate conductor layer 5 is connected to a word line WL (an example of a "word line" in the claims) which is a third wiring conductive layer, and the gate conductor layer 7 is connected to a plate line PL (an example of a "plate line" in the claims) which is a fourth wiring conductive layer. The memory is operated by manipulating the voltages applied to the source line SL, bit line BL, plate line BL, and word line WL. Specific driving methods will be described later.

[0031] FIG. 1B shows a bird's-eye view of the memory cell with the gate conductor layer 4 and gate insulating layer 5 removed from FIG. 1A.

[0032] The gate insulating layers 4 and 6 can be any insulating film used in a typical MOS process, such as a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, a hafnium silicon oxide (HfSiO2) film, or a stacked film of SiO2 / SiN. While the gate insulating layers 4 and 6 are all shown to have the same thickness in FIG. 1, the thickness of the gate insulating layer 4 in contact with the gate conductor layer 5 may vary depending on the location. Similarly, the thickness of the gate insulating layer 6 in contact with the gate conductor layer 7 may vary depending on the location.

[0033] 1, the p-layer 2 is a p-type semiconductor, but the optimum impurity concentration of the p-layer 2 is determined by the amount of excess holes to be stored in the memory, which is determined by parameters such as the thickness and volume of the p-layer 2, the thickness of the gate insulating layers 4 and 6, the material of the gate conductor layers 5 and 7, and the applied voltage. Furthermore, the p-layer 2 may have a profile, and depending on the material and thickness of the gate insulating layers 4 and 6 and the material of the gate conductor layers 5 and 7, the concentration of the p-layer 2 may vary both in plan view and in the depth direction.

[0034] Furthermore, the impurity concentrations of n+ layer 1 and n layer 3 may have a profile, or the impurity concentration of n layer 3 may be increased to form an n+3 layer. Furthermore, in the direction in which n+ layer 1 or n layer 3 is connected to p layer 2, an LDD (Lightly Doped Drain) region having a lower donor concentration than the donor impurity concentration of n layers 1 and 3 may be provided between p layer 2 and n layers 1 and 3. Furthermore, a metal layer connected in the vertical direction may be provided in the center of n+ layer 1 to reduce the resistance between n+ layer 1 and bit line BL of each memory cell.

[0035] Furthermore, the first gate conductor layer 5 may be made of a metal such as W, Pd, Ru, Al, TiN, TaN, or WN, a metal nitride, or an alloy thereof (including silicide), such as TiN / W / TaN, or may be formed of a highly doped semiconductor, as long as the potential of part of the memory cell can be changed via the gate insulating layer 4, and the second gate conductor layer 7 may be made of a metal such as W, Pd, Ru, Al, TiN, TaN, or WN, a metal nitride, or an alloy thereof (including silicide), for example, a stacked structure such as TiN / W / TaN, or may be formed of a highly doped semiconductor. Furthermore, different materials may be used for the first gate conductor layer 5 and the second gate conductor layer 7.

[0036] Furthermore, when the n+ layer 1 and the n layer 3 are formed from a semiconductor region p layer containing a high concentration of acceptor impurities in which holes are the majority carriers, if an n-type semiconductor is used for the p layer 2 and a p-type semiconductor is used for the n layers 1 and 3, the memory of the present invention will operate with electrons as the write carriers.

[0037] Referring to Figure 2, the carrier behavior, storage, and cell current during a write operation of the memory according to the first embodiment of the present invention will be described. First, the majority carriers in the n+ layer 1 and n layer 3 are electrons. For example, poly-Si containing a high concentration of donor impurities is used for the gate conductor layer 5 connected to the word line WL and the gate conductor layer 7 connected to the plate line PL (hereinafter, poly-Si containing a high concentration of donor impurities will be referred to as "n+poly"), and a p-type semiconductor is used for the p layer 2. As shown in Figure 2(a), the MOSFET in this memory cell operates using the n layer 3 as the source, the n layer 1 as the drain, the gate insulating layer 4, the gate conductor layer 5 as the gate, the p layer 2 as the substrate, the gate insulating layer 6, and the gate conductor layer 7 as the plate electrode.

[0038] FIG. 2(d) shows an equivalent circuit of a memory cell according to the first embodiment of the present invention. The bit line BL serves as the drain, which is the n+ layer 1 of the MOSFET; the word line WL serves as the gate, which is the first gate conductor layer 5; and the source line SL serves as the source, which is the n+ layer 1, allowing for application of a voltage similar to that of a conventional MOSFET. The present invention has two features. One is that the MOSFET has a floating body, with no electrodes connected to the substrate. Therefore, in this MOSFET, the p-layer 2 operates as a floating body. The other is that there is another gate, to which the plate line PL is connected across an insulating layer from the p-layer 2. Furthermore, since the channel formed by changing the voltage of the plate line PL does not contact the drain, the BL and SL lines are characterized by a channel formed in contact with the gate insulating layer 6, preventing current from flowing.

[0039] For example, 0 V is input to the n-layer 3 connected to the source line SL, 1.2 V is input to the n-layer 1 connected to the bit line BL, and −1 V is applied to the gate conductor layer 7 connected to the plate line PL. Here, the threshold voltage of the MOSFET using the gate conductor layer 5 as the gate electrode before writing is, for example, 1.0 V when the voltage of the plate line PL is −1 V. Next, when 1.5 V is input to the gate conductor layer 5 connected to the word line WL, an inversion layer 81 is formed directly below the gate insulating layer 4 below the gate conductor layer 5. In this case, a current flows between BL and SL in the MOSFET having the gate conductor layer 5.

[0040] As a result, the electric field becomes large near the inversion layer 81 or n-layer formed in the MOSFET having the gate conductor layer 5, and impact ionization occurs in this region. It does not matter whether the MOSFET operates in the linear region or the saturation region. This impact ionization phenomenon causes electrons accelerated from the n-layer 3 connected to the source line SL toward the n-layer 1 connected to the bit line BL to collide with the Si lattice, and their kinetic energy generates electron-hole pairs. The generated holes diffuse toward areas with lower hole concentrations due to the concentration gradient. As a result, a group of holes 83 accumulates in the p-layer 2.

[0041] In the above example, the plate line PL is set to -1 V, which contributes to two things: narrowing the depletion layer formed below the p-layer 2 in contact with the gate insulating layer 4 and expanding the area that makes it easier to accumulate holes generated by impact ionization, and adjusting the threshold voltage of the MOSFET in the memory cell by the substrate bias effect.

[0042] Furthermore, in the above example, n+poly is used for the gate conductor layer 7 and a negative voltage is biased. However, the same effect can be achieved by using a material for the gate conductor layer 5, which in this example has a higher work function than n+poly, such as p+poly with acceptor-type impurities introduced therein, without applying a voltage as low as that applied when using an n+poly electrode.

[0043] Instead of causing the impact ionization phenomenon, a gate-induced drain leakage (GIDL) current may be passed to generate holes (see, for example, Non-Patent Document 4).

[0044] FIG. 2(b) shows a group of holes 83 in the p-layer 2 immediately after writing, when the plate line PL is at -1 V and the biases of the word line WL, source line SL, and bit line BL are at 0 V. The generated group of holes 83 diffuse from high-concentration regions to low-concentration regions in the p-layer 2 due to differences in carrier concentration. Furthermore, because a negative potential is applied to the second gate conductor layer 7, holes accumulate at a higher concentration near the second gate insulating layer 6. As a result, the threshold voltage of the MOSFET having the gate conductor layer 5 is lowered by the positive substrate bias effect due to the holes temporarily accumulated in the p-layer 2. In this example, as shown in FIG. 2(c), the threshold voltage of the MOSFET having the gate conductor layer 5 connected to the word line WL is approximately 0.5 V, lower than before writing, and current begins to flow when the word line voltage is increased. This write state is assigned to logical storage data "1."

[0045] Normally, in a memory using such a floating body (a 1T DRAM is a typical example), when the planar area is reduced to increase density, the number of holes stored in the body decreases with the area, narrowing the operating margin of the memory. However, in the memory cell of the present invention, by adjusting the thickness of the p-layer 2, the number of holes can be adjusted without changing the planar density, contributing to stable operation of the memory.

[0046] In addition to the above examples, if the voltages applied to the bit line BL, plate line PL, and word line WL are expressed as V-BL, V-PL, and V-WL, respectively, the voltage application conditions can be combinations such as 1.0V (V-BL) / -1V (V-PL) / 2.0V (V-WL), 1.0V (V-BL) / -0.5V (V-PL) / 1.2V (V-WL), or 1.5V (V-BL) / -1V (V-PL) / 2.0V (V-WL), with the source line SL at 0V.

[0047] Next, the erase operation mechanism will be explained using Fig. 3. Before the erase operation, during the so-called standby period, the source line SL, bit line BL, and word line WL are at 0 V, and the voltage of the plate line PL is -1 V. This is the same state as Fig. 2(b).

[0048] As shown in FIG. 3(a), during an erase operation, the bit line BL and word line WL are set to 0V, and the source line SL to 0.5V. The voltage of the plate line PL is set to, for example, 2V. As a result, regardless of the initial potential of the p-layer 2, an electron inversion layer 64 is formed at the interface between the insulating layer 6 and the p-layer 2. At the same time, a depletion layer is formed in the p-layer 2 adjacent to the inversion layer 64. This depletion layer reduces the probability of holes being present, and holes 83 stored in the p-layer 2 recombine with electrons 85 where the inversion layer 84 and the n-layer 3 are in contact. Electrons lost through recombination are replenished from the inversion layer 84 through the n-layer 3. As a result of this hole-electron recombination, the hole concentration in the p-layer 2 rapidly decreases over time. After the erase operation is completed, the standby plate line PL voltage is set to -1V. As shown in FIG. 3(b), the number of carriers present in the floating body p-layer 2 is significantly reduced, and the threshold voltage of the MOSFET becomes higher than when a "1" was written. For example, after an erase operation, the threshold voltage of the MOSFET becomes 1.2V, which is higher than the initial threshold voltage of 1.0V.

[0049] As a result, as shown in FIG. 3(c), a MOSFET having a gate conductor layer 5 connected to this word line WL is in an erased state, with almost no current flowing even when a voltage is applied. This is a significant difference from 1T DRAM, which has a cell current of about 1-10% of the on-current even in the "0" state (see, for example, Non-Patent Document 3). This state is considered the logical memory data "0" of the memory. As such, in this memory cell, the difference in cell current between the data "1" and "0" states is large, resulting in a large memory read margin. Furthermore, with the structure of the present invention, the area formed by the inversion layer increases the opportunity for electron-hole recombination compared to during programming or standby, thereby improving the efficiency of erasure.

[0050] As a method of erasing data other than the examples given above, data can also be erased by applying a positive voltage to the bit line BL and setting the source line SL to 0 V. In this case, data is erased by the recombination of electrons flowing from the source line toward the bit line due to the electric field with holes in the p-layer 2. What is important here is that during the erase operation, one of the source line SL and bit line BL is at a positive potential and the other is at 0 V.

[0051] Therefore, if the voltages applied to the bit line BL, plate line PL, word line WL, and source line SL are respectively represented as V-BL, V-PL, V-WL, and W-SL, then possible voltage application conditions include, for example, combinations of 0V (V-BL) / 2V (W-PL) / -1V (V-WL) / 0.5V (V-SL), 0.5V (V-BL) / 2V (V-PL) / 0V (V-WL) / 0V (V-SL), 1V (V-BL) / 1.5V (V-PL) / 0V (V-WL) / 0V (V-SL), and 0V (V-BL) / 1.5V (V-PL) / 1.5V (V-WL) / 0V (V-SL). However, the above voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are examples for performing a memory erase operation, and other operating conditions that allow a memory erase operation may be used. However, either the bit line BL or the source line SL is always at 0 V, and both electrodes are never at a positive potential simultaneously.

[0052] Furthermore, the n+ layer 1 is electrically isolated from the inversion layer 64 formed when it comes into contact with the gate insulating layer 6 during erasure. This prevents current from flowing between the inversion layer 64 formed between the p layer 2 and the gate insulating layer 6 and the n+ layers 1 and 3 during the memory erase operation. This results in almost no current flowing through the cell during erasure, which helps reduce power consumption during erasure. Patent Document 5 discloses that erasure is performed by simultaneously raising the bit line, source line, and erase gate to a positive potential, coupling the floating body potential with a voltage high enough to make the P / N junction forward. As a result, holes are evacuated from the floating body, lowering its potential, thereby performing the erase operation. However, this operation is not performed in the present invention.

[0053] Furthermore, according to the first embodiment of the present invention, the memory can be erased by applying a positive voltage to the plate line PL during erasure, which has the advantage that the gate conductor layer 7 can be shared by multiple cells and the information in these cells can be erased at once.

[0054] Figure 4 shows typical signal inputs to the bit line BL, plate line PL, word line WL, and source line SL, as well as the cell current flowing through the memory cell during write, erase, and standby. Before T1, all signals except the plate line are 0, and the plate line is at a negative voltage. During write, at T1, BL and WL are at a positive voltage, PL is at a negative voltage, and SL is at 0V. Write ends at T2, and standby occurs until T3. For subsequent reads, a positive voltage is applied to BL and WL, and a current flows between BL and SL, recognizing a "1." Then, at T5, an erase operation is performed by applying a positive voltage to SL and a voltage from negative to positive to PL. Then, from T6 to T7, standby occurs. The same voltage conditions are applied as when reading a "1" between T7 and T8, but no current flows between BL and SL, resulting in a "0" being read.

[0055] Figure 5-1 shows an application example of the first embodiment. In Figure 1, a semiconductor layer containing a high concentration of impurities was used for the memory bit line BL, but in this example, a metal layer 11 is used for the bit line BL (an example of the "first metal layer" in the claims), and a p-layer 2 is formed around a part of it, with the rest of the structure being the same as in Figure 1. Figure 5(b) shows a bird's-eye view of the memory cell in Figure 5(a) with the gate conductor layer 7 and gate insulating layer 5 removed.

[0056] Furthermore, Figure 5-2(c) shows another application example of the first embodiment. While Figure 5-1(a) shows that the p-layer 2 is in direct contact with the metal layer 18 of the memory, this example shows that an n+ layer 22 is formed between the metal layer 18 and the p-layer. Other than that, it has the same structure as Figure 1. Furthermore, Figure 5-2(d) shows that, in addition to Figure 5-2(c), an n+ layer 21 is formed on the source side, and a metal layer 12 is further formed around it. Other than that, it has the same structure as Figure 1. Both examples use lower-resistance materials for parts of the bit line and source line. For the same purpose, there is also a method of using a metal layer 11 in the center of the bit line and surrounding it with an n+ layer 23, as shown in Figure 5-3(e).

[0057] The first embodiment of the present invention has the following features.

[0058] (Feature 1) The memory according to the first embodiment of the present invention is formed from components each having four terminals, and by manipulating two gates, the difference between the current when the memory access transistor is in the on state and the current when it is in the off state can be increased, thereby increasing the read margin of the memory.

[0059] (Feature 2) In the first embodiment of the present invention, the number of holes stored in the floating body can be adjusted without changing the memory density in plan view by adjusting the thickness of the p-layer 2. This allows for a wide range of memory operation.

[0060] (Feature 3) In the first embodiment of the present invention, the cell current that flows during erasure is determined solely by the recombination current of electrons and holes, thereby achieving low power consumption during memory erasure operations.

[0061] (Feature 4) In the memory according to the first embodiment of the present invention, the gate conductor layer 7 is shared, and even when a plurality of memory cells are arranged, an erase operation can be performed simultaneously on a plurality of cells in a single operation.

[0062] Second Embodiment FIGS. 6-1 and 6-2 are diagrams illustrating the cell arrangement of a memory device using a semiconductor element according to the first embodiment. In FIG. 6-1(a), a single cell unit (an example of a "memory cell" in the claims) arranged in the first row, first column, and layer a is indicated by a dotted line. As shown in FIG. 6-1(a), rows and columns are indicated by numbers such as 1, 2, and 3 in the direction of the arrow, and layers are indicated by lowercase letters a, b, and c from top to bottom. In the example of FIG. 6-1(a), the memory cells of FIG. 1 are arranged vertically (hereinafter referred to as the "vertical direction" or "layer," the z-direction) and then horizontally (hereinafter referred to as the "row direction" or "row," the x-direction, and the "column direction" or "column," the y-direction). FIG. 6-1(a) shows an example of a memory device having a total of 18 memory cells in two rows, three columns, and three layers. In an actual memory device, more memory cells can be arranged than this. The layers are separated by insulating layers D1a (an example of the "first insulating layer" in the claims) and D1b.

[0063] Each memory cell enclosed by a dotted line is composed of an n+ layer 111a, a p layer 211a, an n layer 31a, a gate insulating layer 41a, a gate conductor layer 51a, a gate insulating layer 61a, and a gate conductor layer 71a. Furthermore, 111a is connected to the bit line BL11, the gate conductor layer 51a is connected to the word line WLa, the gate conductor layer 71a is connected to the plate line PLa, and the source line SLa is connected to the n layer 31a, and signals are input through these layers. Of these, the n layer 31a and the gate conductor layers 51a and 71a are shared with the a layer in the z direction, and the n+ layer 111a is shared with cells from the a layer to the c layer in the z direction. Figure 6-2(c) shows a memory cell array with the gate conductor layer 51a and gate insulating layer 41a removed.

[0064] When writing to a memory cell surrounded by a dotted line as a target, the bit line BL11 of the layer in which that memory cell is located is selected and a positive potential is applied, and the word line WLa is selected and a positive potential is applied. At this time, all source lines SLa to SLc are at 0V, and the plate lines PLa to PLc are at -1V. Furthermore, when erasing, the plate line PLa is set to 2V, the source line SLa to 0.5V, and all word lines WLa to WLc and all bit lines BLa to BLc are set to 0V, thereby erasing all the cells in layer a at once. Of course, if the plate lines and source lines are separated so that they intersect perpendicularly, random erasure is also possible.

[0065] Figure 7 shows an example of a cell array arrangement using the memory cells of Figure 5-2(c). Focusing on the cell surrounded by the dotted line, it has the same cell array structure and function as the one shown in Figure 6, except that a metal layer is used for 111a connected to the bit line and the periphery is surrounded by an n+ layer 2211a. The dotted line indicates one memory cell unit, and the two-dot chain line indicates a block of nine memory cells arranged in one row, three columns, and three layers.

[0066] 8 shows an example in which the blocks defined in FIG. 7 are separated by dielectrics D21 and D22 (an example of a "second insulating layer" in the claims). In this example, the word lines, source lines, and plate lines are common to the cells in the X direction, but are independent in the Y direction. Therefore, in this figure, the word lines are separated from WLa to WLc (WLb is not shown), the source lines are separated from SLa to SLc (SLb is not shown), and the plate lines are separated from PLa to PLc (PLb is not shown), and each is selected during memory operation and voltages are applied independently.

[0067] FIG. 9 shows an example of a memory cell layout for realizing a higher-density memory device according to the second embodiment of the present invention. This figure shows an example of a cell layout diagram in which adjacent plate electrodes in the z direction are shared. The portion indicated by the dotted line is one cell, and the cell directly below it shares the plate electrode 71a. This diagram shows a total of four layers in the z direction, from layer a to layer d. In this case, that layer can be erased by applying a positive voltage to the source line that performs the erase operation. It is also possible to simultaneously erase cells in the two layers, layer a and layer b, that contact the plate electrode. Note that while all components in layers a to b are shown one by one, only partial representations of layers c and d are shown to avoid complication.

[0068] Furthermore, the memory cell arrays arranged in Figures 6 to 9 may be deployed and arranged vertically or horizontally on any substrate made of a material that can support the cell array, such as a semiconductor, insulator, or metal layer.

[0069] The second embodiment of the present invention has the following features.

[0070] (Feature 1) The memory according to the second embodiment of the present invention is a memory cell array in which one memory cell proposed in the first embodiment is arranged two-dimensionally, and is further separated by dielectrics D1a, D1b, D21, and D22, and stacked three-dimensionally in the vertical direction, thereby realizing a high-density memory cell array.

[0071] (Feature 2) The memory cell array according to the second embodiment of the present invention can freely set word lines, plate lines, and source lines shared by multiple memory cells by using dielectrics D1a, D1b, D21, and D22. (Feature 3) The memory cell array according to the second embodiment of the present invention can write, read, and erase data to desired cells by applying voltages to selected word lines, plate lines, source lines, and bit lines.

[0072] (Third embodiment)

[0073] Figures 10(a) to 10(h) show simple process steps according to the third embodiment used to form the memory cell structure shown in Figure 1. While Figure 10 focuses on one memory cell and shows only a semiconductor layer 902 and two sacrificial layers 911 (first sacrificial layer in the claims) and 912 (second sacrificial layer in the claims), to realize a structure such as that shown in the second embodiment, any number of semiconductor layers 902 and sacrificial layers 911 and 912 can be alternately deposited to form a stacked memory structure.

[0074] 10(a) shows a stacked structure formed by alternately depositing multiple semiconductor layers 903, such as n-type polysilicon or silicon, and multiple sacrificial layers 911, 912, such as oxide or nitride. For example, in this example, silicon oxide is used as sacrificial layer 911, and silicon nitride is used as sacrificial layer 912. These layers can be formed using any suitable deposition process, such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or physical vapor deposition (PVD), or any other suitable process.

[0075] A lithography step is then used to form vertical bitline holes (or openings) 920 by etching the stacked layers using an anisotropic etching process, as shown in FIG. 10(b).

[0076] 10(c) shows how a plasma doping (PLAD) or vapor phase doping process is applied through the vertical bit line holes 920 to dope the semiconductor layer 903 with the opposite type of dopant used to form the p-layer 902. For example, if the semiconductor layer 903 has an N-type dopant such as phosphorus, the plasma doping process will form the P-layer 902 using a P-type dopant such as boron.

[0077] 10(d) shows that the vertical bit line holes 920 are filled with a semiconductor material, such as polysilicon, heavily doped with n-type impurities to form a semiconductor layer 901. The semiconductor layer 901 may be deposited using any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PE-ALD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process, using an in-situ doping process. If the memory cell is an nMOS cell, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition of the semiconductor layer 901. If the memory cell is a PMOS cell, a P-type dopant, such as diborane (B2H6), is added during the deposition of the semiconductor layer 901.

[0078] During this actual process, dopants permeate from the semiconductor layer 901 to the semiconductor layer 902, forming an n-type semiconductor layer 922. This is slightly different from FIG. 1, but there is no essential difference.

[0079] 10(e) shows how the sacrificial layer 911 is selectively removed using an isotropic etching process, such as wet etching. Because the sacrificial layer 911 is a silicon dioxide film, it can be selectively etched using hydrofluoric acid (HF), ammonium fluoride (NH4F), or mixtures of hydrofluoric acid (HF) and other compounds. As a result, the semiconductor layers 901, 902, 903, and 922 are exposed.

[0080] 10(f), a gate insulating layer 904 made of a dielectric material such as silicon dioxide (SiO2), silicon nitride (SiN), hafnium oxide (HfO2), titanium oxide (TiO2), or a laminate thereof is formed on the exposed surfaces of the semiconductor layers 901, 902, 903, and 922, which were previously covered by the sacrificial layer 911. It is important to note that the thickness of the gate insulating layer 906 in contact with the n+ layer 901 is greater than the thickness of the semiconductor layer 922. The gate insulating layer 904 is then contacted by a gate conductor layer 907 made of highly doped n+ polysilicon, metal nitrides such as tungsten (W), tantalum (Ta), titanium (Ti), WN, TaN, or TiN, or a silicide.

[0081] FIG. 10( g ) shows the state in which the sacrificial layer 912 is selectively removed using an isotropic etching process such as plasma etching or wet etching, as in FIG. 11( e ). As a result, the semiconductor layers 901, 902, 903, and 922 are exposed. Thereafter, as shown in FIG. 10( h ), a gate insulating layer 904 and a gate conductor layer 905 are formed in exactly the same manner as the process in FIG. 10( f ). However, an important point here is that the thickness of the gate insulating layer 904 in contact with the n+ layer 901 is thinner than the thickness of the semiconductor layer 922. As a result, the shortest distance from the gate conductor layer 907 to the semiconductor layer 901 is longer than the shortest distance from the gate electrode layer 705 to the semiconductor layer 901, thereby realizing the structure proposed in the first embodiment.

[0082] In this example, a silicon oxide film and a silicon nitride film are used as examples of the two sacrificial layers, but any type of film, including silicon, may be selected as long as they have etching selectivity with respect to each other.

[0083] In addition, when forming the semiconductor layer 903, a method can also be applied in which a layered structure of crystalline silicon (Si), crystalline silicon germanium (SiGe), an alumina film (Al2O3), etc. is first created, and then the SiGe and AlO3 are used as sacrificial films and selectively removed in sequence to form a sacrificial gate insulating layer and a gate conductor (see, for example, non-patent document 9).

[0084] FIG. 11 shows an application example of the third embodiment. Here, instead of the semiconductor layer 901 in FIG. 10( a), a sacrificial layer 903 is deposited on sacrificial layers 901 and 902 to create a stacked structure. Then, as shown in FIG. 11( b), a vertical bit line hole (or opening) 920 is formed, similar to FIG. 10( b). Then, as shown in FIG. 11( c), a metal layer 911 is filled into the vertical bit line hole 920. For example, this shows a method in which a high-melting-point metal such as tungsten (W) is filled by a CVD method or the like. Using the metal layer 911 for the bit line achieves lower bit line resistance.

[0085] Thereafter, as shown in Figure 11(d), sacrificial layer 913 is selectively removed, leaving sacrificial layers 911 and 912. Next, silicon layers, n-layer 922, p-layer 902, and n-layer 903, are formed using metal-assisted epitaxial technology (see, for example, Non-Patent Document 10) and in-situ doping technology, with different dopants used. After that, a cell can be fabricated using the same processes as those shown in Figures 10(e) to 10(h).

[0086] 10 or 11, the process of stacking sacrificial layers and silicon layers is repeated multiple times, and a process of forming bit line holes is performed on the multi-layer stack structure, so it is easy to imagine that the three-dimensional memory cell array shown in the second embodiment can be realized. Increasing the initial number of stacked layers makes it possible to realize a higher density memory without increasing the cell area in plan view.

[0087] The third embodiment of the present invention has the following features.

[0088] (Feature 1) All of the components of the memory according to the third embodiment of the present invention can be formed by a standard MOS process. Furthermore, if a stacked structure is formed by repeatedly forming sacrificial layers and semiconductor layers, stacked cells can be realized without changing the area in a plan view, and a high-density cell array can be realized.

[0089] (Feature 2) The gate conductor layer and gate insulating layer connected to the word line, which are components of the memory according to the third embodiment of the present invention, and the gate conductor layer and gate insulating layer connected to the plate line are formed separately, so that optimal conditions can be selected for writing, reading, and erasing the memory cell.

[0090] (Feature 3) There is a wide range of materials to be selected for filling the bit line holes, and low-resistance materials can be used.

[0091] According to the present invention, it is possible to provide a semiconductor memory device that is denser, faster, and has a wider operating margin than conventional devices.

[0092] 1 First semiconductor layer 2 Second semiconductor layer 3 Third semiconductor layer 4 First gate insulating layer 5 First gate conductor layer 6 Second gate insulating layer 7 Second gate conductor layer 18 Metal layer 19 Metal layer 21 n-layer 22 n-layer 23 n-layer 111a, 112a n-layer 211a, 211b, 211c, 211c p-layer 31a, 31b, 31c, 31d n-layer 41a, 41b, 41c, 41d Gate insulating layer 51a, 51b, 51c, 51d Gate conductor layer 61a, 61b, 61c, gate insulating layer 71a, 71b, 71c, gate conductor layer D1a, D1b, D21, D22 Insulating layer 81 Inversion layer 83 Hole group 84 Inversion layer 85 Electron group 901 Semiconductor layer 902 p layer 903 n layer 904 Dielectric layer 905 Gate conductor body 906 Dielectric layer 907 Gate conductor layer 911, 912, 913 Sacrificial layer 920 Bit line hole SL, SLa, SLB, SLc, SLd Source line PL, PLa, PLB, PLc, PLd Plate line WL, WLa, WLB, WLc, WLd Word line BL, BL11, BL12, BL13, BL21, BL22, BL23 Bit line

Claims

1. A memory cell comprising: a first semiconductor region extending in a direction perpendicular to a substrate; a second semiconductor region surrounding and connected to a portion of the periphery of the first semiconductor region; a third semiconductor region surrounding and connected to a portion of the periphery of the second semiconductor region; a first dielectric film covering a portion of an upper surface of the second semiconductor region; a first gate conductor layer in contact with an upper surface of the first dielectric film; a second dielectric film covering a portion of a lower surface of the second semiconductor region; and a second gate conductor layer in contact with the second dielectric film and located at a minimum distance from the first semiconductor region that is greater than the minimum distance between the second dielectric film and the first semiconductor region, a source line is connected to the third semiconductor region, a bit line is connected to the second wiring conductor layer, a word line is connected to the first gate conductor layer, and a plate line is connected to the second gate conductor layer; voltages are applied to the source line, the bit line, the plate line, the word line, and a control line, respectively, to perform a write operation, an erase operation, and a read operation; and a voltage is applied to only one of the source line and the bit line during an erase operation of the memory.

2. A memory cell using the semiconductor element described in claim 1, characterized in that the polarity of the voltages applied to the bit line and the word line during read and write operations is the same, and the polarity of the voltage applied to them and the plate line is different.

3. A memory cell using a semiconductor element as claimed in claim 1, wherein during an erase operation, a voltage of the same polarity as that of said plate line is applied to either said source line or said bit line.

4. A memory cell using a semiconductor element according to claim 1, wherein the second insulating layer has a thickness greater than that of the first insulating layer.

5. A memory cell using a semiconductor element as claimed in claim 1, wherein the majority carriers in said first semiconductor region and said third semiconductor region are the same and are different from the majority carriers in said second semiconductor region.

6. A memory cell using a semiconductor element according to claim 1, characterized in that a first metal layer is used in place of said first semiconductor region.

7. A memory cell using a semiconductor element according to claim 6, characterized in that the first semiconductor layer is used around the first metal layer.

8. A memory cell using a semiconductor element according to claim 1, further comprising the first metal layer connected to the inside of the first semiconductor region.

9. A memory cell using a semiconductor element according to claim 1, wherein the periphery of said third semiconductor region is covered with a metal layer.

10. A memory device using semiconductor elements, characterized in that a plurality of memory cells as claimed in claim 1 are laid out on a plane, the second semiconductor layer, the third semiconductor layer, the first dielectric film, the first gate conductor layer, the second dielectric film and the second gate conductor layer are shared by a plurality of horizontally adjacent memory cells, and further the memory cells are separated in the vertical direction by a first insulating layer except for the first semiconductor layer, and the first semiconductor layer is shared with memory cells in the vertical direction, thereby stacking a plurality of memory cells in the vertical direction.

11. A memory device using semiconductor elements, characterized in that the memory cells according to claim 10 are arranged in the horizontal direction and separated by a second insulator.

12. A memory device using a semiconductor device according to claim 10, wherein the second gate conductor layer is shared by adjacent memory cells in the vertical direction.

13. A method for manufacturing a memory device, comprising the steps of: depositing a plurality of layers of a semiconductor layer to be a second semiconductor layer and a first sacrificial layer or a second sacrificial film layer alternately to form a laminated structure; forming vertical bit line holes penetrating the laminated structure using a trench process, and introducing impurities into the semiconductor layer using an isotropic doping process penetrating from the bit line holes; and then filling the bit line holes with a semiconductor or metal layer, removing a selected portion of the deposited insulating layer, and forming a dielectric film and a gate conductor layer.

14. The method of claim 12, wherein the bit line regions are comprised of one of metal or polysilicon.

15. The method of manufacturing a memory device according to claim 12, wherein the first sacrificial film and the second sacrificial film have different etching characteristics.

16. The method for manufacturing a memory device according to claim 13, wherein the first sacrificial film and the second semiconductor layer material, or the second sacrificial film and the second semiconductor material, have different etching characteristics.

17. A method for manufacturing a semiconductor memory device, comprising the steps of alternately depositing three or more sacrificial layers to form a stacked structure, forming vertical bit line holes penetrating the stacked structure using a trench process and filling the holes with a semiconductor or metal layer, selectively removing one of the layers and then replacing it with a semiconductor layer while simultaneously carrying out a doping process thereon, and removing a selected portion of the deposited insulating layer and forming a dielectric film and a gate conductor layer.

18. The method for manufacturing a memory device according to claim 17, wherein the plurality of sacrificial film materials have different etching characteristics from one another.

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