Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which is capable of suppressing the occurrence of a structural defect.　Disclosed is a multilayer ceramic capacitor 1 in which if a straight line that passes through a central part in a length direction L and in a width direction W of a laminate 2 and extends in a lamination direction T is defined as a reference line, an arbitrary point on a peripheral edge part of an internal electrode 15 is defined as a reference point, a direction in which the reference point and the reference line SL are aligned is defined as a reference direction, a distance between the reference point and the reference line SL is defined as a reference distance, and a region of the internal electrode 15 in which the distance in the reference direction from the reference point is less than 5% of the reference distance is defined as a first region, a region of the internal electrode 15 in which the distance in the reference direction from the reference point is not less than 5% but less than 15% of the reference distance is defined as a second region, and a region of the internal electrode 15 in which the distance in the reference direction from the reference point is not less than 15% of the reference distance is defined as a third region, the dimension of the first region 20a in the lamination direction T is thinner than the dimension of the second region 20b in the lamination direction T, and the dimension of the second region 20b in the lamination direction T is thinner than the dimension of the third region 20c in the lamination direction T in an end surface internal electrode 20.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] There is a three-terminal multilayer ceramic capacitor that includes a laminate in which dielectric layers each having an internal electrode exposed at an end face of the laminate and a dielectric layer each having an internal electrode exposed at a side face of the laminate are alternately stacked, and includes end face external electrodes arranged on the end faces and side face external electrodes arranged on the side faces (see, for example, Patent Document 1). With this configuration, it is possible to reduce the equivalent series inductance (ESL) of the multilayer ceramic capacitor.

[0003] JP 2016-127262 A

[0004] Multilayer ceramic capacitors are obtained by stacking dielectric sheets on which internal electrodes are printed. Steps may be formed on the dielectric sheets due to the internal electrodes. Therefore, when the dielectric sheets are stacked, the accumulation of these steps may cause structural defects in the multilayer ceramic capacitor.

[0005] In particular, in a three-terminal multilayer ceramic capacitor, structural defects may occur in different ways in the regions near each end face and the regions near each side face of the laminate, which may increase the risk of structural defects such as voids.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of structural defects.

[0007] In order to achieve the above object, a multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor comprising: an inner layer portion including a plurality of dielectric layers and a plurality of internal electrodes stacked alternately; a laminate having first and second main surfaces opposed to each other in the stacking direction; a first side surface and a second side surface opposed to each other in a width direction perpendicular to the stacking direction; and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the stacking direction and the width direction; a pair of side surface external electrodes provided on each of the side surfaces; and a pair of end surface internal electrodes provided on each of the end surfaces, wherein the plurality of internal electrodes include end surface internal electrodes exposed on both of the end surfaces and side surface internal electrodes exposed on both of the side surfaces; and wherein a straight line extending in the stacking direction that passes through a position that is a center of the laminate in the length direction and a center of the width direction is defined as a reference line, and a pair of the laminated electrodes extending parallel to the stacking direction is defined at a position that overlaps with the reference line. a cross section of the body is defined as a reference cross section, a direction in the reference cross section perpendicular to the stacking direction is defined as a reference direction, a distance in the reference cross section between an end of the internal electrode in the reference direction and the reference line is defined as a reference distance, a region of the internal electrode in the reference cross section where the distance in the reference direction from the end in the reference direction is less than 5% of the reference distance is defined as a first region, a region where the distance in the reference direction from the end in the reference direction is 5% or more and less than 15% of the reference distance is defined as a second region, and a region where the distance in the reference direction from the end in the reference direction is 15% or more of the reference distance is defined as a third region, then, in the end face internal electrode, the dimension in the stacking direction of the first region is thinner than the dimension in the stacking direction of the second region adjacent to the first region, and the dimension in the stacking direction of the second region is thinner than the dimension in the stacking direction of the third region adjacent to the second region.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of structural defects.

[0009] 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment; FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1; FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1; FIG. 4 is a cross-sectional view taken along an end face internal electrode 20 of a laminate 2; and FIG. 5 is a cross-sectional view taken along a side face internal electrode 50 of a laminate 2.

[0010] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described with reference to FIGS.

[0011] (Multilayer Ceramic Capacitor 1) As shown in Fig. 1, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a so-called three-terminal structure. The multilayer ceramic capacitor 1 includes a laminate 2, a pair of end surface external electrodes 3, and a pair of side surface external electrodes 4. The laminate 2 is substantially rectangular parallelepiped-shaped and has six outer surfaces. As shown in Fig. 2, the laminate 2 includes an inner layer portion 11 in which dielectric layers 14 and internal electrodes 15 are stacked.

[0012] In this specification, the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the length direction L. The direction perpendicular to both the length direction L and the stacking direction T is referred to as the width direction W.

[0013] Of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides in the stacking direction T are referred to as the first main surface AA and the second main surface AB, a pair of outer surfaces extending in the stacking direction T and on both sides in the width direction W are referred to as the first side surface BA and the second side surface BB, and a pair of outer surfaces extending in the stacking direction T and on both sides in the length direction L are referred to as the first end surface CA and the second end surface CB. The first main surface AA and the second main surface AB may be collectively referred to as "each main surface A." The first side surface BA and the second side surface BB may be collectively referred to as "each side surface B." The first end surface CA and the second end surface CB may be collectively referred to as "each end surface C."

[0014] The pair of end surface external electrodes 3 is provided on each end surface C. The pair of side surface external electrodes 4 is provided on each side surface B.

[0015] A cross section parallel to the length direction L and the stacking direction T and passing through the center of the width direction W of the first draw section 22 is referred to as the "first reference cross section S1." The cross section in Figure 2 is the first reference cross section S1. A cross section parallel to the width direction W and the stacking direction T and passing through the center of the length direction L of the second draw section 52 is referred to as the "second reference cross section S2." The cross section in Figure 3 is the second reference cross section S2.

[0016] (Laminate 2) The laminate 2 has an inner layer portion 11 and a pair of outer layer portions 12 arranged on either side of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. The corners are portions where three surfaces of the laminate intersect. The ridges are portions where two surfaces of the laminate intersect.

[0017] 2 and 3, the inner layer portion 11 has a plurality of dielectric layers 14 and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are alternately stacked.

[0018] (Dielectric Layer 14) The dielectric layer 14 is formed of a dielectric ceramic containing, for example, BaTiO3 as a main component. The dielectric ceramic may contain a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like as a secondary component.

[0019] (Internal Electrode 15) The internal electrode 15 is formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0020] The internal electrode 15 has a plurality of end face internal electrodes 20 and a plurality of side face internal electrodes 50. The end face internal electrodes 20 and the side face internal electrodes 50 are alternately arranged in the stacking direction T. The end face internal electrodes 20 and the side face internal electrodes 50 may be collectively referred to as "internal electrodes 15."

[0021] (End Face Internal Electrode 20) As shown in Fig. 4, the end face internal electrode 20 extends between both end faces C in the length direction L of the laminate 2. Each end of the end face internal electrode 20 in the length direction L is exposed at each end face C. The end face internal electrode 20 is spaced a certain distance from both side faces B in the width direction W. The end face internal electrode 20 has a first opposing portion 21 and two first lead portions 22.

[0022] The first opposing portion 21 is a portion of the end face internal electrode 20 that faces the side face internal electrode 50 adjacent to it in the stacking direction T. The first opposing portion 21 is located in the center between the end faces C. Each first lead portion 22 is a portion of the end face internal electrode 20 that is led out from the first opposing portion 21 to each end face C side. Each first lead portion 22 is exposed at each end face C.

[0023] 5 , each end of the side surface internal electrode 50 in the width direction W is exposed to each side surface B. The side surface internal electrode 50 is spaced a certain distance from both end surfaces C in the length direction L. The side surface internal electrode 50 has a second opposing portion 51 and two second lead portions 52.

[0024] The second opposing portion 51 is a portion of the side surface internal electrode 50 that faces the end face internal electrode 20 adjacent to it in the stacking direction T. The second opposing portion 51 is located in the center between the side surfaces B. Each second extraction portion 52 is a portion of the side surface internal electrode 50 that is extracted from the second opposing portion 51 to each side surface B side. Each second opposing portion 51 is exposed to each side surface B.

[0025] The first opposing portion 21 and the second opposing portion 51 may be collectively referred to as "opposing portions 21, 51." The first drawn-out portion 22 and the second drawn-out portion 52 may be collectively referred to as "draw-out portions 22, 52."

[0026] (Outer Layer Portion 12) The outer layer portion 12 is formed of the same material as the dielectric layer 14 of the inner layer portion 11. Note that no inner electrode 15 is disposed in the outer layer portion 12.

[0027] (End surface external electrodes 3) Each end surface external electrode 3 is disposed on a respective end surface C of the laminate 2. Each end surface external electrode 3 covers not only the end surface C but also a portion of the end surface C side of the main surface A and the side surface B. A first lead portion 22 is connected to each end surface external electrode 3. Each end surface external electrode 3 includes a base electrode layer 31 formed in contact with the surface of the laminate 2, a first plating layer 32 disposed on the base electrode layer 31, and a second plating layer 33 disposed on the first plating layer 32.

[0028] The base electrode layer 31 is a baked layer containing, for example, a conductive metal such as Cu (copper) and glass. The first plating layer 32 is, for example, a Ni (nickel) plating layer. The second plating layer 33 is, for example, a Sn (tin) plating layer.

[0029] (Side surface external electrode 4) Each side surface external electrode 4 is disposed on each side surface B of the laminate 2. Each side surface external electrode 4 covers not only the side surface B but also a portion of the main surface A on the side surface B side. A second lead portion 52 is connected to each side surface external electrode 4. Each side surface external electrode 4 includes a base electrode layer 41 formed in contact with the surface of the laminate 2, a first plating layer 42 disposed on the base electrode layer 41, and a second plating layer 43 disposed on the first plating layer 42.

[0030] The base electrode layer 41 is a baked layer containing, for example, a conductive metal such as Cu and glass. The first plating layer 42 is, for example, a Ni plating layer. The second plating layer 43 is, for example, a Sn plating layer.

[0031] The end surface external electrode 3 and the side surface external electrode 4 may be collectively referred to as "external electrodes 3, 4."

[0032] (Thickness of Internal Electrode 15) Here, the thickness of the internal electrode 15 becomes thinner as it approaches each side surface B and each end surface C of the laminate 2. The configuration of the end surface internal electrode 20 and the side surface internal electrode 50 will be explained in more detail below. In this specification, the thickness of the internal electrode 15 means the dimension of the internal electrode 15 in the stacking direction T.

[0033] A straight line extending in the stacking direction T that passes through a position that is the center of the laminate 2 in the length direction L and the center of the laminate 2 in the width direction W is defined as the "reference line SL." An arbitrary point on the peripheral edge of the internal electrode 15 is defined as the "reference point." A direction perpendicular to the stacking direction T and in which the reference point and the reference line SL are aligned is defined as the "reference direction." The distance between the reference point and the reference line SL is defined as the "reference distance."

[0034] Of the internal electrode 15, the region where the distance from the reference point in the reference direction is less than 5% of the reference distance is defined as the "first region," the region where the distance from the reference point in the reference direction is 5% or more but less than 15% of the reference distance is defined as the "second region," and the region where the distance from the reference point in the reference direction is 15% or more of the reference distance is defined as the "third region."

[0035] The shape of the periphery of the second region is a shape obtained by reducing the shape of the periphery of the first region around the reference line SL, and the shape of the periphery of the third region is a shape obtained by reducing the shape of the periphery of the second region around the reference line SL (see FIGS. 4 and 5). The first, second, and third regions of the end face internal electrode 20 are referred to as the first region 20a, the second region 20b, and the third region 20c (see FIG. 4). The first, second, and third regions of the side face internal electrode 50 are referred to as the first region 50a, the second region 50b, and the third region 50c (see FIG. 5).

[0036] First, the state of the internal electrodes 15 in a cross section of the laminate 2 (i.e., the cross section in FIG. 2 ) extending parallel to the stacking direction T and the length direction L and passing through the center of the laminate 2 in the width direction will be described. The laminate 2 is configured symmetrically with respect to the length direction L. Therefore, only the region of the laminate 2 on the first end face CA side will be described, and a description of the region on the second end face CB side will be omitted.

[0037] In the cross section of Fig. 2, a reference line passes through the center of the laminate 2 in the longitudinal direction L. The reference direction is the longitudinal direction L. The reference point is, for example, the end of each internal electrode 15 on the first end face CA side. The reference distance is, for example, the distance in the longitudinal direction L from the end of each internal electrode 15 on the first end face CA side to the center in the longitudinal direction L, which is half the dimension of each internal electrode 15 in the longitudinal direction L.

[0038] 2, a region of the end face internal electrode where the distance in the length direction L from the end on the first end face CA side is less than 5% of half the dimension of the end face internal electrode 20 in the length direction L is the first region 20a, which is referred to as the "first region 20aa." A region of the end face internal electrode 20 where the distance in the length direction L from the end on the first end face CA side is 5% or more and less than 15% of half the dimension of the end face internal electrode 20 in the length direction L is the second region 20b, which is referred to as the "second region 20ba." A region where the distance in the length direction L from the end on the first end face CA side is 15% or more of half the dimension of the end face internal electrode 20 in the length direction L is the third region 20c, which is referred to as the "third region 20ca." The boundary between the first region 20 aa and the second region 20 ba and the boundary between the second region 20 ba and the third region 20 ca are both located in the first lead-out portion 22 .

[0039] In the end face internal electrode 20, the dimension of the first region 20aa in the stacking direction T is thinner than the dimension of the second region 20ba adjacent to the first region 20aa in the stacking direction T, and the dimension of the second region 20ba in the stacking direction T is thinner than the dimension of the third region 20ca adjacent to the second region 20ba in the stacking direction T.

[0040] In this case, the dimension of the end face internal electrode 20 in the stacking direction T decreases as it approaches the first end face CA. The dimension of the first lead portion 22 in the stacking direction T decreases as it approaches the first end face CA. This reduces the step caused by the end face internal electrode 20, allowing appropriate pressure to be applied to the dielectric layer near the internal electrode when the ceramic green sheets are compressed (described later). This makes it possible to suppress the occurrence of structural defects such as the generation of voids. Therefore, it is possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of structural defects.

[0041] In the end face internal electrode 20, the dimension of the first region 20aa in the stacking direction T is 10% or more and less than 50% of the dimension of the third region 20ca in the stacking direction T.

[0042] In the end face internal electrode 20, the dimension of the second region 20ba in the stacking direction T is 50% or more and less than 80% of the dimension of the third region 20ca in the stacking direction T.

[0043] As a result, the step caused by the end face internal electrode 20 can be more suitably reduced.

[0044] 2, the region of the side internal electrode 50 where the distance in the length direction L from the end on the first end face CA side is less than 5% of half the dimension of the side internal electrode 50 in the length direction L is the first region 50a, which is referred to as the "first region 50aa." The region of the side internal electrode 50 where the distance in the length direction L from the end on the first end face CA side is 5% or more and less than 15% of half the dimension of the side internal electrode 50 in the length direction L is the second region 50b, which is referred to as the "second region 50ba." The region of the side internal electrode 50 where the distance in the length direction L from the end on the first end face CA side is 15% or more of half the dimension of the side internal electrode 50 in the length direction L is the third region 50c, which is referred to as the "third region 50ca." The first region 50aa, the second region 50ba, and the third region 50ca each constitute a part of the second lead portion 52.

[0045] In the side surface internal electrode 50 (second lead portion 52), the dimension of the first region 50aa in the stacking direction T is thinner than the dimension of the second region 50ba adjacent to the first region 50aa in the stacking direction T, and the dimension of the second region 50ba in the stacking direction T is thinner than the dimension of the third region 50ca adjacent to the second region 50ba in the stacking direction T. Therefore, the dimension of the side surface internal electrode 50 (second lead portion 52) in the stacking direction T becomes smaller as it approaches the first end face CA.

[0046] In the side surface internal electrode 50, the dimension of the first region 50aa in the stacking direction T is 10% or more and less than 50% of the dimension of the second region 50ba in the stacking direction T.

[0047] In the side surface internal electrode 50, the dimension of the second region 50ba in the stacking direction T is 50% or more and less than 80% of the dimension of the third region 50ca in the stacking direction T.

[0048] As a result, the step caused by the side surface internal electrode 50 can be suitably reduced, and the occurrence of structural defects can be suppressed.

[0049] Next, the state of the internal electrodes 15 in a cross section of the laminate 2 (i.e., the cross section in FIG. 3 ) extending parallel to the stacking direction T and the width direction W and passing through the center of the longitudinal direction L of the laminate 2 will be described. The laminate 2 has a symmetrical configuration with respect to the width direction W. Therefore, only the region of the laminate 2 on the first side face BA side will be described, and a description of the region on the second side face BB side will be omitted.

[0050] 3, the reference line passes through the center of the laminate 2 in the width direction W. The reference direction is the width direction W. The reference point is, for example, the end of each internal electrode 15 on the first side face BA side. The reference distance is, for example, the distance in the width direction W from the end of each internal electrode 15 on the first side face BA side to the center in the width direction W, which is half the dimension of each internal electrode 15 in the width direction W.

[0051] 3, a region of the end face internal electrode 20 where the distance in the width direction W from the end on the first side face BA side is less than 5% of half the dimension of the end face internal electrode 20 in the width direction W is the first region 20a, which is referred to as the "first region 20ab." A region of the end face internal electrode 20 where the distance in the width direction W from the end on the first side face BA side is 5% or more and less than 15% of half the dimension of the end face internal electrode 20 in the width direction W is the second region 20b, which is referred to as the "second region 20bb." A region of the end face internal electrode 20 where the distance in the width direction W from the end on the first side face BA side is 15% or more of half the dimension of the end face internal electrode 20 in the width direction W is the third region 20c, which is referred to as the "third region 20cb." The first region 20ab, the second region 20bb, and the third region 20cb each constitute a part of the first opposing portion 21.

[0052] In the end face internal electrode 20, the dimension of the first region 20ab in the stacking direction T is thinner than the dimension of the second region 20bb adjacent to the first region 20ab in the stacking direction T, and the dimension of the second region 20bb in the stacking direction T is thinner than the dimension of the third region 20cb adjacent to the second region 20bb in the stacking direction T. Therefore, the dimension of the end face internal electrode 20 (first opposing portion 21) in the stacking direction T becomes smaller as it approaches the first side face BA.

[0053] In the end face internal electrode 20, the dimension of the first region 20ab in the stacking direction T is 10% or more and less than 50% of the dimension of the second region 20bb in the stacking direction T.

[0054] In the end face internal electrode 20, the dimension of the second region 20bb in the stacking direction T is 50% or more and less than 80% of the dimension of the third region 20cb in the stacking direction T.

[0055] As a result, the step due to the end face internal electrode 20 can be suitably reduced, and the end face internal electrode 20 and the dielectric layer 14 can be more suitably adhered to each other, thereby suppressing the occurrence of structural defects.

[0056] 3, a region of the side internal electrode 50 where the distance in the width direction W from the end on the first side face BA side is less than 5% of half the dimension of the side internal electrode 50 in the width direction W is a first region 50a, which is referred to as a "first region 50ab." A region of the side internal electrode 50 where the distance in the width direction W from the end on the first side face BA side is 5% or more and less than 15% of half the dimension of the side internal electrode 50 in the width direction W is a second region 50b, which is referred to as a "second region 50bb." A region of the side internal electrode 50 where the distance in the width direction W from the end on the first side face BA side is 15% or more of half the dimension of the side internal electrode 50 in the width direction W is a third region 50c, which is referred to as a "third region 50c." The boundary between the first region 50ab and the second region 50bb and the boundary between the second region 50bb and the third region 50cb are both located in the second lead-out portion 52.

[0057] In the side internal electrode 50 (second extraction portion 52), the dimension in the stacking direction T of the first region 50ab is thinner than the dimension in the stacking direction T of the second region 50bb adjacent to the first region 50ab, and the dimension in the stacking direction T of the second region 50bb is thinner than the dimension in the stacking direction T of the third region 50cb adjacent to the second region 50bb.

[0058] Therefore, the side surface internal electrode 50 has a dimension in the stacking direction T that decreases toward the first side surface BA. The second lead portion 52 has a dimension in the stacking direction T that decreases toward the first side surface BA.

[0059] In the side surface internal electrode 50, the dimension of the first region 50ab in the stacking direction T is 10% or more and less than 50% of the dimension of the second region 50bb in the stacking direction T.

[0060] In the side surface internal electrode 50, the dimension of the second region 50bb in the stacking direction T is 50% or more and less than 80% of the dimension of the third region 50cb in the stacking direction T.

[0061] As a result, the step caused by the side internal electrode 50 can be suitably alleviated, and pressure can be suitably applied to the dielectric layer near the internal electrode when the ceramic green sheets are pressure-bonded (described later), thereby suppressing the occurrence of structural defects.

[0062] (Method for measuring the thickness of the internal electrode 15) First, the laminate is polished to expose the observation surface described below. Next, the exposed observation surface is observed under a microscope to measure the thickness of the internal electrode. At this time, the thickness of the internal electrode can be determined as the average value of the thicknesses of the internal electrode measured at multiple locations within a predetermined range. Specifically, the observation surface is observed using a scanning electron microscope (SEM). The observation magnification is 10,000 times. The thickness of the internal electrode 15 is measured in an area with a field of view size of 10 μm × 10 μm. The thickness of the internal electrode 15 is measured at any three points. The average value of the measurements at the three points is defined as the thickness of the internal electrode 15.

[0063] The observation surface is a cross section parallel to the stacking direction T. The state of each end of the first lead portion 22 of the end face internal electrode 20 in the length direction L and the state of each end of the second opposing portion 51 of the side face internal electrode 50 in the length direction L can be observed, for example, by using the LT cross section passing through the center of the width direction W of the laminate 2 as the observation surface.

[0064] The state of each end of the first opposing portion 21 of the end face internal electrode 20 in the width direction W and the state of each end of the second extraction portion 52 of the side face internal electrode 50 in the width direction W can be observed, for example, using the WT cross section passing through the center of the longitudinal direction L of the laminate 2 as an observation surface.

[0065] The state of each end of the second lead portion 52 of the side surface internal electrode 50 in the width direction W can be observed, for example, by using an LT cross section passing through the third region 50c of the second lead portion 52 of the side surface internal electrode 50 as an observation surface.

[0066] Note that the cross section is separated from the reference line. However, in the cross section, a region of the side internal electrode 50 where the distance in the width direction W from the end on the first side face BA side is less than 5% of half the dimension of the side internal electrode 50 in the width direction W corresponds to the first region 50a. A region of the side internal electrode 50 where the distance in the width direction W from the end on the first side face BA side is 5% or more but less than 15% of half the dimension of the side internal electrode 50 in the width direction W corresponds to the second region 50b. A region of the side internal electrode 50 where the distance in the width direction W from the end on the first side face BA side is 15% or more of half the dimension of the side internal electrode 50 in the width direction W corresponds to the third region 50c. Therefore, the thicknesses of the first region 50a, the second region 50b, and the third region 50c can be observed on the observation surface.

[0067] The state of each end of the first lead portion 22 of the end surface internal electrode 20 in the width direction W can be observed, for example, by using a WT cross section passing through the third region 50c of the first lead portion 22 of the end surface internal electrode 20 as an observation surface.

[0068] Note that this cross section is separated from the reference line. However, even in this cross section, a region of the side internal electrode (more specifically, the second lead portion 52) where the distance in the length direction L from the end portion on the first end face CA side is less than 5% of half the dimension of the side internal electrode 50 in the length direction L corresponds to the first region 50a. A region of the side internal electrode 50 where the distance in the length direction L from the end portion on the first end face CA side is 5% or more but less than 15% of half the dimension of the side internal electrode 50 in the length direction L corresponds to the second region 50b. A region of the side internal electrode 50 where the distance in the length direction L from the end portion on the first end face CA side is 15% or more of half the dimension of the side internal electrode 50 in the length direction L corresponds to the third region 50c. Therefore, the thicknesses of the first region 50a, the second region 50b, and the third region 50c can be observed on the observation surface.

[0069] Furthermore, the observation plane does not have to be the LT cross section or the WT cross section, but may be a cross section intersecting the length direction L and the width direction W, respectively.

[0070] (Method for Manufacturing Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described.

[0071] (Internal electrode pattern forming process) First, a ceramic green sheet is prepared by forming a ceramic slurry into a sheet shape. Next, patterns of the end surface internal electrodes 20 and the side surface internal electrodes 50 are printed on the ceramic green sheet with a conductive paste. This results in a ceramic green sheet on which the end surface internal electrodes 20 are arranged and a ceramic green sheet on which the side surface internal electrodes 50 are arranged. The internal electrode patterns are formed by, for example, gravure printing or screen printing.

[0072] Here, patterns of the end face internal electrodes 20 and the side face internal electrodes 50 are further printed using a conductive paste on the patterns of the printed end face internal electrodes 20 and the side face internal electrodes 50. The pattern of the internal electrodes printed the second time is printed slightly smaller than the pattern of the internal electrodes printed the first time, and is printed, for example, as a shape obtained by reducing the pattern of the internal electrodes printed the first time, with the center of the pattern of the internal electrodes printed the first time in the length direction L and the width direction W as the center. The peripheral edge of the pattern of the internal electrodes printed the first time and the peripheral edge of the pattern of the internal electrodes printed the second time are separated by a distance that is approximately 5% of half the distance between the peripheral edge and the center of the pattern of the internal electrode printed the first time.

[0073] Similarly, patterns of the end face internal electrodes 20 and the side face internal electrodes 50 are further printed with conductive paste on the patterns of the end face internal electrodes 20 and the side face internal electrodes 50 printed the second time. The pattern of the internal electrodes printed the third time is printed slightly smaller than the pattern of the internal electrodes printed the second time, and is printed as a similar, reduced shape of the pattern of the internal electrodes printed the second time, for example, centered on the center of the pattern of the internal electrodes printed the second time in the length direction L and the width direction W. The peripheral edge of the pattern of the internal electrodes printed the first time and the peripheral edge of the pattern of the internal electrodes printed the third time are separated by a distance that is approximately 15% of half the distance between the peripheral edge and the center of the pattern of the internal electrode printed the first time.

[0074] As a result, an internal electrode pattern is formed on the ceramic green sheet, the thickness of which decreases toward the periphery. The thickness of the internal electrode pattern printed in each iteration may be different. The thickness of the internal electrode pattern can be adjusted by adjusting the amount of conductive paste applied.

[0075] (Laminating Process) Next, the ceramic green sheets on which the end face internal electrodes 20 are arranged and the ceramic green sheets on which the side face internal electrodes 50 are arranged are alternately laminated. Next, on both sides of the laminated ceramic green sheets in the lamination direction T, ceramic green sheets for outer layer portions that will become the outer layer portions 12 are laminated. The ceramic green sheets for outer layer portions are thermocompression bonded to the ceramic green sheets. This results in a mother block.

[0076] Each outer layer portion 12 may be formed by laminating a plurality of ceramic green sheets or by a single ceramic green sheet. The ceramic green sheets for the inner layer portion and the ceramic green sheets for the outer layer portion may contain different components.

[0077] (Mother Block Cutting Process) Next, the mother block is divided along cutting lines corresponding to the dimensions of the laminate. The mother block is cut, for example, in the length direction L and the width direction W. This results in multiple rectangular blocks (referred to as "laminated chips"). It is preferable that the corners and ridges of the laminated chips are rounded, for example, by barrel polishing.

[0078] (Laminate Firing Step) Next, the laminated chip is heated at a predetermined firing temperature in a nitrogen atmosphere for a predetermined time, thereby obtaining the laminate 2.

[0079] (Base electrode layer forming process) Next, a base electrode layer 41 of the side surface external electrode 4 is formed on each side surface B of the laminate 2. Each base electrode layer 41 is formed so as to cover not only the side surface B but also a portion of the side surface B side of the main surface A. Next, a base electrode layer 31 of the end surface external electrode 3 is formed on each end surface C of the laminate 2. Each base electrode layer 31 is formed so as to cover not only the end surface C but also a portion of the end surface C side of the main surface A and the side surface B.

[0080] (Base Electrode Layer Baking Process) Next, the laminate 2 on which the base electrode layers 31 and 41 have been formed is heated in a nitrogen atmosphere at a predetermined firing temperature for a predetermined time, thereby baking the base electrode layers 31 and 41 to the laminate 2.

[0081] (Plating Layer Forming Process) Next, the Ni plating layer 32 is formed on the base electrode layer 31. The Ni plating layer 42 is formed on the base electrode layer 41. The Ni plating layer 32 and the Ni plating layer 42 are formed by, for example, barrel plating. Next, the Sn plating layer 33 is formed on the Ni plating layer 32. The Sn plating layer 43 is formed on the Ni plating layer 42. The Sn plating layer 33 and the Sn plating layer 43 are formed by, for example, barrel plating. As a result, the end surface external electrode 3 and the side surface external electrode 4 are formed on the laminate 2.

[0082] As a result of the above, the multilayer ceramic capacitor 1 shown in FIG. 1 is obtained.

[0083] <Experimental Examples> Multilayer ceramic capacitors were fabricated as samples of experimental examples using the above-mentioned manufacturing method. In each experimental example, the thickness of the first region 20a and the thickness of the second region 20b of the end face internal electrode 20 were changed, while the thickness of the third region 20c of the end face internal electrode 20 and the thickness of each region of the side face internal electrode 50 were constant. For each experimental example, the presence or absence of voids in the laminate, the electrostatic capacitance (Cap) value of the ceramic capacitor, and the DC resistance (Rdc) value were measured.

[0084] 1. Manufacturing of Multilayer Ceramic Capacitor As a sample of an experimental example, a multilayer ceramic capacitor having the structure shown in FIGS. 1 to 5 and the following specifications was manufactured using the manufacturing method according to the embodiment.

[0085] ・Dimensions of multilayer ceramic capacitor: L×W×T = 1.0 mm×0.5 mm×0.4 mm ・Material of dielectric layer (main component): BaTiO3 ・Rated voltage: 6.3 V ・Thickness of dielectric layer: 1 μm ・End face internal electrodes ・Material: Ni ・Shape: Shape shown in FIG. 4 ・Number of sheets: 65 ・Thickness of third region: 0.65 μm ・Thickness of second region: See table ・Thickness of first region: See table ・Thickness of first region / Thickness of third region × 100: See table ・Thickness of second region / Thickness of third region × 100: See table ・Side face internal electrodes ・Material: Ni ・Shape: Shape shown in FIG. 5 ・Number of sheets: 65 ・Thickness of third region (μm): 0.65 μm ・Thickness of second region (μm): 0.65 μm ・Thickness of first region (μm): 0.65 μm ・End face external electrodes・Base electrode layer: Baked layer containing conductive metal (Cu) and glass component ・Thickness at center of end face: Approximately 25 μm ・Plating layer: Two layers of Ni plating layer and Sn plating layer ・Ni plating layer thickness: 3 μm ・Sn plating layer thickness: 4 μm ・Side external electrode ・Base electrode layer: Baked layer containing conductive metal (Cu) and glass component ・Thickness at center of side face: Approximately 20 μm ・Plating layer: Two layers of Ni plating layer and Sn plating layer ・Ni plating layer thickness: 3 μm ・Sn plating layer thickness: 4 μm

[0086] 2. Evaluation Next, the prepared samples were evaluated according to the following measurement methods.

[0087] <Measurement of Thickness of End Face Internal Electrode 20> Measurement was performed using the method for measuring the thickness of the internal electrode described above. In the LT cross section passing through the center of the width direction W of the laminate 2, the thickness of the internal electrode was measured at three locations in each of the first region, the second region, and the third region. Furthermore, in the WT cross section passing through the center of the length direction L of the laminate 2, the thickness of the internal electrode was measured at three locations in each of the first region, the second region, and the third region. As a result, six measured values ​​were obtained for each region of the end face internal electrode 20. The average of the obtained values ​​was taken as the thickness of each region of the end face internal electrode 20.

[0088] <Measurement of Thickness of Side Internal Electrode 50> Measurement was performed using the above-described method for measuring the thickness of the internal electrode. In an LT cross section passing through the third region 50c of the second lead portion 52 of the side internal electrode 50, the thickness of the internal electrode was measured at three locations per region in each of the first region, the second region, and the third region. In an LT cross section passing through the center of the width direction W of the laminate 2, the thickness of the internal electrode was measured at three locations per region in each of the first region, the second region, and the third region. In a WT cross section passing through the third region 50c of the second opposing portion 51 of the side internal electrode 50, the thickness of the internal electrode was measured at three locations per region in each of the first region, the second region, and the third region. In a WT cross section passing through the center of the length direction L of the laminate 2, the thickness of the internal electrode was measured at three locations per region in each of the first region, the second region, and the third region. As a result, 12 measured values ​​were obtained for each region of the side surface internal electrode 50. The average of the obtained values ​​was taken as the thickness of each region of the side surface internal electrode 50.

[0089] When measuring the thickness of the internal electrodes in the LT cross section, the measurement may be performed in only one of the regions obtained by dividing the laminate 2 into two equal parts in the width direction W. When measuring the thickness of the internal electrodes in the WT cross section, the measurement may be performed in only one of the regions obtained by dividing the laminate 2 into two equal parts in the length direction L.

[0090] <Measurement of Voids> Voids were defined as gaps present in the dielectric layer 14 with lengths of 5 μm or more in both directions. The multilayer ceramic capacitor 1 was polished to expose a WT cross section passing through the center of the length direction L. The polished surface was observed under a microscope to confirm whether voids were present near both ends of the internal electrode 15. The observation magnification was 500x.

[0091] If even one void was present in one laminate 2, the laminate 2 was judged to have "voids." If the number of voids judged to be "voids" among the 50 multilayer ceramic capacitors 1 was zero, the laminate 2 was judged to be "excellent," if there were one to five voids, the laminate 2 was judged to be "good," and if there were six or more voids, the laminate 2 was judged to be "poor."

[0092] <Measurement of Capacitance (Cap) Value of Multilayer Ceramic Capacitor> The capacitance between the end face internal electrode 20 and the side face internal electrode 50 was measured using a C meter. The measurement frequency was 1 kHz, and the measurement voltage was 0.5 V. Thirty multilayer ceramic capacitors 1 were prepared for each experimental example, and measurement was performed once for each multilayer ceramic capacitor 1. The average of the obtained values ​​was used as the capacitance (Cap) value for that experimental example. A capacitance value of 1.00 or more was judged to be "good," and a capacitance value of less than 1.00 was judged to be "poor."

[0093] <Measurement of DC Resistance (Rdc) Value of Multilayer Ceramic Capacitor> A current I of 100 mA was passed between each of the end surface external electrodes 3, while measuring the potential difference V between each of the end surface external electrodes 3. The DC resistance Rdc1 was calculated by calculating Rdc1 = V / I (potential difference / 100 mA) using the average value of 30 measurements. An Rdc1 value of less than 30 mΩ was determined to be "good," and an Rdc1 value of 30 mΩ or more was determined to be "poor."

[0094] A current I of 100 mA was applied between each of the side surface external electrodes 4, while measuring the potential difference V between each of the side surface external electrodes 4. The DC resistance Rdc2 was calculated by calculating Rdc2 = V / I (potential difference / 100 mA) using the average value of 30 measurements. An Rdc2 value of less than 45 mΩ was determined to be "good," and an Rdc2 value of 45 mΩ or more was determined to be "poor."

[0095] 3. Measurement Results Tables 1 and 2 show the thickness of each region of the end face internal electrode 20, the presence or absence of voids, and the evaluation results for capacitance (Cap) and DC resistance (Rdc) for each experimental example. Table 1 shows the value of (thickness of the first region of the end face internal electrode 20) / (thickness of the third region)×100, and Table 2 shows the value of (thickness of the second region of the end face internal electrode 20) / (thickness of the third region)×100.

[0096] Although not shown in Tables 1 and 2, in each experimental example, the thickness of each region of the side surface internal electrode 50 was a constant 0.65 μm. In addition, in Tables 1 and 2 and the following description, the thickness of the first region 20 a of the end face internal electrode 20 may be referred to as “A thickness”, the thickness of the second region 20 b as “B thickness”, the thickness of the third region 20 c as “C thickness”, the value of the thickness of the first region / the thickness of the third region × 100 as “A / C thickness ratio”, and the value of the thickness of the second region of the end face internal electrode 20 / the thickness of the third region × 100 as “B / C thickness ratio”.

[0097]

[0098]

[0099] As shown in Table 1, it was confirmed that the smaller the A / C thickness ratio, the better the results for the presence of voids. The void presence evaluation results were poor when the A / C thickness ratio was 50% or greater, good when the A / C thickness ratio was 46% or less, and excellent when the A / C thickness ratio was 40% or less. The number of multilayer ceramic capacitors judged to have voids was six when the A / C thickness ratio was 50%. It was confirmed that when the A / C thickness ratio exceeded 50%, the number of multilayer ceramic capacitors judged to have voids tended to significantly increase as the A / C thickness ratio increased. This revealed that the occurrence of voids can be effectively suppressed by setting the A / C thickness ratio to less than 50%. Furthermore, since suppressing the occurrence of voids can suppress the occurrence of structural defects, the occurrence of structural defects can be effectively suppressed by setting the A / C thickness ratio to less than 50%. The occurrence of structural defects can be even more effectively suppressed by setting the A / C thickness ratio to 40% or less.

[0100] Regarding capacitance, when the A / C thickness ratio was 6%, it was judged to be unacceptable, and when the A / C thickness ratio was 8% or more, it was judged to be good. Furthermore, when the A / C thickness ratio was 8% or more, the capacitance was stable at a roughly constant value, and when the A / C thickness ratio was 6%, it was significantly smaller than the other experimental examples. This demonstrates that by setting the A / C thickness ratio to 8% or more, it is possible to ensure sufficient capacitance for the multilayer ceramic capacitor.

[0101] Regarding DC resistance (Rdc1), when the A / C thickness ratio was 8% or less, it was judged to be unacceptable, and when the A / C thickness ratio was 10% or more, it was judged to be good. It was confirmed that when the A / C thickness ratio was 10% or more, the DC resistance (Rdc1) remained stable at a roughly constant value, but when the A / C thickness ratio was 6% or less, it tended to decrease significantly as the A / C thickness ratio decreased. Regarding DC resistance (Rdc2), good results were obtained in all experimental examples. This revealed that the DC resistance (Rdc) of a multilayer ceramic capacitor can be sufficiently reduced by setting the A / C thickness ratio to 10% or more.

[0102] Therefore, it has become clear that when the A / C thickness ratio is 10% or more and less than 50%, in other words, when the thickness of the first region 20a in the end face internal electrode 20 is 10% or more and less than 50% of the thickness of the third region 20c, the occurrence of structural defects can be suitably suppressed while sufficiently ensuring the performance of the multilayer ceramic capacitor, and when the thickness of the first region 20a is 10% or more and 40% or less of the thickness of the third region 20c, the occurrence of structural defects can be even more suitably suppressed.

[0103] As shown in Table 2, the presence or absence of voids tended to be better as the B / C thickness ratio decreased. The void presence / absence evaluation results were poor when the B / C thickness ratio was 84% ​​or greater, good when the B / C thickness ratio was 80% or less, and excellent when the B / C thickness ratio was 70% or less. The number of multilayer ceramic capacitors judged to have voids was eight when the B / C thickness ratio was 84% ​​and three when the B / C thickness ratio was 80%. It was confirmed that when the B / C thickness ratio exceeded 80%, the number of multilayer ceramic capacitors judged to have voids tended to significantly increase as the B / C thickness ratio increased. This revealed that the occurrence of voids can be effectively suppressed by setting the B / C thickness ratio to less than 80%. Furthermore, since suppressing the occurrence of voids can suppress the occurrence of structural defects, the occurrence of structural defects can be effectively suppressed by setting the B / C thickness ratio to less than 80%. By setting the B / C thickness ratio to 70% or less, the occurrence of structural defects can be more suitably suppressed.

[0104] Regarding capacitance, when the B / C thickness ratio was 40% or less, it was rated as "unacceptable," and when the B / C thickness ratio was 46% or more, it was rated as "good." It was also confirmed that when the B / C thickness ratio was 46% or more, the capacitance remained stable at a roughly constant value, but when the B / C thickness ratio was 40% or less, it tended to decrease significantly as the B / C thickness ratio decreased. This revealed that by setting the B / C thickness ratio to 8% or more, it was possible to ensure sufficient capacitance for the multilayer ceramic capacitor.

[0105] Regarding DC resistance (Rdc1), when the B / C thickness ratio was 46% or less, it was judged to be unacceptable, and when the B / C thickness ratio was 50% or more, it was judged to be good. It was confirmed that when the B / C thickness ratio was 50% or more, the DC resistance (Rdc1) remained stable at a roughly constant value, but when the B / C thickness ratio was 46% or less, it tended to decrease significantly as the B / C thickness ratio decreased. Regarding DC resistance (Rdc2), good results were obtained in all experimental examples. This revealed that the DC resistance (Rdc) of a multilayer ceramic capacitor can be sufficiently reduced by setting the B / C thickness ratio to 50% or more.

[0106] Therefore, it has become clear that when the B / C thickness ratio is 50% or more and less than 80%, in other words, when the thickness of the second region 20b in the end face internal electrode 20 is 50% or more and less than 80% of the thickness of the third region 20c, the occurrence of structural defects can be suitably suppressed while sufficiently ensuring the performance of the multilayer ceramic capacitor, and when the thickness of the second region 20b is 50% or more and 70% or less of the thickness of the third region 20c, the occurrence of structural defects can be even more suitably suppressed.

[0107] (Effects of the Embodiment) According to the present embodiment, the following effects can be obtained.

[0108] According to this embodiment, in the end face internal electrode 20, the dimension of the first region 20a in the stacking direction T is thinner than the dimension of the second region 20b adjacent to the first region 20a in the stacking direction T, and the dimension of the second region 20b in the stacking direction T is thinner than the dimension of the third region 20c adjacent to the second region 20b in the stacking direction T.

[0109] In this case, the dimension of the end face internal electrode 20 in the stacking direction T decreases as it approaches the first end face CA. This reduces the step caused by the end face internal electrode 20, allowing appropriate pressure to be applied to the dielectric layers near the internal electrodes when the ceramic green sheets are compressed. This makes it possible to suppress the occurrence of structural defects such as the occurrence of voids. Therefore, it is possible to provide a multilayer ceramic capacitor 1 that can suppress the occurrence of structural defects.

[0110] According to this embodiment, in the end face internal electrode 20, the dimension of the first region 20a in the stacking direction T is 10% or more and less than 50% of the dimension of the second region 20b in the stacking direction T.

[0111] This makes it possible to suitably reduce the step caused by the end face internal electrode 20, thereby more suitably bringing the end face internal electrode 20 into close contact with the dielectric layer 14. Therefore, it is possible to more suitably suppress the occurrence of structural defects.

[0112] According to this embodiment, in the end face internal electrode 20, the dimension of the second region 20b in the stacking direction T is 50% or more and less than 80% of the dimension of the third region 20c in the stacking direction T.

[0113] This makes it possible to suitably reduce the step caused by the end face internal electrode 20, thereby more suitably bringing the end face internal electrode 20 into close contact with the dielectric layer 14. Therefore, it is possible to more suitably suppress the occurrence of structural defects.

[0114] According to this embodiment, in the side internal electrode 50, the dimension of the first region 20a in the stacking direction T is thinner than the dimension of the second region 20b adjacent to the first region 20a in the stacking direction T, and the dimension of the second region 20b in the stacking direction T is thinner than the dimension of the third region 20c adjacent to the second region 20b in the stacking direction T.

[0115] In this case, the dimension of the side surface internal electrode 50 in the stacking direction T becomes smaller as it approaches the first side surface BA. This makes it possible to suitably reduce the step caused by the side surface internal electrode 50, thereby suitably bringing the side surface internal electrode 50 and the dielectric layer 14 into close contact with each other. Therefore, it is possible to more suitably suppress the occurrence of structural defects.

[0116] According to this embodiment, in the side surface internal electrode 50, the dimension of the first region 50a in the stacking direction T is 10% or more and less than 50% of the dimension of the second region 50b in the stacking direction T.

[0117] This makes it possible to more suitably reduce the step caused by the side surface internal electrode 50, thereby making it possible to suitably adhere the side surface internal electrode 50 to the dielectric layer 14. Therefore, it is possible to more suitably suppress the occurrence of structural defects.

[0118] According to this embodiment, in the side surface internal electrode 50, the dimension of the second region 50b in the stacking direction T is 50% or more and less than 80% of the dimension of the third region 50c in the stacking direction T.

[0119] This makes it possible to more suitably reduce the step caused by the side surface internal electrode 50, thereby making it possible to suitably adhere the side surface internal electrode 50 to the dielectric layer 14. Therefore, it is possible to more suitably suppress the occurrence of structural defects.

[0120] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0121] For example, the condition that the dimension of the first region in the stacking direction T is thinner than the dimension of the second region in the stacking direction T, and that the dimension of the second region in the stacking direction T is thinner than the dimension of the third region in the stacking direction T, only needs to be satisfied in at least a portion of the peripheral portion of the internal electrode 15. Furthermore, it is not necessary for all of the multiple internal electrodes to satisfy this condition; it is sufficient for at least some of the internal electrodes to satisfy this condition. However, in order to more reliably suppress the occurrence of structural defects, it is preferable that this condition be satisfied in as many portions of the internal electrode 15 as possible, and it is preferable that as many of the multiple internal electrodes 15 as possible satisfy this condition.

[0122] The present invention also includes the following combinations:

[0123] <1> A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of alternately stacked dielectric layers and a plurality of internal electrodes; a laminate having first and second main surfaces opposing each other in the stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of side surface external electrodes provided on each of the side surfaces; and a pair of end surface internal electrodes provided on each of the end surfaces, wherein the plurality of internal electrodes include end surface internal electrodes exposed on both of the end surfaces and side surface internal electrodes exposed on both of the side surfaces; wherein a straight line extending in the stacking direction that passes through a position that is a center of the laminate in the length direction and a center of the laminate in the width direction is defined as a reference line; and a cross section of the laminate extending parallel to the stacking direction at a position that overlaps with the reference line is defined as a reference cross section, a direction orthogonal to the stacking direction in the reference cross section is defined as a reference direction, a distance in the reference cross section between an end of the internal electrode in the reference direction and the reference line is defined as a reference distance, a region of the internal electrode in the reference cross section where the distance in the reference direction from the end of the reference direction is less than 5% of the reference distance is defined as a first region, a region where the distance in the reference direction from the end of the reference direction is 5% or more and less than 15% of the reference distance is defined as a second region, and a region where the distance in the reference direction from the end of the reference direction is 15% or more of the reference distance is defined as a third region, wherein, in the end face internal electrode, the dimension in the stacking direction of the first region is thinner than the dimension in the stacking direction of the second region adjacent to the first region, and the dimension in the stacking direction of the second region is thinner than the dimension in the stacking direction of the third region adjacent to the second region.

[0124] <2> The multilayer ceramic capacitor according to <1>, wherein in the end face internal electrode, the dimension of the first region in the stacking direction is 10% or more and less than 50% of the dimension of the second region in the stacking direction.

[0125] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein, in the end face internal electrode, the dimension of the second region in the stacking direction is 50% or more and less than 80% of the dimension of the third region in the stacking direction.

[0126] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein, in the side internal electrode, the dimension of the first region in the stacking direction is thinner than the dimension of the second region adjacent to the first region in the stacking direction, and the dimension of the second region in the stacking direction is thinner than the dimension of the third region adjacent to the second region in the stacking direction.

[0127] <5> The multilayer ceramic capacitor according to <4>, wherein the dimension of the first region in the stacking direction of the side surface internal electrode is 10% or more and less than 50% of the dimension of the second region in the stacking direction.

[0128] <6> The multilayer ceramic capacitor according to <4> or <5>, wherein in the side internal electrode, the dimension of the second region in the stacking direction is 50% or more and less than 80% of the dimension of the third region in the stacking direction.

[0129] <7> A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of dielectric layers and a plurality of internal electrodes stacked alternately; a laminate having first and second main surfaces opposed to each other in the stacking direction; first and second side surfaces opposed to each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposed to each other in a length direction perpendicular to the stacking direction and the width direction; a pair of side surface external electrodes provided on each of the side surfaces; and a pair of end surface internal electrodes provided on each of the end surfaces, wherein the plurality of internal electrodes include end surface internal electrodes exposed on both of the end surfaces and side surface internal electrodes exposed on both of the side surfaces; a first region of the internal electrode, a region in which the distance from the reference point in the reference direction is 5% or more and less than 15% of the reference distance; a second region of the internal electrode, a region in which the distance from the reference point in the reference direction is 5% or more and less than 15% of the reference distance; and a third region of the internal electrode, a region in which the distance from the reference point in the reference direction is 15% or more of the reference distance. In the multilayer ceramic capacitor according to any one of <1> to <6>, a dimension in the stacking direction of the first region is smaller than a dimension in the stacking direction of the second region adjacent to the first region, and a dimension in the stacking direction of the second region is smaller than a dimension in the stacking direction of the third region adjacent to the second region.

[0130] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 End face external electrode (external electrode) 4 Side face external electrode (external electrode) 14 Dielectric layer 15 Internal electrode 20 End face internal electrode (internal electrode) 20a First region 20b Second region 20c Third region 50 Side face internal electrode (internal electrode) 50a First region 50b Second region 50c Third region AA First main surface AB Second main surface BA First side surface BB Second side surface CA First end surface CB Second end surface SL Reference line

Claims

1. A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of alternately stacked dielectric layers and a plurality of internal electrodes; a laminate having first and second main faces opposing each other in a stacking direction, a first side face and a second side face opposing each other in a width direction perpendicular to the stacking direction, and a first end face and a second end face opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of side face external electrodes provided on each of the side faces; and a pair of end face internal electrodes provided on each of the end faces, wherein the plurality of internal electrodes include end face internal electrodes exposed on both of the end faces and side face internal electrodes exposed on both of the side faces, a first region is a region of the internal electrode in the reference cross section where the distance in the reference direction from the end in the reference direction is less than 5% of the reference distance, a second region is a region of the internal electrode in the reference cross section where the distance in the reference direction from the end in the reference direction is 5% or more and less than 15% of the reference distance, and a third region is a region of the internal electrode in the reference cross section where the distance in the reference direction from the end in the reference direction is 15% or more of the reference distance, 2. The multilayer ceramic capacitor according to claim 1, wherein in said end face internal electrode, the dimension of said first region in said lamination direction is 10% or more and less than 50% of the dimension of said second region in said lamination direction.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein in said end face internal electrode, the dimension of said second region in said lamination direction is 50% or more and less than 80% of the dimension of said third region in said lamination direction.

4. A multilayer ceramic capacitor as described in any one of claims 1 to 3, wherein, in the side internal electrode, the dimension in the stacking direction of the first region is smaller than the dimension in the stacking direction of the second region adjacent to the first region, and the dimension in the stacking direction of the second region is smaller than the dimension in the stacking direction of the third region adjacent to the second region.

5. The multilayer ceramic capacitor according to claim 4, wherein the dimension of said first region in said stacking direction in said side surface internal electrode is 10% or more and less than 50% of the dimension of said second region in said stacking direction.

6. The multilayer ceramic capacitor according to claim 5, wherein the dimension of said second region in said stacking direction in said side surface internal electrode is 50% or more and less than 80% of the dimension of said third region in said stacking direction.

7. A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of alternately stacked dielectric layers and a plurality of internal electrodes; a laminate having first and second main faces opposing each other in a stacking direction, first and second side faces opposing each other in a width direction perpendicular to the stacking direction, and first and second end faces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of side surface external electrodes provided on each of the side surfaces; and a pair of end surface internal electrodes provided on each of the end surfaces, wherein the plurality of internal electrodes include end surface internal electrodes exposed on both of the end surfaces and side surface internal electrodes exposed on both of the side surfaces, wherein a straight line extending in the stacking direction that passes through a position that is a center of the stack in the length direction and a center of the width direction is defined as a reference line, an arbitrary point on a peripheral portion of the internal electrode is defined as a reference point, a direction in which the reference point and the reference line are aligned is defined as a reference direction, and a distance between the reference point and the reference line is defined as a reference distance, The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein a region of the internal electrode where the distance from the reference point in the reference direction is less than 5% of the reference distance is defined as a first region, a region where the distance from the reference point in the reference direction is 5% or more and less than 15% of the reference distance is defined as a second region, and a region where the distance from the reference point in the reference direction is 15% or more of the reference distance is defined as a third region, wherein in the side internal electrode, a dimension in the stacking direction of the first region is thinner than a dimension in the stacking direction of the second region adjacent to the first region, and a dimension in the stacking direction of the second region is thinner than a dimension in the stacking direction of the third region adjacent to the second region.

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