Semiconductor package, semiconductor device, and method for manufacturing semiconductor package

Abstract

The present invention improves heat dissipation in a semiconductor package provided with external terminals.　This semiconductor package includes a wiring board, a semiconductor chip, a transparent member, and a metal plate. A predetermined number of external terminals are arranged on a light receiving surface of the frame-shaped wiring board. The semiconductor chip is electrically connected to the wiring board. The transparent member is connected to the light receiving surface of the wiring board or the semiconductor chip with a sealing material therebetween. The metal plate has higher rigidity and higher thermal conductivity than a mounting substrate connected to the external terminals, and is connected to the surface facing the light receiving surface among the surfaces of the wiring board.

Description

Semiconductor package, semiconductor device, and method for manufacturing semiconductor package

[0001] The present technology relates to a semiconductor package, and more particularly to a semiconductor package provided with a semiconductor chip, a semiconductor device, and a method for manufacturing the semiconductor package.

[0002] Conventionally, semiconductor packages for protecting semiconductor chips such as image sensors have sometimes used metal members to dissipate heat generated by the chips. For example, a semiconductor package has been proposed in which an image sensor is mounted in a cavity of a frame-shaped frame substrate, the frame substrate is sandwiched between a frame-shaped upper metal portion and a plate-shaped lower metal portion, and glass is placed on top (see, for example, Patent Document 1). In this semiconductor package, the outer periphery of the lower metal portion is smaller than the outer periphery of the frame substrate, and a connector is disposed on the underside of the frame substrate in the region between the outer periphery of the frame substrate and the outer periphery of the lower metal portion as an external terminal for external connection.

[0003] International Publication No. 2023 / 032260

[0004] In the above-mentioned conventional technology, the upper metal portion and the lower metal portion are used to dissipate heat generated by the image sensor. However, in the above-mentioned structure, external terminals (such as connectors) must be placed on the underside of the frame substrate, which restricts the area of ​​the lower metal portion. As a result, the area of ​​the lower metal portion cannot be expanded, making it difficult to improve heat dissipation.

[0005] This technology was developed in light of these circumstances, and aims to improve heat dissipation in semiconductor packages that have external terminals.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor package including a frame-shaped wiring substrate having a predetermined number of external terminals arranged on a light-receiving surface thereof, a semiconductor chip electrically connected to the wiring substrate, a transparent member connected to the light-receiving surface of the wiring substrate or the semiconductor chip via a sealant, and a metal plate having higher rigidity and thermal conductivity than a mounting substrate connected to the external terminals and connected to one of both surfaces of the wiring substrate facing the light-receiving surface, and a manufacturing method thereof, which improves heat dissipation.

[0007] In addition, in the first side surface, the outer periphery of the sealing material may be larger than the outer periphery of the transparent member when viewed from a direction perpendicular to the light receiving surface, thereby providing the effect of preventing dust from entering.

[0008] In addition, in the first aspect, a stopper may be further provided between the outer periphery of the wiring board and the sealing material, thereby improving the accuracy of the optical axis.

[0009] In the first aspect, the stopper may include a first stopper formed along the outer periphery of the wiring board, thereby improving the accuracy of the optical axis.

[0010] In the first aspect, the stopper may include a second stopper formed between the sealing material and the external terminal, thereby improving the accuracy of the optical axis.

[0011] In this first aspect, the height of the stopper from the wiring board may be smaller than the height of the external terminal from the wiring board, and the elastic modulus of the stopper may be larger than that of the external terminal, thereby improving the accuracy of the optical axis.

[0012] In addition, the first aspect may further comprise a first wall formed between the external terminal and the sealing material, thereby providing the effect of preventing dust from entering.

[0013] In the first aspect, the height of the first wall from the wiring board may be greater than the height of the external terminal from the wiring board, and the elastic modulus of the first wall may be smaller than that of the external terminal, thereby providing an effect of preventing intrusion of dust.

[0014] In addition, the first side surface may further include a second wall formed between the first wall and the sealing material, thereby preventing the sealing material from leaking out.

[0015] In this first aspect, the height of the sealing material from the wiring substrate may be greater than the height of the external terminals from the wiring substrate, and the elastic modulus of the sealing material may be smaller than that of the external terminals, thereby providing an effect of preventing intrusion of dust.

[0016] In this first aspect, the height of the light receiving surface of the transparent member from the wiring board may be greater than the height of the external terminal from the wiring board, thereby providing an effect that light is incident on the transparent member that is higher than the external terminal.

[0017] In addition, in the first side face, the external terminals may be disposed inside the outer periphery of the metal plate when viewed from a direction perpendicular to the light-receiving surface of the wiring board, thereby achieving a space-saving semiconductor package.

[0018] In addition, in the first aspect, a through hole may be formed in the mounting substrate, and the transparent member may be disposed in the through hole, thereby providing an effect of forming a cavity.

[0019] In this first aspect, the external terminals may be solder balls or pins, thereby providing an effect of electrically connecting the semiconductor package to the mounting substrate.

[0020] In addition, in this first aspect, the device may further include bonding wires that electrically connect the semiconductor chip and the wiring board, and a sealing material that covers the bonding wires, thereby providing the effect of protecting the bonding wires.

[0021] In this first aspect, the semiconductor chip may be electrically connected to the wiring board by bumps, thereby eliminating the need for bonding wires.

[0022] A second aspect of the present technology is a semiconductor device including a semiconductor package including a mounting substrate, a lens unit mounted on the mounting substrate, a wiring substrate having a light-receiving surface on which a predetermined number of external terminals are arranged, a semiconductor chip electrically connected to the wiring substrate, a transparent member connected to the light-receiving surface of the wiring substrate or the semiconductor chip via a sealant, and a metal plate having higher rigidity and thermal conductivity than the mounting substrate connected to the external terminals and connected to one of the surfaces of the wiring substrate facing the light-receiving surface, thereby improving the heat dissipation of the semiconductor device.

[0023] In addition, in the second aspect, the semiconductor device may further include an external heat sink, and one of the two surfaces of the metal plate may be connected to the wiring board and the other surface may be connected to the external heat sink, thereby improving the heat dissipation of the semiconductor device.

[0024] 1 is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present technology; FIG. 2 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package according to the first embodiment of the present technology; FIG. 3 is an example of a plan view of a mounting substrate and a wiring substrate according to the first embodiment of the present technology; FIG. 4 is a view for explaining a manufacturing method up to bonding of metal plates according to the first embodiment of the present technology; FIG. 5 is a view for explaining a manufacturing method up to forming a dam according to the first embodiment of the present technology; FIG. 6 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package according to a first modified example of the first embodiment of the present technology; FIG. 7 is a cross-sectional view of a case where a dust prevention wall according to a first modified example of the first embodiment of the present technology is also used as a dam; FIG. 8 is a cross-sectional view showing an example of a semiconductor device in which a lens unit is tilted; FIG. 9 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package according to a second modified example of the first embodiment of the present technology; FIG. 1 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package in a first modified example of the second embodiment of the present technology. FIG. 2 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package in a second modified example of the second embodiment of the present technology. FIG. 3 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package in a third modified example of the second embodiment of the present technology. FIG. 4 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package in a third modified example of the second embodiment of the present technology, from which a dust prevention wall is removed, in a third modified example of the second embodiment of the present technology. FIG. 5 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package in a fourth modified example of the second embodiment of the present technology. FIG. 6 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package in a fifth modified example of the second embodiment of the present technology. FIG. 7 is a cross-sectional view showing a configuration example of a semiconductor package in a sixth modified example of the second embodiment of the present technology. FIG. 8 is a diagram for explaining a manufacturing method up to the formation of a sealing material in a sixth modified example of the second embodiment of the present technology.10 is a diagram for explaining a manufacturing method up to the formation of an external terminal according to a sixth modified example of the second embodiment of the present technology. FIG. 11 is a cross-sectional view showing an example of a configuration of a semiconductor package according to a third embodiment of the present technology. FIG. 12 is a block diagram showing an example of a configuration of an electronic device according to an embodiment of the present technology.

[0025] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The descriptions will be given in the following order: 1. First embodiment (an example in which external terminals are provided on the upper surface of a wiring substrate) 2. Second embodiment (an example in which the area of ​​a transparent member is increased and external terminals are provided on the upper surface of a wiring substrate) 3. Third embodiment (an example in which external terminals are provided on the upper surface of a wiring substrate and a semiconductor chip is connected by bumps) 4. Configuration examples of electronic devices

[0026] 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to an embodiment of the present technology. The semiconductor device 100 is a device that captures image data and includes a lens module. A lens unit 110, a mounting substrate 120, a semiconductor package 200, and an external heat sink 130 are arranged within the lens module. Examples of the semiconductor device 100 include smartphones, digital still cameras, and in-vehicle cameras.

[0027] The lens unit 110 is a component that houses a predetermined number of lenses, such as lenses 111 and 112, and is mounted on a mounting substrate 120. The lens unit 110 condenses incident light and guides it to the semiconductor package 200.

[0028] Hereinafter, the optical axis of the lens unit 110 will be referred to as the "Z axis," and a specific axis perpendicular to the Z axis will be referred to as the "X axis." An axis perpendicular to the X axis and Z axis will be referred to as the "Y axis." This figure shows a cross-sectional view seen from the Y axis direction.

[0029] The mounting substrate 120 is a substrate on which the semiconductor package 200 is mounted, and is also called a motherboard. A through hole is formed in the mounting substrate 120, and light is incident on the light receiving surface of the semiconductor package 200 through the through hole.

[0030] Hereinafter, of the two surfaces of the substrate or layer, the light-receiving surface will be referred to as the "upper surface," and the surface facing the light-receiving surface will be referred to as the "lower surface." Furthermore, the space surrounded by the lower surface of lens unit 110, the side surface of mounting substrate 120, and the upper surface of semiconductor package 200 will be referred to as the "cavity."

[0031] The semiconductor package 200 is a package that houses a semiconductor chip such as a solid-state image sensor. The configuration of the semiconductor package 200 will be described in detail later.

[0032] The external heat sink 130 is connected to the underside of the semiconductor package 200 and dissipates heat generated in the semiconductor package 200. As the external heat sink 130, for example, a metal member on which a predetermined number of fins are formed is used.

[0033] 2A and 2B are a cross-sectional view and a plan view showing a configuration example of a semiconductor package 200 according to the first embodiment of the present technology. In the figure, "a" shows a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in "a" in the figure indicates the outline of the mounting substrate 120. In the figure, "b" shows a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0034] As shown in FIG. 1A, the semiconductor package 200 includes a transparent member 210, a wiring substrate 220, a semiconductor chip 230, and a metal plate 240. The area of ​​the transparent member 210 is slightly smaller than the area of ​​the semiconductor chip 230.

[0035] The metal plate 240 is a metal substrate that dissipates heat generated by the semiconductor chip 230 and the wiring board 220. The rigidity and thermal conductivity of the metal plate 240 are higher than those of the mounting board 120, and the upper surface of the metal plate 240 is connected to the lower surface of the wiring board 220. The outer periphery of the metal plate 240, for example, approximately matches the outer periphery of the wiring board 220. Here, "approximately matches" means a perfect match, or a difference within an allowable value.

[0036] The wiring substrate 220 is a frame-shaped substrate, also called an interposer, for electrically connecting the semiconductor package 200 to the mounting substrate 120. The wiring substrate 220 may be, for example, an organic substrate.

[0037] As illustrated in b in the figure, the outer periphery of the wiring substrate 220 is rectangular when viewed from the Z-axis direction, and a rectangular through-hole 221 is formed in the center. The dotted line in b in the figure indicates the outer periphery of the transparent member 210.

[0038] Furthermore, on the upper surface (i.e., the light-receiving surface) of the wiring substrate 220, a predetermined number of external terminals 251 are arranged inside the outer periphery of the metal plate 240 when viewed from the Z-axis direction. These external terminals 251 are, for example, solder balls. Each of the external terminals 251 is connected to the mounting substrate 120. Note that pins can also be used as the external terminals 251. A package in which solder balls are arranged is also called a BGA (Ball Grid Array) package. A package in which pins are arranged is also called a PGA (Pin Grid Array) package.

[0039] As shown in FIG. 1A, the semiconductor chip 230 is placed in a through hole 221 of the wiring substrate 220. The lower surface of the semiconductor chip 230 is bonded with an adhesive 256 to the upper surface of the metal plate 240 exposed in the through hole 221. The semiconductor chip 230 is electrically connected to the upper surface of the wiring substrate 220 by a bonding wire 253. The bonding wire 253 is covered with a sealing material 254. A dam 255 is placed outside the bonding wire 253. The semiconductor chip 230 may be a solid-state imaging element that captures image data by photoelectric conversion.

[0040] Furthermore, a transparent member 210 is connected to the upper surface (light-receiving surface) of the semiconductor chip 230 via a sealing material 252. A resin or the like is used as the sealing material 252. The transparent member 210 is a member that transmits incident light and protects the semiconductor chip 230, and is also called a cover glass or a sealing glass. The height Z1 of the upper surface of the transparent member 210 from the wiring substrate 220 is set to be greater than the height of the external terminals 251 from the wiring substrate 220.

[0041] When the semiconductor package 200 is observed from above, it is actually possible to see the semiconductor chip 230, the encapsulant 254, and the sealant 252. However, in FIG. 1B, these are omitted for the sake of convenience.

[0042] The outer periphery of the sealing material 252 is equal to or smaller than the outer periphery of the transparent member 210, and for example, the outer peripheries of the sealing material 252 and the transparent member 210 are substantially the same. Therefore, as illustrated in b in the figure, the sealing material 252 hardly protrudes from the transparent member 210 when viewed from the Z-axis direction.

[0043] As shown in FIG. 10A, the height Z2 of the sealing material 252 from the wiring substrate 220 is slightly greater than the height of the external terminals 251 from the wiring substrate 220. The sealing material 252 has a lower elastic modulus than the external terminals 251.

[0044] As described above, a predetermined number of external terminals 251 are arranged on the upper surface (light-receiving surface) of frame-shaped wiring substrate 220, and semiconductor chip 230 is electrically connected to the upper surface of wiring substrate 220 by bonding wires 253. Transparent member 210 is connected to the upper surface of wiring substrate 220 via sealing material 252. Metal plate 240 has higher rigidity and thermal conductivity than mounting substrate 120, and is connected to the lower surface of wiring substrate 220.

[0045] Here, a comparative example is considered in which external terminals 251 are arranged on the underside of wiring substrate 220. In this comparative example, in order to arrange external terminals 251, the outer periphery of metal plate 240 needs to be smaller than the outer periphery of wiring substrate 220, which restricts the area of ​​metal plate 240.

[0046] In contrast, in the semiconductor package 200 illustrated in FIGS. 1A and 1B, the external terminals 251 are disposed on the upper surface of the wiring substrate 220, so the area of ​​the metal plate 240 is not restricted and can be made larger than in the comparative example, thereby improving heat dissipation compared to the comparative example.

[0047] Furthermore, by arranging the external terminals 251 on the upper surface of the wiring substrate 220, the mounting substrate 120 can be compressed from above when mounting the mounting substrate 120, thereby preventing the semiconductor package 200 from peeling off from the mounting substrate 120.

[0048] Furthermore, by arranging the external terminals 251 on the upper surface of the wiring substrate 220, the size of the lens unit 110 (not shown) as viewed from the Z-axis direction can be made approximately the same as that of the semiconductor package 200. This makes it possible to realize a space-saving semiconductor device 100.

[0049] 3A and 3B are examples of plan views of the mounting substrate 120 and the wiring substrate 220 according to the first embodiment of the present technology. In the drawing, "a" is an example of the plan view of the mounting substrate 120, and "b" is an example of the plan view of the wiring substrate 220.

[0050] As illustrated in a in the figure, the outer periphery of the mounting substrate 120 is rectangular when viewed from the Z-axis direction, and a rectangular through-hole 121 is formed in the center thereof. A transparent member 210 (not shown) is disposed inside this through-hole 121. The dotted line in a in the figure indicates the outer periphery of the transparent member 210.

[0051] As shown in b in the figure, the outer periphery of the wiring substrate 220 is rectangular when viewed from the Z-axis direction, and a rectangular through-hole 221 is formed in the center thereof. A semiconductor chip 230 (not shown) is disposed in this through-hole 221. The dotted line in b in the figure indicates the outer periphery of the semiconductor chip 230.

[0052] As illustrated in a and b in the figure, the outer periphery of the mounting substrate 120 is larger than the outer periphery of the wiring substrate 220 , and the area of ​​the through-hole 121 is larger than the area of ​​the through-hole 221 .

[0053] [Method for Manufacturing Semiconductor Package] Next, a method for manufacturing the semiconductor package 200 will be described with reference to FIGS.

[0054] First, as shown in FIG. 4A, a wiring substrate 220 is created. Then, as shown in FIG. 4B, a film-like adhesive 222 is attached to the underside of the wiring substrate 220. Then, as shown in FIG. 4C, through holes are formed in the wiring substrate 220 by router processing or the like. Then, a metal plate 240 is connected to the underside of the wiring substrate 220 via the adhesive 222. When connecting this metal plate 240, for example, pressure application and curing are performed.

[0055] 5A, a paste-like adhesive 256 is applied to the area of ​​the upper surface of the metal plate 240 that is exposed from the through-holes of the wiring substrate 220. Then, as shown in FIG. 5B, the semiconductor chip 230 is attached (in other words, die-bonded) to the upper surface of the metal plate 240. During die-bonding, for example, curing is performed. Then, as shown in FIG. 5C, the semiconductor chip 230 and the wiring substrate 220 are electrically connected by bonding wires 253. Then, as shown in FIG. 5D, a sealant 252 is formed around the pixel region of the semiconductor chip 230.

[0056] Next, as shown in FIG. 6A, the transparent member 210 is placed. Then, as shown in FIG. 6B, a dam 255 is formed on the outside of the bonding wire 253. The dam 255 is formed, for example, by applying resin with a dispenser. Then, as shown in FIG. 6C, the bonding wire 253 is covered with a sealing material 254. Then, as shown in FIG. 6D, a predetermined number of external terminals 251 are formed on the upper surface of the wiring substrate 220.

[0057] As described above, according to the first embodiment of the present technology, a predetermined number of external terminals 251 are arranged on the upper surface (i.e., the light-receiving surface) of the wiring substrate 220, and the metal plate 240 is connected to the lower surface of the substrate, so that the area of ​​the metal plate 240 can be made larger than that of the comparative example, thereby improving the heat dissipation performance of the semiconductor package 200.

[0058] [First Modification] In the first embodiment described above, there is a risk of dust entering the cavity through gaps in the external terminals 251. The semiconductor package 200 in this first modification of the first embodiment differs from the first embodiment in that a dust prevention wall is formed between the sealing material 252 and the external terminals 251 to prevent dust from entering.

[0059] 7A and 7B are a cross-sectional view and a plan view showing a configuration example of a semiconductor package 200 according to a first modified example of the first embodiment of the present technology. In the figure, "a" shows a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in "a" in the figure indicates the outline of the mounting substrate 120. In the figure, "b" shows a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0060] As illustrated in a in the same figure, the semiconductor package 200 in the first modified example of the first embodiment differs from the first embodiment in that a dust prevention wall 260 is formed between the external terminals 251 and the sealing material 252.

[0061] This dust prevention wall 260 is formed along the inner periphery of the mounting substrate 120 (not shown) at the bottom thereof. The height Z2 of the dust prevention wall 260 from the wiring substrate 220 is slightly greater than the height of the external terminals 251 from the wiring substrate 220. A material (such as rubber packing) with a lower modulus of elasticity than the external terminals 251 is used as this dust prevention wall 260. The dust prevention wall 260 is an example of a first wall as defined in the claims.

[0062] As shown in the diagram b, the dust prevention wall 260 is formed so as to surround the outer periphery of the transparent member 210. This dust prevention wall 260 prevents dust from entering the cavity.

[0063] As shown in FIG. 8, in the first modification of the first embodiment, the dam 255 can be eliminated and the dust prevention wall 260 can function as a dam.

[0064] As described above, according to the first variant of the first embodiment of the present technology, a dust prevention wall 260 is formed between the sealing material 252 and the external terminal 251, thereby preventing dust from entering the cavity.

[0065] [Second Modification] In the first embodiment described above, the mounting substrate 120 is mounted on top of the semiconductor package 200, and the lens unit 110 is mounted on top of that. However, with this configuration, for example, environmental changes such as temperature changes can cause distortion in the components within the semiconductor package 200, which could cause the optical axis of the lens unit 110 to deviate from the optical axis of the semiconductor package 200, as illustrated in Fig. 9. The semiconductor package 200 in this second modification of the first embodiment differs from the first embodiment in that a stopper is formed along the outer periphery of the wiring substrate 220 to suppress deviation of the optical axis.

[0066] 10A and 10B are a cross-sectional view and a plan view showing a configuration example of a semiconductor package 200 according to a second modified example of the first embodiment of the present technology. In the figure, a indicates a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in a indicates the outline of the mounting substrate 120. b indicates a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0067] As shown in the diagram (a), the second modified semiconductor package 200 of the first embodiment differs from the first embodiment in that a stopper 271 is formed on the upper surface of the wiring substrate 220 along the outer periphery thereof. Furthermore, the height Z3 of the stopper 271 from the wiring substrate 220 is slightly smaller than the height of the external terminals 251 from the wiring substrate 220. The stopper 271 has a higher elastic modulus than the external terminals 251. The stopper 271 is an example of a first stopper as defined in the claims.

[0068] As illustrated in FIG. 1B, the stopper 271 is formed along the outer periphery of the wiring substrate 220 so as to surround the many external terminals 251. In other words, the stopper 271 is disposed outside the external terminals 251.

[0069] As illustrated in a and b in the figure, by forming stoppers 271 along the outer periphery of the wiring substrate 220, it is possible to suppress deviation of the optical axis and improve the precision of the optical axis.

[0070] As described above, according to the second modified example of the first embodiment of the present technology, the stopper 271 is formed along the outer periphery of the wiring substrate 220, and therefore, the accuracy of the optical axis can be improved.

[0071] 2. Second Embodiment In the first embodiment described above, the area of ​​transparent member 210 is smaller than that of semiconductor chip 230, but this is not limiting. Semiconductor package 200 in this second embodiment differs from the first embodiment in that the area of ​​transparent member 210 is larger than that of semiconductor chip 230.

[0072] 11 is a cross-sectional view showing an example of a configuration of a semiconductor package 200 according to the second embodiment of the present technology. The drawing shows a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in the drawing indicates the outline of the mounting substrate 120.

[0073] The semiconductor package 200 in the second embodiment differs from the first embodiment in that the area of ​​the transparent member 210 is larger than that of the semiconductor chip 230. In this case, the sealing material 252 is disposed on the outer side of the bonding wires 253, and the dam 255 is disposed on the inner side of the bonding wires 253.

[0074] Next, a method for manufacturing the semiconductor package 200 according to the second embodiment will be described with reference to Figures 12 and 13. In the second embodiment, the process up to bonding the metal plate 240 is the same as in the first embodiment.

[0075] After the metal plate 240 is bonded, as shown in FIG. 12 a, a paste-like adhesive 256 is applied to the area of ​​the upper surface of the metal plate 240 that is exposed from the through-hole of the wiring substrate 220. Then, as shown in FIG. 12 b, the semiconductor chip 230 is bonded (in other words, die-bonded) to the upper surface of the metal plate 240. During die-bonding, for example, curing is performed. Then, as shown in FIG. 12 c, the semiconductor chip 230 and the wiring substrate 220 are electrically connected by bonding wires 253. Then, as shown in FIG. 12 d, a dam 255 is formed around the pixel region of the semiconductor chip 230 to protect that region. The dam 255 is formed, for example, by applying resin using a dispenser.

[0076] 13A, a seal material 252 is formed on the upper surface of the wiring substrate 220 around the bonding wires 253. Then, as shown in FIG. 13B, the bonding wires 253 are covered with a sealing material 254. Then, as shown in FIG. 13C, the transparent member 210 is placed. Then, as shown in FIG. 13D, a predetermined number of external terminals 251 are formed on the upper surface of the wiring substrate 220.

[0077] As described above, according to the second embodiment of the present technology, the area of ​​the transparent member 210 is made larger than that of the semiconductor chip 230 , so that the sealing material 252 can be formed on the upper surface of the wiring substrate 220 .

[0078] [First Modification] In the second embodiment described above, the outer periphery of the sealing material 252 is the same as the outer periphery of the transparent member 210 when viewed from the Z-axis direction, but this configuration raises the risk of dust entering the cavity through gaps in the external terminals 251. If dust enters, it may adhere to the lenses in the lens unit 110 or the transparent member 210, degrading the image quality of the image data. The semiconductor package 200 in this first modification of the second embodiment differs from the second embodiment in that the outer periphery of the sealing material 252 is made larger than the outer periphery of the transparent member 210 to prevent dust from entering.

[0079] 14 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package 200 according to a first modified example of the second embodiment of the present technology. In the figure, a indicates a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in a indicates the outline of the mounting substrate 120. b indicates a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0080] As illustrated in a and b in the same figure, in the first variant of the second embodiment, when viewed from the Z-axis direction, the outer periphery of the sealing material 252 is larger than the outer periphery of the transparent member 210 and is equal to or larger than the outer periphery of the through hole in the wiring substrate 220.

[0081] For example, as illustrated in FIG. 1A, the coordinates of the left and right ends of the sealing material 252 in the X-axis direction are designated X1 and X6. The coordinates of the left and right ends of the through-hole in the wiring substrate 220 (not shown) are designated X2 and X4. The coordinates of the left and right ends of the transparent member 210 are designated X3 and X4. In this case, the distance from X1 to X6 is greater than the distance from X2 to X5. The distance from X2 to X5 is also greater than the distance from X3 to X4.

[0082] As illustrated in FIG. 10B, a portion of the sealing material 252 protrudes outside the transparent member 210 when viewed from the Z-axis direction.

[0083] As illustrated in a and b in the same figure, by making the outer periphery of the sealing material 252 larger than the outer periphery of the transparent member 210 when viewed from the Z-axis direction, the sealing material 252 can also function as a barrier to prevent dust from entering.

[0084] Thus, according to the first variant of the second embodiment of the present technology, the outer periphery of the sealing material 252 is larger than the outer periphery of the transparent member 210 when viewed from the Z-axis direction, thereby preventing dust from entering the cavity.

[0085] [Second Modification] In the second embodiment described above, the outer periphery of the sealing material 252 is the same as the outer periphery of the transparent member 210 when viewed from the Z-axis direction, but this configuration raises the risk of dust entering the cavity through gaps in the external terminals 251. The semiconductor package 200 in this second modification of the second embodiment differs from the second embodiment in that a dust prevention wall is formed between the sealing material 252 and the external terminals 251 to prevent dust from entering.

[0086] 15A and 15B are a cross-sectional view and a plan view showing a configuration example of a semiconductor package 200 according to a second modified example of the second embodiment of the present technology. In the figure, "a" shows a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in "a" in the figure indicates the outline of the mounting substrate 120. In the figure, "b" shows a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0087] As illustrated in FIG. 11A, the semiconductor package 200 of the third embodiment differs from the first embodiment in that a dust prevention wall 260 is formed between an external terminal 251 and a sealing material 252. The outer periphery of the sealing material 252 is the same as the outer periphery of the transparent member 210.

[0088] This dust prevention wall 260 is formed along the inner periphery of the mounting substrate 120 (not shown) at the bottom thereof. The height Z2 of the dust prevention wall 260 from the wiring substrate 220 is slightly greater than the height of the external terminals 251 from the wiring substrate 220. A material (such as rubber packing) with a lower modulus of elasticity than the external terminals 251 is used as this dust prevention wall 260. The dust prevention wall 260 is an example of a first wall as defined in the claims.

[0089] As shown in the diagram (b), the dust prevention wall 260 is formed to surround the outer periphery of the transparent member 210. The dust prevention wall 260 prevents dust from entering the cavity. The dust prevention wall 260 also prevents the sealing material 252 from flowing out into the area where the external terminals 251 are arranged.

[0090] Thus, according to the second variant of the second embodiment of the present technology, a dust prevention wall 260 is formed between the sealing material 252 and the external terminal 251, thereby preventing dust from entering the cavity.

[0091] [Third Modification] In the second modification of the second embodiment described above, the mounting substrate 120 is mounted on top of the semiconductor package 200, and the lens unit 110 is mounted on top of that. However, with this configuration, there is a risk that environmental changes, such as temperature changes, will cause distortion in the components within the semiconductor package 200, causing the optical axis of the lens unit 110 to deviate from the optical axis of the semiconductor package 200. The semiconductor package 200 in this third modification of the second embodiment differs from the second modification of the second embodiment in that a stopper is formed along the outer periphery of the wiring substrate 220 to suppress deviation of the optical axis.

[0092] 16 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package 200 according to a third modified example of the second embodiment of the present technology. In the figure, a indicates a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in a indicates the outline of the mounting substrate 120. b in the figure indicates a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0093] As illustrated in FIG. 11A, the semiconductor package 200 of the third modified example of the second embodiment differs from the second modified example of the second embodiment in that a stopper 271 is formed on the upper surface of the wiring substrate 220 along the outer periphery thereof. Furthermore, the height Z3 of the stopper 271 from the wiring substrate 220 is slightly smaller than the height of the external terminals 251 from the wiring substrate 220. The stopper 271 has a higher elastic modulus than the external terminals 251. The stopper 271 is an example of a first stopper as defined in the claims.

[0094] As illustrated in FIG. 1B, the stopper 271 is formed along the outer periphery of the wiring substrate 220 so as to surround the many external terminals 251. In other words, the stopper 271 is disposed outside the external terminals 251.

[0095] As illustrated in a and b in the figure, by forming stoppers 271 along the outer periphery of the wiring substrate 220, it is possible to suppress deviation of the optical axis and improve the precision of the optical axis.

[0096] As shown in FIG. 17, in the third modified example of the second embodiment, the dust prevention wall 260 can be omitted.

[0097] As described above, according to the third modified example of the second embodiment of the present technology, the stopper 271 is formed along the outer periphery of the wiring substrate 220, and therefore, the accuracy of the optical axis can be improved.

[0098] [Fourth Modification] In the third modification of the second embodiment described above, the stoppers 271 are arranged on the outside of the external terminals 251, but to further improve the accuracy of the optical axis, it is preferable to also arrange stoppers on the inside of the external terminals 251. The semiconductor package 200 in this fourth modification of the second embodiment differs from the third modification of the second embodiment in that stoppers are also arranged on the inside of the external terminals 251.

[0099] 18 is a cross-sectional view and a plan view showing a configuration example of a semiconductor package 200 according to a fourth modified example of the second embodiment of the present technology. In the figure, a indicates a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in a indicates the outline of the mounting substrate 120. b in the figure indicates a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0100] As illustrated in FIG. 11A, the semiconductor package 200 according to the fourth modified example of the second embodiment differs from the third modified example of the second embodiment in that a stopper 272 is further formed on the upper surface of the wiring substrate 220 between the sealing material 252 and the external terminals 251. For example, the stopper 272 is disposed on the outer side of the dust prevention wall 260. The elastic modulus and height of the stopper 272 are similar to those of the stopper 271. The stopper 272 is an example of a second stopper as defined in the claims.

[0101] As illustrated in FIG. 10B, the stopper 272 is formed between the dust prevention wall 260 and the external terminal 251 so as to surround the dust prevention wall 260 when viewed from the Z-axis direction.

[0102] As illustrated in a and b in the figure, by forming a stopper 272 between the sealing material 252 and the external terminal 251, the precision of the optical axis can be further improved.

[0103] Although both stoppers 271 and 272 are provided, it is also possible to provide only stopper 272. Furthermore, although stopper 272 is formed on the outside of dust prevention wall 260, it is also possible to enlarge the outer periphery of dust prevention wall 260 and form stopper 272 on the inside thereof.

[0104] As described above, according to the fourth modified example of the second embodiment of the present technology, a stopper 272 is further formed between the sealing material 252 and the external terminal 251, thereby further improving the accuracy of the optical axis.

[0105] [Fifth Modification] In the second modification of the second embodiment described above, a dust prevention wall 260 is formed below the mounting substrate 120 to prevent the intrusion of dust and the outflow of the sealing material 252. However, this configuration may result in the sealing material 252 leaking into the cavity. The semiconductor package 200 in this fifth modification of the second embodiment differs from the second modification of the second embodiment in that the sealing material outflow prevention wall prevents the sealing material 252 from leaking into the cavity.

[0106] 19 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to a fifth modified example of the second embodiment of the present technology. In the figure, "a" shows a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in "a" in the figure indicates the outline of the mounting substrate 120. In the figure, "b" shows a plan view of the semiconductor package 200 as viewed from the Z-axis direction.

[0107] As illustrated in FIG. 11A, the semiconductor package 200 of the fifth modified example of the second embodiment differs from the second modified example of the second embodiment in that a sealant outflow prevention wall 280 is further formed on the outer side of the sealant 252. The height of the sealant outflow prevention wall 280 from the wiring substrate 220 is set to be equal to or greater than the height of the sealant 252 from the wiring substrate 220.

[0108] As illustrated in b in the figure, the sealing material outflow prevention wall 280 is formed on the outside of the sealing material 252 (not shown) so as to surround it when viewed from the Z-axis direction. The sealing material outflow prevention wall 280 is an example of a second wall described in the claims.

[0109] As shown in a and b in the figure, by forming a sealant outflow prevention wall 280 on the outside of the sealant 252, it is possible to prevent the sealant 252 from outflowing into the cavity.

[0110] The fifth modified example of the second embodiment can also be applied to each of the second embodiment and its first, third, and fourth modified examples.

[0111] As described above, according to the fifth variant of the second embodiment of the present technology, a sealant outflow prevention wall 280 is formed on the outside of the sealant 252, thereby preventing the sealant 252 from outflowing into the cavity.

[0112] [Sixth Modification] In the second embodiment described above, the bonding wires 253 are sealed, but this is not limiting. The semiconductor package 200 in this sixth modification of the second embodiment differs from the second embodiment in that the bonding wires 253 are not sealed.

[0113] 20 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to a sixth modified example of the second embodiment of the present technology. The drawing shows a cross-sectional view of the semiconductor package 200 as viewed from the Y-axis direction. The thick dotted line in the drawing indicates the outline of the mounting substrate 120.

[0114] The semiconductor package 200 in the sixth modification of the second embodiment differs from the first embodiment in that the bonding wires 253 are not sealed with the sealing material 254 .

[0115] 21 and 22, a method for manufacturing the semiconductor package 200 according to the sixth modification of the second embodiment will be described. In the sixth modification of the second embodiment, the steps up to bonding the metal plate 240 are the same as those in the first embodiment.

[0116] After the metal plate 240 is bonded, as shown in FIG. 21 a, a paste-like adhesive 256 is applied to the area of ​​the upper surface of the metal plate 240 that is exposed from the through-hole of the wiring substrate 220. Then, as shown in FIG. 21 b, the semiconductor chip 230 is bonded (in other words, die-bonded) to the upper surface of the metal plate 240. During die-bonding, for example, curing is performed. Then, as shown in FIG. 21 c, the semiconductor chip 230 and the wiring substrate 220 are electrically connected by bonding wires 253. Then, as shown in FIG. 21 a, a sealant 252 is formed on the upper surface of the wiring substrate 220, outside the bonding wires 253.

[0117] 22A, the transparent member 210 is placed on the substrate 220. Then, as shown in FIG. 22B, a predetermined number of external terminals 251 are formed on the upper surface of the wiring substrate 220.

[0118] As described above, according to the sixth modification of the second embodiment of the present technology, the bonding wires 253 are not sealed, so that it is possible to reduce a part of the manufacturing process.

[0119] 3. Third Embodiment In the first embodiment described above, the semiconductor chip 230 is connected to the wiring substrate 220 by bonding wires, but it can also be connected by bumps. The semiconductor package 200 in this third embodiment differs from the first embodiment in that the semiconductor chip 230 is connected by bumps.

[0120] 23 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to the third embodiment of the present technology. The drawing shows a cross-sectional view of the semiconductor package 200 as seen from the Y-axis direction. The thick dotted line in the drawing indicates the outline of the mounting substrate 120.

[0121] In the third embodiment, a frame-shaped wiring substrate 225 is used instead of the wiring substrate 220. The area of ​​the top surface of the semiconductor chip 230 is larger than the area of ​​the through-holes in the wiring substrate 225. The area of ​​the top surface of the semiconductor chip 230 surrounding the pixel region is connected to the bottom surface of the wiring substrate 225 by bumps. In the figure, X1 and X2 are the coordinates of the left and right ends of the pixel region. A package with the configuration illustrated in the figure is also called a fan-out package.

[0122] The area of ​​the metal plate 240 is larger than that of the semiconductor chip 230 and is approximately the same as that of the wiring board 225. A molding resin 290 is filled between the wiring board 225 and the metal plate 240.

[0123] Furthermore, the outer periphery of the sealing material 252 is larger than the outer periphery of the transparent member 210, similar to the second embodiment.

[0124] As shown in the figure, by connecting the semiconductor chip 230 to the wiring board 225 by means of bumps, the wire bonding process becomes unnecessary.

[0125] As described above, according to the third embodiment of the present technology, the semiconductor chip 230 is connected to the wiring board 225 by the bumps, so wire bonding is not required.

[0126] 4. Configuration Example of Electronic Device> An example of application of the solid-state imaging device according to the above-described embodiment to an electronic device will be described with reference to FIG.

[0127] The semiconductor package 200 according to the present technology can be applied to all electronic devices that use a solid-state imaging element in an image capture section (photoelectric conversion section), such as camera devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, and copiers that use a solid-state imaging element in an image reading section.

[0128] 24 , a camera device 300 as an electronic device includes an optical unit 302, a solid-state imaging device 301, a DSP (Digital Signal Processor) circuit 303 which is a camera signal processing circuit, a frame memory 304, a display unit 305, a recording unit 306, an operation unit 307, and a power supply unit 308. The DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, the operation unit 307, and the power supply unit 308 are appropriately connected via connection lines 309 such as bus lines. The solid-state imaging device 301 is housed in any one of the semiconductor packages 200 according to the above-described embodiments.

[0129] The optical unit 302 includes a plurality of lenses, takes in incident light (image light) from a subject, and forms an image on the imaging surface of the solid-state imaging device 301. The solid-state imaging device 301 converts the amount of incident light formed on the imaging surface by the optical unit 302 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0130] The display unit 305 is formed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving images or still images captured by the solid-state imaging device 301. The recording unit 306 records the moving images or still images captured by the solid-state imaging device 301 on a recording medium such as a hard disk or semiconductor memory.

[0131] The operation unit 307, under the operation of a user, issues operation commands for various functions of the camera device 300. The power supply unit 308 appropriately supplies various types of power to the DSP circuit 303, frame memory 304, display unit 305, recording unit 306, and operation unit 307 as operating power sources.

[0132] According to the camera device 300 as described above, the solid-state imaging device 301 can achieve good heat dissipation with a simple configuration.

[0133] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0134] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0135] The present technology may also be configured as follows: (1) A semiconductor package comprising: a frame-shaped wiring substrate having a predetermined number of external terminals arranged on a light-receiving surface thereof; a semiconductor chip electrically connected to the wiring substrate; a transparent member connected to the light-receiving surface of the wiring substrate or the semiconductor chip via a sealing material; and a metal plate having higher rigidity and thermal conductivity than a mounting substrate connected to the external terminals, and connected to one of the two surfaces of the wiring substrate facing the light-receiving surface. (2) The semiconductor package according to (1), wherein the outer periphery of the sealing material is larger than the outer periphery of the transparent member when viewed from a direction perpendicular to the light-receiving surface. (3) The semiconductor package according to (1) or (2), further comprising a stopper formed between the outer periphery of the wiring substrate and the sealing material. (4) The semiconductor package according to (3), wherein the stopper includes a first stopper formed along the outer periphery of the wiring substrate. (5) The semiconductor package according to (3) or (4), wherein the stopper includes a second stopper formed between the sealing material and the external terminals. (6) The semiconductor package according to any one of (3) to (5), wherein the height of the stopper from the wiring board is smaller than the height of the external terminal from the wiring board, and the elastic modulus of the stopper is larger than that of the external terminal. (7) The semiconductor package according to any one of (1) to (6), further comprising a first wall formed between the external terminal and the sealing material. (8) The semiconductor package according to (7), wherein the height of the first wall from the wiring board is larger than the height of the external terminal from the wiring board, and the elastic modulus of the first wall is smaller than that of the external terminal. (9) The semiconductor package according to (7) or (8), further comprising a second wall formed between the first wall and the sealing material. (10) The semiconductor package according to any one of (1) to (9), wherein the height of the sealing material from the wiring board is larger than the height of the external terminal from the wiring board, and the elastic modulus of the sealing material is smaller than that of the external terminal. (11) The semiconductor package according to any one of (1) to (10), wherein the height of the light-receiving surface of the transparent member from the wiring board is greater than the height of the external terminals from the wiring board.(12) The semiconductor package according to any one of (1) to (11), wherein the external terminals are arranged inside the outer periphery of the metal plate when viewed from a direction perpendicular to the light-receiving surface of the wiring board. (13) The semiconductor package according to any one of (1) to (12), wherein through holes are formed in the mounting board, and the transparent member is arranged in the through holes. (14) The semiconductor package according to any one of (1) to (13), wherein the external terminals are solder balls or pins. (15) The semiconductor package according to any one of (1) to (14), further comprising: bonding wires that electrically connect the semiconductor chip and the wiring board; and a sealing material that covers the bonding wires. (16) The semiconductor package according to (1), wherein the semiconductor chip is electrically connected to the wiring board by bumps. (17) A semiconductor device comprising: a mounting substrate, a lens unit mounted on the mounting substrate, a wiring substrate having a predetermined number of external terminals arranged on a light-receiving surface thereof, a semiconductor chip electrically connected to the wiring substrate, a transparent member connected via a sealant to the wiring substrate or the light-receiving surface of the semiconductor chip, and a metal plate having higher rigidity and thermal conductivity than the mounting substrate connected to the external terminals and connected to one of the surfaces of the wiring substrate facing the light-receiving surface. (18) The semiconductor device according to (17), further comprising an external heat sink, one of the surfaces of the metal plate being connected to the wiring substrate and the other being connected to the external heat sink. (19) A method for manufacturing a semiconductor package, comprising the steps of: connecting a metal plate to one of both sides of a frame-shaped wiring board, the frame-shaped wiring board having higher rigidity and thermal conductivity than a mounting board, the surface facing the light-receiving surface; electrically connecting a semiconductor chip to the wiring board; connecting a transparent member to the light-receiving surface of the wiring board or the semiconductor chip via a sealing material; and forming a predetermined number of external terminals on the light-receiving surface of the wiring board.

[0136] REFERENCE SIGNS LIST 100 Semiconductor device 110 Lens unit 111, 112 Lens 120 Mounting substrate 121, 221 Through hole 130 External heat sink 200 Semiconductor package 210 Transparent member 220, 225 Wiring substrate 222, 256 Adhesive 230 Semiconductor chip 240 Metal plate 251 External terminal 252 Sealant 253 Bonding wire 254 Sealant 255 Dam 260 Dust prevention wall 271, 272 Stopper 280 Sealant outflow prevention wall 290 Molded resin 300 Camera device 301 Solid-state imaging device 302 Optical section 303 DSP circuit 304 Frame memory 305 Display section 306 Recording section 307 Operation section 308 Power supply section 309 Connecting wire

Claims

1. A semiconductor package comprising: a frame-shaped wiring board having a predetermined number of external terminals arranged on its light-receiving surface; a semiconductor chip electrically connected to the wiring board; a transparent member connected to the light-receiving surface of the wiring board or the semiconductor chip via a sealant; and a metal plate having higher rigidity and thermal conductivity than a mounting board connected to the external terminals, the metal plate being connected to one of both sides of the wiring board that faces the light-receiving surface.

2. The semiconductor package according to claim 1, wherein the outer periphery of the sealing material is larger than the outer periphery of the transparent member when viewed in a direction perpendicular to the light receiving surface.

3. The semiconductor package according to claim 1, further comprising a stopper formed between the outer periphery of the wiring board and the sealing material.

4. The semiconductor package according to claim 3, wherein the stopper includes a first stopper formed along the outer periphery of the wiring board.

5. The semiconductor package according to claim 3, wherein the stopper includes a second stopper formed between the sealing material and the external terminal.

6. The semiconductor package according to claim 3, wherein the height of said stopper from said wiring board is smaller than the height of said external terminal from said wiring board, and the elastic modulus of said stopper is greater than that of said external terminal.

7. The semiconductor package according to claim 1, further comprising a first wall formed between said external terminals and said sealing material.

8. The semiconductor package according to claim 7, wherein the height of said first wall from said wiring board is greater than the height of said external terminal from said wiring board, and the elastic modulus of said first wall is smaller than that of said external terminal.

9. The semiconductor package according to claim 7, further comprising a second wall formed between said first wall and said sealant.

10. The semiconductor package according to claim 1, wherein the height of said sealant from said wiring board is greater than the height of said external terminals from said wiring board, and the elastic modulus of said sealant is smaller than that of said external terminals.

11. The semiconductor package according to claim 1, wherein the height of the light receiving surface of the transparent member from the wiring board is greater than the height of the external terminals from the wiring board.

12. The semiconductor package according to claim 1, wherein the external terminals are disposed inside the outer periphery of the metal plate when viewed in a direction perpendicular to the light-receiving surface of the wiring board.

13. The semiconductor package according to claim 1, wherein a through hole is formed in the mounting substrate, and the transparent member is disposed in the through hole.

14. The semiconductor package according to claim 1, wherein the external terminals are solder balls or pins.

15. The semiconductor package according to claim 1, further comprising: bonding wires electrically connecting said semiconductor chip and said wiring board; and a sealing material covering said bonding wires.

16. The semiconductor package according to claim 1, wherein the semiconductor chip is electrically connected to the wiring board by bumps.

17. A semiconductor device comprising: a mounting board; a lens unit mounted on the mounting board; a wiring board having a predetermined number of external terminals arranged on its light-receiving surface; a semiconductor chip electrically connected to the wiring board; a transparent member connected to the light-receiving surface of the wiring board or the semiconductor chip via a sealant; and a metal plate having higher rigidity and thermal conductivity than the mounting board connected to the external terminals, and connected to one of the two surfaces of the wiring board facing the light-receiving surface.

18. The semiconductor device according to claim 17, further comprising an external heat sink, one of both surfaces of said metal plate being connected to said wiring board and the other being connected to said external heat sink.

19. A method for manufacturing a semiconductor package, comprising the steps of: connecting a metal plate to the surface of a frame-shaped wiring board, the surface facing the light-receiving surface and having higher rigidity and thermal conductivity than a mounting board; electrically connecting a semiconductor chip to the wiring board; connecting a transparent member to the light-receiving surface of the wiring board or the semiconductor chip via a sealing material; and forming a predetermined number of external terminals on the light-receiving surface of the wiring board.

Images