Semiconductor device

Abstract

[Problem] To provide a semiconductor device capable of further reducing on-resistance. [Solution] A semiconductor device comprising: a semiconductor substrate; a first semiconductor region of a first conductivity type provided on the semiconductor substrate; a second semiconductor region of a second conductivity type different from the first conductivity type provided over the first semiconductor region; a third semiconductor region of the first conductivity type provided over the second semiconductor region; a first electrode provided over the third semiconductor region; a second electrode in contact with the second semiconductor region through an insulator; a conductor connected to the first electrode, insulated from the first semiconductor region through the insulator, and provided under the second electrode; and a fourth semiconductor region of the second conductivity type connected to the first electrode and provided under the conductor.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] In recent years, there has been progress in the development of power devices capable of handling large currents at high voltages.

[0003] For example, Patent Document 1 listed below discloses a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in which the breakdown voltage of an edge termination region is improved by using an N-P-N sandwich structure. The power MOSFET disclosed in Patent Document 1 is a vertically structured power MOSFET in which current flows in the thickness direction of the semiconductor substrate between a drain electrode provided on one surface of the semiconductor substrate and a source electrode provided on the other surface opposite the one surface. A vertically structured power MOSFET can increase current density compared to a horizontally structured power MOSFET in which the drain electrode and source electrode are arranged in the plane direction of the semiconductor substrate, thereby reducing on-resistance.

[0004] Special Publication No. 2011-512676

[0005] Here, in a vertical-structure power MOSFET, there has been a demand for a further reduction in on-resistance in order to improve the switching characteristics.

[0006] Therefore, the present disclosure proposes a new and improved semiconductor device that can further reduce the on-resistance.

[0007] According to the present disclosure, there is provided a semiconductor device comprising: a semiconductor substrate; a first semiconductor region of a first conductivity type provided in the semiconductor substrate; a second semiconductor region of a second conductivity type different from the first conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first electrode provided on the third semiconductor region; a second electrode in contact with the second semiconductor region via an insulator; a conductor connected to the first electrode, insulated from the first semiconductor region via the insulator, and provided below the second electrode; and a fourth semiconductor region of the second conductivity type connected to the first electrode and provided below the conductor.

[0008] FIG. 1 is a longitudinal sectional view schematically showing a cross-sectional configuration of a semiconductor device according to an embodiment of the present disclosure; FIG. 2 is a longitudinal sectional view schematically showing a cross-sectional configuration of a semiconductor device according to a first modified example; FIG. 3 is a longitudinal sectional view schematically showing a cross-sectional configuration of a semiconductor device according to a second modified example; FIG. 4 is a plan view schematically showing a planar configuration of a semiconductor device according to the second modified example; FIG. 5 is a plan view schematically showing a configuration example of a semiconductor device according to a third modified example; FIG. 6 is a plan view schematically showing another configuration example of a semiconductor device according to the third modified example; FIG. 7 is a plan view schematically showing another configuration example of a semiconductor device according to the fourth modified example; FIG. 8 is a plan view schematically showing another configuration example of a semiconductor device according to the fourth modified example;

[0009] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0010] The description will be given in the following order: 1. Configuration of the semiconductor device 2. Modifications 2.1. First modification 2.2. Second modification 2.3. Third modification 2.4. Fourth modification 2.5. Fifth modification 3. Application example

[0011] 1. Configuration of the Semiconductor Device First, the configuration of a semiconductor device according to an embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a vertical cross-sectional view that schematically shows the cross-sectional configuration of a semiconductor device 1 according to this embodiment.

[0012] 1 , the semiconductor device 1 includes a third electrode 103, a semiconductor substrate 100, a fifth semiconductor region 150, a first semiconductor region 110, a second semiconductor region 120, a sixth semiconductor region 121, a third semiconductor region 130, a second electrode 102, an insulator 160, a conductor 170, a fourth semiconductor region 140, and a first electrode 101. The semiconductor device 1 is a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a so-called trench structure.

[0013] Hereinafter, the "first conductivity type" refers to either the "p type" or the "n type", and the "second conductivity type" refers to the other of the "p type" or the "n type" that is different from the "first conductivity type".

[0014] The third electrode 103 is made of a conductive material and is provided on the first main surface of the semiconductor substrate 100. The third electrode 103 is electrically connected to the semiconductor substrate 100 via an ohmic junction or the like, and functions as a drain electrode of the semiconductor device 1, which is a vertical MOSFET. The third electrode 103 may be made of, for example, copper (Cu), nickel (Ni), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), gold (Au), silver (Ag), or a combination of these metals.

[0015] The semiconductor substrate 100 is a substrate made of a semiconductor material of a first conductivity type. For example, the semiconductor substrate 100 may be a highly doped n-type SiC substrate. The concentration of the first conductivity type impurity (e.g., nitrogen (N) or phosphorus (P)) in the semiconductor substrate 100 is 1.0×10 １８ cm －３ ~3.0 x 10 １９ cm －３ The thickness of the semiconductor substrate 100 may be 100 μm to 350 μm.

[0016] The first semiconductor region 110 is made of a semiconductor material of the first conductivity type and is provided on a second main surface of the semiconductor substrate 100 opposite to the first main surface with the fifth semiconductor region 150 interposed therebetween. For example, the first semiconductor region 110 may be formed by epitaxially growing low-concentration n-type SiC. The concentration of the first conductivity type impurity (e.g., nitrogen (N) or phosphorus (P)) in the first semiconductor region 110 is 5.0×10 １５ cm －３ ~1.2 × 10 １６ cm －３ may be.

[0017] The fifth semiconductor region 150 is made of a semiconductor material of the first conductivity type, and is optionally provided between the semiconductor substrate 100 and the first semiconductor region 110. The fifth semiconductor region 150 is a layer configured so that the concentration of first conductivity type impurities on the first semiconductor region 110 side is lower than the concentration of first conductivity type impurities on the semiconductor substrate 100 side. For example, the fifth semiconductor region 150 may be made of n-type SiC.

[0018] Specifically, the concentration of the first conductivity type impurity on the semiconductor substrate 100 side of the fifth semiconductor region 150 may be the same as or lower than the concentration of the first conductivity type impurity in the semiconductor substrate 100. On the other hand, the concentration of the first conductivity type impurity on the first semiconductor region 110 side of the fifth semiconductor region 150 may be the same as or higher than the concentration of the first conductivity type impurity in the first semiconductor region 110. In this way, the fifth semiconductor region 150 can alleviate the concentration gap of the first conductivity type impurity between the semiconductor substrate 100 and the first semiconductor region 110, and therefore the first semiconductor region 110 can be epitaxially grown with fewer defects.

[0019] As one example, the fifth semiconductor region 150 may be provided as a layer having a concentration gradient in which the concentration of the first conductivity type impurity gradually decreases from the semiconductor substrate 100 side toward the first semiconductor region 110 side. As another example, the fifth semiconductor region 150 may be provided in a stacked structure in which a plurality of (e.g., 3, 4, or 5 or more) layers are stacked, in which the concentration of the first conductivity type impurity gradually decreases from the semiconductor substrate 100 side toward the first semiconductor region 110 side.

[0020] The second semiconductor region 120 is made of a semiconductor material of a second conductivity type and is provided on the first semiconductor region 110. For example, the second semiconductor region 120 may be made by epitaxially growing p-type SiC. The concentration of the second conductivity type impurity (e.g., aluminum (Al)) in the second semiconductor region 120 is 1.0×10 １６ cm －３ ~5.0 x 10 １７ cm －３ The second semiconductor region 120 is provided with a third semiconductor region 130 and a sixth semiconductor region 121, which will be described later.

[0021] The second electrode 102 is made of a conductive material and is provided as a trench electrode inside a trench T provided in the second semiconductor region 120 and the first semiconductor region 110. The trench T is a groove dug from the second semiconductor region 120 side in the stacking direction of the second semiconductor region 120 and the first semiconductor region 110 to a depth reaching a fourth semiconductor region 140 (described later). Inside the trench T, the second electrode 102 and a conductor 170 (described later) are provided extending in a direction perpendicular to the plane of FIG. 1 . The second electrode 102 may be provided, for example, inside the trench T at a depth corresponding to the second semiconductor region 120 and the interface between the second semiconductor region 120 and the first semiconductor region 110. The second electrode 102 may be made of, for example, poly-Si doped with conductive impurities. The second electrode 102 functions as a gate electrode of the semiconductor device 1, which is a vertical MOSFET.

[0022] The insulator 160 is made of an insulating material and is provided so as to bury the inside of the trench T, enclosing the second electrode 102 and the conductor 170 described below. The insulator 160 can form a MOS (Metal-Oxide-Semiconductor) gate structure by being interposed between the inner wall of the trench T and the second electrode 102. The insulator 160 can also electrically insulate the conductor 170 from the first semiconductor region 110. The insulator 160 can be made of, for example, silicon oxide (SiO ｘ ) may be configured.

[0023] The third semiconductor region 130 is a semiconductor region of the first conductivity type and is provided on the second semiconductor region 120. Specifically, the third semiconductor region 130 may be provided inside the second semiconductor region 120 on both sides of the second electrode 102, spaced apart from the first semiconductor region 110 in the depth direction of the second semiconductor region 120, so as to sandwich the trench T. As a result, the first semiconductor region 110, the second semiconductor region 120, and the third semiconductor region 130 are aligned in the vertical direction (i.e., the depth direction of the second semiconductor region 120) on the side surfaces of the second electrode 102. For example, the third semiconductor region 130 may be a high-concentration n-type SiC region. The concentration of the first conductivity type impurity (e.g., nitrogen (N) or phosphorus (P)) in the third semiconductor region 130 is 7.0×10１８ cm －３ ~7.0 x 10 １９ cm －３ may be.

[0024] The sixth semiconductor region 121 is a semiconductor region of the second conductivity type, and is provided on the second semiconductor region 120 on the opposite side of the third semiconductor region 130 from the second electrode 102. The sixth semiconductor region 121 is provided between the third semiconductor regions 130 of adjacent semiconductor devices 1, and connects the first electrode 101 and the second semiconductor region 120. The sixth semiconductor region 121 may be, for example, a high-concentration p-type SiC region. The concentration of the second conductivity type impurity (e.g., aluminum (Al)) in the sixth semiconductor region 121 is 7.0×10 １８ cm －３ ~7.0 x 10 １９ cm －３ may be.

[0025] The first electrode 101 is made of a conductive material and is provided on the second semiconductor region 120 including the third semiconductor region 130 and the sixth semiconductor region 121. The first electrode 101 is electrically connected to the third semiconductor region 130 via an ohmic junction or the like, and functions as a source electrode of the semiconductor device 1, which is a vertical MOSFET. The first electrode 101 may be made of, for example, copper (Cu), nickel (Ni), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), gold (Au), silver (Ag), or a combination of these metals.

[0026] The conductor 170 is made of a conductive material and is provided inside the trench T below the second electrode 102. The conductor 170 may be provided, for example, inside the trench T at a depth corresponding to the first semiconductor region 110. The conductor 170 may be made of, for example, poly-Si doped with conductive impurities.

[0027] The conductor 170 is electrically insulated from the first semiconductor region 110 by the insulator 160 and electrically connected to the first electrode 101 in a region not shown. This results in the conductor 170 being at approximately the same potential as the third semiconductor region 130. "Approximately the same potential" means that the same voltage is supplied without any voltage drop due to intentional resistance or load. This allows the conductor 170 to relax the electric field between the second electrode 102 and the third electrode 103, thereby reducing the parasitic capacitance generated between the third electrode 103 and the second electrode 102. In other words, the semiconductor device 1 can reduce the opposing area between the second electrode 102 (gate electrode) and the third electrode 103 (drain electrode) by providing the conductor 170 electrically connected to the first electrode 101 (source electrode) directly below the second electrode 102 (gate electrode). Therefore, the semiconductor device 1 can significantly reduce the gate-drain capacitance between the third electrode 103 and the second electrode 102. Therefore, the conductor 170 can further improve the switching characteristics of the semiconductor device 1 .

[0028] The fourth semiconductor region 140 is made of a semiconductor material of the second conductivity type and is provided below the conductor 170. Specifically, the fourth semiconductor region 140 may be provided in the first semiconductor region 110 below the conductor 170 so as to be in contact with the bottom surface of the trench T. For example, the fourth semiconductor region 140 may be made of high-concentration p-type SiC. The concentration of the second conductivity type impurity (e.g., aluminum (Al)) in the fourth semiconductor region 140 is 1.0×10 １８ cm －３ ~3.0 x 10 １９ cm －３ The fourth semiconductor region 140 is electrically connected to the first electrode 101 in a region not shown, and thereby has approximately the same potential as the third semiconductor region 130. As described above, approximately the same potential means that the same voltage is supplied without any voltage drop due to intentional resistance or load.

[0029] The fourth semiconductor regions 140 may be provided in a stripe pattern by extending parallel to each other below each conductor 170 of the semiconductor device 1. In this way, at the depth where the fourth semiconductor regions 140 are provided, the fourth semiconductor regions 140 and the first semiconductor regions 110 are alternately arranged, thereby forming a so-called superjunction structure. Therefore, the semiconductor device 1 can more easily ensure voltage resistance due to the depletion layer extending from the fourth semiconductor region 140 to the first semiconductor region 110, and therefore the on-resistance can be reduced by increasing the impurity concentration of the first semiconductor region 110.

[0030] Furthermore, the fourth semiconductor region 140 is provided further below the conductor 170, and thus, like the conductor 170, can further reduce the electric field between the third electrode 103 and the second electrode 102. Therefore, like the conductor 170, the fourth semiconductor region 140 can further reduce the parasitic capacitance generated between the third electrode 103 and the second electrode 102, and therefore, the switching characteristics of the semiconductor device 1 can be further improved.

[0031] Furthermore, the fourth semiconductor region 140 is provided with a second conductivity type different from the first conductivity type of the first semiconductor region 110, thereby making it possible to prevent a high electric field from being applied to the insulator 160 at the tip of the conductor 170. Therefore, the fourth semiconductor region 140 can prevent the insulator 160 at the tip of the conductor 170 from being broken down by a sudden large current or high voltage.

[0032] When the semiconductor device 1 operates as a pn diode, the pn diode can be formed between the fourth semiconductor region 140 electrically connected to the first electrode 101 and the first semiconductor region 110. This allows the semiconductor device 1 to form the pn diode over a shorter distance, thereby making it possible to further reduce the on-resistance when operating as a pn diode.

[0033] When the second electrode 102 is turned on by application of a voltage, the semiconductor device 1 having the above configuration forms an inversion layer in the second semiconductor region 120 between the first semiconductor region 110 and the third semiconductor region 130 on the side surface of the second electrode 102. This allows the semiconductor device 1 to form a channel serving as a current path in the second semiconductor region 120 between the third semiconductor region 130 and the first semiconductor region 110, thereby establishing electrical continuity between the third semiconductor region 130 and the first semiconductor region 110. Therefore, the semiconductor device 1 can pass a current between the first electrode 101 and the third electrode 103.

[0034] On the other hand, in the semiconductor device 1, when the second electrode 102 is turned off by stopping the voltage application, the channel formed in the second semiconductor region 120 between the first semiconductor region 110 and the third semiconductor region 130 on the side surface of the second electrode 102 is lost. This allows the semiconductor device 1 to make the third semiconductor region 130 and the first semiconductor region 110 non-conductive, thereby stopping the flow of current between the first electrode 101 and the third electrode 103.

[0035] In the semiconductor device 1 according to this embodiment, by further providing the fourth semiconductor region 140 below the conductor 170, a superjunction structure can be formed between the fourth semiconductor region 140 and the first semiconductor region 110. This allows the semiconductor device 1 to further increase the impurity concentration of the first semiconductor region 110, thereby making it possible to reduce the on-resistance.

[0036] Furthermore, the semiconductor device 1 can further reduce the parasitic capacitance generated between the third electrode 103 and the second electrode 102 by the fourth semiconductor region 140 provided below the conductor 170, thereby further improving the switching characteristics. Furthermore, the semiconductor device 1 can prevent a high electric field from being applied to the insulator 160 at the tip of the conductor 170, thereby preventing the insulator 160 at the tip of the conductor 170 from undergoing dielectric breakdown.

[0037] 2. Modifications Next, first to fifth modifications of the semiconductor device 1 according to this embodiment will be described with reference to FIGS.

[0038] (2.1. First Modification) A semiconductor device 1A according to a first modification will be described with reference to Fig. 2. Fig. 2 is a vertical cross-sectional view schematically showing the cross-sectional configuration of the semiconductor device 1A according to the first modification.

[0039] As shown in FIG. 2, in the semiconductor device 1A according to the first modification, the conductor 170 is provided so as to be connected to the fourth semiconductor region 140 .

[0040] Specifically, in the semiconductor device 1A, the conductor 170 is provided so as to penetrate below the insulator 160 and directly connect to the fourth semiconductor region 140. The conductor 170 and the fourth semiconductor region 140 are electrically connected to the first electrode 101 so as to be at approximately the same potential as the third semiconductor region 130. Therefore, by directly connecting the conductor 170 and the fourth semiconductor region 140 to each other, it is possible to form an electrical connection with the first electrode 101 collectively. Therefore, the semiconductor device 1A can have a simpler structure than the semiconductor device 1. Note that the connection between the conductor 170 and the fourth semiconductor region 140 can be easily formed by etching the insulator 160 below the conductor 170.

[0041] In the semiconductor device 1A, sufficient voltage resistance is ensured by the junction between the fourth semiconductor region 140 and the first semiconductor region 110, and therefore it is not necessary to consider the voltage resistance of the junction between the fourth semiconductor region 140 and the conductor 170. Therefore, in the semiconductor device 1A, it is possible to reduce the resistance by setting the concentration of the conductive impurities in the conductor 170 higher.

[0042] (2.2. Second Modification) A semiconductor device 1B according to a second modification will be described with reference to Figures 3A and 3B. Figure 3A is a vertical cross-sectional view schematically showing the cross-sectional configuration of the semiconductor device 1B according to the second modification. Figure 3B is a plan view schematically showing the planar configuration of the semiconductor device 1B according to the second modification.

[0043] As shown in FIGS. 3A and 3B, in a semiconductor device 1B according to the second modification, the fourth semiconductor region 140 is provided extending in a direction perpendicular to the second electrode 102 and the conductor 170.

[0044] Specifically, in the semiconductor device 1B, the second electrode 102 and the conductor 170 are arranged to extend in a first direction (up and down when facing directly at FIG. 3B), and the fourth semiconductor region 140 is arranged to extend in a second direction (left and right when facing directly at FIG. 3B) that is perpendicular to the first direction.

[0045] Even in such a case, the fourth semiconductor region 140 can form a so-called superjunction structure between the fourth semiconductor region 140 and the first semiconductor region 110 by extending in a stripe pattern. This allows the semiconductor device 1B to more easily ensure breakdown voltage due to the depletion layer extending from the fourth semiconductor region 140 to the first semiconductor region 110, thereby making it possible to reduce the on-resistance by increasing the impurity concentration of the first semiconductor region 110. In particular, the semiconductor device 1B does not need to extend the fourth semiconductor region 140 in parallel directly below the second electrode 102 and the conductor 170, making it possible to further increase the area of ​​the fourth semiconductor region 140. Therefore, the semiconductor device 1B can further reduce the on-resistance by further increasing the impurity concentration of the first semiconductor region 110.

[0046] Furthermore, in the semiconductor device 1B, in the region where the fourth semiconductor region 140, the second electrode 102, and the conductor 170 intersect and overlap at right angles, the fourth semiconductor region 140 can further reduce the parasitic capacitance generated between the third electrode 103 and the second electrode 102. Therefore, the semiconductor device 1B can improve switching characteristics. Furthermore, in the region where the fourth semiconductor region 140, the second electrode 102, and the conductor 170 intersect and overlap at right angles, the fourth semiconductor region 140 can prevent a high electric field from being applied to the insulator 160 at the tip of the conductor 170. Therefore, the semiconductor device 1B can prevent dielectric breakdown of the insulator 160 at the tip of the conductor 170 due to a sudden large current or high voltage.

[0047] (2.3. Third Modification) Semiconductor devices 1C and 1D according to a third modification will be described with reference to Fig. 4 and Fig. 5. Fig. 4 is a plan view schematically showing a configuration example of a semiconductor device 1C according to the third modification. Fig. 5 is a plan view schematically showing a configuration example of a semiconductor device 1D according to the third modification.

[0048] As shown in FIGS. 4 and 5, in semiconductor devices 1C and 1D according to the third modification, the second electrodes 102 and the conductors 170 are provided extending in a grid pattern.

[0049] Specifically, in semiconductor devices 1C and 1D, second electrodes 102 and conductors 170 are provided to extend in a first direction (up-down direction when facing directly at FIGS. 4 and 5 ) and a second direction (left-right direction when facing directly at FIGS. 4 and 5 ) that is orthogonal to the first direction. That is, in semiconductor devices 1C and 1D, second electrodes 102 and conductors 170 are provided in a two-dimensional lattice pattern in which rectangular openings are repeatedly formed in a matrix.

[0050] In such a case, the semiconductor devices 1C and 1D can form the third semiconductor region 130 along the inside of the rectangular opening provided in the second electrode 102. This allows the semiconductor devices 1C and 1D to form channels on each side of the inside of the rectangular opening surrounded by the second electrode 102, making it possible to pass a larger current between the first electrode 101 and the third electrode 103.

[0051] 4, the fourth semiconductor region 140 may be provided directly below the second electrode 102 and the conductor 170 extending in the second direction, or may be provided offset from the second electrode 102 and the conductor 170 extending in the second direction so as not to overlap with them, as shown in FIG. 5. In either case, the fourth semiconductor region 140 extends in a stripe pattern in the second direction, thereby forming a so-called superjunction structure between the fourth semiconductor region 140 and the first semiconductor region 110. Therefore, in the semiconductor devices 1C and 1D, the on-resistance can be reduced by increasing the impurity concentration of the first semiconductor region 110.

[0052] Furthermore, in the semiconductor devices 1C and 1D, in the region where the fourth semiconductor region 140, the second electrode 102, and the conductor 170 intersect and overlap at right angles, the fourth semiconductor region 140 can further reduce the parasitic capacitance generated between the third electrode 103 and the second electrode 102. Therefore, the semiconductor devices 1C and 1D can improve switching characteristics. Furthermore, in the semiconductor devices 1C and 1D, in the region where the fourth semiconductor region 140, the second electrode 102, and the conductor 170 intersect and overlap at right angles, the fourth semiconductor region 140 can prevent a high electric field from being applied to the insulator 160 at the tip of the conductor 170. Therefore, the semiconductor devices 1C and 1D can prevent dielectric breakdown of the insulator 160 at the tip of the conductor 170 due to a sudden large current or high voltage.

[0053] (2.4. Fourth Modification) Semiconductor devices 1E and 1F according to a fourth modification will be described with reference to Fig. 6 and Fig. 7. Fig. 6 is a plan view schematically showing a configuration example of the semiconductor device 1E according to the fourth modification. Fig. 7 is a plan view schematically showing a configuration example of the semiconductor device 1F according to the fourth modification.

[0054] As shown in Figures 6 and 7, in semiconductor devices 1E and 1F relating to the fourth modified example, the second electrode 102 and the conductor 170 are provided so as to spread over a predetermined region, and the third semiconductor region 130 is provided inside circular openings H that are periodically formed in the second electrode 102 and the conductor 170.

[0055] In the semiconductor devices 1E and 1F, the third semiconductor region 130 can be formed along the inside of the circular opening H provided in the second electrode 102. Therefore, in the semiconductor devices 1E and 1F, a channel can be formed inside the circular opening H surrounded by the second electrode 102, and therefore a larger current can be passed between the first electrode 101 and the third electrode 103.

[0056] The openings H provided in the second electrode 102 may be periodically arranged at positions corresponding to the vertices and centers of a hexagon (a so-called hexagonal lattice arrangement), for example, as shown in Fig. 6. Alternatively, the openings H provided in the second electrode 102 may be periodically arranged at positions corresponding to the vertices of a square (a so-called tetragonal lattice arrangement), as shown in Fig. 7. The openings H provided in the second electrode 102 may be circular as shown in Figs. 6 and 7, but needless to say, they may also be elliptical or polygonal.

[0057] The fourth semiconductor region 140 may be provided in a stripe pattern extending in any direction below the second electrode 102 and the conductor 170. For example, the fourth semiconductor region 140 may be provided passing between the openings H and extending in the row arrangement direction of the openings H. This allows the semiconductor devices 1E and 1F to form a so-called super junction structure between the fourth semiconductor region 140 and the first semiconductor region 110, thereby making it possible to reduce the on-resistance.

[0058] Furthermore, in the semiconductor devices 1E and 1F, in the region where the fourth semiconductor region 140 overlaps with the second electrode 102 and the conductor 170, the fourth semiconductor region 140 can further reduce the parasitic capacitance generated between the third electrode 103 and the second electrode 102. Therefore, the semiconductor devices 1E and 1F can improve the switching characteristics. Furthermore, in the region where the fourth semiconductor region 140 overlaps with the second electrode 102 and the conductor 170, the fourth semiconductor region 140 can prevent a high electric field from being applied to the insulator 160 at the tip of the conductor 170. Therefore, the semiconductor devices 1E and 1F can prevent the insulator 160 at the tip of the conductor 170 from being broken down by a sudden large current or high voltage.

[0059] (2.5. Fifth Modification) Semiconductor devices 1G and 1H according to a fifth modification will be described with reference to Fig. 8 and Fig. 9. Fig. 8 is a plan view schematically showing a configuration example of a semiconductor device 1G according to the fifth modification. Fig. 9 is a plan view schematically showing a configuration example of a semiconductor device 1H according to the fifth modification.

[0060] As shown in Figures 8 and 9, in semiconductor devices 1G and 1H relating to the fifth modified example, the second electrode 102 and the conductor 170 are provided so as to spread over a predetermined region, and the third semiconductor region 130 is provided inside hexagonal openings H formed periodically in the second electrode 102 and the conductor 170.

[0061] In the semiconductor devices 1G and 1H, the third semiconductor region 130 can be formed along the inside of the hexagonal opening H provided in the second electrode 102. Therefore, in the semiconductor devices 1G and 1H, a current can be passed along each side of the inside of the hexagonal opening H surrounded by the second electrode 102, and therefore a larger current can be passed between the first electrode 101 and the third electrode 103.

[0062] The openings H provided in the second electrode 102 may be periodically arranged in a close-packed arrangement at positions corresponding to the vertices and the center of a hexagon, as shown in Fig. 8. For example, the openings H may be arranged in rows at a predetermined pitch in a first direction (the up-down direction when facing Fig. 8), and may be arranged such that each row of openings H is shifted by ½ pitch in a second direction (the left-right direction when facing Fig. 8) perpendicular to the first direction.

[0063] 9, the openings H formed in the second electrode 102 may be formed in a hexagonal shape and arrangement elongated in one direction. In this case, the openings H can ensure a larger margin for misalignment in the elongated longitudinal direction when contacting the first electrode 101. Therefore, the openings H can reliably contact the first electrode 101 in the elongated longitudinal direction, thereby further improving the reliability of the semiconductor device 1H.

[0064] The fourth semiconductor region 140 may be provided in a striped pattern extending in any direction below the second electrode 102 and the conductor 170. For example, as illustrated in Figures 8 and 9, the fourth semiconductor region 140 may be provided extending in a second direction in which the openings H are arranged at a ½ pitch. Alternatively, the fourth semiconductor region 140 may be provided extending in a first direction in which the openings H are arranged in a row. This allows the semiconductor devices 1G and 1H to form a so-called super junction structure between the fourth semiconductor region 140 and the first semiconductor region 110, thereby reducing the on-resistance.

[0065] Furthermore, in the semiconductor devices 1G and 1H, in the region where the fourth semiconductor region 140 overlaps with the second electrode 102 and the conductor 170, the fourth semiconductor region 140 can further reduce the parasitic capacitance generated between the third electrode 103 and the second electrode 102. Therefore, the semiconductor devices 1G and 1H can improve the switching characteristics. Furthermore, in the region where the fourth semiconductor region 140 overlaps with the second electrode 102 and the conductor 170, the fourth semiconductor region 140 can prevent a high electric field from being applied to the insulator 160 at the tip of the conductor 170. Therefore, the semiconductor devices 1G and 1H can prevent the insulator 160 at the tip of the conductor 170 from being broken down by a sudden large current or high voltage.

[0066] 3. Application Examples The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0067] The semiconductor device 1 according to the present embodiment can be applied to, for example, a transistor included in a control circuit of an electrical component of a vehicle. The technology according to the present disclosure can further reduce the on-resistance of the transistor, thereby further improving the switching characteristics of the transistor.

[0068] Although the preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0069] For example, in the above embodiment, the semiconductor device 1 has been described as a vertical MOSFET, but the present technology is not limited to this example. For example, the semiconductor device 1 may be a lateral MOSFET in which the drain electrode and the source electrode are arranged in the plane direction of the semiconductor substrate.

[0070] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0071] The following configurations also fall within the technical scope of the present disclosure: (1) A semiconductor device comprising: a semiconductor substrate; a first semiconductor region of a first conductivity type provided in the semiconductor substrate; a second semiconductor region of a second conductivity type different from the first conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first electrode provided on the third semiconductor region; a second electrode in contact with the second semiconductor region via an insulator; a conductor connected to the first electrode, insulated from the first semiconductor region via the insulator, and provided below the second electrode; and a fourth semiconductor region of the second conductivity type connected to the first electrode and provided below the conductor. (2) The semiconductor device according to (1), further comprising: a fifth semiconductor region of the first conductivity type provided between the semiconductor substrate and the first semiconductor region, wherein in the fifth semiconductor region, a concentration of conductivity-type impurities on the first semiconductor region side is lower than a concentration of conductivity-type impurities on the semiconductor substrate side. (3) The semiconductor device according to (1) or (2), further comprising a trench provided in the second semiconductor region and the first semiconductor region, and the second electrode provided inside the trench. (4) The semiconductor device according to (3), wherein the insulator is provided between an inner wall of the trench and the second electrode. (5) The semiconductor device according to (3) or (4), wherein the conductor is provided inside the trench below the second electrode. (6) The semiconductor device according to (5), wherein the insulator further extends between the inner wall of the trench and the conductor. (7) The semiconductor device according to (6), wherein the conductor is in contact with the fourth semiconductor region. (8) The semiconductor device according to any one of (1) to (7), wherein the second electrode, the conductor, and the fourth semiconductor region are provided extending in the same direction. (9) The semiconductor device according to any one of (1) to (7), wherein the fourth semiconductor region is provided below the conductor in at least a portion thereof. (10) The semiconductor device according to (9), wherein the second electrode and the conductor are provided extending in a first direction, and the fourth semiconductor region is provided extending in a second direction perpendicular to the first direction.(11) The semiconductor device according to any one of (1) to (7), wherein the second electrode is provided so as to spread over a predetermined region, and the third semiconductor region is provided along the inner walls of a plurality of openings periodically provided in the second electrode. (12) The semiconductor device according to (11), wherein the shape of the plurality of openings is circular, rectangular, or hexagonal. (13) The semiconductor device according to (12), wherein the plurality of openings are provided in a tetragonal lattice array or a hexagonal lattice array.

[0072] REFERENCE SIGNS LIST 1 semiconductor device 100 semiconductor substrate 101 first electrode 102 second electrode 103 third electrode 110 first semiconductor region 120 second semiconductor region 121 sixth semiconductor region 130 third semiconductor region 140 fourth semiconductor region 150 fifth semiconductor region 160 insulator 170 conductor T trench H opening

Claims

1. A semiconductor device comprising: a semiconductor substrate; a first semiconductor region of a first conductivity type provided on the semiconductor substrate; a second semiconductor region of a second conductivity type different from the first conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first electrode provided on the third semiconductor region; a second electrode in contact with the second semiconductor region via an insulator; a conductor connected to the first electrode, insulated from the first semiconductor region via the insulator, and provided below the second electrode; and a fourth semiconductor region of the second conductivity type connected to the first electrode and provided below the conductor.

2. The semiconductor device according to claim 1, further comprising a fifth semiconductor region of the first conductivity type provided between the semiconductor substrate and the first semiconductor region, wherein in the fifth semiconductor region, a concentration of the conductivity type impurity on the first semiconductor region side is lower than a concentration of the conductivity type impurity on the semiconductor substrate side.

3. The semiconductor device according to claim 1, further comprising a trench provided in said second semiconductor region and said first semiconductor region, said second electrode being provided inside said trench.

4. The semiconductor device according to claim 3, wherein the insulator is provided between an inner wall of the trench and the second electrode.

5. The semiconductor device according to claim 3, wherein the conductor is provided inside the trench below the second electrode.

6. The semiconductor device according to claim 5, wherein the insulator further extends between the inner wall of the trench and the conductor.

7. The semiconductor device according to claim 6, wherein said conductor is in contact with said fourth semiconductor region.

8. The semiconductor device according to claim 1, wherein the second electrode, the conductor, and the fourth semiconductor region are provided extending in the same direction.

9. The semiconductor device according to claim 1, wherein the fourth semiconductor region is provided below the conductor in at least a portion thereof.

10. The semiconductor device according to claim 9, wherein the second electrode and the conductor are provided extending in a first direction, and the fourth semiconductor region is provided extending in a second direction perpendicular to the first direction.

11. The semiconductor device according to claim 1, wherein the second electrode is provided spreading over a predetermined region, and the third semiconductor region is provided along the inner walls of a plurality of openings periodically provided in the second electrode.

12. The semiconductor device according to claim 11, wherein the shape of the plurality of openings is a circle, a rectangle, or a hexagon.

13. The semiconductor device according to claim 12, wherein the plurality of openings are arranged in a tetragonal lattice array or a hexagonal lattice array.

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