Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device includes: a silicon carbide layer 12 of a first conductivity type; a plurality of well regions 50 of a second conductivity type, the plurality of well regions 50 being provided on the silicon carbide layer 12; source regions 40 of a first conductivity type, the source regions 40 being provided in the well regions 50; a JFET region 20 of the first conductivity type, the JFET region 20 being formed in a region sandwiched between the plurality of well regions 50 on the silicon carbide layer 12; an insulating film covering the JFET region 20; and a gate electrode 80 provided on the JFET region 20 with the insulating film interposed therebetween. First-conductivity-type impurities injected into the JFET region 20 are also injected into the well regions 50. Within the well regions 50, the concentration of second-conductivity-type impurities is higher than the concentration of the first-conductivity-type impurities.

Description

Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

[0001] The present invention relates to a silicon carbide semiconductor device having a JFET region and a method for manufacturing the silicon carbide semiconductor device.

[0002] Silicon carbide semiconductor devices having a JFET region have been known for some time. For example, Japanese Patent No. 7127748 discloses a silicon carbide semiconductor device having a semiconductor substrate made of silicon carbide, a drift layer made of a silicon carbide semiconductor of a first conductivity type formed on the semiconductor substrate, one or more well regions of a second conductivity type formed in a surface layer portion of the drift layer, a JFET region of the first conductivity type that is part of the drift layer and sandwiched between the well regions, and a source region of the first conductivity type that is formed on the surface side of the well region and spaced apart from the drift layer, and that has a higher concentration of first conductivity type impurities than the drift layer.

[0003] In actual silicon carbide semiconductor devices, when the JFET concentration is high, if the JFET region is completely connected to the well region, sufficient breakdown voltage cannot be ensured, so it is common to separate the JFET region from the well region and create a region with a low impurity concentration.However, if such a region with a low impurity concentration exists, there is a problem that the on-resistance increases.

[0004] In view of the above, the present invention provides a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device that can ensure a sufficient breakdown voltage while suppressing the on-resistance.

[0005] [Concept 1] A silicon carbide semiconductor device according to the present invention comprises: a silicon carbide layer of a first conductivity type; a plurality of well regions of a second conductivity type provided in the silicon carbide layer; a source region of a first conductivity type provided in the well region; a JFET region of a first conductivity type formed in a region of the silicon carbide layer that is sandwiched between the plurality of well regions; an insulating film covering the JFET region; and a gate electrode provided on the JFET region via the insulating film, wherein first conductivity type impurities implanted into the JFET region are also implanted into the well regions, and a concentration of the second conductivity type impurities in the well region may be greater than a concentration of the first conductivity type impurities.

[0006] [Concept 2] In the silicon carbide semiconductor device according to Concept 1, the first conductivity type impurity may be implanted into a range from the JFET region to a position below at least an end of the source region on the JFET region side in the well region.

[0007] [Concept 3] In the silicon carbide semiconductor device according to Concept 1 or 2, within the well region, nitrogen may be implanted as the first conductivity type impurity in an upper region, and phosphorus may be implanted as the first conductivity type impurity in a lower region below the upper region.

[0008] [Concept 4] In the silicon carbide semiconductor device according to Concept 3, the concentrations of the nitrogen and the phosphorus may be lower than the concentration of the second conductivity type impurity at any depth position in the well region.

[0009] [Concept 5] In the silicon carbide semiconductor device according to Concept 3 or 4, the distance in the depth direction between the lower limit point where the nitrogen impurity concentration starts to decrease in the direction of increasing depth and the upper limit point where the phosphorus impurity concentration starts to decrease in the direction of decreasing depth may be 0.5 μm or less.

[0010] [Concept 6] In the silicon carbide semiconductor device according to any one of Concepts 3 to 5, the difference between the maximum impurity concentration of nitrogen and the maximum impurity concentration of phosphorus may be within 20%.

[0011] [Concept 7] A method for manufacturing a silicon carbide semiconductor device according to the present invention comprises the steps of: forming a plurality of well regions of a second conductivity type in a silicon carbide layer of a first conductivity type; forming a source region of a first conductivity type in the well region; forming a JFET region in the region of the silicon carbide layer that is sandwiched between the plurality of well regions by injecting impurities of the first conductivity type into a region of the silicon carbide layer that is sandwiched between the plurality of well regions and into a region of the well region on the silicon carbide layer side; forming an insulating film that covers the JFET region; and forming a gate electrode that is provided on the JFET region via the insulating film, wherein a concentration of the second conductivity type impurities in the well region may be greater than a concentration of the first conductivity type impurities.

[0012] According to the present invention, the first conductivity type impurity is implanted into the JFET region to such an extent that it also penetrates into the well region, so that the first conductivity type impurity can be implanted without providing a gap between the JFET region and the well region, thereby suppressing the on-resistance. Furthermore, since the concentration of the second conductivity type impurity in the well region is higher than the concentration of the first conductivity type impurity, a sufficient breakdown voltage can be ensured.

[0013] 1 is a graph showing the relationship between the atomic concentration of aluminum, nitrogen, and phosphorus and depth in a cross section of a well region along line III-III′ in FIG.

[0014] A silicon carbide semiconductor device according to the present embodiment will be described. In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this. The first conductivity type may be p-type and the second conductivity type may be n-type. In this embodiment, a plane perpendicular to the up-down direction in FIG. 1 is referred to as an in-plane direction.

[0015] 1 , the silicon carbide semiconductor device of this embodiment is, for example, a power MOSFET, and one example is a planar power MOSFET. The silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate 11, an n-type silicon carbide layer 12 provided on a first main surface (upper surface) of the silicon carbide semiconductor substrate 11, a plurality of p-type well regions 50 provided in the silicon carbide layer 12, an n-type source region 40 provided in the well region 50, an n-type JFET region 20 formed in a region of the silicon carbide layer 12 sandwiched between the plurality of well regions 50, a gate insulating film 60 that is an insulating film covering the JFET region 20, and a gate electrode 80 provided on the JFET region 20 via the gate insulating film 60.

[0016] The well region 50 is deep enough that its bottom surface is positioned higher than the bottom surface of the silicon carbide layer 12, and the well region 50 is provided in the silicon carbide layer 12. The source region 40 is deep enough that its bottom surface is positioned higher than the bottom surface of the well region 50, and the source region 40 is formed in the well region 50.

[0017] When forming the JFET region 20, n-type impurities are implanted into a region of the silicon carbide layer 12 that is sandwiched between a plurality of well regions 50, but in this embodiment, the n-type impurities implanted into the JFET region 20 are also implanted into the well regions 50. Therefore, no gap is provided between the JFET region 20 and the well region 50, and the JFET region 20 and the well region 50 are in contact with each other in the in-plane direction at least on their upper end surfaces. By adopting such an embodiment, n-type impurities are implanted without providing a gap between the JFET region 20 and the well region 50, thereby making it possible to suppress the on-resistance.

[0018] In this embodiment, the n-type impurities used to form the JFET region 20 are implanted into the well region 50. However, as shown in FIG. 3 , the concentration of the p-type impurities is higher than the concentration of the n-type impurities. Since the concentration of the p-type impurities in the well region 50 is thus higher than the concentration of the n-type impurities (because the p-type well region 50 can be secured with the designed size), a sufficient breakdown voltage can be ensured even if no gap is provided between the JFET region 20 and the well region 50 and the JFET region 20 and the well region 50 are in in-plane contact at least at the upper end surface. As an example, FIG. 3 is a graph showing the relationship between atomic concentration and depth when aluminum, nitrogen, and phosphorus are implanted into the well region 50. The atomic concentration of aluminum (Al), which is a p-type impurity, is higher than the atomic concentrations of phosphorus (P) and nitrogen (N), which are n-type impurities.

[0019] The silicon carbide layer 12 may be formed by a CVD method or the like on the first main surface of the silicon carbide semiconductor substrate 11. The n-type impurity concentration in the silicon carbide layer 12 may be lower than the n-type impurity concentration in the silicon carbide semiconductor substrate 11, and the silicon carbide layer 12 may be in a low concentration region (n － Nitrogen (N), phosphorus (P), or the like can be used as n-type impurities, and aluminum (Al), boron (B), or the like can be used as p-type impurities.

[0020] The gate electrode 80 may be made of, for example, polysilicon. As shown in FIG. 1 , an interlayer insulating film 65 may be formed so as to cover the gate electrode 80. The gate electrode 80 may be formed using a CVD method, a photolithography technique, or the like. The interlayer insulating film 65 may be formed by a CVD method or the like, and may be made of, for example, silicon dioxide. The gate insulating film 60 may also be made of silicon dioxide or the like.

[0021] The well region 50 may be formed, for example, by implanting p-type impurities into the silicon carbide layer 12, and the source region 40 may be formed, for example, by implanting n-type impurities into the well region 50. A drain electrode 90 may be provided on the second main surface (lower surface) of the silicon carbide semiconductor substrate 11. A breakdown voltage structure (not shown) may be provided outside the periphery of the region used as the cell. The drain electrode 90 may be made of, for example, titanium, aluminum, nickel, or the like.

[0022] N-type impurities may be implanted in a range from the JFET region 20 to a position below at least the end of the source region 40 in the well region 50 on the JFET region side, so that the n-type impurities are present in this range (see FIG. 2 ). More specifically, in the horizontal direction of FIG. 2 , n-type impurities may be implanted at least between the right end of the source region 40 shown on the left side of FIG. 2 and the left end of the source region 40 shown on the right side of FIG. 2 , so that the n-type impurities are present in this region. By adopting such an embodiment, n-type impurities can be present in a wide range of the well region 50, and the on-resistance can be more reliably reduced. The n-type impurities may be implanted below the bottom end of the source region 40, or may be implanted to the bottom end or above the bottom end of the well region 50.

[0023] Nitrogen may be implanted as an n-type impurity in the upper region 31 of the silicon carbide layer 12 and the well region 50, and phosphorus may be implanted as an n-type impurity in the lower region 32 below the upper region 31. Nitrogen may be implanted to a depth of 0.4 to 0.6 μm, for example. Phosphorus may be implanted to a depth of 1.3 to 1.8 μm, for example. In this case, phosphorus is also implanted in shallow regions, but its concentration may be smaller than that of nitrogen (see FIG. 3).

[0024] By adopting this embodiment in which nitrogen is implanted into the upper region 31 and phosphorus is implanted into the lower region 32, phosphorus can be positioned at a distance from the gate electrode 80 in the vertical direction of FIG. 2 . The presence of phosphorus over a wide area in proximity to the gate electrode 80 can potentially have adverse effects on the silicon carbide semiconductor device. However, implanting nitrogen above the phosphorus, as in this embodiment, can prevent such adverse effects. Furthermore, the inventors of the present application have confirmed that providing phosphorus at a deep depth allows for an impurity concentration that is consistent with the impurity concentration of p-type impurities such as aluminum, which is beneficial in ensuring electrical stability in the silicon carbide semiconductor device. To explain this point using a specific example, in the region of FIG. 3 where the depth is approximately greater than 0.7 μm (region C in FIG. 3 ), the phosphorus impurity concentration is consistent with the aluminum impurity concentration. Having the phosphorus impurity concentration consistent with the aluminum impurity concentration in this manner is beneficial in ensuring electrical stability in the silicon carbide semiconductor device. The inventors of the present application have confirmed that it is difficult to adjust the n-type impurity concentration to match the p-type impurity concentration with nitrogen, but it is relatively easy to adjust with phosphorus. For this reason, providing phosphorus at a deep position within well region 50 is very beneficial.

[0025] At any depth position in the well region 50, the concentration of n-type impurities such as nitrogen and phosphorus may be lower than the concentration of p-type impurities such as aluminum (see FIG. 3). By adopting such an embodiment, the p-type can be maintained at any depth position in the well region 50. In this case, it is preferable that the concentration of n-type impurities such as nitrogen and phosphorus be 70% or less of the concentration of p-type impurities such as aluminum at any depth position in the well region 50.

[0026] The distance D in the depth direction between the lower limit point where the nitrogen impurity concentration starts to decrease in the depth direction (see arrow A in FIG. 3 ) and the upper limit point where the phosphorus impurity concentration starts to decrease in the depth direction (see arrow B in FIG. 3 ) may be 0.5 μm or less, more preferably 0.3 μm or less, and even more preferably 0.15 μm or less. By adopting such an embodiment, the difference in impurity concentration can be reduced when switching from nitrogen to phosphorus in the depth direction, and the electrical stability of the silicon carbide semiconductor device can be further ensured.

[0027] The difference between the maximum value of the nitrogen impurity concentration and the maximum value of the phosphorus impurity concentration may be within 20%. By adopting such an embodiment, it is possible to prevent a large difference between the maximum value of the n-type impurity concentration and the maximum value of the p-type impurity concentration present in the well region 50. The difference between the maximum value of the nitrogen impurity concentration and the maximum value of the phosphorus impurity concentration being within 20% means that the maximum value of the nitrogen impurity concentration (N max ) and the highest value of phosphorus impurity concentration (P max The absolute value of the difference between the maximum nitrogen impurity concentration (N max ) and the highest value of the phosphorus impurity concentration (P max This means that the value is within 20% of the larger of the two. max >P max x In the case of (N max -P max ) / N max This means that the value is ≦0.2.

[0028] The source region 40 is an ultra-high concentration n-type semiconductor region (n ＋＋ In this embodiment, the ultra-high concentration n-type region (n ＋＋ ) impurity concentration is, for example, 2×10 １９ ~1 x 10 ２１ cm －３ In this embodiment, the impurity concentration in the intermediate concentration n-type region (n) is, for example, 2×10 １６ ~1 x 10 １８ cm －３ and the low concentration n-type region (n － ) impurity concentration is, for example, 1×10１４ ~4 x 10 １６ cm －３ and the high concentration n-type region (n ＋ ) impurity concentration is, for example, 1×10 １８ ~1 x 10 ２０ cm －３ As an example, the JFET region is a heavily doped n-type region (n ＋ In this embodiment, the concentration of p-type impurities in the well region 50 is low (P － ), for example, 5 x 10 １７ ~1 x 10 １９ cm －３ is.

[0029] An example of a method for manufacturing the silicon carbide semiconductor device of this embodiment will be described.

[0030] A low-concentration n-type silicon carbide layer 12 is formed by epitaxial growth on a first main surface (upper surface) of an n-type silicon carbide semiconductor substrate 11 .

[0031] Next, p-type impurities are ion-implanted into the n-type silicon carbide layer 12 to form a plurality of p-type well regions 50 in the n-type silicon carbide layer 12 .

[0032] Next, n-type impurity ions are implanted into the p-type well region 50 to form the n-type source region 40 in the p-type well region 50 .

[0033] Next, n-type impurities are implanted into a region of the silicon carbide layer 12 sandwiched between the multiple well regions 50 and into a region of the well region 50 on the silicon carbide layer 12 side, thereby forming a JFET region 20 in the region of the silicon carbide layer 12 sandwiched between the multiple well regions 50. At this time, the n-type impurities may be implanted into the well region 50 at least to a position below the end of the source region 40 on the JFET region side. Alternatively, phosphorus may be ion-implanted as an impurity first to form the lower region 32 at a deep position. Nitrogen may then be ion-implanted as an impurity to form the upper region 31 at a shallower position. At this time, phosphorus ion-implantation may be performed in multiple steps, and similarly, nitrogen ion-implantation may be performed in multiple steps.

[0034] When n-type impurities are implanted into the regions of the silicon carbide layer 12 sandwiched between the multiple well regions 50 and into the regions of the well regions 50 on the silicon carbide layer 12 side, the concentration of p-type impurities such as aluminum is adjusted to be higher than the concentration of n-type impurities in the well regions 50. Furthermore, when phosphorus is implanted to form the lower region 32, the impurity concentration of phosphorus in the lower region 32 is adjusted to be in line with the concentration of p-type impurities such as aluminum.

[0035] After the nitrogen and phosphorus implantation is completed, an activation anneal is performed.

[0036] Next, a gate insulating film 60 made of silicon dioxide or the like is formed to cover the JFET region 20 .

[0037] Next, a gate electrode 80 made of polysilicon or the like is formed on the gate insulating film 60 using a CVD method, photolithography technology or the like.

[0038] Thereafter, an interlayer insulating film 65 made of silicon dioxide or the like is formed so as to cover the gate electrode 80 .

[0039] Thereafter, a drain electrode 90 is formed on the second main surface (lower surface) of n-type silicon carbide semiconductor substrate 11. For example, a metal containing titanium, aluminum, nickel, or the like is provided by, for example, vapor deposition, chemical vapor deposition (CVD), application / coating, electroplating, or the like.

[0040] In this manner, a silicon carbide semiconductor device is manufactured.

[0041] The above-mentioned description of each embodiment and the disclosure of the drawings are merely examples for explaining the invention described in the claims, and the invention described in the claims is not limited by the description of the above-mentioned embodiment or the disclosure of the drawings. Furthermore, the description of the claims as originally filed is merely an example, and the description of the claims may be changed as appropriate based on the description in the specification, drawings, etc.

[0042] 12 silicon carbide layer 20 JFET region 40 source region 50 well region 60 gate insulating film (insulating film)

Claims

1. A silicon carbide semiconductor device comprising: a silicon carbide layer of a first conductivity type; a plurality of well regions of a second conductivity type provided in the silicon carbide layer; a source region of a first conductivity type provided in the well region; a JFET region of a first conductivity type formed in a region of the silicon carbide layer sandwiched between the plurality of well regions; an insulating film covering the JFET region; and a gate electrode provided on the JFET region via the insulating film, wherein first conductivity type impurities implanted into the JFET region are also implanted into the well regions, and a concentration of the second conductivity type impurities in the well regions is greater than a concentration of the first conductivity type impurities.

2. The silicon carbide semiconductor device according to claim 1, wherein the first conductivity type impurity is implanted into a region extending from the JFET region to a position below at least the end of the source region on the JFET region side of the well region.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein, within said well region, nitrogen is implanted as said first conductivity type impurity in an upper region, and phosphorus is implanted as said first conductivity type impurity in a lower region below said upper region.

4. The silicon carbide semiconductor device according to claim 3, wherein the concentrations of said nitrogen and said phosphorus are lower than the concentration of said second conductivity type impurity at any depth position in said well region.

5. The silicon carbide semiconductor device of claim 3, wherein the distance in the depth direction between the lower limit point where the nitrogen impurity concentration starts to decrease in the depth direction and the upper limit point where the phosphorus impurity concentration starts to decrease in the depth direction is 0.5 μm or less.

6. The silicon carbide semiconductor device according to claim 3, wherein the difference between the maximum impurity concentration of nitrogen and the maximum impurity concentration of phosphorus is within 20%.

7. A method for manufacturing a silicon carbide semiconductor device, comprising the steps of: forming a plurality of well regions of a second conductivity type in a silicon carbide layer of a first conductivity type; forming a source region of a first conductivity type in the well region; forming a JFET region in a region of the silicon carbide layer sandwiched between the plurality of well regions by injecting impurities of the first conductivity type into a region of the silicon carbide layer sandwiched between the plurality of well regions and a region of the well region on the silicon carbide layer side; forming an insulating film covering the JFET region; and forming a gate electrode provided on the JFET region via the insulating film, wherein a concentration of the second conductivity type impurities in the well region is greater than a concentration of the first conductivity type impurity.

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