Semiconductor processing device and power supply method

Abstract

This semiconductor processing device includes: a power supply unit in which a plurality of power supplies are connected in parallel; and a device body that processes a semiconductor on the basis of the output power of the power supply unit. The device body can be switched between a first mode and a second mode in which power consumption is larger than that in the first mode. The power supply unit selects, in the first mode, power supplies that can most efficiently supply output power among the plurality of power supplies to supply output power to the device body, and selects, in the second mode, power supplies that can most efficiently supply output power among the plurality of power supplies in a combination different from the first mode to supply output power to the device body.

Description

Semiconductor processing apparatus and power supply method

[0001] The present disclosure relates to a semiconductor manufacturing device and a power supply method.

[0002] Patent Document 1 discloses a semiconductor processing apparatus (production efficiency improvement apparatus) that switches between a standby mode that consumes power to quickly start processing an object to be processed, and a sleep mode that consumes a minimum amount of power to quickly transition to the standby mode.

[0003] Furthermore, in some cases, the main body of the semiconductor processing equipment that processes the workpieces consumes a large amount of power. In such cases, the semiconductor processing equipment may be configured to include multiple power sources, each of which supplies power to the main body.

[0004] JP 2017-55128 A

[0005] The present disclosure provides a technique that can suppress power loss in a configuration in which power is supplied to a device main body from multiple power sources.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor processing apparatus including a power supply unit in which a plurality of power sources are connected in parallel, and an apparatus main body that processes semiconductors based on the output power of the power supply unit, wherein the apparatus main body is switchable between a first mode and a second mode that consumes more power than the first mode, and in the first mode, the power supply unit selects a power source from the plurality of power sources that can most efficiently supply output power and supplies the output power to the apparatus main body, and in the second mode, selects a power source from the plurality of power sources that can most efficiently supply output power in a combination different from that in the first mode and supplies the output power to the apparatus main body.

[0007] According to one aspect, power loss can be reduced in a configuration in which power is supplied to the device main body from a plurality of power sources.

[0008] FIG. 1 is a perspective view showing an inspection system which is a semiconductor processing apparatus according to an embodiment; FIG. 2 is a plan sectional view showing the inspection system; FIG. 3 is a block diagram showing a configuration for supplying power to the inspection system according to the first embodiment; FIG. 4 is a flowchart showing a standby mode of the power supply method according to the first embodiment; FIG. 5 is a flowchart showing an operation mode of the power supply method according to the first embodiment; FIG. 6 is a block diagram showing a configuration for supplying power to the inspection system according to a second embodiment; FIG. 7 is a flowchart showing a standby mode of the power supply method according to the second embodiment; and FIG. 8 is a flowchart showing an operation mode of the power supply method according to the second embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] As an example of a semiconductor processing apparatus according to an embodiment of the present disclosure, an inspection system 1 that inspects the electrical characteristics of a wafer W (substrate: see FIG. 2) having semiconductor devices, as shown in FIG. 1, will be described. For example, semiconductor devices such as LSIs (Large Scale Integration), semiconductor memories, and semiconductor elements are formed on the surface of the wafer W. Note that the object to be inspected by the inspection system 1 is not limited to the wafer W, and may be a carrier on which semiconductor devices are arranged, a glass substrate, a single chip, an electronic circuit board, or the like.

[0011] The inspection system 1 includes an apparatus main body 10 that inspects multiple wafers W, a power supply unit 50 that supplies power to the apparatus main body 10, and an electric circuit 60 that connects the apparatus main body 10 and the power supply unit 50. Although Fig. 1 shows the electric circuit 60 as wiring 61 extending between the apparatus main body 10 and the power supply unit 50, the electric circuit 60 may be provided within the housing of the apparatus main body 10 or within the housing 51 of the power supply unit 50 (see also Fig. 3). Furthermore, the inspection system 1 may include the power supply unit 50 and the electric circuit 60 within the apparatus main body 10, for example, rather than having the apparatus main body 10, the power supply unit 50, and the electric circuit 60 as separate entities.

[0012] The apparatus main body 10 includes an inspection unit 11 and a loader 40 that transfers wafers W between the inspection unit 11. The inspection system 1 also includes a controller 90 in the loader 40 that controls the entire inspection system 1.

[0013] The inspection section 11 includes a plurality of inspection units 12 capable of inspecting wafers W. The inspection section 11 is formed as an assembly in which the inspection units 12 are assembled together along the X-axis direction and the Z-axis direction in FIG. 1 . The inspection section 11 can simultaneously (parallelly) inspect a plurality of wafers W using each inspection unit 12. The inspection section 11 shown in FIG. 1 includes a total of 12 inspection units 12, with four inspection units 12 arranged in a matrix along the X-axis direction and three in the Z-axis direction. The number of inspection units 12 in the inspection section 11 is not particularly limited, and may be any number appropriate depending on the inspection content, inspection efficiency, and the like. The inspection system 1 may have scalability, allowing the number of inspection units 12 to be increased (or decreased) depending on the factory footprint and the inspection content.

[0014] The loader 40 of the inspection system 1 is installed adjacent to the inspection unit 11 in the positive direction of the X axis. The loader 40 includes a box-shaped housing 41. The loader 40 may be configured to be able to reduce the pressure inside the housing 41 to a vacuum atmosphere. The loader 40 has multiple load ports 42 on a stepped surface of the housing 41 in the negative direction of the Y axis. A FOUP (Front Opening Unified Pod) 19 capable of accommodating multiple wafers W is set in each load port 42. A user interface (such as a touch panel: see FIG. 1 ) 95 is provided on the side of the housing 41 to allow a user of the inspection system 1 to view and operate the FOUP. The user interface 95 is connected to a controller 90 inside the housing 41.

[0015] 2, the loader 40 includes, in the housing 41, a transfer robot 43 that transfers the wafer W, an aligner 44 that adjusts the posture of the wafer W before inspection, and an elevator 45 that moves up and down in the Z-axis direction within the housing 41. Although not shown, the loader 40 may also include a configuration for loading and unloading a probe card (not shown) used in each inspection unit 12.

[0016] The transfer robot 43 in the loader 40 takes out the uninspected wafer W from the FOUP 19 via the load port 42 and transfers the wafer W within the housing 41. For example, the loader 40 transfers the uninspected wafer W to the aligner 44 using the transfer robot 43, adjusts the circumferential position of the wafer W in the aligner 44, and then transfers the wafer W to the elevator 45 using the transfer robot 43.

[0017] The elevator 45 is provided on the side surface (the side surface in the negative X-axis direction) of the housing 41 adjacent to the inspection unit 11, and moves up and down along the Z-axis direction. The elevator 45 positions the wafer W with respect to multiple (three) transfer areas 13 in the Z-axis direction that are formed for transferring the wafer W within the inspection unit 11.

[0018] The three transport areas 13 in the Z-axis direction have transport paths 14 extending parallel to each other (in the X-axis direction) on the positive Y-axis side of the inspection section 11. Each transport area 13 is also equipped with a transport device 15 that moves the wafer W in the X-axis direction and transports the wafer W in and out of the target inspection unit 12.

[0019] The transfer device 15 includes an arm unit 16 that holds the wafer W, and a mobile body 17 that is mounted with the arm unit 16 and is self-propelled on the transfer path 14. The mobile body 17 moves back and forth on the transfer path 14 under the control of a controller 90. The arm unit 16 receives or transfers the wafer W between itself and the elevator 45 of the loader 40 at a position adjacent to the elevator 45 (on the positive X-axis side). Furthermore, when the mobile body 17 moves to the target inspection unit 12, the arm unit 16 receives or transfers the wafer W between itself and the mobile unit 30 of the inspection unit 12.

[0020] Each inspection unit 12 of the inspection section 11 has a tester 20 that actually performs electrical inspection of the wafer W, and a moving part (stage) 30 that supports and transports the wafer W within the inspection unit 12. Note that Fig. 2 shows a plan cross-sectional view between the tester 20 and the moving part 30, and for this reason, the tester 20 is depicted by a virtual line (two-dot chain line).

[0021] The tester 20 has a test motherboard (not shown) inside and holds a probe card (not shown) below it that is connected to the test motherboard. The probe card has a plurality of probes that come into contact with the wafer W to test its electrical characteristics.

[0022] The moving part 30 of the inspection unit 12 moves the wafer W below the tester 20. The moving part 30 includes a moving mechanism 31 capable of transporting the wafer W in four axial directions (X-axis direction, Y-axis direction, Z-axis direction, and about the θ-axis) within the inspection unit 12, and a mounting table 33 mounted on the upper part of the moving mechanism 31. Note that the moving directions of the wafer W by the moving mechanism 31 are not limited to the four axial directions, and may be three axial directions (X-axis direction, Y-axis direction, Z-axis direction, etc.).

[0023] 1 , the controller 90 of the inspection system 1 is a computer including a processor, memory, input / output interface, communication interface, etc. (not shown). The processor is one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a circuit made up of a plurality of discrete semiconductors, etc., and executes and processes programs stored in memory. The memory includes a main storage device made up of a semiconductor memory, etc., and an auxiliary storage device made up of a disk, a drive, a semiconductor memory (flash memory), etc.

[0024] For example, the controller 90 determines that an appropriate one of the inspection units 12 in the inspection section 11 will inspect the wafer W. Based on the determination of the inspection unit 12 to be inspected, the transfer device 15 on the same level as the inspection unit 12 is moved to a position adjacent to the loader 40, and the transfer device 15 holds the wafer W on the elevator 45. Furthermore, the controller 90 moves the transfer device 15 to a position facing the target inspection unit 12, and then transfers the wafer W to the mounting table 33 which has moved in the positive direction of the Y axis and is waiting based on a command from the controller 90.

[0025] Furthermore, upon receiving a command from the controller 90, the inspection unit 12 transports the wafer W below the probe card using the moving part 30 and then raises the wafer W to bring the wafer W into contact with each probe of the probe card. Thereafter, the tester 20 passes a current through the electronic circuit of each semiconductor device on the wafer W and acquires a signal returned from the wafer W, thereby electrically inspecting each semiconductor device on the wafer W.

[0026] The inspection system 1 supplies power required for inspecting the wafer W from a power supply unit 50 to the apparatus main body 10 via an electric circuit 60. The configurations of the power supply unit 50 and the electric circuit 60 according to the first embodiment will be described below with reference to FIG.

[0027] First Embodiment The power supply unit 50 according to the first embodiment includes multiple (four in FIG. 3 ) power supplies 52 housed within a housing 51 to supply power to the device main body 10. Hereinafter, the multiple power supplies 52 will be referred to as a first power supply 52A, a second power supply 52B, a third power supply 52C, and a fourth power supply 52D, in that order, from top to bottom of the paper shown in FIG. 3 . While FIGS. 1 and 3 show an example in which multiple power supplies 52 are housed within a single housing 51, this is not limiting, and multiple power supplies 52 may be installed in separate housings. Furthermore, the power supply unit 50 is not particularly limited in the number of power supplies 52 installed, and may include two, three, five, or more.

[0028] Each power supply 52 has an AC-DC converter that converts a commercial power supply (AC power supply) (not shown) into DC power. Also, although not shown, each power supply 52 has a cooling mechanism that cools the AC-DC converter and a control unit such as a control board that controls the power supply 52 itself. The control unit of each power supply 52 can be a computer having a processor, memory, input / output interface, etc., or may have a control function that combines multiple discrete semiconductors. Each power supply 52 outputs a current corresponding to the power consumption of the device main body 10 to its secondary side while maintaining a set voltage.

[0029] Furthermore, each power supply 52 has a protection function that monitors the power supply 52 itself for abnormalities and turns off the output power if an abnormality is detected. Examples of abnormalities in the power supply 52 itself include overcurrent and high temperature. For example, if an abnormality occurs in any of the multiple power supplies 52, the power supply unit 50 can take measures such as shutting down the power supply 52 with the abnormality and increasing the current of the other power supplies 52. The power supply unit 50 may not have a control unit for each of the multiple power supplies 52, but may have a unified control unit and operate each power supply 52 under the control of this control unit.

[0030] Furthermore, each power supply 52 may have a function of performing a hiccup operation to automatically restore the protection function. For example, the control unit of the power supply 52 in which an abnormality has occurred performs a process of detecting the abnormal state of the power supply 52 again in the hiccup operation. Then, if the abnormal state is detected again, the power supply 52 continues to turn off the output power, but if no abnormal state is detected, the power supply 52 automatically restores and resumes supplying the output power. Note that if the power supply 52 detects an abnormality after restoring, it turns off the output power again using the protection function.

[0031] Alternatively, each power supply 52 may be configured to perform a latch operation in which the output power remains off without automatically restoring after a protective function is activated. In this case, the power supply 52 in which an abnormality has occurred will be restored and resume supply of output power by performing an operation such as turning off and restarting the entire power supply unit 50.

[0032] The power supply unit 50 according to the first embodiment is configured to supply output power from different power supplies 52 among the multiple power supplies 52 in the standby mode (first mode) and the operating mode (second mode) of the device main body 10. Specifically, the first power supply 52A is the power supply 52 that mainly supplies output power in the standby mode of the device main body 10, and the second power supply 52B to fourth power supplies 52D are the power supplies 52 that mainly supply output power in the operating mode of the device main body 10.

[0033] The standby mode of the apparatus main body 10 refers to a mode in which the start switch of the apparatus main body 10 is turned off by an operator or the like, and therefore the transfer and inspection of wafers W are not being performed. However, even in the standby mode, the power supply unit 50 supplies power to some of the electronic devices, such as the controller 90, to operate those electronic devices. By having some of the controller 90 operating, for example, when transitioning from the standby mode to the operating mode, the controller 90 can start processing quickly, allowing for a smooth mode switch.

[0034] The amount of power consumed by the device main body 10 in the standby mode is sufficiently smaller than the amount of power consumed by the device main body 10 in the operating mode. For example, the amount of power consumed in the standby mode is kept to one-third or less of the amount of power consumed in the operating mode.

[0035] In contrast, the operating mode of the apparatus main body 10 refers to a mode in which the start switch of the apparatus main body 10 is turned on by an operator or the like, and the apparatus main body 10 transfers and inspects wafers W. In this mode, the power supply unit 50 supplies the output power required for the operation of each component of the apparatus main body 10. In particular, when inspecting wafers W in multiple inspection units 12, the apparatus main body 10 consumes a large amount of power. By using the second power supply 52B to the fourth power supply 52D, the power supply unit 50 can supply output power that covers the power consumption of the apparatus main body 10.

[0036] In addition, the power supply unit 50 and electrical circuit 60 of the first embodiment are capable of seamlessly switching between a standby mode in which output power is supplied from the first power source 52A to the device main body 10, and an operating mode in which output power is supplied from the second power source 52B to the fourth power source 52D to the device main body 10.

[0037] Specifically, the electric circuit 60 connects the power sources 52 (first power source 52A to fourth power source 52D) in parallel inside the housing 51 via a plurality of branch wirings 62 connected to a connection point 63. The first power source 52A is connected to the connection point 63 via a first branch wiring 62A. The second power source 52B is connected to the connection point 63 via a second branch wiring 62B. The third power source 52C is connected to the connection point 63 via a third branch wiring 62C. The fourth power source 52D is connected to the connection point 63 via a fourth branch wiring 62D. The connection point 63 and the device main body 10 are connected by the above-mentioned wiring 61, which is a junction wiring of the plurality of branch wirings 62.

[0038] The electric circuit 60 also has a backflow prevention diode (backflow prevention element) 64 installed in the first branch wiring 62A. Examples of the backflow prevention diode 64 include a SiC diode or a Si diode. The backflow prevention diode 64 prevents the output power supplied from the second power source 52B to the fourth power source 52D from flowing toward the first power source 52A in the active mode. The backflow prevention element is not limited to a diode, and a thyristor, for example, may also be used.

[0039] The power supply unit 50 sets the voltage values ​​of the power supplies 52 to different values, rather than being constant. Specifically, the voltage value of the first power supply 52A is set to, for example, 25 V as the first voltage value V1 of the power supply unit 50. On the other hand, the voltage values ​​of the second power supplies 52B to fourth power supplies 52D are set to, for example, 24 V as the second voltage value V2 of the power supply unit 50. In other words, in the standard settings of the power supply unit 50, the relationship between the first voltage value V1 of the first power supply 52A and the second voltage values ​​V2 of the second power supplies 52B to fourth power supplies 52D is V1>V2.

[0040] The inspection system 1 can use power with high efficiency in both standby mode and operating mode by receiving output power from the power supply unit 50 having such reference settings. Next, a power supply method for the inspection system 1 using the power supply unit 50 and the electric circuit 60 according to the first embodiment will be described.

[0041] The main body 10 of the inspection system 1 is placed in standby mode when an operator turns off the start switch, etc. In this case, the main body 10 consumes less power than in active mode because only parts such as the controller 90 operate. Therefore, the power supply unit 50 supplies a sufficiently small amount of output power to the main body 10.

[0042] As described above, in the reference settings of the power supplies 52 of the power supply unit 50, the first voltage value V1 of the first power supply 52A is greater than the second voltage value V2 of each of the second power supply 52B to fourth power supply 52D. Therefore, when a small output power is to be supplied in the standby mode, the first power supply 52A, of the power supplies 52, whose first voltage value V1 is greater than the second voltage value V2, selectively supplies the output power.

[0043] 4A, in the power supply method in the standby mode of the inspection system 1, output power is supplied from the first power source 52A to the device main body 10 (step S101). In this way, the output power of the first power source 52A alone can provide sufficient power for the device main body 10 in the standby mode to operate.

[0044] In conventional power supply units, the voltages of multiple power supplies are set to the same value, so that output power is supplied simultaneously from multiple power supplies in standby mode, resulting in each of the multiple power supplies dispersing a small amount of output current.

[0045] Generally, power supplies are designed to supply power most efficiently within a usage rate range of 50% to 80%. The efficiency of a power supply is the ratio of the output current (DC current) output by the power supply to the input current (AC current) input to the power supply. When multiple power supplies distribute output current in standby mode, the usage rate of each power supply falls significantly below 50%. In this case, each power supply outputs power that is less efficient than the most efficient power. In other words, the output power of the power supply unit in standby mode experiences increased power loss due to the decrease in efficiency (the difference from the efficiency at a usage rate of 50% to 80%) associated with the reduced usage rate of each power supply. In particular, increased power loss in each of the multiple power supplies results in increased power loss for the power supply unit as a whole.

[0046] Therefore, in the first embodiment, the first voltage value V1 of the first power source 52A is set higher than the second voltage values ​​of the second power sources 52B to 52D. As a result, in standby mode, the power supply unit 50 supplies output power from the first power source 52A to the device main body 10, while the second power sources 52B to 52D hardly supply output power to the device main body 10. As a result, the usage rate of the first power source 52A can be set to a range of 50% to 80%, and the power supply unit 50 can supply the device main body 10 with the efficient output power of the first power source 52A. In other words, the inspection system 1 can reduce power loss in standby mode as much as possible.

[0047] Furthermore, the main body 10 of the inspection system 1 transitions from standby mode to operating mode when an operator turns on a start switch or the like. In this case, the main body 10 consumes a lot of power by transporting wafers W and performing inspections in each inspection unit 12. This requires the power supply unit 50 to supply a large amount of output power to the main body 10. The power supply unit 50 supplies output power to the main body 10 from the second power supply 52B to the fourth power supply 52D in accordance with the power consumption of the main body 10.

[0048] 4B , in the power supply method in the operation mode of the inspection system 1, the first power source 52A of the power supply unit 50 operates to supply a large amount of power to the device main body 10, resulting in an overcurrent state (step S111). Therefore, the first power source 52A turns off its output power using its protection function. As a result, in the operation mode, the first voltage value V1 of the first power source 52A drops to zero, and the relationship with the second voltage value V2 of the second power sources 52B to 52D changes to V1<V2.

[0049] Therefore, in the operating mode, the power supply unit 50 supplies output power from the second power source 52B to the fourth power source 52D to the device main body 10 (step S112). The second power source 52B to the fourth power source 52D each have a high usage rate in the operating mode, allowing them to efficiently supply output power (with little power loss) to the device main body 10. Therefore, the device main body 10 can operate stably using the output power of the power supply unit 50.

[0050] On the other hand, even if the first power supply 52A performs a hiccup operation and automatically recovers, it immediately enters an overcurrent state and the output power is turned off. Note that if the first power supply 52A performs a latch operation, it does not automatically recover and the output power remains off. In other words, the device main body 10 can operate using the output power of the second power supply 52B to the fourth power supply 52D, regardless of the output power supply of the first power supply 52A.

[0051] As described above, the inspection system 1 can seamlessly change the power of each power source 52 by adjusting the voltage values ​​of the first power source 52A and the second power source 52B to the fourth power source 52D of the power source unit 50. In particular, the power source unit 50 can output highly efficient output power from the first power source 52A even when the device main body 10 is in standby mode, thereby promoting energy conservation in standby mode.

[0052] The semiconductor processing apparatus (inspection system 1) and power supply method of the present disclosure are not limited to the above-described embodiment and may take various modifications. For example, in the above-described power supply unit 50 and electric circuit 60, the first voltage value V1 of the first power supply 52A is set higher than the voltage values ​​of the second to fourth power supplies 52B to 52D, thereby enabling selection of the power supply 52 in each mode. Alternatively, the electric circuit 60 may include a switch in each branch wiring 62, and the output power supply of each power supply 52 may be switched by switching the switch.

[0053] Furthermore, the first and second modes of the inspection system 1 are not limited to the standby mode and the operating mode. As an example, the inspection system 1 may be configured to execute a power-saving mode (first mode) with low power consumption and a high-power mode (second mode) with high power consumption for faster processing in the operating mode. In this case, the power supply unit 50 may select two of the multiple power supplies 52 to supply output power in the power-saving mode, and three of the multiple power supplies 52 to supply output power in the high-power mode. In short, the power supply unit 50 can optimize the utilization rate of each power supply 52 by appropriately selecting the power supplies 52 to supply power in two modes with different power consumptions, thereby reducing power loss.

[0054] [Second embodiment] As shown in Figure 5, an inspection system 1A according to the second embodiment differs from the inspection system 1 according to the first embodiment in that it includes a power supply unit 50A equipped with multiple (three) power supplies 53, and an electric circuit 70 capable of communicating information with the power supply unit 50A.

[0055] The power supply unit 50A has a first power supply 53A, a second power supply 53B, and a third power supply 53C as multiple power supplies 53. The function of each power supply 53 is the same as the function of each power supply 52 in the power supply unit 50 according to the first embodiment. It goes without saying that the power supply unit 50A is not particularly limited in number as long as it has multiple power supplies 53.

[0056] The electric circuit 70 also includes a junction wiring 71 and a plurality of branch wirings 72 (first branch wiring 72A, second branch wiring 72B, and third branch wiring 72C) connected in parallel to a junction point 73. The first power source 53A is connected to the junction point 73 by the first branch wiring 72A. The second power source 53B is connected to the junction point 73 by the second branch wiring 72B. The third power source 53C is connected to the junction point 73 by the third branch wiring 72C. Note that the first branch wiring 72A according to the second embodiment does not include a backflow prevention diode 64 (see FIG. 3 ).

[0057] Furthermore, the electric circuit 70 connects the controller 90 (see FIG. 1) of the apparatus main body 10 and the first power source 53A of the power supply unit 50A via a communication line 75. The communication line 75 transmits a voltage variable signal from the controller 90 to the first power source 53A. Note that the inspection system 1A may be configured to perform wireless communication between the controller 90 and the first power source 53A.

[0058] The voltage variable signal includes information related to the standby mode and operating mode of the device main body 10. The controller 90 determines whether the device main body 10 is in standby mode or operating mode, and, for example, if the device is in standby mode, continuously transmits information indicating the standby mode to the first power source 53A. On the other hand, if the device is in operating mode, the controller 90 continuously transmits information indicating the operating mode to the first power source 53A. Alternatively, the controller 90 may transmit information on the voltage value output by the first power source 53A as the voltage variable signal.

[0059] The first power supply 53A is capable of changing its voltage value based on a voltage variable signal transmitted from the device main body 10. For example, when standby mode information is received from the voltage variable signal, the first power supply 53A sets the voltage to a first voltage value for standby mode (e.g., 25 V) and supplies output power. On the other hand, when operating mode information is received from the voltage variable signal, the first power supply 53A sets the voltage to a second voltage value for operating mode (e.g., 24 V) and supplies output power.

[0060] The inspection system 1A according to the second embodiment is basically configured as described above, and a power supply method for the inspection system 1A will be described below.

[0061] The main body 10 of the inspection system 1 executes the standby mode when an operator turns off the activation switch, etc. At this time, as shown in Fig. 6A, the main body 10 transmits a voltage variable signal indicating the standby mode to the first power source 53A of the power supply unit 50A (step S201).

[0062] As a result, the first power source 53A sets the voltage value of its output power to a first voltage value V1 that is higher than the second voltage value V2 of the second power source 53B and the third power source 53C (step S202). For example, if the second voltage value V2 of the second power source 53B and the third power source 53C is 24 V, the first voltage value V1 of the first power source 53A is set to 25 V. Therefore, when a small amount of output power is to be supplied to the device main body 10 in standby mode, the first power source 52A, which has the first voltage value V1 that is higher than the second voltage value V2, among the power sources 52, selectively supplies the output power.

[0063] That is, the power supply unit 50 supplies output power from the first power supply 52A to the apparatus main body 10 (step S203). As described above, the usage rate of the first power supply 52A can be set to the range of 50% to 80%, and the power supply unit 50 can supply the efficient output power of the first power supply 52A to the apparatus main body 10. That is, the inspection system 1 can reduce standby power loss in standby mode as much as possible.

[0064] The main body 10 of the inspection system 1 transitions from the standby mode to the operating mode when an operator turns on the activation switch, etc. At this time, as shown in Fig. 6B, the main body 10 transmits a voltage variable signal indicating the operating mode to the first power source 53A of the power supply unit 50A (step S211).

[0065] As a result, the first power supply 53A changes the voltage value of the output power to the same voltage value (i.e., the second voltage value) as the second voltage value V2 of the second power supply 53B and the third power supply 53C (step S212). For example, if the second voltage value V2 of the second power supply 53B and the third power supply 53C is 24 V, the first power supply 53A is also changed to 24 V.

[0066] Therefore, when supplying output power to the device main body 10 in the operating mode, the output power is supplied to the device main body 10 from the first power source 53A to the third power source 53C, which have the same voltage value (step S212). The first power source 53A to the third power source 53C each have a high usage rate in the operating mode, allowing them to supply output power efficiently (with little loss) to the device main body 10. This allows the device main body 10 to operate stably using the output power of the power supply unit 50A.

[0067] As described above, in the inspection system 1A according to the second embodiment, the first power supply 52A can output highly efficient output power in standby mode, thereby promoting energy conservation in standby mode. Furthermore, in operation mode, the voltages of the first power supply 53A to the third power supply 53C can be matched, allowing the apparatus main body 10 to smoothly transport and inspect the wafer W. In particular, because the power supply unit 50A can reuse the first power supply 53A, the number of power supplies 53 can be reduced, thereby promoting cost reduction and miniaturization.

[0068] The semiconductor processing apparatus (inspection system 1A) and power supply method according to the second embodiment may also be modified in various ways. For example, the power supply 53 that changes the voltage when transitioning from standby mode to active mode is not limited to the first power supply 53A, but may be the second power supply 53B or the third power supply 53C. Alternatively, the power supply unit 50A may be configured to change the voltage of all power supplies 53 to appropriate values ​​for each mode.

[0069] The technical ideas and effects of the present disclosure explained in the above embodiments will be described below.

[0070] A first aspect of the present disclosure is a semiconductor processing apparatus (inspection system 1, 1A) including a power supply unit 50, 50A in which a plurality of power supplies 52, 53 are connected in parallel, and an apparatus main body 10 that processes semiconductors based on the output power of the power supply unit 50, 50A, wherein the apparatus main body 10 is switchable between a first mode (standby mode) and a second mode (operating mode) that consumes more power than the first mode, and in the first mode, the power supply unit 50, 50A selects a power supply (first power supply 52A, 53A) that can most efficiently supply output power from the plurality of power supplies 52, 53 and supplies the output power to the apparatus main body 10, and in the second mode, selects a power supply (second power supply 52B to fourth power supply 52D, first power supply 53A to third power supply 53C) that can most efficiently supply output power from the plurality of power supplies 52, 53 in a combination different from that in the first mode and supplies the output power to the apparatus main body 10.

[0071] As described above, in the semiconductor processing apparatus (inspection system 1, 1A), by using the power supply (first power supply 52A, 53A) capable of supplying output power most efficiently in the first mode, power loss in the first mode can be reduced. Moreover, in the second mode, the power supply unit 50, 50A can supply output power most efficiently in a combination different from that in the first mode, thereby enabling stable operation of the apparatus main body 10.

[0072] Furthermore, in the first mode, the power supply units 50, 50A supply output power to the device main body 10 from one power source (first power source 52A, 53A) of the multiple power sources 52, 53, and in the second mode, supply output power to the device main body 10 from two or more power sources (second power source 52B to fourth power source 52D, first power source 53A to third power source 53C) of the multiple power sources 52, 53. This allows the semiconductor processing apparatus to efficiently obtain output power from a single power source even when the device main body 10 is not operating or is operating at a low current in the first mode. Furthermore, the semiconductor processing apparatus can stably obtain output power from two or more power sources even when the device main body 10 requires a large amount of power in the second mode.

[0073] Furthermore, power supply units 50, 50A set the voltage value of the power supply (first power supply 52A, 53A) that supplies output power to device main body 10 in the first mode to be higher than the voltage value of the power supplies (second power supply 52B to fourth power supply 52D, first power supply 53A to third power supply 53C) that supply output power to device main body 10 in the second mode. This allows the semiconductor processing apparatus to suppress the output power from the power supply with the lower voltage value to device main body 10 and smoothly supply output power to device main body 10 from the power supply with the higher voltage value.

[0074] The plurality of power supplies 52 include a first-mode power supply (first power supply 52A) that supplies output power in the first mode, and second-mode power supplies (second power supply 52B to fourth power supply 52D) that supply output power in the second mode. This allows the semiconductor processing apparatus to switch between supplying output power in the first mode and supplying output power in the second mode with a simple configuration.

[0075] Furthermore, when transitioning from the first mode to the second mode, the power supply unit 50 reduces the voltage of the first-mode power supply (first power supply 52A) so that the second-mode power supplies (second power supply 52B to fourth power supply 52D) supply output power to the apparatus main body 10. This allows the semiconductor processing apparatus to seamlessly switch from the first mode to the second mode.

[0076] Furthermore, when transitioning from the first mode to the second mode, the power supply unit 50 turns off the output power based on the fact that the first-mode power supply (first power supply 52A) is in an overcurrent state. This allows the power supply unit 50 to easily turn off the first-mode power supply, enabling smoother switching to the second-mode power supply.

[0077] Furthermore, power supply unit 50 includes a backflow prevention element (backflow prevention diode 64) between node 63, at which the first-mode power supply (first power supply 52A) and the second-mode power supplies (second power supply 52B to fourth power supplies 52D) are connected, and the first-mode power supplies. This allows power supply unit 50 to prevent the output power of the second-mode power supply from flowing toward the first-mode power supply even when the first-mode power supply is turned off.

[0078] Furthermore, power supply unit 50A changes the voltage value of at least one power supply (first power supply 53A) among multiple power supplies 53 based on information relating to the first mode and the second mode received from device main body 10. This allows power supply unit 50A to reuse one power supply in both the first mode and the second mode, thereby promoting efficient operation of power supply 53, lower costs, smaller size, etc.

[0079] Furthermore, based on information related to the first mode, power supply unit 50A sets a predetermined power supply (first power supply 53A) among the multiple power supplies 53 to a voltage value corresponding to the first mode, and based on information related to the second mode, sets the predetermined power supply to a voltage value that matches the voltage values ​​of the other power supplies (second power supply 53B, third power supply 53C) among the multiple power supplies 53. This allows power supply unit 50A to achieve both efficient supply of output power in the first mode and stable supply of power to device main body 10 in the second mode.

[0080] The main body 10 also has a plurality of inspection units 12 for inspecting semiconductors, which allows the semiconductor processing apparatus to reduce power loss in a system having a plurality of inspection units 12.

[0081] A second aspect of the present disclosure is a power supply method for a semiconductor processing apparatus (inspection system 1, 1A) including a power supply unit 50, 50A in which multiple power supplies 52, 53 are connected in parallel, and an apparatus main body 10 that processes semiconductors based on the output power of the power supply unit 50, 50A, the power supply method comprising the steps of: (A) selecting, in a first mode (standby mode) of the apparatus main body 10, a power supply (first power supply 52A, 53A) that can most efficiently supply output power from the multiple power supplies 52, 53, and supplying the output power to the apparatus main body 10; and (B) selecting, in a second mode (operating mode) in which the apparatus main body 10 uses more power than in the first mode, a power supply (second power supply 52B to fourth power supply 52D, first power supply 53A to third power supply 53C) that can most efficiently supply output power from the multiple power supplies 52, 53, in a combination different from that in the first mode, and supplying the output power to the apparatus main body 10. Even in this case, the power supply method can suppress power loss in a configuration in which power is supplied to the apparatus main body 10 from the multiple power supplies 52, 53.

[0082] The semiconductor processing apparatus and power supply method according to the presently disclosed embodiments are illustrative in all respects and are not limiting. The embodiments may be modified and improved in various ways without departing from the spirit and scope of the appended claims. The features described in the above embodiments may be configured differently and may be combined within a consistent range.

[0083] The semiconductor processing apparatus is not limited to the inspection systems 1 and 1A that inspect substrates (wafers W), but may be, for example, substrate processing apparatuses that perform substrate processing such as film formation, etching, cleaning, bonding, temperature adjustment, or other processing, or transport apparatuses that transport substrates, etc. Furthermore, the inspection system 1 is not limited to those that inspect the electrical characteristics of substrates, but may also be an inspection apparatus that measures the thickness of a film on a substrate, measures the shape of a substrate, etc.

[0084] This application claims priority from basic application No. 2023-194961, filed with the Japan Patent Office on November 16, 2023, the entire contents of which are incorporated herein by reference.

[0085] 1, 1A Inspection system 10 Device main body 50, 50A Power supply unit 52, 53 Power supply 52A, 53A First power supply 52B, 53B Second power supply 52C, 53C Third power supply 52D Fourth power supply

Claims

1. A semiconductor processing apparatus including: a power supply unit in which a plurality of power sources are connected in parallel; and an apparatus main body that processes semiconductors based on the output power of the power supply unit, wherein the apparatus main body is switchable between a first mode and a second mode that consumes more power than the first mode, and the power supply unit, in the first mode, selects a power source from the plurality of power sources that can supply output power most efficiently and supplies the output power to the apparatus main body, and in the second mode, selects a power source from the plurality of power sources that can supply output power most efficiently in a combination different from that in the first mode and supplies the output power to the apparatus main body.

2. The semiconductor processing apparatus according to claim 1, wherein the power supply unit supplies output power from one of the plurality of power sources to the device body in the first mode, and supplies output power from two or more of the plurality of power sources to the device body in the second mode.

3. The semiconductor processing apparatus according to claim 1, wherein the power supply unit sets the voltage value of the power supply that supplies output power to the apparatus main body in the first mode higher than the voltage value of the power supply that supplies output power to the apparatus main body in the second mode.

4. The semiconductor processing apparatus according to any one of claims 1 to 3, wherein the plurality of power sources includes a first mode power source that supplies output power in the first mode, and a second mode power source that supplies output power in the second mode.

5. The semiconductor processing apparatus according to claim 4, wherein the power supply unit supplies output power to the apparatus main body by the second mode power supply by lowering the voltage of the first mode power supply when transitioning from the first mode to the second mode.

6. The semiconductor processing apparatus according to claim 5, wherein said power supply unit turns off output power when said first mode power supply is in an overcurrent state during transition from said first mode to said second mode.

7. The semiconductor processing apparatus according to claim 5, wherein said power supply section includes a backflow prevention element between said first mode power supply and said second mode power supply and a connection point at which said first mode power supply and said second mode power supply are connected.

8. A semiconductor processing apparatus according to any one of claims 1 to 3, wherein the power supply unit changes a voltage value of at least one of the plurality of power supplies based on information received from the apparatus main body relating to the first mode and the second mode.

9. The semiconductor processing apparatus according to claim 8, wherein the power supply unit sets a predetermined power supply among the plurality of power supplies to a voltage value corresponding to the first mode based on information related to the first mode, and sets the predetermined power supply to a voltage value that matches a voltage value of another power supply among the plurality of power supplies based on information related to the second mode.

10. The semiconductor processing apparatus according to any one of claims 1 to 3, wherein the apparatus body has a plurality of inspection units for inspecting the semiconductor.

11. A power supply method for a semiconductor processing apparatus including a power supply unit in which a plurality of power sources are connected in parallel, and an apparatus main body for processing semiconductors based on the output power of the power supply unit, comprising: (A) a step of selecting a power source capable of supplying output power most efficiently from among the plurality of power sources in a first mode of the apparatus main body, and supplying the output power to the apparatus main body; and (B) a step of selecting a power source capable of supplying output power most efficiently from among the plurality of power sources in a combination different from that in the first mode, and supplying the output power to the apparatus main body in a second mode of the apparatus main body in which the amount of power consumption is greater than in the first mode.

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