Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes: a step for preparing a silicon substrate that has a first main surface; a step for forming a silicon oxide film on the first main surface of the silicon substrate; a step for forming an amorphous silicon film on the silicon oxide film; a step for forming a metal layer on the amorphous silicon film; a step for changing the amorphous silicon film into a crystal silicon film by annealing the silicon substrate on which the metal layer has been formed; a step for forming a transistor that uses a part of the crystal silicon film as a channel; and a step for forming a capacitor which is adjacent to the transistor in a direction that is perpendicular to the first main surface, and which is electrically connected to the transistor.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

[0002] A technique is known in which an amorphous silicon film and a metal film are formed in this order on a substrate, and then annealed at a predetermined temperature to convert the amorphous silicon film into a crystalline silicon film (see, for example, Patent Documents 1 and 2).

[0003] JP 2006-303218 A JP 2002-313719 A

[0004] The present disclosure provides a technique for forming a semiconductor device including a transistor in which a part of a crystalline silicon film serves as a channel, without using an SOI (Silicon On Insulator) substrate.

[0005] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes the steps of: preparing a silicon substrate having a first main surface; forming a silicon oxide film on the first main surface of the silicon substrate; forming an amorphous silicon film on the silicon oxide film; forming a metal layer on the amorphous silicon film; annealing the silicon substrate on which the metal layer has been formed to change the amorphous silicon film into a crystalline silicon film; forming a transistor having a channel made of a portion of the crystalline silicon film; and forming a capacitor adjacent to the transistor in a direction perpendicular to the first main surface and electrically connected to the transistor.

[0006] According to the present disclosure, a semiconductor device including a transistor in which a part of a crystalline silicon film serves as a channel can be formed without using an SOI substrate.

[0007] FIG. 1 is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view (part 2) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 3 is a cross-sectional view (part 3) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 4 is a cross-sectional view (part 4) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 5 is a cross-sectional view (part 5) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6 is a cross-sectional view (part 6) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 7 is a cross-sectional view (part 7) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 8 is a cross-sectional view (part 8) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 9 is a cross-sectional view (part 9) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 10 is a cross-sectional view (part 10) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 11 is a cross-sectional view (part 11) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 12 is a cross-sectional view (part 12) illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 13 is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to a second embodiment. FIG. 14 is a cross-sectional view (part 2) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 15 is a cross-sectional view (part 3) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 16 is a cross-sectional view (part 4) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 17 is a cross-sectional view (part 5) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 18 is a cross-sectional view (part 6) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 19 is a cross-sectional view (part 7) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 20 is a cross-sectional view (part 8) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 21 is a cross-sectional view (part 9) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 22 is a cross-sectional view (part 10) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 23 is a cross-sectional view (part 11) illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 24 is a cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to a third embodiment. FIG. 25 is a cross-sectional view (part 2) illustrating the method for manufacturing a semiconductor device according to the third embodiment.FIG. 26 is a cross-sectional view (part 3) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 27 is a cross-sectional view (part 4) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 28 is a cross-sectional view (part 5) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 29 is a cross-sectional view (part 6) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 30 is a cross-sectional view (part 7) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 31 is a cross-sectional view (part 8) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 32 is a cross-sectional view (part 9) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 33 is a cross-sectional view (part 10) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 34 is a cross-sectional view (part 11) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 35 is a cross-sectional view (part 12) showing the method for manufacturing a semiconductor device according to the third embodiment. FIG. 36 is a cross-sectional view (part 13) showing the method for manufacturing a semiconductor device according to the third embodiment.

[0008] Hereinafter, non-limiting exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In all the accompanying drawings, the same or corresponding reference numerals are used to designate the same or corresponding members or components, and redundant descriptions will be omitted.

[0009] First Embodiment A method for manufacturing a semiconductor device 1 according to a first embodiment will be described with reference to Figures 1 to 12. Figures 1 to 12 are cross-sectional views showing the method for manufacturing a semiconductor device 1 according to the first embodiment.

[0010] First, as shown in Fig. 1, a silicon substrate 112 is prepared. The silicon substrate 112 has a first main surface 112a and a second main surface 112b. The second main surface 112b is the surface opposite to the first main surface 112a. In this embodiment, the silicon substrate 112 is a silicon single crystal substrate.

[0011] Next, as shown in FIG. 2 , a silicon oxide film 114, an amorphous silicon film 116, and a metal layer 118 are formed in this order on the first main surface 112a of the silicon substrate 112. In this embodiment, first, the silicon oxide film 114 is formed on the first main surface 112a of the silicon substrate 112 by chemical vapor deposition (CVD), thermal oxidation, or the like. Next, the amorphous silicon film 116 is formed on the silicon oxide film 114 by CVD or the like. Next, the metal layer 118 is formed on the amorphous silicon film 116 by CVD, physical vapor deposition (PVD), or the like. The metal layer 118 is formed of, for example, nickel (Ni), a nickel-aluminum alloy (Ni—Al), cobalt (Co), or palladium (Pd). Next, alloying annealing may be performed. As a result, at least a part of the metal layer 118 reacts with silicon (Si) constituting the amorphous silicon film 116 and becomes silicide.

[0012] Next, as shown in FIG. 3 , the silicon substrate 112 on which the metal layer 118 is formed is annealed to convert the amorphous silicon film 116 into a crystalline silicon film 120. In this embodiment, the amorphous silicon film 116 is crystallized by metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), or the like to form the crystalline silicon film 120. Specifically, the silicon substrate 112 on which the metal layer 118 is formed is annealed at a predetermined temperature in an inert gas atmosphere. As a result, the metal constituting the metal layer 118 diffuses into the amorphous silicon film 116, and the amorphous silicon film 116 is crystallized by metal-induced crystallization or metal-induced lateral crystallization using the metal diffused into the amorphous silicon film 116 as nuclei to form the crystalline silicon film 120. At this time, the metal constituting the metal layer 118 may also diffuse into the silicon oxide film 114. Next, the metal layer 118 is removed by wet etching or the like.

[0013] 4, the crystalline silicon film 120 is processed into a columnar shape. In this embodiment, first, a thin film for a hard mask 122 is formed on the crystalline silicon film 120 by CVD or the like. The thin film for the hard mask 122 is, for example, a SiN film or a SiO ２ Next, a resist mask having openings in areas other than the area where the crystalline silicon film 120 is to be left is formed by lithography. Next, the crystalline silicon film 120 is etched and removed using the resist mask. Next, the resist mask is removed. As a result, the crystalline silicon film 120 is processed into a columnar shape extending in a direction perpendicular to the first main surface 112a.

[0014] Next, as shown in FIG. 5, a gate stack structure is formed. In this embodiment, first, an insulating film 124 is formed on the silicon oxide film 114. The insulating film 124 is, for example, a SiN film, a SiOCN film, or a SiOC film. Next, an insulating film 126a for the gate insulating film 126 is formed on the side surface of the crystalline silicon film 120 by thermal oxidation, ALD, or the like. The insulating film 126a is, for example, a SiO ２ Next, a metal film 128a for the gate electrode 128 is formed so as to cover the crystalline silicon film 120, the hard mask 122, the insulating film 124, and the insulating film 126a. The metal film 128a is made of, for example, tungsten (W), cobalt, or molybdenum (Mo).

[0015] Next, as shown in FIG. 6 , a gate insulating film 126 and a gate electrode 128 are formed. In this embodiment, first, the insulating film 126a and the metal film 128a are etched by etch-back or the like, leaving the insulating film 126a and the metal film 128a on part of the side surface of the crystalline silicon film 120. Next, the hard mask 122 is etched and removed by wet etching, dry etching, or the like. Next, the insulating film 124 is etched and removed by wet etching, dry etching, or the like. As a result, the gate insulating film 126 is formed from the insulating film 126a, and the gate electrode 128 is formed from the metal film 128a. The gate insulating film 126 and the gate electrode 128 are formed, for example, in the central portion of the crystalline silicon film 120 in a direction perpendicular to the first major surface 112a. The gate electrode 128 is electrically connected to a word line (not shown).

[0016] 7, the interlayer insulating film 130 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 130 is formed so as to cover the silicon oxide film 114, the crystalline silicon film 120, the gate insulating film 126, and the gate electrode 128. The insulating film for the interlayer insulating film 130 is made of, for example, SiO ２ The crystalline silicon film 120 is formed on the SiOCN film, the SiOC film, and the SiOC film. Next, the upper surface of the crystalline silicon film 120 is exposed by chemical mechanical polishing (CMP) or the like. This forms the interlayer insulating film 130. Next, ions are implanted into the crystalline silicon film 120 on the side of the bit line 138. For example, a source region (not shown) is formed by ion implantation. In the ion implantation to form the source region, n-type impurities such as arsenic (As) or phosphorus (P) are ion-implanted. The source region is electrically connected to the bit line 138. Next, activation annealing is performed by RTA (Rapid Thermal Anneal), a heating furnace, or the like.

[0017] 8, the bit line 138 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 132 is formed on the crystalline silicon film 120 and the interlayer insulating film 130. The insulating film for the interlayer insulating film 132 is made of, for example, SiO ２film, SiOCN film, and SiOC film. Next, a resist mask having an opening is formed on the crystalline silicon film 120 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 132 is etched and removed by dry etching or the like. This forms a via 134 that exposes the crystalline silicon film 120. Next, a metal film is formed so as to fill the via 134, and the surface is planarized by CMP or the like. This forms a metal film 136 inside the via 134. The metal film 136 is formed of, for example, titanium nitride (TiN), tungsten, cobalt, molybdenum, or ruthenium (Ru). Next, an insulating film for an interlayer insulating film (not shown) that insulates between the bit lines 138 is formed on the interlayer insulating film 132 and the metal film 136. The insulating film for the interlayer insulating film is, for example, SiO ２ The insulating film for the interlayer insulating film is a SiOCN film, or a SiOC film. Next, a resist mask having an opening in the region where the bit line 138 is to be formed is formed by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film is etched by dry etching or the like. This forms a trench that exposes the interlayer insulating film 132 and the metal film 136. Next, a metal film for the bit line 138 is formed so as to fill the trench, and the surface is planarized by CMP or the like. This forms the bit line 138 inside the trench. The bit line 138 is made of titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an interlayer insulating film 140 is formed on the bit line 138 and the interlayer insulating film that insulates the bit line 138 from one another. The interlayer insulating film 140 is made of, for example, SiO ２ film, SiOCN film, and SiOC film.

[0018] Next, as shown in FIG. 9 , the first main surface 112 a of the first substrate 110, on which the interlayer insulating film 140 has been formed, is bonded to a second substrate 190 that has been prepared in advance. In this embodiment, the second substrate 190 is a CMOS (Complementary Metal Oxide Semiconductor) substrate. The second substrate 190 has a CMOS section 192 and a wiring section 194. The CMOS section 192 includes a silicon substrate 192 a and a plurality of transistors 192 b. The plurality of transistors 192 b includes P-type transistors and N-type transistors. The wiring section 194 includes wiring 194 a and an interlayer insulating film 194 b. The wiring 194 a is formed in multiple layers. The interlayer insulating film 194 b provides insulation between the wirings 194 a. The first substrate 110 and the second substrate 190 are bonded so that the interlayer insulating film 140 and the wiring section 194 are in contact with each other.

[0019] Next, as shown in FIG. 10 , the first substrate 110 is thinned by removing the silicon substrate 112 and the silicon oxide film 114 from the second main surface 112b side of the silicon substrate 112. In this embodiment, first, grinding and CMP are performed in this order to polish the silicon substrate 112 from the second main surface 112b side. Next, the silicon substrate 112 is selectively etched and removed relative to the silicon oxide film 114 by wet etching, dry etching, or the like. Instead of grinding, the silicon substrate 112 may be removed by laser lift-off or a laser-based peeling technique. When using laser lift-off, for example, a peeling layer is provided between the silicon substrate 112 and the silicon oxide film 114, and the peeling layer is peeled off by laser irradiation, thereby removing the silicon substrate 112 along with the peeling layer. When using a laser-based peeling technique, for example, a modified layer is formed inside the silicon substrate 112 by laser irradiation, and the silicon substrate 112 can be removed starting from the modified layer. Next, the silicon oxide film 114 is selectively etched away from the crystalline silicon film 120 and the interlayer insulating film 130. In this case, metals that may diffuse into the silicon oxide film 114 are removed along with the silicon oxide film 114, and therefore do not remain in the final semiconductor device 1. Furthermore, it is easy to uniformize the length of the columnar crystalline silicon film 120 that does not overlap with the gate electrode 128 across the entire surface of the first substrate 110. In contrast, if the length of the crystalline silicon film 120 is controlled by stopping the etching midway instead of using etching selectivity, it is difficult to uniformize the length of the columnar crystalline silicon film 120 that does not overlap with the gate electrode 128 across the entire surface of the first substrate 110. Next, ions are implanted into the crystalline silicon film 120 on the capacitor 160 side. For example, a drain region (not shown) is formed by ion implantation. This forms a transistor 142 having a channel (not shown) between the source and drain regions of the crystalline silicon film 120. The ion implantation to form the drain region involves ion implantation of n-type impurities such as arsenic or phosphorus. The drain region is electrically connected to the capacitor 160. Next, activation annealing is performed using RTA, a heating furnace, or the like.

[0020] 11, a pad 154 for the capacitor 160 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 144 is formed on the crystalline silicon film 120 and the interlayer insulating film 130. The insulating film for the interlayer insulating film 144 is made of, for example, SiO ２ film, SiOCN film, and SiOC film. Next, a resist mask having an opening is formed on the crystalline silicon film 120 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 144 is etched and removed by dry etching or the like. This forms a via 146 that exposes the crystalline silicon film 120. Next, a metal film is formed so as to fill the via 146, and the surface is planarized by CMP or the like. This forms a metal film 148 inside the via 146. The metal film 148 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for the interlayer insulating film 150 is formed on the interlayer insulating film 144 and the metal film 148. The insulating film for the interlayer insulating film 150 is formed of, for example, SiO ２ The metal film 148 is then formed of a metal oxide film, a silicon dioxide film, a silicon dioxide nitride film, or a silicon carbide (SiOCN) film. Next, a resist mask having an opening is formed on the metal film 148 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 150 is etched and removed by dry etching or the like. This forms an opening 152 that exposes the metal film 148. Next, a metal film is formed so as to fill the opening 152, and the surface is planarized by CMP or the like. This forms a pad 154 inside the opening 152. The pad 154 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium.

[0021] 12, a capacitor 160 is formed adjacent to the transistor 142 in a direction perpendicular to the first main surface 112a and electrically connected to the transistor 142. In this embodiment, first, an insulating film for the interlayer insulating film 156 is formed on the interlayer insulating film 150 and the pad 154. The insulating film for the interlayer insulating film 156 is made of, for example, SiO ２The insulating films are a SiOCN film, a SiOC film, and a SiON film. Next, a resist mask having an opening on the pad 154 is formed by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 156 is etched and removed by dry etching or the like. This forms a capacitor hole 158 that exposes the pad 154. Next, a capacitor 160 is formed inside the capacitor hole 158. The capacitor 160 has a structure in which an insulating film is sandwiched between, for example, metal films. Next, an insulating film 162 is formed to cover the upper surface of the interlayer insulating film 156 and the upper surface of the capacitor 160.

[0022] In this way, the semiconductor device 1 according to the first embodiment is manufactured. The semiconductor device 1 is configured as a dynamic random access memory (DRAM) having a plurality of memory cells 164. Each memory cell 164 includes a transistor 142 and a capacitor 160 connected in series.

[0023] As described above, according to the manufacturing method of the semiconductor device 1 of the first embodiment, first, a silicon substrate 112 having a first main surface 112a is prepared. Next, a silicon oxide film 114, an amorphous silicon film 116, and a metal layer 118 are formed in this order on the first main surface 112a of the silicon substrate 112. Next, the silicon substrate 112 on which the metal layer 118 has been formed is annealed to convert the amorphous silicon film 116 into a crystalline silicon film 120. Next, a transistor 142 is formed, with a portion of the crystalline silicon film 120 serving as a channel. Next, a capacitor 160 is formed adjacent to the transistor 142 in a direction perpendicular to the first main surface 112a and electrically connected to the transistor 142. In this case, a semiconductor device 1 including a transistor 142 with a portion of the crystalline silicon film 120 serving as a channel can be formed without using an SOI substrate.

[0024] Second Embodiment A method for manufacturing a semiconductor device 2 according to a second embodiment will be described with reference to Figures 13 to 23. Figures 13 to 23 are cross-sectional views showing the method for manufacturing a semiconductor device 2 according to the second embodiment.

[0025] First, as shown in Fig. 13, a silicon substrate 212 is prepared. The silicon substrate 212 has a first main surface 212a and a second main surface 212b. The second main surface 212b is the surface opposite to the first main surface 212a. In this embodiment, the silicon substrate 212 is a silicon single crystal substrate.

[0026] Next, as shown in FIG. 14 , a silicon oxide film 214, an amorphous silicon film 216, and a metal layer 218 are formed in this order on the first main surface 212a of the silicon substrate 212. In this embodiment, first, the silicon oxide film 214 is formed on the first main surface 212a of the silicon substrate 212 by CVD, thermal oxidation, or the like. Next, the amorphous silicon film 216 is formed on the silicon oxide film 214 by CVD or the like. The amorphous silicon film 216 is deposited so as to be thicker than the crystalline silicon film 220 that will remain in the final semiconductor device 2. For example, the thickness of the amorphous silicon film 216 may be at least twice the thickness of the crystalline silicon film 220 that will remain in the final semiconductor device 2. Next, a metal layer 218 is formed on the amorphous silicon film 216 by CVD, PVD, or the like. The metal layer 218 can be formed in the same manner as the metal layer 118.

[0027] 15, the silicon substrate 212 on which the metal layer 218 has been formed is annealed to change the amorphous silicon film 216 into a crystalline silicon film 220. The crystalline silicon film 220 can be formed in the same manner as the crystalline silicon film 120.

[0028] 16, the crystalline silicon film 220 is processed into a columnar shape. In this embodiment, first, a thin film for a hard mask 222 is formed on the crystalline silicon film 220 by CVD or the like. The thin film for the hard mask 222 is, for example, a SiN film or a SiO ２ Next, a resist mask having openings in areas other than the area where the crystalline silicon film 220 is to be left is formed by lithography. Next, the crystalline silicon film 220 is etched and removed using the resist mask. Next, the resist mask is removed. As a result, the crystalline silicon film 220 is processed into a columnar shape extending in a direction perpendicular to the first main surface 212a.

[0029] 17, a gate insulating film 226 and a gate electrode 228 are formed. The gate insulating film 226 and the gate electrode 228 can be formed in the same manner as the gate insulating film 126 and the gate electrode 128. The gate insulating film 226 and the gate electrode 228 are formed, for example, in the central portion of the crystalline silicon film 220 in the direction perpendicular to the first main surface 212a.

[0030] 18, an interlayer insulating film 230 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 230 is formed so as to cover the silicon oxide film 214, the crystalline silicon film 220, the gate insulating film 226, and the gate electrode 228. The insulating film for the interlayer insulating film 230 is made of, for example, SiO ２ The crystalline silicon film 220 is then formed by a process such as CMP, which exposes the top surface of the crystalline silicon film 220. This results in the formation of the interlayer insulating film 230. At this time, the crystalline silicon film 220 is polished down to the vicinity of the gate electrode 228 to reduce its thickness. This process removes the crystalline silicon film 220 near the initiation region of metal-induced crystallization or metal-induced lateral crystallization. The initiation region of metal-induced crystallization or metal-induced lateral crystallization is prone to poor or non-uniform crystallinity. Therefore, by removing the initiation region of metal-induced crystallization or metal-induced lateral crystallization, the crystalline silicon film 220 with good crystallinity can be used as a channel. Next, ions are implanted into the crystalline silicon film 220 on the side of the bit line 238. For example, a source region (not shown) is formed by ion implantation. The ion implantation to form the source region involves the implantation of n-type impurities such as arsenic or phosphorus. The source region is electrically connected to the bit line 238. Next, activation annealing is performed using RTA, a heating furnace, or the like.

[0031] 19, the bit line 238 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 232 is formed on the crystalline silicon film 220 and the interlayer insulating film 230. The insulating film for the interlayer insulating film 232 is made of, for example, SiO ２film, SiOCN film, and SiOC film. Next, a resist mask having an opening is formed on the crystalline silicon film 220 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 232 is etched and removed by dry etching or the like. This forms a via 234 that exposes the crystalline silicon film 220. Next, a metal film is formed so as to fill the via 234, and the surface is planarized by CMP or the like. This forms a metal film 236 inside the via 234. The metal film 236 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for an interlayer insulating film (not shown) that insulates between the bit lines 238 is formed on the interlayer insulating film 232 and the metal film 236. The insulating film for the interlayer insulating film is, for example, SiO ２ The insulating film for the interlayer insulating film is a film, a SiOCN film, or a SiOC film. Next, a resist mask having an opening in the region where the bit line 238 is to be formed is formed by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film is etched by dry etching or the like. This forms a trench that exposes the interlayer insulating film 232 and the metal film 236. Next, a metal film for the bit line 238 is formed so as to fill the trench, and the surface is planarized by CMP or the like. This forms the bit line 238 inside the trench. The bit line 238 is made of titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an interlayer insulating film 240 is formed on the bit line 238 and the interlayer insulating film that insulates the bit line 238 from one another. The interlayer insulating film 240 is made of, for example, SiO ２ film, SiOCN film, and SiOC film.

[0032] Next, as shown in FIG. 20 , the first main surface 212 a of the first substrate 210, on which the interlayer insulating film 240 has been formed, is bonded to a second substrate 290 that has been prepared in advance. In this embodiment, the second substrate 290 is a CMOS substrate. The second substrate 290 has a CMOS section 292 and a wiring section 294. The CMOS section 292 includes a silicon substrate 292 a and a plurality of transistors 292 b. The plurality of transistors 292 b includes P-type transistors and N-type transistors. The wiring section 294 includes wiring 294 a and an interlayer insulating film 294 b. The wiring 294 a is formed in multiple layers. The interlayer insulating film 294 b provides insulation between the wirings 294 a. The first substrate 210 and the second substrate 290 are bonded so that the interlayer insulating film 240 and the wiring section 294 are in contact with each other.

[0033] Next, as shown in FIG. 21 , the first substrate 210 is thinned by removing the silicon substrate 212, the silicon oxide film 214, a portion of the crystalline silicon film 220, and a portion of the interlayer insulating film 230 from the second main surface 212b side of the silicon substrate 212. In this embodiment, grinding and CMP are first performed in this order to polish and remove the silicon substrate 212, the silicon oxide film 214, a portion of the crystalline silicon film 220, and a portion of the interlayer insulating film 230 from the second main surface 212b side. In this process, metal that may diffuse into the silicon oxide film 214 is removed along with the silicon oxide film 214 and therefore does not remain in the final semiconductor device 2. When polishing the portion of the crystalline silicon film 220, the crystalline silicon film 220 is polished to the vicinity of the gate electrode 228 to reduce its thickness. In this process, the crystalline silicon film 220 near the end point region of metal-induced crystallization or metal-induced lateral crystallization is removed. The vicinity of the end point region of metal-induced crystallization or metal-induced lateral crystallization is prone to poor or non-uniform crystallinity. Therefore, by removing the vicinity of the end point region of metal-induced crystallization or metal-induced lateral crystallization, the crystalline silicon film 220 with good crystallinity can be used as a channel. Next, ion implantation is performed on the capacitor 260 side of the crystalline silicon film 220. For example, a drain region (not shown) is formed by ion implantation. This results in the formation of a transistor 242 with a channel (not shown) between the source and drain regions of the crystalline silicon film 220. The ion implantation to form the drain region involves ion implantation of n-type impurities such as arsenic or phosphorus. The drain region is electrically connected to the capacitor 260. Next, activation annealing is performed using RTA, a heating furnace, or the like.

[0034] 22, a pad 254 for the capacitor 260 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 244 is formed on the crystalline silicon film 220 and the interlayer insulating film 230. The insulating film for the interlayer insulating film 244 is made of, for example, SiO ２film, SiOCN film, and SiOC film. Next, a resist mask having an opening is formed on the crystalline silicon film 220 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 244 is etched and removed by dry etching or the like. As a result, a via 246 is formed that exposes the crystalline silicon film 220. Next, a metal film is formed so as to fill the via 246, and the surface is planarized by CMP or the like. As a result, a metal film 248 is formed inside the via 246. The metal film 248 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for the interlayer insulating film 250 is formed on the interlayer insulating film 244 and the metal film 248. The insulating film for the interlayer insulating film 250 is formed of, for example, SiO ２ The insulating film for the interlayer insulating film 250 is a silicon dioxide film, a silicon nitride film, or a silicon carbide (SiOCN) film. Next, a resist mask having an opening is formed on the metal film 248 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 250 is etched and removed by dry etching or the like. This forms an opening 252 that exposes the metal film 248. Next, a metal film is formed so as to fill the opening 252, and the surface is planarized by CMP or the like. This forms a pad 254 inside the opening 252. The pad 254 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium.

[0035] 23, a capacitor 260 is formed adjacent to the transistor 242 in a direction perpendicular to the first main surface 212a and electrically connected to the transistor 242. In this embodiment, first, an insulating film for the interlayer insulating film 256 is formed on the interlayer insulating film 250 and the pad 254. The insulating film for the interlayer insulating film 256 is made of, for example, SiO ２The insulating films are a SiOCN film, and a SiOC film. Next, a resist mask having an opening on the pad 254 is formed by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 256 is etched and removed by dry etching or the like. This forms a capacitor hole 258 that exposes the pad 254. Next, a capacitor 260 is formed inside the capacitor hole 258. The capacitor 260 has a structure in which an insulating film is sandwiched between, for example, metal films. Next, an insulating film 262 is formed to cover the upper surface of the interlayer insulating film 256 and the upper surface of the capacitor 260.

[0036] In this way, the semiconductor device 2 according to the second embodiment is manufactured. The semiconductor device 2 is configured as a DRAM having a plurality of memory cells 264. Each memory cell 264 includes a transistor 242 and a capacitor 260 connected in series.

[0037] As described above, according to the manufacturing method of the semiconductor device 2 of the second embodiment, first, a silicon substrate 212 having a first main surface 212a is prepared. Next, a silicon oxide film 214, an amorphous silicon film 216, and a metal layer 218 are formed in this order on the first main surface 212a of the silicon substrate 212. Next, the silicon substrate 212 on which the metal layer 218 has been formed is annealed to convert the amorphous silicon film 216 into a crystalline silicon film 220. Next, a transistor 242 is formed, with a portion of the crystalline silicon film 220 serving as a channel. Next, a capacitor 260 is formed adjacent to the transistor 242 in a direction perpendicular to the first main surface 212a and electrically connected to the transistor 242. In this case, a semiconductor device 2 including a transistor 242 with a portion of the crystalline silicon film 220 serving as a channel can be formed without using an SOI substrate.

[0038] Furthermore, according to the manufacturing method of the semiconductor device 2 according to the second embodiment, the vicinity of the start point region and the vicinity of the end point region of the metal-induced crystallization or the metal-induced lateral crystallization are removed from the crystalline silicon film 220. In this case, the crystalline silicon film 220 with good crystallinity can be used as a channel.

[0039] Third Embodiment A method for manufacturing a semiconductor device 3 according to a third embodiment will be described with reference to Figures 24 to 36. Figures 24 to 36 are cross-sectional views showing the method for manufacturing a semiconductor device 3 according to the third embodiment.

[0040] First, as shown in Fig. 24, a silicon substrate 312 is prepared. The silicon substrate 312 has a first main surface 312a and a second main surface 312b. The second main surface 312b is the surface opposite to the first main surface 312a. In this embodiment, the silicon substrate 312 is a silicon single crystal substrate.

[0041] 25 , a silicon oxide film 314 and an amorphous silicon film 316 are formed in this order on the first main surface 312a of the silicon substrate 312. In this embodiment, first, the silicon oxide film 314 is formed on the first main surface 312a of the silicon substrate 312 by CVD, thermal oxidation, or the like. Next, the amorphous silicon film 316 is formed on the silicon oxide film 314 by CVD or the like. The amorphous silicon film 316 is deposited to the same thickness as the amorphous silicon film 216, for example.

[0042] 26, the amorphous silicon film 316 is processed into a columnar shape. In this embodiment, first, a thin film for a hard mask 322 is formed on the amorphous silicon film 316 by CVD or the like. The thin film for the hard mask 322 is, for example, a SiN film or a SiO ２ Next, a resist mask having openings in areas other than the area where amorphous silicon film 316 is to remain is formed by lithography. Next, amorphous silicon film 316 is etched and removed using the resist mask. Next, the resist mask is removed. As a result, amorphous silicon film 316 is processed into a columnar shape extending in a direction perpendicular to first main surface 312a.

[0043] 27, a gettering film 372 and a metal layer 318 are formed. In this embodiment, first, the hard mask 322 is etched and removed by wet etching, dry etching, or the like. Next, a thin film for the gettering film 372 is formed so as to cover the side and upper surfaces of the amorphous silicon film 316. The thin film for the gettering film 372 is made of, for example, SiO ２The amorphous silicon film 316 is made of a silicon nitride film, a silicon nitride film, and a polysilicon film doped with impurities. Next, the upper surface of the amorphous silicon film 316 is exposed by CMP or the like. This forms a gettering film 372. Next, a metal layer 318 is formed on the amorphous silicon film 316 and the gettering film 372 by CVD, PVD, or the like. The metal layer 318 can be formed in the same manner as the metal layer 118.

[0044] Next, as shown in FIG. 28 , the silicon substrate 312 on which the metal layer 318 is formed is annealed to convert the amorphous silicon film 316 into a crystalline silicon film 320. In this embodiment, the amorphous silicon film 316 is crystallized by metal-induced crystallization, metal-induced lateral crystallization, or the like to form the crystalline silicon film 320. Specifically, the silicon substrate 312 on which the metal layer 318 is formed is annealed at a predetermined temperature in an inert gas atmosphere. As a result, the metal constituting the metal layer 318 diffuses into the amorphous silicon film 316, and the amorphous silicon film 316 crystallizes by metal-induced crystallization or metal-induced lateral crystallization using the metal diffused into the amorphous silicon film 316 as nuclei to form the crystalline silicon film 320. At this time, the metal constituting the metal layer 318 may remain in the crystalline silicon film 320. Annealing diffuses the remaining metal from the crystalline silicon film 320 into the silicon oxide film 114 and the gettering film 372, thereby reducing the concentration of the metal remaining in the crystalline silicon film 320. As a result, it is possible to improve the reliability of the transistor 342 that uses the crystalline silicon film 320 as a channel. Next, the metal layer 318 is removed by wet etching or the like.

[0045] 29, the gettering film 372 is etched and removed by dry etching, wet etching, etc. This makes it possible to prevent the metal in the gettering film 372 from being taken into the crystalline silicon film 320 again.

[0046] 30 , a gate insulating film 326 and a gate electrode 328 are formed. The gate insulating film 326 and the gate electrode 328 can be formed in the same manner as the gate insulating film 126 and the gate electrode 128. The gate insulating film 326 and the gate electrode 328 are formed, for example, in the central portion of the crystalline silicon film 320 in the direction perpendicular to the first main surface 312 a.

[0047] 31, an interlayer insulating film 330 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 330 is formed so as to cover the silicon oxide film 314, the crystalline silicon film 320, the gate insulating film 326, and the gate electrode 328. The insulating film for the interlayer insulating film 330 is made of, for example, SiO ２ The crystalline silicon film 320 is then exposed by CMP or the like, thereby forming the interlayer insulating film 330. At this time, the crystalline silicon film 320 is polished down to the vicinity of the gate electrode 328 to reduce its thickness. In this process, the crystalline silicon film 320 is removed from the vicinity of the initiation region of metal-induced crystallization or metal-induced lateral crystallization. The vicinity of the initiation region of metal-induced crystallization or metal-induced lateral crystallization is prone to poor or non-uniform crystallinity. Therefore, by removing the vicinity of the initiation region of metal-induced crystallization or metal-induced lateral crystallization, the crystalline silicon film 320 with good crystallinity can be used as a channel. Next, ions are implanted into the crystalline silicon film 320 on the side of the bit line 338. For example, a source region (not shown) is formed by ion implantation. The ion implantation to form the source region involves ion implantation of n-type impurities such as arsenic or phosphorus. The source region is electrically connected to the bit line 338. Next, activation annealing is performed using RTA, a heating furnace, or the like.

[0048] 32, a bit line 338 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 332 is formed on the crystalline silicon film 320 and the interlayer insulating film 330. The insulating film for the interlayer insulating film 332 is made of, for example, SiO ２film, SiOCN film, and SiOC film. Next, a resist mask having an opening is formed on the crystalline silicon film 320 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 332 is etched and removed by dry etching or the like. This forms a via 334 that exposes the crystalline silicon film 320. Next, a metal film is formed so as to fill the via 334, and the surface is planarized by CMP or the like. This forms a metal film 336 inside the via 334. The metal film 336 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for an interlayer insulating film (not shown) that insulates between the bit lines 338 is formed on the interlayer insulating film 332 and the metal film 336. The insulating film for the interlayer insulating film is, for example, SiO ２ The insulating film for the interlayer insulating film is a SiOCN film, or a SiOC film. Next, a resist mask having an opening in the region where the bit line 338 is to be formed is formed by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film is etched by dry etching or the like. This forms a trench that exposes the interlayer insulating film 332 and the metal film 336. Next, a metal film for the bit line 338 is formed so as to fill the trench, and the surface is planarized by CMP or the like. This forms the bit line 338 inside the trench. The bit line 338 is made of titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an interlayer insulating film 340 is formed on the bit line 338 and the interlayer insulating film that insulates the bit line 338 from one another. The interlayer insulating film 340 is made of, for example, SiO ２ film, SiOCN film, and SiOC film.

[0049] Next, as shown in FIG. 33 , the first main surface 312 a of the first substrate 310, on which the interlayer insulating film 340 has been formed, is bonded to a second substrate 390 that has been prepared in advance. In this embodiment, the second substrate 390 is a CMOS substrate. The second substrate 390 has a CMOS section 392 and a wiring section 394. The CMOS section 392 includes a silicon substrate 392 a and a plurality of transistors 392 b. The plurality of transistors 392 b includes P-type transistors and N-type transistors. The wiring section 394 includes wiring 394 a and an interlayer insulating film 394 b. The wiring 394 a is formed in multiple layers. The interlayer insulating film 394 b provides insulation between the wirings 394 a. The first substrate 310 and the second substrate 390 are bonded so that the interlayer insulating film 340 and the wiring section 394 are in contact with each other.

[0050] Next, as shown in FIG. 34 , the first substrate 310 is thinned by removing the silicon substrate 312, the silicon oxide film 314, a portion of the crystalline silicon film 320, and a portion of the interlayer insulating film 330 from the second main surface 312b side of the silicon substrate 312. In this embodiment, grinding and CMP are first performed in this order to polish and remove the silicon substrate 312, the silicon oxide film 314, a portion of the crystalline silicon film 320, and a portion of the interlayer insulating film 330 from the second main surface 312b side. In this process, metal that may diffuse into the silicon oxide film 314 is removed along with the silicon oxide film 314 and therefore does not remain in the final semiconductor device 3. When polishing a portion of the crystalline silicon film 320, the crystalline silicon film 320 is polished to the vicinity of the gate electrode 328 to reduce its thickness. In this process, the crystalline silicon film 320 near the end point region of metal-induced crystallization or metal-induced lateral crystallization is removed. The vicinity of the end point region of metal-induced crystallization or metal-induced lateral crystallization is prone to poor or non-uniform crystallinity. Therefore, by removing the vicinity of the end point region of metal-induced crystallization or metal-induced lateral crystallization, the crystalline silicon film 320 with good crystallinity can be used as a channel. Next, ion implantation is performed on the capacitor 360 side of the crystalline silicon film 320. For example, a drain region (not shown) is formed by ion implantation. This results in the formation of a transistor 342 with a channel (not shown) between the source and drain regions of the crystalline silicon film 320. The ion implantation to form the drain region involves ion implantation of n-type impurities such as arsenic or phosphorus. The drain region is electrically connected to the capacitor 360. Next, activation annealing is performed using RTA, a heating furnace, or the like.

[0051] 35, a pad 354 for the capacitor 360 is formed. In this embodiment, first, an insulating film for the interlayer insulating film 344 is formed on the crystalline silicon film 320 and the interlayer insulating film 330. The insulating film for the interlayer insulating film 344 is made of, for example, SiO ２film, SiOCN film, and SiOC film. Next, a resist mask having an opening is formed on the crystalline silicon film 320 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 344 is etched and removed by dry etching or the like. As a result, a via 346 is formed that exposes the crystalline silicon film 320. Next, a metal film is formed so as to fill the via 346, and the surface is planarized by CMP or the like. As a result, a metal film 348 is formed inside the via 346. The metal film 348 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for the interlayer insulating film 350 is formed on the interlayer insulating film 344 and the metal film 348. The insulating film for the interlayer insulating film 350 is formed of, for example, SiO ２ The insulating film for the interlayer insulating film 350 is a silicon dioxide film, a silicon nitride film, or a silicon carbide (SiOCN) film. Next, a resist mask having an opening is formed on the metal film 348 by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 350 is etched and removed by dry etching or the like. This forms an opening 352 that exposes the metal film 348. Next, a metal film is formed so as to fill the opening 352, and the surface is planarized by CMP or the like. This forms a pad 354 inside the opening 352. The pad 354 is formed of, for example, titanium nitride, tungsten, cobalt, molybdenum, or ruthenium.

[0052] 36, a capacitor 360 is formed adjacent to the transistor 342 in a direction perpendicular to the first main surface 312a and electrically connected to the transistor 342. In this embodiment, first, an insulating film for the interlayer insulating film 356 is formed on the interlayer insulating film 350 and the pad 354. The insulating film for the interlayer insulating film 356 is made of, for example, SiO ２The insulating films are a SiOCN film, and a SiOC film. Next, a resist mask having an opening on the pad 354 is formed by lithography. Next, using the resist mask, the insulating film for the interlayer insulating film 356 is etched and removed by dry etching or the like. This forms a capacitor hole 358 that exposes the pad 354. Next, a capacitor 360 is formed inside the capacitor hole 358. The capacitor 360 has a structure in which an insulating film is sandwiched between, for example, metal films. Next, an insulating film 362 is formed to cover the upper surface of the interlayer insulating film 356 and the upper surface of the capacitor 360.

[0053] In this way, the semiconductor device 3 according to the third embodiment is manufactured. The semiconductor device 3 is configured as a DRAM having a plurality of memory cells 364. Each memory cell 364 includes a transistor 342 and a capacitor 360 connected in series.

[0054] As described above, according to the manufacturing method of the semiconductor device 3 of the third embodiment, first, a silicon substrate 312 having a first main surface 312a is prepared. Next, a silicon oxide film 314, an amorphous silicon film 316, and a metal layer 318 are formed in this order on the first main surface 312a of the silicon substrate 312. Next, the silicon substrate 312 on which the metal layer 318 has been formed is annealed to convert the amorphous silicon film 316 into a crystalline silicon film 320. Next, a transistor 342 is formed, with a portion of the crystalline silicon film 320 serving as a channel. Next, a capacitor 360 is formed adjacent to the transistor 342 in a direction perpendicular to the first main surface 312a and electrically connected to the transistor 342. In this case, a semiconductor device 3 including a transistor 342 with a portion of the crystalline silicon film 320 serving as a channel can be formed without using an SOI substrate.

[0055] Furthermore, according to the manufacturing method of the semiconductor device 3 of the third embodiment, the vicinity of the start point region and the vicinity of the end point region of the metal-induced crystallization or the metal-induced lateral crystallization are removed from the crystalline silicon film 320. In this case, the crystalline silicon film 320 with good crystallinity can be used as a channel.

[0056] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive, and the above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims.

[0057] This international application claims priority based on Japanese Patent Application No. 2023-194952, filed on November 16, 2023, the entire contents of which are incorporated herein by reference.

[0058] 1, 2, 3 Semiconductor device 112, 212, 312 Silicon substrate 112a, 212a, 312a First main surface 114, 214, 314 Silicon oxide film 116, 216, 316 Amorphous silicon film 118, 218, 318 Metal layer 120, 220, 320 Crystalline silicon film 142, 242, 342 Transistor 160, 260, 360 Capacitor

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: preparing a silicon substrate having a first main surface; forming a silicon oxide film on the first main surface of the silicon substrate; forming an amorphous silicon film on the silicon oxide film; forming a metal layer on the amorphous silicon film; annealing the silicon substrate on which the metal layer has been formed, thereby changing the amorphous silicon film into a crystalline silicon film; forming a transistor in which a portion of the crystalline silicon film serves as a channel; and forming a capacitor adjacent to the transistor in a direction perpendicular to the first main surface and electrically connected to the transistor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the transistor comprises the steps of: bonding the first main surface side of the silicon substrate to a second silicon substrate; and removing the silicon substrate and the silicon oxide film from a second main surface side of the silicon substrate bonded to the second silicon substrate, the second main surface side being opposite to the first main surface.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the second silicon substrate is a CMOS substrate.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the crystalline silicon film has a first surface in contact with the silicon oxide film and a second surface opposite to the first surface, and the step of forming the transistor includes a step of polishing the second surface of the crystalline silicon film to reduce a film thickness.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the step of forming the transistor includes a step of polishing the first surface of the crystalline silicon film to reduce a film thickness after the step of removing the silicon substrate and the silicon oxide film.

6. The method for manufacturing a semiconductor device according to claim 2, wherein the step of removing the silicon substrate and the silicon oxide film includes removing the silicon substrate by laser lift-off or a peeling technique using a laser.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising a step of processing the crystalline silicon film into a pillar shape extending in a direction perpendicular to the first main surface between the step of converting the crystalline silicon film into a crystalline silicon film and the step of forming the transistor.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising, between the step of forming the amorphous silicon film and the step of forming the metal layer, a step of processing the amorphous silicon film into a columnar shape extending in a direction perpendicular to the first main surface.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of forming a gettering film covering a side surface of said amorphous silicon film between said step of processing into a pillar shape and said step of forming said metal layer.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of removing said gettering film after said step of forming said metal layer.

Images