Gate driver circuit and switching circuit

Abstract

A gate driver circuit (200) drives an N-type power transistor (110) on the basis of a control signal CTRL. A first transistor M1 is connected between a high-side line (202) and an output line (206). A second transistor M2 is connected between the output line (206) and a low-side line (204). A third transistor M3 is connected in parallel with the second transistor M2 between the output line (206) and the low-side line (204). When the control signal CTRL transitions from an off level to an on level, an auxiliary circuit (220) turns on the third transistor M3 for a prescribed duration.

Description

Gate driver and switching circuits

[0001] The present disclosure relates to gate driver circuits.

[0002] 2. Description of the Related Art In the field of power electronics, including DC / DC converters, AC / DC converters, and inverters, switching circuits such as half-bridge circuits and full-bridge circuits are used.

[0003] The switching circuit includes an N-type power transistor and a gate driver circuit that drives the power transistor. The gate driver circuit switches the gate-source voltage of the power transistor between a low-level voltage and a high-level voltage, thereby switching between an on state and an off state.

[0004] JP 2021-10258 A JP 2023-52044 A

[0005] [Summary] A gate driver circuit outputs a high-level voltage when turning on a power transistor. This high-level voltage charges the gate of the power transistor, and when the gate-source voltage of the power transistor exceeds the threshold voltage, the power transistor turns on. When a parasitic inductor is present in the path of the current supplied to the gate during the turn-on operation of the power transistor, the gate voltage overshoots. If the overshoot is too large, it may exceed the withstand voltage of the power transistor.

[0006] The present disclosure has been made in view of the above-mentioned problems, and one exemplary purpose of an embodiment thereof is to provide a gate driver circuit that suppresses overshoot of the gate voltage.

[0007] A gate driver circuit according to an embodiment of the present disclosure drives an N-type power transistor based on a control signal. The gate driver circuit includes: a low-side line connected to a source of the power transistor; an output line connected to a gate of the power transistor; a high-side line generating a high-level voltage higher than the voltage of the low-side line; a first transistor connected between the high-side line and the output line; a second transistor connected between the output line and the low-side line; a third transistor connected in parallel with the second transistor between the output line and the low-side line; a pre-driver that turns on the first transistor and turns off the second transistor when the control signal is at an on level instructing the power transistor to be on, and turns off the first transistor and turns on the second transistor when the control signal is at an off level instructing the power transistor to be off; and an auxiliary circuit that turns on the third transistor for a predetermined time when the control signal transitions from the off level to the on level.

[0008] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention.

[0009] FIG. 1 is a block diagram of a switching circuit including a gate driver circuit according to an embodiment. FIG. 2 is a waveform diagram illustrating the operation of a gate driver circuit according to a comparative technique. FIG. 3 is a waveform diagram illustrating the operation of the switching circuit of FIG. 1. FIG. 4 is a circuit diagram showing an example configuration of an auxiliary circuit. FIG. 5 is a circuit diagram showing another example configuration of the auxiliary circuit. FIG. 6 is a circuit diagram showing another example configuration of the auxiliary circuit. FIG. 7 is a circuit diagram showing a specific example of the auxiliary circuit of FIG. 6. FIG. 8 is a circuit diagram showing a modified example of a gate driver circuit. FIG. 9 is a circuit diagram of a switching circuit including a gate driver circuit.

[0010] DETAILED DESCRIPTION (Summary of the Embodiments) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0011] A gate driver circuit according to one embodiment drives an N-type power transistor based on a control signal. The gate driver circuit includes: a low-side line connected to a source of the power transistor; an output line connected to a gate of the power transistor; a high-side line generating a high-level voltage higher than the voltage of the low-side line; a first transistor connected between the high-side line and the output line; a second transistor connected between the output line and the low-side line; a third transistor connected in parallel with the second transistor between the output line and the low-side line; a pre-driver that turns on the first transistor and turns off the second transistor when the control signal is at an on level instructing the power transistor to be on, and turns off the first transistor and turns on the second transistor when the control signal is at an off level instructing the power transistor to be off; and an auxiliary circuit that turns on the third transistor for a predetermined time when the control signal transitions from an off level to an on level.

[0012] According to this aspect, after the first transistor is turned on, the third transistor is turned on during a period in which an overshoot may occur, and is kept on for a predetermined time, thereby making it possible to sink a portion of the current flowing into the gate of the power transistor into a different path, thereby suppressing overshoot of the gate voltage.

[0013] In one embodiment, the auxiliary circuit may include a pulse generator that generates a pulse signal having a pulse width corresponding to a predetermined time.

[0014] In one embodiment, the high level of the pulse signal may be a high level voltage, and the pulse signal may be supplied to the gate of the third transistor.

[0015] In one embodiment, the auxiliary circuit may further include a buffer that receives the pulse signal at its input and has an output connected to the gate of the third transistor.

[0016] In one embodiment, the buffer may include a CMOS inverter having a power supply terminal connected to the output line and an output connected to the gate of the third transistor.

[0017] In one embodiment, the auxiliary circuit may further include a level shifter having an input that receives the pulse signal, an output that is connected to the gate of the third transistor, and a level shifter that shifts the high level of the pulse signal to an intermediate level voltage that is lower than the high level voltage. In this configuration, the amount of sink current drawn by the third transistor can be optimized according to the intermediate level voltage.

[0018] In one embodiment, the level shifter may include a constant voltage element having a first end connected to the output line, a power supply terminal connected to a second end of the constant voltage element, and a CMOS inverter having an output connected to the gate of the third transistor. The constant voltage element may be a diode.

[0019] In one embodiment, the auxiliary circuit may further include a MOS transistor connected between the drain of the third transistor and the output line, with the gate and drain of the MOS transistor being wired together. By adding the MOS transistor, the amount of sink current can be adjusted depending on the size of the MOS transistor.

[0020] In one embodiment, the predetermined time may be between 1 and 20 ns.

[0021] In one embodiment, the gate driver circuit may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on the semiconductor substrate, and cases where the main circuit components are monolithically integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be maintained uniform.

[0022] A switching circuit according to one embodiment may include a power transistor and any of the gate driver circuits described above that drive the power transistor.

[0023] (Embodiments) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0024] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their connection.

[0025] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0026] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0027] 1 is a block diagram of a switching circuit 100 including a gate driver circuit 200 according to an embodiment. The switching circuit 100 includes an N-type power transistor 110 and the gate driver circuit 200.

[0028] The gate driver circuit 200 drives the power transistor 110 based on a control signal CTRL. The control signal CTRL switches between an on level (e.g., a high level) that instructs the power transistor 110 to be in an on state and an off level (e.g., a low level) that instructs the power transistor 110 to be in an off state.

[0029] The gate driver circuit 200 includes a high-side line 202, a low-side line 204, an output line 206, a first transistor M1, a second transistor M2, a third transistor M3, a pre-driver 210, and an auxiliary circuit 220. The gate driver circuit 200 is an integrated circuit (IC) integrated on a single semiconductor substrate.

[0030] An output pin OUT of the gate driver circuit 200 is connected to the gate of the power transistor 110. An output line 206 is connected to the gate of the power transistor 110 via the output pin OUT. In reality, bonding wires, via holes, and wiring (not shown) are connected to the output pin OUT, and these become the parasitic inductor Lp.

[0031] The source pin S is connected to the source of the power transistor 110. The low-side line 204 is connected to the source of the power transistor 110 via the source pin S. The voltage of the low-side line 204 is V Ｓ When the power transistor 110 is a low-side transistor, the voltage V Ｓ is 0V, and when the power transistor 110 is a high-side transistor, the voltage VＳ is a switching voltage that switches between 0 V and the input voltage of the switching circuit 100.

[0032] The high-side line 202 is connected to a high-level voltage V Ｈ A high-level voltage V Ｈ is the voltage V of the low-side line 204 Ｓ This voltage is higher by a predetermined voltage ΔV than the voltage at the output of the power supply.

[0033] The first transistor M1 is a PMOS transistor and is connected between the high-side line 202 and the output line 206. The second transistor M2 is an NMOS transistor and is connected between the output line 206 and the low-side line 204.

[0034] The third transistor M3 is connected in parallel with the second transistor M2 between the output line 206 and the low side line 204.

[0035] When the control signal CTRL is at an ON level, the pre-driver 210 turns on the first transistor M1 and turns off the second transistor M2. When the control signal CTRL is at an OFF level, the pre-driver 210 turns off the first transistor M1 and turns on the second transistor M2.

[0036] When the control signal CTRL transitions from an off level to an on level, the auxiliary circuit 220 turns on the third transistor M3 for a predetermined time T. When the third transistor M3 is turned on, a current I ＳＮＫ is synced.

[0037] The above is the configuration of the switching circuit 100. Next, the operation of the switching circuit 100 will be described. The advantages of the gate driver circuit 200 will become clear when compared with a comparative technology. Therefore, the comparative technology will be described.

[0038] The gate driver circuit according to the comparative technique has a configuration in which the third transistor M3 and the auxiliary circuit 220 are omitted from the gate driver circuit 200 in Fig. 1. The operation of the gate driver circuit according to the comparative technique will be described.

[0039] 2 is a waveform diagram illustrating the operation of the gate driver circuit according to the comparative technique. The waveform diagram illustrates the control signal CTRL, the first transistor M1, the second transistor M2, and the gate voltage V of the power transistor 110. Ｇ is shown.

[0040] Time t ０ Before this, the control signal CTRL is at an off level (low level), the first transistor M1 is off, and the second transistor M2 is on. Since the second transistor M2 is on, the output voltage V Ｇ That is, the gate voltage V of the power transistor 110 Ｇ is the voltage V of the low-side line 204 Ｓ and the gate-source voltage V of the power transistor 110 ＧＳ is 0V, and the power transistor 110 is fixed off.

[0041] Time t ０ When the control signal CTRL transitions from an off level to an on level, the first transistor M1 is turned on and the second transistor M2 is turned off. Ｇ is the high-level voltage V Ｈ rises towards

[0042] The output voltage V rises sharply Ｇ is applied to the parasitic inductor Lp, the gate-source voltage V ＧＳ This causes overshoot, followed by undershoot and ringing. ＧＳ If the overshoot exceeds the breakdown voltage of the power transistor 110, it will be a factor that reduces the reliability of the power transistor 110. In addition, the undershoot will cause the gate-source voltage V ＧＳ is the gate-source threshold voltage V ＧＳ（ｔｈ） If the voltage Vcc is less than 1 V, the power transistor 110 will be turned off. This is the problem that occurs in the gate driver circuit according to the comparative technique. Returning to the embodiment.

[0043] 3 is a waveform diagram illustrating the operation of the switching circuit 100 of FIG. 2. The waveform diagram illustrates the control signal CTRL, the states of the first transistor M1, the second transistor M2, and the third transistor M3, the output voltage V of the gate driver circuit 200, and the output voltage V Ｇ , the sink current I flowing through the third transistor M3 ＳＮＫ In addition, the output voltage V Ｇ The waveform of is shown by a dashed line.

[0044] Time t ０ Before this, the control signal CTRL is at an off level (low level), the first transistor M1 is off, and the second transistor M2 is on. The third transistor M3 is off. Since the second transistor M2 is on, the output voltage V Ｇ That is, the gate voltage V of the power transistor 110 Ｇ is the voltage V of the low-side line 204 Ｓ and the gate-source voltage V of the power transistor 110 ＧＳ is 0V, and the power transistor 110 is fixed off.

[0045] Time t ０ When the control signal CTRL transitions from an off level to an on level, the first transistor M1 is turned on and the second transistor M2 is turned off. Ｇ is the high-level voltage V Ｈ rises towards

[0046] Time t ０ From the above, the delay time τ １ Time t after the lapse of １ Then, the third transistor M3 is turned on, and after a predetermined time τ ２ is in the ON state during the time t ２ The delay time τ １ and a given time τ ２ The combination of lengths can be determined based on the period during which overshoot may occur in the comparison technique.

[0047] During the period when an overshoot may occur, the third transistor M3 is turned on, and a part of the current that is about to flow into the gate of the power transistor 110 is diverted to the third transistor M3 as a sink current I ＳＮＫ and is released to the source of the power transistor 110. As a result, the output voltage V Ｓ The overshoot is suppressed, and the subsequent undershoot and ringing are also suppressed.

[0048] The above is the operation and effect of the gate driver circuit 200.

[0049] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0050] 4 is a circuit diagram showing an example of the configuration of the auxiliary circuit 220. The auxiliary circuit 220 includes a delay circuit 222 and a pulse generator 224. The delay circuit 222 outputs the control signal CTRL for a delay time τ １ The pulse generator 224 receives the delayed control signal CTRLd and delays it for a predetermined time τ ２ and supplies the pulse signal Sp to the gate of the third transistor M3. In this configuration, the high level of the pulse signal Sp is Ｈ is equal to.

[0051] 5 is a circuit diagram showing another example configuration (220A) of the auxiliary circuit 220. The auxiliary circuit 220A includes a buffer 226 in addition to a delay circuit 222 and a pulse generator 224. The buffer 226 receives the pulse signal Sp at its input node, and has an output node connected to the gate of the third transistor M3.

[0052] For example, the buffer 226 is composed of two stages of CMOS inverters 226a and 226b. Each of the CMOS inverters 226a and 226b is composed of a CMOS inverter including a PMOS transistor MP11 and an NMOS transistor MN11. The power supply terminal of the CMOS inverter 226b, i.e., the source of the PMOS transistor MP11, is connected to the output line 206. During the period when the output pulse Sp is generated, the voltage V Ｇ is the high-level voltage V Ｈ It is in the vicinity of .

[0053] The source of the PMOS transistor MP11 may be connected to the high-side line 202.

[0054] 6 is a circuit diagram showing another example (220B) of the auxiliary circuit 220. The level shifter 228 shifts the high level of the pulse signal Sp to a high-level voltage V Ｈ an intermediate level voltage V Ｍ The level-shifted pulse signal Sp'' is supplied to the gate of the third transistor M3.

[0055] In the configuration of FIG. 3 or FIG. 4, the high-level voltage V Ｈ is applied to the gate of the third transistor M3. Therefore, the high-level voltage V Ｈ In applications where the sink current I flows through the third transistor M3, ＳＮＫ 5, the amount of the intermediate level voltage V Ｍ In response to this, a sink current I flows through the third transistor M3. ＳＮＫ The amount of

[0056] 7 is a circuit diagram showing a specific example of the auxiliary circuit 220B of FIG. 6. The level shifter 228 includes a CMOS inverter 228a, a CMOS inverter 228b, and a constant voltage element 228c. A first end of the constant voltage element 228c is connected to the output line 206. The constant voltage element 228c is, for example, a diode. In this example, a so-called diode-connected NMOS transistor with its gate and drain connected is used as the constant voltage element 228c. Note that the constant voltage element 228c may be any element that generates a substantially constant voltage drop, and may be, for example, a resistor.

[0057] The power supply terminal of the CMOS inverter 228b, i.e., the source of the PMOS transistor MP11, is connected to the second terminal of the constant voltage element 229. The second terminal of the constant voltage element 229 is connected to V Ｍ =V Ｇ -V Ｆ An intermediate level voltage of V Ｆ is the voltage drop of the constant voltage element 229, and V Ｈ ≒V Ｇ Therefore, V Ｍ <V Ｈ The output of the CMOS inverter 228b is connected to the gate of the third transistor.

[0058] 8 is a circuit diagram showing a modified example (200D) of the gate driver circuit 200. The gate driver circuit 200D further includes a constant voltage element 230. The constant voltage element 230 may be a MOS transistor with its gate and drain wired together. Note that the constant voltage element 230 may instead be a diode or a resistor.

[0059] By inserting the constant voltage element 230, the sink current I that flows when the third transistor M3 is on is ＳＮＫ can be adjusted.

[0060] 9 is a circuit diagram of a switching circuit 100E including a gate driver circuit 300. The switching circuit 100E includes a high-side transistor 110H, a low-side transistor 110L, a gate driver circuit 300, a bootstrap capacitor C ＢＴ Equipped with.

[0061] The high-side transistor 110H and the low-side transistor 110L are NMOS transistors that form a half-bridge circuit. The high-side transistor 110H is connected between the input line 102 and the switching line 104, and the low-side transistor 110L is connected between the switching line 104 and the ground line 106.

[0062] The gate driver circuit 300 controls the states of the high-side transistor 110H and the low-side transistor 110L to control the electrical state (switching voltage) V ＳＷ It is an IC (Integrated Circuit) that controls the above.

[0063] The gate of the high-side transistor 110H is connected to the high-side gate pin HG of the gate driver circuit 300, and the gate of the low-side transistor 110L is connected to the low-side gate pin LG. The switching pin SW is connected to the switching line 104, and the ground pin GND is connected to the ground line 106. A bootstrap capacitor C is connected between the bootstrap pin BT and the switching pin SW. ＢＴ is connected.

[0064] The gate driver circuit 300 includes a high-side driver 200H that drives the high-side transistor 110H, and a low-side driver 200L that drives the low-side transistor 110L.

[0065] The bootstrap line 302 is connected to the bootstrap pin BT. The switching line 304 is connected to the switching pin SW. The high-side gate line 306 is connected to the high-side gate pin HG. A constant voltage V is applied to the bootstrap line 302 via a rectifying element 310 such as a diode. ＲＥＧ is applied to the rectifying element 310 and the bootstrap capacitor C ＢＴ forms a bootstrap circuit, and a constant voltage V ＲＥＧ bootstrap voltage V ＢＴGenerates.

[0066] The high-side driver 200H drives the high-side transistor 110H based on the high-side control signal CTRLH.

[0067] The power supply line 312 is connected to a power supply voltage V ＤＤ is supplied to the ground line 314, which is connected to the ground pin GND. The low-side gate line 316 is connected to the low-side gate pin LG.

[0068] The low-side driver 200L drives the low-side transistor 110L based on a low-side control signal CTRLL.

[0069] Each of the high-side driver 200H and the low-side driver 200L can be configured with the gate driver circuit 200 described with reference to FIGS.

[0070] For example, the switching circuit 100E may be part of a switching power supply such as a DC / DC converter.

[0071] Alternatively, the switching circuit 100E may be a three-phase inverter, a motor driver, or the like.

[0072] Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims. The scope of the present invention is defined by the claims, and therefore, embodiments, examples, and modifications not described herein are also included in the scope of the present invention.

[0073] (Additional Note) The following techniques are disclosed in this specification.

[0074] a first transistor connected between the high-side line and the output line; a second transistor connected between the output line and the low-side line; a third transistor connected in parallel with the second transistor between the output line and the low-side line; a pre-driver that turns on the first transistor and turns off the second transistor when the control signal is at an on level instructing the power transistor to be on, and turns off the first transistor and turns on the second transistor when the control signal is at an off level instructing the power transistor to be off; and an auxiliary circuit that turns on the third transistor for a predetermined time when the control signal transitions from the off level to the on level.

[0075] (Item 2) The gate driver circuit according to item 1, wherein the auxiliary circuit includes a pulse generator that generates a pulse signal having a pulse width corresponding to the predetermined time.

[0076] (Item 3) The gate driver circuit according to item 2, wherein the high level of the pulse signal is the high-level voltage, and the pulse signal is supplied to the gate of the third transistor.

[0077] (Item 4) The gate driver circuit according to item 2, wherein the auxiliary circuit further includes a buffer having an input that receives the pulse signal and an output that is connected to the gate of the third transistor.

[0078] (Item 5) The gate driver circuit according to item 4, wherein the buffer includes a CMOS inverter having a power supply terminal connected to the output line and an output connected to the gate of the third transistor.

[0079] (Item 6) The gate driver circuit according to item 2, wherein the auxiliary circuit further includes a level shifter that receives the pulse signal at an input, has an output connected to the gate of the third transistor, and level-shifts a high level of the pulse signal to an intermediate level voltage that is lower than the high level voltage.

[0080] (Item 7) The gate driver circuit according to item 6, wherein the level shifter includes: a constant voltage element having a first end connected to the output line; and a CMOS inverter having a power supply terminal connected to a second end of the constant voltage element and an output connected to the gate of the third transistor.

[0081] (Item 8) The gate driver circuit according to any one of items 1 to 7, further comprising a MOS transistor connected between the drain of the third transistor and the output line, the gate and drain of the MOS transistor being wired together.

[0082] (Item 9) The gate driver circuit according to any one of items 1 to 8, wherein the predetermined time is 1 to 20 ns.

[0083] (Item 10) The gate driver circuit according to any one of items 1 to 9, which is monolithically integrated on a single semiconductor substrate.

[0084] (Item 11) A switching circuit comprising: a power transistor; and a gate driver circuit according to any one of items 1 to 10 that drives the power transistor.

[0085] The present disclosure relates to gate driver circuits.

[0086] 100 Switching circuit 110 Power transistor 110H High-side transistor 110L Low-side transistor 102 Input line 104 Switching line 106 Ground line C ＢＴBootstrap capacitor 200 Gate driver circuit 200H High-side driver 200L Low-side driver CTRL Control signal M1 First transistor M2 Second transistor M3 Third transistor 202 High-side line 204 Low-side line 206 Output line OUT Output pin 210 Pre-driver 220 Auxiliary circuit 222 Delay circuit 224 Pulse generator 226 Buffer 228 Level shifter 228a CMOS inverter 228c Constant voltage element 228b CMOS inverter 229 Constant voltage element 300 Switching circuit 302 Bootstrap line 304 Switching line 306 High-side gate line 310 Rectifying element 312 Power supply line 314 Ground line 316 Low-side gate line 316

Claims

1. A gate driver circuit that drives an N-type power transistor based on a control signal, comprising: a low side line connected to a source of the power transistor; an output line connected to a gate of the power transistor; a high side line generating a high level voltage higher than the voltage of the low side line; a first transistor connected between the high side line and the output line; a second transistor connected between the output line and the low side line; a third transistor connected in parallel with the second transistor between the output line and the low side line; a pre-driver that turns on the first transistor and turns off the second transistor when the control signal is at an on level instructing the power transistor to be on, and turns off the first transistor and turns on the second transistor when the control signal is at an off level instructing the power transistor to be off; and an auxiliary circuit that turns on the third transistor for a predetermined time when the control signal transitions from the off level to the on level.

2. The gate driver circuit of claim 1, wherein the auxiliary circuit includes a pulse generator that generates a pulse signal having a pulse width corresponding to the predetermined time.

3. The gate driver circuit of claim 2, wherein the high level of the pulse signal is the high level voltage, and the pulse signal is supplied to the gate of the third transistor.

4. The gate driver circuit of claim 2, wherein the auxiliary circuit further includes a buffer having an input receiving the pulse signal and an output connected to the gate of the third transistor.

5. The gate driver circuit of claim 4, wherein the buffer includes a CMOS inverter having a power supply terminal connected to the output line and an output connected to the gate of the third transistor.

6. The gate driver circuit according to claim 2, wherein the auxiliary circuit further includes a level shifter having an input receiving the pulse signal and an output connected to the gate of the third transistor, the level shifter shifting a high level of the pulse signal to an intermediate level voltage lower than the high level voltage.

7. The gate driver circuit according to claim 6, wherein the level shifter includes: a constant voltage element having a first end connected to the output line; and a CMOS inverter having a power supply terminal connected to a second end of the constant voltage element and an output connected to the gate of the third transistor.

8. The gate driver circuit according to claim 1, further comprising a MOS transistor connected between the drain of the third transistor and the output line, the gate and drain of the MOS transistor being connected together.

9. The gate driver circuit according to claim 1, wherein the predetermined time is 1 to 20 ns.

10. The gate driver circuit according to any one of claims 1 to 7, which is monolithically integrated on a single semiconductor substrate.

11. A switching circuit comprising: a power transistor; and a gate driver circuit according to any one of claims 1 to 7 that drives the power transistor.

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