Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that comprises a semiconductor substrate having an upper surface and a lower surface, and that has a diode part provided on the semiconductor substrate. The diode part includes first cathode regions of a first conductivity type and second cathode regions of a second conductivity type, and the first cathode regions and the second cathode regions are repeatedly provided in a first direction. The repetition pitch of the first cathode regions and the second cathode regions in the first direction is 40-200 μm, and the ratio of the area of the second cathode regions to the sum of the areas of the first cathode regions and the second cathode regions is 0.1-0.8.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, a structure in which N-type and P-type regions are mixed as the cathode region of a diode has been known (see, for example, Patent Documents 1 and 2). Patent Document 1: JP 2019-091857 A Patent Document 2: JP 2022-015861 A Problem to be solved

[0003] In a semiconductor device, it is preferable to arrange N-type and P-type cathode regions so as to have predetermined characteristics. General disclosure

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device including a semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate being provided with a diode section. In the semiconductor device, the diode section may include a drift region of a first conductivity type provided in the semiconductor substrate. In any of the semiconductor devices, the diode section may include a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. In any of the semiconductor devices, the diode section may include a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate. In any of the semiconductor devices, the first cathode region and the second cathode region may be repeatedly provided in a first direction, and the repetition pitch of the first cathode region and the second cathode region in the first direction may be 40 μm or more and 200 μm or less. In any of the above semiconductor devices, the ratio of the area of ​​the second cathode region to the sum of the areas of the first cathode region and the second cathode region may be 0.1 or more and 0.8 or less.

[0005] In any of the above semiconductor devices, the repeat pitch may be not less than 80 μm and not more than 160 μm.

[0006] In any of the above semiconductor devices, the area ratio may be 0.6 or less.

[0007] In any of the above semiconductor devices, the first cathode region and the second cathode region may each have a longitudinal direction different from the first direction. In any of the above semiconductor devices, the area ratio may be 0.5 or less.

[0008] In any of the above semiconductor devices, the first cathode region and the second cathode region may be repeatedly arranged in a second direction different from the first direction. In any of the above semiconductor devices, the area ratio may be 0.6 or less.

[0009] In any of the above semiconductor devices, the repeat pitch may be 100 μm or more and 130 μm or less.

[0010] In any of the above semiconductor devices, the repeat pitch may be 40 μm or more and 80 μm or less.

[0011] In any of the semiconductor devices described above, the diode section may have an anode region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, a dose of dopant ions in the anode region may be 5.0×10 １２ / cm ２ That's it, 5.0 x 10 １３ / cm ２ It may be the following:

[0012] In any of the above semiconductor devices, the dose of dopant ions in the second cathode region is 1.0×10 １３ / cm ２ That's it, 1.0 x 10 １４ / cm ２ It may be the following:

[0013] In any of the above semiconductor devices, a transistor section connected in anti-parallel to the diode section may be provided on the semiconductor substrate.

[0014] In any of the above semiconductor devices, the transistor portion may have a collector region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate, and the doping concentration of the second cathode region may be the same as the doping concentration of the collector region.

[0015] In any of the above semiconductor devices, the diode section may have an anode region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the transistor section may have an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the transistor section may have the drift region. In any of the above semiconductor devices, the transistor section may have a base region of a second conductivity type provided between the emitter region and the drift region. In any of the above semiconductor devices, the doping concentration of the anode region and the doping concentration of the base region may be the same.

[0016] In any of the above semiconductor devices, a carrier lifetime in the drift region of the diode portion may be 1 μs or more.

[0017] A second aspect of the present invention provides a method for manufacturing a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface and a first conductivity type drift region, the semiconductor substrate being provided with a diode portion. The manufacturing method may include forming a first cathode region of the first conductivity type in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, and a second cathode region of the second conductivity type in contact with the lower surface of the semiconductor substrate. In any of the manufacturing methods, the first cathode region and the second cathode region may be repeatedly formed in a first direction, with a repetition pitch of the first cathode region and the second cathode region in the first direction being 40 μm or more and 200 μm or less. In any of the manufacturing methods, the first cathode region and the second cathode region may be formed such that the area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region is 0.1 or more and 0.8 or less.

[0018] In any of the above manufacturing methods, the semiconductor device may include a transistor section provided on the semiconductor substrate and connected in anti-parallel to the diode section. In any of the above manufacturing methods, the transistor section may have a collector region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate. In any of the above manufacturing methods, the collector region may be formed in a common process with the second cathode region.

[0019] In any of the above manufacturing methods, the semiconductor device may include a transistor section provided on the semiconductor substrate and connected in anti-parallel to the diode section. In any of the above manufacturing methods, the diode section may include an anode region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above manufacturing methods, the transistor section may include an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above manufacturing methods, the transistor section may include the drift region. In any of the above manufacturing methods, the transistor section may include a base region of a second conductivity type provided between the emitter region and the drift region. In any of the above manufacturing methods, the anode region and the base region may be formed in a common process.

[0020] In any of the above manufacturing methods, the diode section may have a second conductivity type anode region provided in contact with the upper surface of the semiconductor substrate. In any of the above manufacturing methods, an initial value of a design value of a doping concentration of the anode region may be set. In any of the above manufacturing methods, a forward voltage-reverse recovery loss characteristic of the diode section when the initial value is used may be obtained for a plurality of the repetition pitches. In any of the above manufacturing methods, the design value of the doping concentration of the anode region may be adjusted based on a plurality of the forward voltage-reverse recovery loss characteristics for a plurality of the repetition pitches.

[0021] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0022] 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. It is an enlarged view of region D in FIG. 1. It is a diagram showing an example of a cross section taken along line e-e in FIG. 2. It is a diagram showing an example of an arrangement of first cathode regions 81 and second cathode regions 82 on the lower surface 23 of the semiconductor substrate 10. It is a diagram showing another example of an arrangement of the first cathode regions 81 and second cathode regions 82 in one cathode region 83. It is a diagram showing another example of an arrangement of the first cathode regions 81 and second cathode regions 82 in one cathode region 83. It is a diagram showing another example of an arrangement of the first cathode regions 81 and second cathode regions 82 in one diode section 80. It is a diagram showing another example of an arrangement of the first cathode regions 81 and second cathode regions 82 in one cathode region 83. It is a diagram showing another example of an arrangement of the first cathode regions 81 and second cathode regions 82 in one cathode region 83. 1 is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one diode section 80. FIG. 2 is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. FIG. 3 is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. FIG. 4 is a diagram showing the relationship between the area ratio R and the forward voltage of the diode section 80. FIG. 5 is a diagram showing the relationship between the forward voltage and reverse recovery loss with respect to the area ratio R. FIG. 6 is a diagram showing the relationship between the forward voltage and reverse recovery loss with respect to the length Y2 of the second cathode region 82 in the first direction. FIG. 7 shows the relationship between the area ratio R and the magnitude of the variation in forward voltage due to the variation in patterning in the manufacturing process. FIG. 8 shows the relationship between the length Y2 of the second cathode region 82 with respect to the magnitude of the variation in forward voltage due to the variation in patterning in the manufacturing process. 1 shows the relationship between the magnitude of variation in forward voltage and the area ratio R when the patterning variation is ±0.2 μm. 2 shows the relationship between the magnitude of variation in forward voltage and the length Y2 of the second cathode region 82 when the patterning variation is ±0.2 μm. 3 shows another example of the relationship between the area ratio R and the forward voltage of the diode section 80. 4 shows the anode voltage-anode current characteristics of the diode section 80.10 is a diagram showing another example of the anode voltage-anode current characteristics of the diode section 80. FIG. 11 is a diagram showing the relationship between the length Y2 of the second cathode region 82 and the forward voltage. FIG. 12 is a diagram showing the relationship between the length Y2 of the second cathode region 82 and the forward voltage. FIG. 13 is a diagram explaining a manufacturing method of the semiconductor device 100. FIG. 14 is a diagram explaining an example of the design stage S1002.

[0023] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0025] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0026] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0027] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0028] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0030] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0031] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, in which a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as a donor that supplies electrons. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, an interstitial Si—H in a silicon semiconductor, in which an interstitial silicon (Si-i) is bonded to hydrogen, or a CiOi-H in which an interstitial carbon (Ci) is bonded to interstitial oxygen (Oi) and hydrogen, also functions as a donor that supplies electrons. In this specification, a VOH defect, CiOi-H, or interstitial Si—H may be referred to as a hydrogen donor.

[0032] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants contained substantially uniformly in the ingot that is the base of the semiconductor substrate when the ingot is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors include, but are not limited to, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donors are phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 １７ ~7 x 10 １７ / cm ３ The oxygen concentration in the substrate manufactured by the FZ method is 1×10 １５ ~5 x 10 １６ / cm ３ The higher the oxygen concentration, the more likely it is that hydrogen donors are generated. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or may be a value between 90% and 100% of the chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 １０ / cm ３ That's it, 5 x 10 １２ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 １１ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 １２ / cm ３ The concentrations in the present invention may be values ​​at room temperature, for example, values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0033] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0034] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0035] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0036] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0037] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. The semiconductor substrate may be silicon, silicon carbide, gallium nitride, diamond, or gallium oxide.

[0038] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0039] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0040] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0041] The active section 160 is provided with a diode section 80 including a diode element such as a free wheel diode (FWD). The active section 160 may further be provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). In the example of FIG. 1 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT). The transistor section 70 and the diode section 80 are connected in anti-parallel to each other. That is, the emitter of the transistor section 70 and the anode of the diode section 80 are electrically connected, and the collector of the transistor section 70 and the cathode of the diode section 80 are electrically connected.

[0042] In FIG. 1 , the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1 ). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0043] The diode section 80 has an N+ type first cathode region and a P+ type second cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, a repeating structure including the first cathode region and the second cathode region is periodically arranged in a predetermined direction on the lower surface of the semiconductor substrate 10. The region in which the first cathode region or the second cathode region is arranged is referred to as the diode section 80. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the diode section 80.

[0044] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0045] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0046] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0047] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0048] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0049] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0050] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0051] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 extends in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y axis direction. When the active section 160 is divided by the active side gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X axis direction in each divided region.

[0052] The semiconductor device 100 may include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) which simulates the operation of a transistor section provided in the active section 160.

[0053] In the present example, the semiconductor device 100 includes an edge termination structure 150 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 150 in the present example is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 150 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 150 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0054] 2 is an enlarged view of region D in FIG. 1 . Region D includes a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0055] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0056] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0057] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0058] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0059] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0060] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0061] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0062] At least a portion of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0063] In the transistor section 70, the dummy trench section 30 is provided between each of the linear portions 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the linear portions 39. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have a linear section 29 and a tip section 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both linear dummy trench sections 30 without tip sections 31 and dummy trench sections 30 with tip sections 31.

[0064] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0065] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0066] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e located at one end of each mesa portion in the extension direction, a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 may be provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0067] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0068] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0069] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction of the trench portion (Y-axis direction). For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0070] The mesa portion 61 of the diode section 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0071] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact region 15 does not have to be provided in the diode portion 80. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0072] In the diode section 80, a cathode region 83 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. The cathode region 83 is a region in which N+ type first cathode regions and P+ type second cathode regions are periodically arranged. In FIG. 2, the first cathode region and the second cathode region are omitted. In the region of the lower surface of the semiconductor substrate 10 where the cathode region 83 is not provided, a P+ type collector region 22 may be provided. The cathode region 83 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. The cathode region 83 and the collector region 22 may contact the lower surface 23 of the semiconductor substrate 10. In FIG. 2, a boundary 90 between the cathode region 83 and the collector region 22 is indicated by a dotted line.

[0073] The boundary 90 may coincide with the boundary between the transistor portion 70 and the diode portion 80 in a top view seen from the upper surface 21. The position of the boundary 90 may be the boundary between the transistor portion 70 and the diode portion 80, determined based on the structure of the upper surface 21 side of the semiconductor substrate 10. The boundary 90 in the X-axis direction may be located in a trench portion between the mesa portion 60 of the transistor portion 70 that is located closest to the diode portion 80 and the mesa portion 61 of the diode portion 80 that is located closest to the transistor portion 70. The boundary 90 in the X-axis direction may be the center position of the trench in the X-axis direction. The trench may be the trench closest to the diode portion 80 among the trench portions that contact the emitter region 12.

[0074] In a top view seen from the upper surface 21, the boundary 90 in the Y-axis direction may be located more inward (in this example, on the +Y-axis direction side) than the end in the Y-axis direction of the contact hole 54 provided in the diode section 80, and may be located so as to overlap with the base region 14 exposed at the upper surface 21. In a top view seen from the upper surface 21, the distance from the end in the Y-axis direction of the contact hole 54 provided in the diode section 80 to the boundary 90 in the Y-axis direction may be equal to or greater than a length equivalent to half the thickness of the semiconductor substrate 10, may be equal to or greater than a length equivalent to 75% of the thickness of the semiconductor substrate 10, or may be equal to or greater than a length equivalent to the thickness of the semiconductor substrate 10.

[0075] The first cathode region included in the cathode region 83 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the N+ type first cathode region and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the first cathode region in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the first cathode region in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0076] 3 is a diagram showing an example of the e-e cross section in FIG. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 83. The cathode region 83 has an N+ type first cathode region 81 and a P+ type second cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0077] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact holes 54 described with reference to FIG. 2 .

[0078] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0079] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0080] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0081] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0082] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0083] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0084] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. The base region 14 of the diode portion 80 functions as the anode region of the diode portion 80. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 61.

[0085] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0086] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the collector region 22 and the cathode region 83.

[0087] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0088] In the diode section 80, a first cathode region 81 and a second cathode region 82 are provided below the buffer region 20. In the example of FIG. 3 , the first cathode region 81 is in contact with the collector region 22, but the second cathode region 82 may be in contact with the collector region 22.

[0089] The donor concentration of the first cathode region 81 is higher than the donor concentration of the drift region 18. The donor of the first cathode region 81 is, for example, arsenic, hydrogen, or phosphorus. The acceptor of the second cathode region 82 is, for example, boron, indium, or aluminum. The acceptor concentration of the second cathode region 82 may be higher than the acceptor concentration of the base region 14. The acceptor concentration of the second cathode region 82 may be the same as or different from that of the acceptor region of the collector region 22. Note that the elements that serve as the donor and acceptor in each region are not limited to the above-mentioned examples.

[0090] When the second cathode region 82 and the collector region 22 have the same acceptor concentration and are in contact with each other, the trench portion between the mesa portion 60 in which the emitter region 12 is disposed and the mesa portion 61 in which the emitter region 12 is not disposed may be the boundary position between the second cathode region 82 and the collector region 22. More specifically, the center position of the trench portion in the X-axis direction may be the boundary position between the second cathode region 82 and the collector region 22.

[0091] The collector region 22 and the cathode region 83 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0092] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions.

[0093] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 83 and the collector region 22.

[0094] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0095] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0096] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0097] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0098] By including the second cathode region 82 in the diode section 80, holes in the drift region 18 and the like can be extracted via the second cathode region 82. This suppresses the accumulation of holes in the diode section 80 in the on-state, reducing loss during reverse recovery. Furthermore, by providing the second cathode region 82, the forward voltage of the diode section 80 in the on-state changes. By adjusting the arrangement of the first cathode region 81 and the second cathode region 82, characteristics such as reverse recovery loss and forward voltage can be adjusted.

[0099] 4A is a diagram showing an example of the arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. FIG. 4A shows an example of the arrangement of the first cathode region 81 and the second cathode region 82 in one diode section 80. All of the diode sections 80 may have the arrangement shown in FIG. 4A. FIG. 4A also shows the collector region 22 around the diode section 80. Furthermore, the position of one of the contact holes 54 provided in the upper surface 21 is shown by a dotted line.

[0100] In this example, the first cathode region 81 and the second cathode region 82 are repeatedly arranged in a first direction. In the example of FIG. 4A , the first direction is the Y-axis direction. A structure of the first cathode region 81 and the second cathode region 82 repeated in the first direction is referred to as a repeating structure 85. For example, the repeating structure 85 includes only one set of the first cathode region 81 and the second cathode region 82 arranged alternately in the first direction. In the diode section 80, at least two repeating structures 85 are arranged in contact with each other in the first direction. When the first cathode region 81 and the second cathode region 82 are repeatedly arranged in multiple directions, at least two repeating structures 85 are arranged in contact with each other in each direction in the diode section 80.

[0101] In this example, the length of the first cathode region 81 included in the repeating structure 85 in the X-axis direction is greater than the length of the Y-axis direction. The length of the second cathode region 82 included in the repeating structure 85 in the X-axis direction is also greater than the length of the Y-axis direction.

[0102] The length of one cathode region 83 in the X-axis direction is defined as Xa, and the length of one repeating structure 85 in the Y-axis direction is defined as Ya. The length of one repeating structure 85 in the X-axis direction is defined as Xr, and the length of one repeating structure 85 in the Y-axis direction is defined as Yr. In this specification, the length of the repeating structure 85 (Yr in this example) in the direction in which the first cathode region 81 and the second cathode region 82 are repeatedly arranged (the Y-axis direction in FIG. 4A ) is referred to as the repeat pitch P of the first cathode region 81 and the second cathode region 82. When the first cathode region 81 and the second cathode region 82 are repeatedly arranged in multiple directions, the length of the repeating structure 85 in each direction is defined as the repeat pitch P. When multiple repeating structures 85 with different lengths exist in one direction, the average length of the multiple repeating structures 85 in that direction may be defined as the repeat pitch P.

[0103] Furthermore, the area of ​​the first cathode region 81 included in one repeating structure 85 is defined as S1, and the area of ​​the second cathode region 82 is defined as S2. In this specification, the ratio (S2 / (S1+S2)) of the area of ​​the second cathode region 82 to the sum (S1+S2) of the areas of the first cathode region 81 and the second cathode region 82 included in one repeating structure 85 is defined as the area ratio R. When there are multiple repeating structures 85 with different area ratios, the average value of the area ratios of the multiple repeating structures 85 included in the cathode region 83 may be defined as the area ratio R.

[0104] 4A, the first cathode region 81 and the second cathode region 82 are repeatedly arranged in the Y-axis direction. When both the first cathode region 81 and the second cathode region 82 are continuously provided from one end to the other end of the cathode region 83 in the X-axis direction, the length Xa of the cathode region 83 in the X-axis direction is defined as the length Xr of the repeating structure 85 in the X-axis direction.

[0105] The cathode region 83 may have a margin region 84. The margin region 84 is a region from the boundary 90 to the first cathode region 81. The margin region 84 may be of the same conductivity type as the second cathode region 82. The margin region 84 may have the same doping concentration distribution as the second cathode region 82. The length of the margin region 84 in the X-axis direction is set to Xm, and the length of the margin region 84 in the Y-axis direction is set to Ym.

[0106] 4A , when the length in the X-axis direction of one of the first cathode region 81 and the second cathode region 82 is shorter than the length Xa in the X-axis direction of the cathode region 83, the length Xr in the X-axis direction of the repeating structure 85 is set to be the same as the shorter length in the X-axis direction of the first cathode region 81 or the second cathode region 82. In the example of FIG. 4A , the length X2 of the second cathode region 82 is shorter than the length Xa of the cathode region 83. In this case, the length X2 of the second cathode region 82 is set to the length Xr of the repeating structure 85.

[0107] In this example, the length Yr of the repeating structure 85 in the Y-axis direction is the sum of the length Y1 of one first cathode region 81 in the Y-axis direction and the length Y2 of one second cathode region 82 in the Y-axis direction. The repeating pitch P in this example is Y1 + Y2. The area ratio R is S2 / (S1 + S2) = Y2 / (Y1 + Y2). By adjusting the repeating pitch P and the area ratio R within a predetermined range, characteristics such as forward voltage and reverse recovery loss can be adjusted. The ranges within which the repeating pitch P and the area ratio R should be adjusted will be described later.

[0108] The first cathode regions 81 having a length Xe may be disposed in contact with both ends of the second cathode region 82 in the X-axis direction. The length Xe is 0 μm or greater. The length Xe may be smaller than the length Xr, smaller than the length Y1, or smaller than the length Y2. The length Xe may be 1 time or greater, 2 times or greater, 5 times or greater, 10 times or greater, or 20 times or greater than the width of the mesa portion 61 in the X-axis direction. The length Xe may be 50 times or less, or 30 times or less than the width of the mesa portion 61 in the X-axis direction. By having the first cathode regions 81 having the length Xe in contact with both ends of the second cathode region 82, electrical interference due to hole inflow between the diode portion 80 and the transistor portion 70 can be suppressed.

[0109] The length in the Y-axis direction of the first cathode region 81 or the second cathode region 82 arranged at both ends of the cathode region 83 in the Y-axis direction is defined as Ye. In the example of FIG. 4A , the first cathode region 81 is arranged at both ends of the cathode region 83. The length Ye is 0 μm or more. The length Ye may be smaller than the length Yr, may be smaller than the length Y1, or may be smaller than the length Y2. By having the first cathode region 81 or the second cathode region 82 of length Ye at both ends of the cathode region 83, the movement of carriers at the ends of the diode section 80 in the Y-axis direction can be made relatively uniform.

[0110] The length F is the length by which the contact hole 54 protrudes beyond the boundary 90 in the Y-axis direction. The length F is 0 μm or more. The length F may be smaller than the length Yr, the length Y1, or the length Y2. By having the length F, it is possible to suppress carrier concentration at the end of the contact hole 54 in the Y-axis direction.

[0111] In a top view of the first cathode region 81, the corner closest to the transistor unit 70 in the X-axis direction and located outermost in the Y-axis direction may have a chamfered chamfered portion 91. The chamfered portion 91 may be a region in which the width of the first cathode region 81 in the Y-axis direction decreases as the chamfered portion 91 approaches the transistor unit 70. A margin region 84 or a second cathode region 82 may be provided in place of the first cathode region 81 at the corner of the first cathode region 81 chamfered by the chamfered portion 91. In this example, the portion indicated by the dashed line at the corner may be the chamfered portion 91, which may serve as the boundary between the first cathode region 81 and the margin region 84. This has the effect of preventing electron current from concentrating at the corner of the first cathode region 81 during reverse recovery.

[0112] FIG. 4B is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. In this example, the first cathode region 81 and the second cathode region 82 in FIG. 4A are interchanged. In this example, the repeat pitch P is Y1 + Y2, and the area ratio R is S2 / (S1 + S2) = Y2 / (Y1 + Y2). Furthermore, the lengths Xe, Ye, and F may be the same as or different from those in the example of FIG. 4A. A margin region 84 may or may not be provided. In this example, the length Xm and the length Ym of the margin region 84 are both zero.

[0113] FIG. 4C is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. FIG. 4C differs from FIG. 4A in that the first cathode region 81 and the second cathode region 82 are arranged repeatedly in the X-axis direction with the Y-axis direction as the longitudinal direction. Various dimensions, repetition pitch P, area ratio R, etc. may be the same as those in FIG. 4A. However, lengths X1, X2, and Xr in the example of FIG. 4C correspond to lengths Y1, Y2, and Yr in the example of FIG. 4A. Furthermore, lengths Y2 and Yr in the example of FIG. 4C correspond to lengths X2 and Xr in the example of FIG. 4A.

[0114] FIG. 5A is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one diode section 80. In this example, the first cathode region 81 and the second cathode region 82 are repeatedly arranged in multiple directions. In the example of FIG. 5A , the multiple directions are the X-axis direction and the Y-axis direction. In this example, the structure of the first cathode region 81 and the second cathode region 82 repeated in both the X-axis direction and the Y-axis direction is referred to as a repeating structure 85. In the diode section 80, at least two repeating structures 85 are arranged in contact with each other in the X-axis direction, and at least two repeating structures 85 are also arranged in contact with each other in the Y-axis direction. For example, the repeating structure 85 has a rectangular shape that includes only one set of the first cathode region 81 and the second cathode region 82 arranged alternately in the X-axis direction and only one set of the first cathode region 81 and the second cathode region 82 arranged alternately in the Y-axis direction.

[0115] In this example, rectangular second cathode regions 82 are arranged at predetermined intervals in both the X-axis direction and the Y-axis direction inside the cathode region 83. In the cathode region 83, the region other than the second cathode regions 82 is the first cathode region 81.

[0116] The length of one second cathode region 82 in the X-axis direction is defined as X2, and the length of one second cathode region 82 in the Y-axis direction is defined as Y2. The length of one first cathode region 81 sandwiched between two second cathode regions 82 in the X-axis direction is defined as X1. The length of one first cathode region 81 sandwiched between two second cathode regions 82 in the Y-axis direction is defined as Y1.

[0117] In this example, the length Xr of the repeat structure 85 in the X-axis direction is X1 + X2, and the length Yr of the repeat structure 85 in the Y-axis direction is Y1 + Y2. The first cathode region 81 and the second cathode region 82 in this example are arranged at a repeat pitch Px = Xr in the X-axis direction and at a repeat pitch Py = Yr in the Y-axis direction. When a range or value of the repeat pitch is described in this specification, at least one of the repeat pitch Px and the repeat pitch Py may have the range or value, or both the repeat pitch Px and the repeat pitch Py may have the range or value. Furthermore, the repeat pitches Px and Py may have the same value. The area ratio R in this example is (X2 × Y2) / (Xr × Yr) = (X2 × Y2) / ((X1 + X2) × (Y1 + Y2)).

[0118] The lengths Xe, Ye, and F may be the same as or different from those in the example of Figure 4A. The length Xe in this example may be equal to or greater than X2 / 2 and equal to or less than X1 / 2. The length Ye in this example may be equal to or greater than Y2 / 2 and equal to or less than Y1 / 2.

[0119] FIG. 5B is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. In this example, the first cathode region 81 and the second cathode region 82 in FIG. 5A are interchanged. In this example, the repeat pitch Px is X1+X2, and the repeat pitch Py is Y1+Y2. The area ratio R is 1-((X1×Y1) / (Xr×Yr))=1-((X1×Y1) / ((X1+X2)×(Y1+Y2))). Furthermore, the lengths Xe, Ye, and F may be the same as or different from those in the example of FIG. 5A. The length Xe in this example may be equal to or greater than X2 / 2 and equal to or less than X1 / 2. The length Ye in this example may be equal to or greater than Y2 / 2 and equal to or less than Y1 / 2.

[0120] FIG. 5C is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. In this example, the second cathode region 82 in FIG. 5A is closer to the transistor section 70 than the first cathode region 81 in the X-axis direction and protrudes further outward than the first cathode region 81 in the Y-axis direction. This differs from FIG. 5A in that the first cathode region 81 does not have corners. The rest of the example may be the same as FIG. 5A . All ends of the first cathode region 81 in the X-axis direction may be located inside the ends of the second cathode region 82. All ends of the first cathode region 81 in the Y-axis direction may be located inside the ends of the second cathode region 82. The term "inner" refers to the side closer to the center of the cathode region 83.

[0121] In this example, the second cathode region 82 protrudes from the end of the first cathode region 81 by a length Xe in the X-axis direction and by a length Ye in the Y-axis direction. The length Xe may be equal to or less than half, or may be equal to or less than one-quarter, of the length X2 of the second cathode region 82. The length Xe may be equal to or more than one-tenth of the length X2. The length Ye may be equal to or less than half, or may be equal to or less than one-quarter of the length Y2 of the second cathode region 82. The length Ye may be equal to or more than one-tenth of the length Y2.

[0122] 5C , the repeating structure 85 arranged on the outside and the repeating structure 85 arranged on the inside may have different structures. More specifically, the repeating structure 85 including the end of the first cathode region 81 has a different arrangement pattern of the first cathode region 81 compared to the other repeating structures 85. In this example, the repeating structure 85 may be determined based on the pattern of the second cathode region 82 and the region other than the second cathode region 82 (the margin region 84 and the first cathode region 81). In other words, when determining the repeating structure 85, the margin region 84 may be treated as the first cathode region 81.

[0123] The portion of the second cathode region 82 that protrudes outward beyond the end of the first cathode region 81 may be treated as the collector region 22. This portion may have the same doping concentration as the collector region 22.

[0124] 6A is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one diode section 80. In this example, the shape of the second cathode region 82 is different from the example in FIG. 5A. The other structures are the same as those in FIG. 5A. The shape of the second cathode region 82 in this example is circular. Note that the shape of the second cathode region 82 is not limited to rectangular or circular.

[0125] The radius of one second cathode region 82 is defined as R2. In the X-axis direction, the minimum length of the first cathode region 81 sandwiched between the second cathode regions 82 is defined as X1. In the Y-axis direction, the minimum length of the first cathode region 81 sandwiched between the second cathode regions 82 is defined as Y1.

[0126] In this example, the length Xr of the repeating structure 85 in the X-axis direction is X1 + 2 × R2, and the length Yr of the repeating structure 85 in the Y-axis direction is Y1 + 2 × R2. The first cathode region 81 and the second cathode region 82 in this example are arranged at a repeat pitch Px = Xr in the X-axis direction, and at a repeat pitch Py = Yr in the Y-axis direction. The area ratio R in this example is (π × R2 ２ ) / (Xr × Yr) = (π × R2 ２ ) / ((2×R2+X1)×(2×R2+Y1)).

[0127] The lengths Xe, Ye, and F may be the same as or different from those in the example of Figure 5A. The length Xe in this example may be equal to or greater than X1 and equal to or less than R2. The length Ye in this example may be equal to or greater than Y1 and equal to or less than R2.

[0128] FIG. 6B is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. In this example, the first cathode region 81 and the second cathode region 82 in FIG. 6A are interchanged. The radius of the first cathode region 81 is R1. In this example, the repeat pitch Px is X2+2×R1, and the repeat pitch Py is Y2+2×R1. The area ratio R is expressed as 1-(π×R1 ２ ) / (Xr × Yr) = 1 - (π × R1 ２ ) / ((2×R1+X2)×(2×R1+Y2)). Additionally, lengths Xe, Ye, and F may be the same as or different from those in the example of FIG. 6A. In this example, length Xe may be equal to or greater than X2 / 2 and equal to or less than R1. In this example, length Ye may be equal to or greater than Y2 / 2 and equal to or less than R1.

[0129] FIG. 6C is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 in one cathode region 83. In this example, the second cathode region 82 in FIG. 6A is closer to the transistor section 70 than the first cathode region 81 in the X-axis direction and protrudes further outward than the first cathode region 81 in the Y-axis direction. This differs from FIG. 6A in that the first cathode region 81 does not have corners. The rest of the example may be the same as FIG. 6A. The arrangement of the end of the first cathode region 81 may be the same as in the example of FIG. 5C. Furthermore, the determination of the repeating structure 85 may also be the same as in the example of FIG. 5C.

[0130] 5A, 5B, 5C, 6A, 6B, and 6C, the repeating structures 85 are periodically arranged along a square lattice (or rectangular lattice), but are not limited thereto. The repeating structures 85 may be periodically arranged along a triangular lattice or a honeycomb lattice.

[0131] FIG. 7 shows the relationship between the area ratio R and the forward voltage of the diode section 80. The forward voltage is normalized with the voltage when R = 0 being 1. In other figures, the forward voltage may also be normalized in a similar manner. FIG. 7 shows the characteristics of each sample in the example shown in FIG. 4A when the repeat pitch P is 10 μm, 20 μm, 40 μm, 80 μm, 160 μm, 320 μm, or 640 μm. Note that the example shown in FIG. 4B also has similar characteristics.

[0132] As the area ratio R increases, the area of ​​the second cathode region 82 increases. This increases the number of holes extracted from the cathode region 83 when the diode section 80 is in the on state, increasing the on-resistance of the diode section 80. Therefore, as the area ratio R increases, the forward voltage increases. In particular, when the area ratio R exceeds 0.8, the forward voltage increases rapidly. For this reason, the area ratio R is preferably 0.8 or less. The area ratio R may be 0.7 or less, or may be 0.6 or less. Furthermore, if the second cathode region 82 is too small, the effect of reducing reverse recovery loss is reduced. The area ratio R is preferably 0.1 or more. The area ratio R may be 0.15 or more, or may be 0.2 or more.

[0133] As shown in Figure 7, as the repeat pitch P increases from 10 μm to 80 μm, the forward voltage tends to decrease. When the repeat pitch P is small, the length Y1 of the first cathode region 81 also becomes relatively small. When the length Y1 of the first cathode region 81 is small, the distance between the holes present above the first cathode region 81 and the second cathode region 82 cannot be secured, and the holes present above the first cathode region 81 are easily extracted by the second cathode region 82. This makes it difficult for the diode section 80 to turn on, and the forward voltage increases. It is believed that as the repeat pitch P increases, the diode section 80 becomes easier to turn on, and the forward voltage decreases.

[0134] On the other hand, when the repeat pitch P increases from 160 μm to 640 μm, the forward voltage tends to increase. When the repeat pitch P is relatively small, the length Y2 of the second cathode region 82 is also relatively small, so that electrons injected from the first cathode region 81 tend to flow around the entire second cathode region 82 when the diode section 80 is turned on. Therefore, the region above the second cathode region 82 also functions as a diode. When the repeat pitch P increases to a certain extent, a region above the second cathode region 82 is created where electrons from the first cathode region 81 cannot flow around. Therefore, a portion of the region above the second cathode region 82 no longer functions as a diode. As the repeat pitch P increases, the region that does not function as a diode also increases, resulting in an increase in the forward voltage. Therefore, as shown in FIG. 7 , when the repeat pitch P increases from 160 μm to 640 μm, the forward voltage is thought to increase.

[0135] As described above, the forward voltage decreases as the repeat pitch P increases from 10 μm to 80 μm, and increases as the repeat pitch P increases from 160 μm to 640 μm. Therefore, the forward voltage is relatively stable when the repeat pitch P is in the range of 40 μm or more and 200 μm or less. When the repeat pitch P is in the range of 40 μm or more and 200 μm or less, when the carrier lifetime is relatively long (1 μs or more), a balance is achieved between the effect of appropriately maintaining the concentration of minority carriers (holes in this example) in the drift region 18 from the first cathode region 81 to the upper surface 21 side and the effect of reducing the carrier concentration due to shorting of minority carriers in the second cathode region 82. As a result, the forward voltage is considered to be appropriate and relatively stable. The repeat pitch P is preferably in the range of 40 μm or more and 200 μm or less. By setting the repeat pitch P to be 40 μm or more and 200 μm or less, it is possible to suppress variations in the forward voltage due to manufacturing variations in the repeat pitch P. Then, by adjusting the area ratio R, it is possible to adjust the forward voltage to a predetermined value.

[0136] The repeat pitch P may be 80 μm or more. The repeat pitch P may be 160 μm or less. As shown in FIG. 7, the forward voltage exhibits similar characteristics when the repeat pitch P is 80 μm and when it is 160 μm. This allows for further reduction in the variation in forward voltage. From the results shown in FIG. 7, it is estimated that the repeat pitch P reaches a minimum value when the repeat pitch P is between 80 μm and 160 μm. The repeat pitch P may be 100 μm or more. The repeat pitch P may be 130 μm or less.

[0137] When the area ratio R is 0.6 or less, the forward voltages are almost the same in the examples where the repeat pitch P is 80 μm and 160 μm. The area ratio R may be 0.6 or less. In this case, the repeat pitch P may be 80 μm or more and 160 μm or less.

[0138] When the area ratio R is 0.5 or less, the variation in forward voltage is relatively small when the repeat pitch P is 40 μm or more. When the first cathode region 81 and the second cathode region 82 included in the repeat structure 85 each have a longitudinal direction (X-axis direction) different from the first direction (Y-axis direction) as shown in FIG. 4A , the area ratio R may be 0.5 or less. The area ratio R may be 0.4 or less. The repeat pitch P may be 40 μm or more and 200 μm or less.

[0139] In another example, the repeat pitch P may be 40 μm or more and 80 μm or less. In this region, the forward voltage increases as the repeat pitch P increases. Therefore, the forward voltage can be adjusted by adjusting the repeat pitch P.

[0140] 8 is a diagram showing the relationship between the forward voltage and the reverse recovery loss with respect to the area ratio R. The diode section 80 in FIG. 8 has the structure shown in FIG. 5A and the repeat pitch P is 80 μm. The forward voltage is ２ This is the case when the current density is relatively high.

[0141] As shown in FIG. 8 , as the area ratio R increases, the reverse recovery loss decreases and the forward voltage increases. The upper limit of the area ratio R may be determined based on the characteristics of the area ratio versus the forward voltage. For example, the upper limit of the area ratio R (0.8 in FIG. 8 ) may be set so that the forward voltage is equal to or less than an allowable value. The lower limit of the range of the area ratio R may be determined based on the characteristics of the area ratio versus the reverse recovery loss. For example, the lower limit of the area ratio R (0.1 in FIG. 8 ) may be set so that the reverse recovery loss is equal to or less than an allowable value.

[0142] 9 is a diagram showing the relationship between the forward voltage and the reverse recovery loss with respect to the length Y2 in the first direction of the second cathode region 82. The diode section 80 in FIG. 9 has the structure shown in FIG. 5A, and the repeat pitch P is 80 μm.

[0143] As shown in FIG. 9 , as the length Y2 increases, the reverse recovery loss decreases and the forward voltage increases. The upper limit of the length Y2 may be determined based on the length Y2-forward voltage characteristics. For example, the upper limit of the length Y2 may be set so that the forward voltage is equal to or less than an allowable value. The length Y2 may be 65 μm or less, 60 μm or less, or 55 μm or less. The lower limit of the length Y2 may be determined based on the length Y2-reverse recovery loss characteristics. For example, the lower limit of the length Y2 may be set so that the reverse recovery loss is equal to or less than an allowable value. The length Y2 may be 10 μm or more, 15 μm or more, or 20 μm or more.

[0144] 10 shows the relationship between the magnitude of the variation in forward voltage due to the variation in patterning in the manufacturing process and the area ratio R. The diode section 80 in FIG. 10 has the structure shown in FIG. 5A, and the repeat pitch P is 80 μm.

[0145] 10, the patterning variation is ±0.5 μm. That is, the length Y1 of the first cathode region 81 and the length Y2 of the second cathode region 82 each have a variation of ±0.5 μm. Furthermore, the magnitude of the variation in forward voltage is normalized, as in the example of FIG. 7, with the magnitude of the forward voltage when R=0 being 1.

[0146] As shown in FIG. 10 , when the area ratio R is greater than 0.8, the forward voltage variation increases rapidly. When the area ratio of the second cathode region 82 is large, the area of ​​the first cathode region 81 required for conductivity modulation becomes relatively small. Therefore, it is believed that the influence of line width variation in the first cathode region 81 increases. The area ratio R is preferably 0.8 or less. The area ratio R may be 0.6 or less. This further suppresses the forward voltage variation. As shown in FIG. 10 , when the area ratio R is less than 0.05, the forward voltage variation increases rapidly. When the area ratio of the second cathode region 82 is too small, it is believed that the influence of line width variation in the first cathode region 81 strongly affects the degree of minority carrier shorting in the second cathode region 82. The area ratio R is preferably 0.05 or more. The area ratio R may be 0.1 or more, or may be 0.15 or more. By setting the area ratio of the second cathode region 82 within the above range, it is believed that when the carrier lifetime is relatively long, such as 1 μs or more, even if the line width of the first cathode region 81 varies, the balance between the effect of appropriately maintaining the concentration of minority carriers (holes in this example) and the effect of reducing the carrier concentration due to short-circuiting of minority carriers in the second cathode region 82 will be stabilized.

[0147] 11 shows the relationship between the magnitude of the variation in forward voltage due to the variation in patterning in the manufacturing process and the length Y2 of the second cathode region 82. The diode section 80 in FIG. 11 has the structure shown in FIG. 5A and has a repeat pitch P of 80 μm. In the example of FIG. 11, the variation in patterning is ±0.5 μm.

[0148] As shown in FIG. 11 , when the length Y2 is greater than 65 μm, the forward voltage variation increases rapidly. When the length of the second cathode region 82 is long, the area of ​​the first cathode region 81 required for conductivity modulation becomes relatively small. This is thought to increase the influence of linewidth variation in the first cathode region 81. The length Y2 is preferably 65 μm or less. The length Y2 may be 60 μm or less, or may be 55 μm or less. This further suppresses the forward voltage variation. As shown in FIG. 11 , when the length Y2 is less than 4 μm, the forward voltage variation increases rapidly. When the length of the second cathode region 82 is too short, the influence of linewidth variation in the first cathode region 81 is thought to strongly affect the degree of minority carrier shorting in the second cathode region 82. The length Y2 is preferably 4 μm or more. The length Y2 may be 8 μm or more, or may be 12 μm or more.

[0149] 12 shows the relationship between the magnitude of the variation in forward voltage and the area ratio R when the patterning variation is set to ±0.2 μm. In this example, the same results as those in the example shown in FIG.

[0150] 13 shows the relationship between the magnitude of the variation in forward voltage and the length Y2 of the second cathode region 82 when the patterning variation is ±0.2 μm. In this example, the same results as those in the example shown in FIG.

[0151] 14 is a diagram showing another example of the relationship between the area ratio R and the forward voltage of the diode section 80. FIG. 14 shows the characteristics of each sample in the example shown in FIG. 5A when both the repeat pitches Px and Py are set to 10 μm, 20 μm, 40 μm, 80 μm, 160 μm, 320 μm, or 640 μm. In each sample, Px = Py. Note that the same characteristics are obtained in the example shown in FIG. 5B.

[0152] As in the example of FIG. 7 , the area ratio R is preferably 0.8 or less. The area ratio R may be 0.7 or less, or may be 0.6 or less. Furthermore, if the second cathode region 82 is too small, the effect of reducing reverse recovery loss is reduced. The area ratio R is preferably 0.1 or more. The area ratio R may be 0.15 or more, or may be 0.2 or more.

[0153] 14, when the repeat pitch P increases from 10 μm to 160 μm, the forward voltage tends to decrease, whereas when the repeat pitch P increases from 160 μm to 640 μm, the forward voltage tends to increase.

[0154] 14, the second cathode region 82 is surrounded on all four sides by the first cathode region 81, so that electrons injected from the first cathode region 81 when the diode section 80 is turned on are more likely to flow upward into the entire second cathode region 82. Therefore, compared to the example of FIG. 7, the region above the second cathode region 82 is more likely to function as a diode up to a range where the repeat pitch P is large. As a result, the example of FIG. 14 is thought to show a tendency for the forward voltage to decrease up to a relatively large repeat pitch P.

[0155] As described above, the forward voltage decreases as the repeat pitch P increases from 10 μm to 160 μm, and increases as the repeat pitch P increases from 160 μm to 640 μm. Therefore, the forward voltage is relatively stable when the repeat pitch P is in the range of 40 μm or more and 200 μm or less. The repeat pitch P is preferably 40 μm or more and 200 μm or less.

[0156] As shown in Figure 14, when the repeat pitch P is 160 µm, the forward voltage is lower than that of the other samples. The repeat pitch P may be set to a value close to 160 µm. The repeat pitch P may be 80 µm or more, 100 µm or more, or 120 µm or more. The repeat pitch P may be 200 µm or less, or 180 µm or less.

[0157] In another example, the repeat pitch P may be 40 μm or more and 160 μm or less. In this region, the forward voltage increases as the repeat pitch P increases. Therefore, the forward voltage can be adjusted by adjusting the repeat pitch P.

[0158] 5A in which the first cathode regions 81 and the second cathode regions 82 are repeatedly arranged in a second direction (e.g., the X-axis direction) different from the first direction (e.g., the Y-axis direction), the area ratio R may be set to be larger than in the structure of Fig. 4A. The area ratio R may be 0.8 or less, 0.7 or less, or 0.6 or less.

[0159] FIG. 15 is a diagram showing a comparative example of the anode voltage-anode current characteristics of the diode section 80. The diode section 80 in FIG. 15 has the structure shown in FIG. 4A and a repeat pitch P of 10 μm. The example in FIG. 15 shows the anode voltage-anode current characteristics when the area ratio R is changed from 0.001 to 0.9. When the repeat pitch P is small, the change in the anode voltage-anode current characteristics when the area ratio R is changed is large. In particular, the change in the anode voltage-anode current characteristics when the area ratio R is 0.1 (i.e., a configuration in which the second cathode region 82 is slightly present) is large compared to the characteristics when the area ratio R is 0.001 (i.e., a configuration in which the second cathode region 82 is almost absent). Therefore, if the repeat pitch P is too small, it is difficult to accurately adjust the anode voltage-anode current characteristics in a region in which the difference from the characteristics when the area ratio R is 0.001 is relatively small.

[0160] FIG. 16 is a diagram showing another example of the anode voltage-anode current characteristics of the diode section 80. The diode section 80 of FIG. 16 has the structure of FIG. 4A , with a repeat pitch P of 80 μm. As shown in FIG. 16 , when the repeat pitch P is relatively large, the change in the anode voltage-anode current characteristics when the area ratio R is changed is small. In particular, the change in the anode voltage-anode current characteristics when the area ratio R is 0.1 (i.e., a configuration in which the second cathode region 82 is slightly present) is smaller than the change in the area ratio R of 0.001 (i.e., a configuration in which the second cathode region 82 is almost absent) compared to the example of FIG. 15 . Therefore, the anode voltage-anode current characteristics can be adjusted with high precision. From this perspective, the repeat pitch P may be 40 μm or more. The repeat pitch P may be 60 μm or more, or may be 80 μm or more.

[0161] FIG. 17 is a diagram showing the relationship between the length Y2 of the second cathode region 82 and the forward voltage. The diode section 80 of this example has the structure shown in FIG. 4A, and the repeat pitch P is 80 μm. As shown in FIG. 17, when the length Y2 is greater than 60 μm, the increase in forward voltage becomes steep. The length Y2 may be 50 μm or less, which is the region where the forward voltage changes linearly. The area ratio R may be 0.6 or less.

[0162] 18 is a diagram showing the relationship between the forward voltage and reverse recovery loss of the diode section 80. As shown in FIG. 18, there is a trade-off between the forward voltage and reverse recovery loss in the diode section 80. In other words, the lower the reverse recovery loss, the higher the forward voltage. As the forward voltage increases, the loss when the diode section 80 is on increases.

[0163] Comparative Examples 1 and 2 are examples in which the cathode region 83 has the first cathode region 81 but does not have the second cathode region 82. Comparative Example 1 shows the relationship between the forward voltage and the reverse recovery loss when the doping concentration of the anode region (base region 14) of the diode section 80 is changed. Comparative Example 2 shows the relationship between the forward voltage and the reverse recovery loss when the doping concentration of the cathode region 83 of the diode section 80 is changed.

[0164] Example 1 shows the relationship between forward voltage and reverse recovery loss when the area ratio R is changed in an example in which the diode section 80 has the structure of FIG. 4A and the repeat pitch is 80 μm. As shown in FIG. 18, Example 1 has improved trade-off characteristics compared to Comparative Examples 1 and 2.

[0165] In Example 1, the doping concentration of the base region 14 (anode region) of the diode section 80 and the base region 14 of the transistor section 70 are the same. Therefore, the base region 14 of the diode section 80 and the base region 14 of the transistor section 70 can be formed in the same ion implantation process. In other words, the base regions 14 of the transistor section 70 and the diode section 80 can be formed by implanting dopant ions in parallel at the same dose using a common mask. In contrast, in Comparative Examples 1 and 2, the doping concentration of the anode region of the diode section 80 is changed, which complicates the manufacturing process.

[0166] In the first embodiment, the doping concentration of the second cathode region 82 of the diode portion 80 is the same as the doping concentration of the collector region 22 of the transistor portion 70. Therefore, the second cathode region 82 of the diode portion 80 and the collector region 22 of the transistor portion 70 can be formed using the same ion implantation process. This structure allows the semiconductor device 100 to be manufactured using a simple manufacturing process and with improved trade-off characteristics. However, the base region 14 of the diode portion 80 and the base region 14 of the transistor portion 70 may have different doping concentrations. Furthermore, the second cathode region 82 of the diode portion 80 and the collector region 22 of the transistor portion 70 may have different doping concentrations.

[0167] The dose of dopant ions in the base region 14 (anode region) of the diode section 80 is 5.0×10 １２ / cm ２ That's it, 5.0 x 10 １３ / cm ２ The dose of dopant ions may be equal to or less than the doping concentration ( / cm ３) in the depth direction may be used. When the base region 14 is in contact with the upper surface 21 and the drift region 18, the dose may be calculated by integrating the doping concentration of the base region 14 from the upper surface 21 to the drift region 18. In another example, the dose may be calculated by integrating the peak of the doping concentration in the depth direction of the base region 14 over the full width at half maximum range.

[0168] The dose of dopant ions in the second cathode region 82 is 1.0×10 １３ / cm ２ That's it, 1.0 x 10 １４ / cm ２ The dose of dopant ions may be less than the doping concentration ( / cm ３ ) in the depth direction may be used. When the second cathode region 82 is in contact with the lower surface 23 and the N-type region, the dose may be calculated by integrating the doping concentration of the second cathode region 82 from the lower surface 23 to the N-type region. In another example, the dose may be calculated by integrating the peak of the doping concentration in the depth direction of the second cathode region 82 over the range of the full width at half maximum.

[0169] In order to adjust the forward voltage and reverse recovery loss, a carrier lifetime killer may be formed in the diode section 80. For example, by forming charged particles such as helium below the anode region of the diode section 80, a carrier recombination center is formed at that location, thereby reducing the carrier lifetime.

[0170] The semiconductor device 100 of this example does not require a carrier lifetime killer to be formed in the diode section 80. As described with reference to FIGS. 1 to 18 , the characteristics of the diode section 80 can be adjusted by adjusting the repetition pitch P and area ratio R of the cathode region 83. The carrier lifetime in the drift region 18 of the diode section 80 may be 1 μs or more throughout the entire drift region 18. The carrier lifetime may be 2 μs or more, or 3 μs or more. The carrier lifetime may be 10 μs or more, 20 μs or more, or 30 μs or more. The carrier lifetime may be 10 ms or less, 1 ms or less, 500 μs or less, 200 μs or less, or 100 μs or less. Furthermore, helium may not be present in the drift region 18 of the diode section 80. The carrier lifetime in the drift region 18 of the diode section 80 may exhibit a maximum value within the semiconductor substrate 10. This makes it possible to omit the step of forming a carrier lifetime killer, simplifying the manufacturing process, and also to prevent the occurrence of leakage current due to carrier recombination centers or generation centers.

[0171] FIG. 19 is a diagram illustrating a manufacturing method of the semiconductor device 100. FIG. 19 illustrates a step of forming the cathode region 83 in the manufacturing process of the semiconductor device 100. In the setting step S1002, the repeat pitch P and the area ratio R in the cathode region 83 are set. In the setting step S1002, the repeat pitch P and the area ratio R are set so that the forward voltage and reverse recovery loss that the diode section 80 should have fall within predetermined ranges. In S1002, the repeat pitch P and the area ratio R may be set with reference to the characteristics shown in FIG. 7 or FIG. 14. In the setting step S1002, the repeat pitch P is set to 40 μm or more and 200 μm or less, and the area ratio R is set to 0.1 or more and 0.8 or less. In the setting step S1002, the repeat pitch P and the area ratio R may be set as described with reference to FIGS. 1 to 18.

[0172] In the formation step S1004, the first cathode region 81 and the second cathode region 82 are formed in the semiconductor substrate 10 so as to have the set repetition pitch P and area ratio R. In the formation step S1004, the first cathode region 81 and the second cathode region 82 may be formed by implanting dopant ions from the lower surface 23 of the semiconductor substrate 10 and performing a heat treatment.

[0173] In the formation step S1004, the collector region 22 of the transistor portion 70 may be formed in a common process with the second cathode region 82. For example, in the formation step S1004, dopant ions are implanted using a mask that exposes regions where the collector region 22 and the second cathode region 82 are to be formed. This simplifies the process of forming the second cathode region 82 and the collector region 22.

[0174] In the formation step S1004, the anode region (base region 14) of the diode section 80 and the base region 14 of the transistor section 70 may be formed in a common process. For example, in the formation step S1004, dopant ions are implanted using a mask that exposes the regions where the anode region and the base region 14 are to be formed. This simplifies the process of forming the anode region and the base region 14.

[0175] FIG. 20 is a diagram illustrating an example of the design stage S1002. FIG. 20 shows the relationship between forward voltage and reverse recovery loss for the diode section 80. FIG. 20 shows a characteristic 302 of forward voltage versus reverse recovery loss when the doping concentration of the anode region of the diode section 80 is varied in a structure in which the cathode region 83 has the first cathode region 81 but does not have the second cathode region 82. Also shown is a characteristic group 304 for a diode section 80 having the structure shown in FIG. 4A , formed using the doping concentration of the anode region at a predetermined reference point A in characteristic 302. Characteristic group 304 shows the characteristics of each sample with a repeat pitch P varied from 10 μm to 640 μm. For each characteristic in characteristic group 304, the forward voltage and reverse recovery loss are adjusted by changing the area ratio R.

[0176] In the design stage S1002, an initial value for the design value of the doping concentration of the anode region is set. The initial value is the doping concentration of the anode region at any point on the characteristic 302. In the example of Fig. 20, the doping concentration of the anode region at reference point A is set as the initial value.

[0177] In the design stage S1002, the forward voltage-reverse recovery loss characteristics of the diode section 80 when the initial values ​​are used are obtained for a plurality of repetition pitches P. In the example of Fig. 20, a characteristics group 304 is obtained.

[0178] In the design stage S1002, the design value of the doping concentration of the anode region may be adjusted based on the acquired characteristic set 304. For example, from each characteristic included in the characteristic set 304, a characteristic that can achieve the desired forward voltage and reverse recovery loss may be selected, and the repetition pitch P and area ratio R may be determined from the selected characteristic. However, the characteristic set 304 for the reference point A may not include the desired forward voltage and reverse recovery loss. In this case, in the design stage S1002, a new reference point B is set so that the desired forward voltage and reverse recovery loss are obtained, and a new characteristic set 304 for the reference point B is acquired. For example, if it is desired to shift the reverse recovery loss range of the characteristic set 304 in the direction of decreasing loss, a reference point B with a smaller forward voltage (and reverse recovery loss) is set relative to the reference point A. The forward voltage can be reduced by increasing the doping concentration of the anode region. This process may be repeated until the desired forward voltage and reverse recovery loss are set.

[0179] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0180] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0181] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 20...Buffer region, 21...Upper surface, 22...Collector region, 23...Lower surface, 24...Collector electrode, 29...Straight portion, 30...Dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 41...Tip portion, 42...Gate insulating film, 44...Gate Conductive portion, 52...emitter electrode, 54...contact hole, 60, 61...mesa portion, 70...transistor portion, 80...diode portion, 81...first cathode region, 82...second cathode region, 83...cathode region, 84...margin region, 85...repeated structure, 90...boundary, 91...chamfered portion, 100...semiconductor device, 130...peripheral gate wiring, 131...active side gate wiring, 150...edge termination structure portion, 160...active portion, 162...edge, 164...gate pad, 302...characteristics, 304...characteristic group

Claims

1. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, the diode portion being provided on the semiconductor substrate, the diode portion comprising: a drift region of a first conductivity type provided on the semiconductor substrate; a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate, the first cathode region and the second cathode region being repeatedly provided in a first direction, a repetition pitch of the first cathode region and the second cathode region in the first direction being 40 μm or more and 200 μm or less, and an area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region being 0.1 or more and 0.8 or less.

2. The semiconductor device according to claim 1, wherein the repeat pitch is not less than 80 μm and not more than 160 μm.

3. The semiconductor device according to claim 2, wherein the area ratio is 0.6 or less.

4. The semiconductor device according to claim 1, wherein each of the first cathode region and the second cathode region has a longitudinal direction different from the first direction, and the area ratio is 0.5 or less.

5. The semiconductor device according to claim 1, wherein the first cathode region and the second cathode region are repeatedly arranged in a second direction different from the first direction, and the area ratio is 0.6 or less.

6. The semiconductor device according to claim 1, wherein the repeat pitch is not less than 100 μm and not more than 130 μm.

7. The semiconductor device according to claim 1, wherein the repeat pitch is 40 μm or more and 80 μm or less.

8. The diode portion has an anode region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate, and a dose amount of dopant ions in the anode region is 5.0×10 １２ / cm ２ That's it, 5.0 x 10 １３ / cm ２ The semiconductor device according to claim 1 , wherein:

9. The dose of dopant ions in the second cathode region is 1.0×10 １３ / cm ２ That's it, 1.0 x 10 １４ / cm ２ The semiconductor device according to claim 8 , wherein:

10. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor substrate is provided with a transistor section connected in anti-parallel to the diode section.

11. The semiconductor device according to claim 10, wherein the transistor portion has a collector region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate, and the doping concentration of the second cathode region is the same as the doping concentration of the collector region.

12. The semiconductor device according to claim 10, wherein the diode section has an anode region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate, and the transistor section has an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate, the drift region, and a base region of a second conductivity type provided between the emitter region and the drift region, and a doping concentration of the anode region and a doping concentration of the base region are the same.

13. The semiconductor device according to claim 1, wherein the carrier lifetime in the drift region of the diode portion is 1 μs or more.

14. A method for manufacturing a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate having a first conductivity type drift region, the semiconductor substrate being provided with a diode portion, the method comprising: forming a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, and a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate; in forming the first cathode region and the second cathode region, the first cathode region and the second cathode region are repeatedly provided in a first direction, the repetition pitch of the first cathode region and the second cathode region in the first direction being 40 μm or more and 200 μm or less; and the area ratio of the second cathode region to the sum of the areas of the first cathode region and the second cathode region being 0.1 or more and 0.8 or less.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the semiconductor device has a transistor portion provided on the semiconductor substrate and connected in anti-parallel to the diode portion, the transistor portion having a collector region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate, and the collector region is formed in a process common to that for the second cathode region.

16. A method for manufacturing a semiconductor device as described in claim 14, wherein the semiconductor device has a transistor section provided on the semiconductor substrate and connected in anti-parallel to the diode section, the diode section having an anode region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate, and the transistor section has an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate, the drift region, and a base region of a second conductivity type provided between the emitter region and the drift region, and the anode region and the base region are formed by a common process.

17. A method for manufacturing a semiconductor device as described in claim 14, wherein the diode section has an anode region of a second conductivity type provided in contact with the upper surface of the semiconductor substrate, an initial value of a design value of a doping concentration of the anode region is set, forward voltage-reverse recovery loss characteristics of the diode section when the initial value is used are obtained for a plurality of the repetition pitches, and the design value of the doping concentration of the anode region is adjusted based on a plurality of the forward voltage-reverse recovery loss characteristics for a plurality of the repetition pitches.

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