Alignment mark used in wafer bonding process and wafer bonding method using same

Abstract

The present invention relates to an alignment mark and a wafer bonding method using same, the alignment mark being used for aligning a first semiconductor wafer and a second semiconductor wafer in a wafer bonding process for aligning and coupling the first semiconductor wafer to the second semiconductor wafer being inverted, so that surfaces thereof on which semiconductor devices are formed face each other. The present invention provides an alignment mark that is used in a wafer bonding process for aligning and coupling a first semiconductor wafer and an inverted second semiconductor wafer, the alignment mark including: a first alignment mark formed in a predetermined region of the first semiconductor wafer and having a first center of symmetry; and a second alignment mark which has a second center of symmetry and is formed in a predetermined region of the second semiconductor wafer such that, when the first semiconductor wafer and the inverted second semiconductor wafer are coupled to each other, the second alignment mark overlaps the first alignment mark, while inverted.

Description

Alignment marks used in the wafer bonding process and wafer bonding methods using them

[0001] The present invention relates to an alignment mark used for aligning a first semiconductor wafer and a second semiconductor wafer in a wafer bonding process in which a first semiconductor wafer and an inverted second semiconductor wafer are aligned and bonded so that the surfaces on which semiconductor elements are formed face each other, and to a wafer bonding method using the same.

[0002] In the past, integration of semiconductor devices was achieved through miniaturization of patterns on the XY plane, but recently, integration of semiconductors is being achieved by stacking patterns in the Z-axis direction.

[0003] Furthermore, semiconductor integration is being achieved using wafer bonding technology, which joins two semiconductor wafers formed with semiconductor devices into one. For example, a method is being used to bond a semiconductor wafer formed with memory devices to a semiconductor wafer formed with logic devices, electrically connecting the pads of the memory devices to the pads of the logic devices.

[0004] At this time, if misalignment occurs between semiconductor wafers, there is a problem that the pads of the memory elements and the pads of the logic elements are not electrically connected.

[0005] To solve these problems, a method is being used in which alignment marks are formed on each semiconductor wafer and the semiconductor wafers are aligned using these alignment marks.

[0006] For example, U.S. Patent Publication No. US 2023 / 0135060 A1 discloses a method for aligning a first wafer and a second wafer by aligning a first alignment mark on a first wafer and a second alignment mark on a second wafer.

[0007] [Prior Art Literature]

[0008] (Patent Document 1) US Patent Publication No. US 2023 / 0135060 A1

[0009] The present invention aims to provide a novel alignment mark used in a wafer bonding process.

[0010] In order to achieve the above-described object, the present invention provides an alignment mark used in a wafer bonding process for aligning and bonding a first semiconductor wafer and a flipped second semiconductor wafer, the alignment mark including: a first alignment mark formed in a predetermined region of the first semiconductor wafer and having a first center of symmetry; and a second alignment mark formed in a predetermined region of the second semiconductor wafer and having a second center of symmetry so as to overlap the first alignment mark in an inverted state when bonding the first semiconductor wafer and the flipped second semiconductor wafer.

[0011] Here, when the first semiconductor wafer and the flipped second semiconductor wafer are aligned, the first symmetry center and the second symmetry center overlap, and the difference between the first symmetry center and the second symmetry center represents an alignment error between the first semiconductor wafer and the flipped second semiconductor wafer.

[0012] And the first alignment mark is rotationally symmetrical at 90 degrees and 180 degrees with respect to the first symmetry center, and is asymmetrical with respect to the first axis passing through the first symmetry center.

[0013] The above first alignment mark and the above second alignment mark have the same shape and size.

[0014] In addition, the first alignment mark may include a first alignment mark element and a third alignment mark element formed in two quadrants arranged diagonally among the quadrants divided by the first axis and a second axis orthogonal to the first axis, and a second alignment mark element and a fourth alignment mark element formed in the remaining two quadrants, respectively.

[0015] The first alignment mark element may include at least one first bar formed long in the second axis direction, the second alignment mark element may include at least one second bar formed long in the first axis direction, the third alignment mark element may include at least one third bar formed long in the second axis direction, and the fourth alignment mark element may include at least one fourth bar formed long in the first axis direction.

[0016] In addition, the second alignment mark includes a fifth bar, a sixth bar, a seventh bar, and an eighth bar corresponding to the first bar, the second bar, the third bar, and the fourth bar of the first alignment mark, respectively, and the bars of the first alignment mark and the flipped bars of the second alignment mark belonging to the same quadrant can form a right angle.

[0017] Additionally, the bars of the first alignment mark belonging to the same quadrant and the bars of the second alignment mark flipped over can be orthogonal.

[0018] In addition, the present invention provides a wafer bonding method for aligning and bonding a first semiconductor wafer and an inverted second semiconductor wafer, the method comprising: forming a first alignment mark having a first center of symmetry in a predetermined region of the first semiconductor wafer; forming a second alignment mark having a second center of symmetry in a predetermined region of the second semiconductor wafer so as to overlap the first alignment mark in an inverted state when bonding the first semiconductor wafer and the inverted second semiconductor wafer; aligning the first alignment mark and the second alignment mark; and bonding the first semiconductor wafer and the second semiconductor wafer.

[0019] Here, when the first semiconductor wafer and the flipped second semiconductor wafer are aligned, the first symmetry center and the second symmetry center overlap, and the difference between the first symmetry center and the second symmetry center represents an alignment error between the first semiconductor wafer and the flipped second semiconductor wafer.

[0020] And the first alignment mark is rotationally symmetrical at 90 degrees and 180 degrees with respect to the first symmetry center, and is asymmetrical with respect to the first axis passing through the first symmetry center.

[0021] The above first alignment mark and the above second alignment mark have the same shape and size.

[0022] The alignment marks according to the present invention have the same shape as the first alignment mark and the second alignment mark formed on the first and second semiconductor wafers, respectively. Therefore, the influence of the exposure process for forming the first and second alignment marks can be minimized as much as possible. Furthermore, the influence of the optical measuring device for measuring alignment errors can also be minimized.

[0023] Figure 1 shows a first semiconductor wafer on which a first alignment mark is formed.

[0024] Figure 2 shows a second semiconductor wafer on which a second alignment mark is formed.

[0025] Figure 3 is a drawing for explaining a method for checking the alignment error between a first semiconductor wafer and a flipped second semiconductor wafer.

[0026] Figure 4 shows an example of the first alignment mark illustrated in Figure 1.

[0027] Figure 5 shows an example of the second alignment mark illustrated in Figure 2.

[0028] Figure 6 shows an inverted second alignment mark.

[0029] Figure 7 is a drawing showing an example of an alignment mark image.

[0030] Figure 8 is a drawing for explaining a method for measuring alignment error.

[0031] Figure 9 is a drawing showing another example of the first alignment mark and the second alignment mark.

[0032] Figure 10 shows an alignment mark image in which the first alignment mark of Figure 9 and the flipped second alignment mark are overlapped.

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those with average knowledge in the art. Therefore, the shapes of elements in the drawings are exaggerated to emphasize a clearer description, and elements indicated by the same reference numerals in the drawings represent the same elements.

[0034] Fig. 1 is a drawing showing a first semiconductor wafer on which a first alignment mark is formed, and Fig. 2 is a drawing showing a second semiconductor wafer on which a second alignment mark is formed.

[0035] The first semiconductor wafer (1) and the second semiconductor wafer (2) may include a silicon wafer and a plurality of pattern layers forming a semiconductor device. Wafers other than silicon wafers may also be used.

[0036] As illustrated in Fig. 1, a first alignment mark (10) is formed in a predetermined area of ​​a first semiconductor wafer (1). A plurality of first alignment marks (10) may be formed on the first semiconductor wafer (1).

[0037] As illustrated in Fig. 2, a second alignment mark (20) is formed in a predetermined area of ​​a second semiconductor wafer (2). A plurality of second alignment marks (20) may be formed on the second semiconductor wafer (2).

[0038] The second alignment marks (20) are arranged so as to overlap with the corresponding first alignment marks (10) when combining the first semiconductor wafer (1) and the flipped second semiconductor wafer (2). For example, the central second alignment mark (20) of FIG. 2 overlaps with the central first alignment mark (10) of FIG. 1, the left second alignment mark (20) of FIG. 2 overlaps with the left first alignment mark (10) of FIG. 1, and the right second alignment mark (20) of FIG. 2 overlaps with the right first alignment mark (10) of FIG. 1.

[0039] In addition, when the second semiconductor wafer (2) is flipped so that the left and right sides are reversed in the drawing, the left second alignment mark (20) of FIG. 2 may overlap with the right first alignment mark (10) of FIG. 1, and the right second alignment mark (20) of FIG. 2 may overlap with the left first alignment mark (10) of FIG. 1.

[0040] In FIGS. 1 and 2, the first alignment mark (10) and the second alignment mark (20) are shown as being formed on the top layer and exposed to the outside, but another layer may be formed on the first alignment mark (10) and the second alignment mark (20).

[0041] Figure 3 is a drawing for explaining a method for obtaining an alignment mark image.

[0042] As illustrated in FIG. 3, the first alignment mark (10) and the second alignment mark (20) that are overlapped are photographed simultaneously using a camera (5) to obtain an alignment mark image that includes both the first alignment mark (10) and the flipped second alignment mark (20). Then, the alignment error can be confirmed by analyzing the obtained alignment mark image. The lighting used for photographing may be lighting that has high reflectivity for the first alignment mark (10) and the second alignment mark (20), low reflectivity for the second semiconductor wafer (2), and high transmittance. For example, when a silicon wafer is used as the second semiconductor wafer (2), the wavelength band of the lighting is preferably 900 nm to 2000 nm. This is because, although there is a difference depending on the thickness of the silicon wafer, an edge region of light transmittance is formed where the transmittance rapidly changes (increases) from about 900 nm.

[0043] When the first alignment mark (10) is embedded in the first semiconductor wafer (1), the light may also have high transmittance to the first semiconductor wafer (1). The light passes through the second semiconductor wafer (2) and is reflected at the second alignment mark (20) and the first alignment mark (10).

[0044] The alignment mark image can be acquired during the alignment process, as illustrated in FIG. 3, or can be acquired after bonding of the first semiconductor wafer (1) and the second semiconductor wafer (2) is completed. If acquired during the alignment process, the measured alignment error can be used to align the first semiconductor wafer (1) and the second semiconductor wafer (2). If acquired after bonding is completed, the measured alignment error can be used to determine whether the bonded wafer is defective.

[0045] The first semiconductor wafer (1) and the second semiconductor wafer (2) are fixed to a stage, table, vacuum chuck, etc. that can move in the X, Y, and Z directions, so that the plane movement for alignment and the distance adjustment between the first semiconductor wafer (1) and the second semiconductor wafer (2) for bonding are possible.

[0046] Fig. 4 shows an example of the first alignment mark illustrated in Fig. 1. Fig. 4 shows the first alignment mark (10) as viewed from above the first semiconductor wafer (1).

[0047] As illustrated in Fig. 4, the first alignment mark (10) is rotationally symmetrical at 90 degrees and 180 degrees with respect to the first symmetry center (COS1). However, it is asymmetrical with respect to the first axis (X-axis or Y-axis in Fig. 4) passing through the first symmetry center (COS1). In addition, it is also asymmetrical with respect to the second axis orthogonal to the first axis. Hereinafter, the X-axis will be described as the first axis.

[0048] The first alignment mark (10) includes a first alignment mark element (11), a second alignment mark element (13), a third alignment mark element (15), and a fourth alignment mark element (17).

[0049] The first alignment mark element (11) and the third alignment mark element (15) are arranged in the first quadrant and the third quadrant, respectively, and the second alignment mark element (13) and the fourth alignment mark element (17) are arranged in the second quadrant and the fourth quadrant, respectively.

[0050] The first alignment mark element (11) includes at least one first bar formed elongated in the Y-axis direction. When including a plurality of first bars, the first bars are arranged at intervals along the X-axis direction. Although two first bars are illustrated, three or more may be present.

[0051] The second alignment mark element (13) includes at least one second bar formed elongated in the X-axis direction. When a plurality of second bars are included, the second bars are spaced apart along the X-axis direction. Although two second bars are illustrated, three or more may be present.

[0052] The third alignment mark element (15), like the first alignment mark element (11), includes at least one third bar formed long in the Y-axis direction.

[0053] The fourth alignment mark element (17), like the second alignment mark element (13), includes at least one fourth bar formed long in the X-axis direction.

[0054] Fig. 5 shows an example of the second alignment mark illustrated in Fig. 2. Fig. 5 shows the second alignment mark (20) as viewed from above the second semiconductor wafer (2). Fig. 6 shows the second alignment mark (20) flipped so that it is upside down.

[0055] As illustrated in Fig. 5, the second alignment mark (20) is completely identical in shape and size to the first alignment mark (10). Therefore, the influence of the exposure process for forming the first alignment mark (10) and the second alignment mark (20) can be minimized as much as possible. In addition, the influence of the optical measuring device that measures alignment errors can also be minimized. For example, not only are the pattern shapes of each layer consistent, but the patterns are evenly distributed in the same area, so that measurement distortion due to aberrations caused by the optical measuring device can be minimized.

[0056] The second alignment mark (20) includes a fifth alignment mark element (21), a sixth alignment mark element (23), a seventh alignment mark element (25), and an eighth alignment mark element (27), which are formed of bars arranged in each quadrant, similar to the first alignment mark (10).

[0057] The second alignment mark (20), like the first alignment mark (10), is not symmetrical with respect to the X-axis or the Y-axis. Therefore, as illustrated in Fig. 6, the inverted second alignment mark (20) has a different shape from the first alignment mark (10). That is, it is a shape that is flipped left and right or up and down based on the shape on the plane.

[0058] Fig. 7 is a drawing showing an example of an alignment mark image. As shown in Fig. 7, an alignment mark image can be obtained in which a first alignment mark (10) and an inverted second alignment mark (20) are overlapped. The alignment mark image shown in Fig. 7 shows a state in which the first alignment mark (10) of Fig. 4 and the second alignment mark (20) of Fig. 6 are overlapped.

[0059] The COI in Fig. 7 represents the center of the alignment mark image. The center of the alignment mark image (COI) can be found in various ways. For example, the center of rotational symmetry of the alignment mark image and the image of the alignment mark image rotated 180 degrees can be found as the center of the alignment mark image (COI).

[0060] In Fig. 7, for convenience, the symmetry center (COS1) of the first alignment mark (10), the symmetry center (COS2) of the second alignment mark (20), and the center (COI) of the alignment mark image are all illustrated as being aligned. However, if there is an alignment error, the symmetry center (COS1) of the first alignment mark (10) and the symmetry center (COS2) of the second alignment mark (20) do not coincide with each other. And regardless of the presence or absence of an alignment error, the center (COI) of the alignment mark image may be different from the symmetry center (COS1) of the first alignment mark (10) and the symmetry center (COS2) of the second alignment mark (20).

[0061] The alignment error between the first semiconductor wafer (1) and the flipped second semiconductor wafer (2) can be measured by measuring the offset between the center of symmetry (COS1) of the first alignment mark (10) and the center of symmetry (COS2) of the second alignment mark (20).

[0062] When the alignment error between the first semiconductor wafer (1) and the flipped second semiconductor wafer (2) is 0 (zero), the symmetry center (COS1) of the first alignment mark (10) and the symmetry center (COS2) of the second alignment mark (20) coincide with each other. The difference between the symmetry center (COS1) of the first alignment mark (10) and the symmetry center (COS2) of the second alignment mark (20) represents the alignment error between the first semiconductor wafer (1) and the flipped second semiconductor wafer (2).

[0063] Below, a method for measuring X-axis alignment error is described using the alignment mark image shown in Fig. 7.

[0064] A method for measuring alignment error may include the following steps:

[0065] First, the difference between the X value of the center of symmetry (COS1) of the first alignment mark (10) and the X value of the center (COI) of the acquired alignment mark image is obtained (S11).

[0066] As illustrated in Fig. 7, an area (A1) is selected in the first quadrant of the acquired alignment mark image, and an area (A2) that is 180 degrees symmetrical with respect to the center (COI) of the acquired alignment mark image is selected. This area (A2) is located approximately in the third quadrant.

[0067] Next, the two-dimensional images of the two selected areas (A1, A2) are each projected into one dimension. That is, the gray values ​​of pixels with the same X value in the two-dimensional image are added, the average of the gray values ​​is calculated, or the gray values ​​are normalized. Then, as shown in (a) and (b) of Fig. 8, graphs (G) showing the change in gray value according to the X value are generated. X1 ,G X2 ) can be drawn respectively. At this time, the graph representing the A2 area (G X2 ) may be a graph obtained by projecting a two-dimensional image of area A2 and then flipping it left and right.

[0068] Since the gray level of the first bars (11) is different from the gray level of the space between the first bars (11), a graph (G) in which a peak appears at the location of the first bars (11) as shown in (a) of Fig. 8 X1 ) can be obtained. Since the influence of the 6th bar (23, horizontal bar) is the same depending on the X value, the influence of the 6th bar (23) can be almost ignored. Graph (G) of Fig. 8 (b) X2 ) for the same reason, the influence of the 8th bar (27) is almost ignored.

[0069] If the X value of the center of symmetry (COS1) of the first alignment mark (10) and the X value of the center (COI) of the acquired alignment mark image are the same, the two graphs (G X1 ,G X2 ) should be almost identical to each other.

[0070] If the X value of the center of symmetry (COS1) of the first alignment mark (10) and the X value of the center (COI) of the acquired alignment mark image are not the same, the two graphs (G X1 ,G X2) are offset. And this offset value (ΔX) represents the difference between the X value of the center of symmetry (COS1) of the first alignment mark (10) and the X value of the center (COI) of the acquired alignment mark image.

[0071] Next, the difference between the X value of the center of symmetry (COS2) of the second alignment mark (20) and the X value of the center (COI) of the acquired alignment mark image is obtained. In this step, an area (A3) of the second quadrant is selected from the acquired alignment mark image, and an area (A4) that is 180 degrees symmetrical with respect to the center (COI) of the acquired alignment mark image is selected. This area (A4) is located in the fourth quadrant. Then, graphs representing the two selected areas (A2, A4) are drawn, and these are used to obtain the difference between the X value of the center of symmetry (COS2) of the second alignment mark (20) and the X value of the center (COI) of the acquired alignment mark image.

[0072] Next, the alignment error value in the X-axis direction is obtained by using the difference between the X value of the symmetry center (COS1) of the first alignment mark (10) obtained previously and the X value of the center (COI) of the acquired alignment mark image and the difference between the X value of the symmetry center (COS2) of the second alignment mark (20) and the X value of the center (COI) of the acquired alignment mark image.

[0073] By changing only the projection direction, the difference between the Y value of the center of symmetry (COS1) of the first alignment mark (10) and the Y value of the center of symmetry (COI) of the acquired alignment mark image and the difference between the Y value of the center of symmetry (COS1) of the second alignment mark (20) and the Y value of the center of symmetry (COI) of the acquired alignment mark image can be obtained in the same way, and using this, the alignment error value in the Y-axis direction can be obtained.

[0074] Hereinafter, a wafer bonding method for aligning and bonding a first semiconductor wafer (1) and an inverted second semiconductor wafer (2) using the above-described alignment marks will be described.

[0075] First, as shown in FIGS. 1 and 2, a first alignment mark (10) and a second alignment mark (20) are formed in predetermined areas of a first semiconductor wafer (1) and a second semiconductor wafer (2), respectively.

[0076] The second alignment mark (20) is formed in a predetermined area of ​​the second semiconductor wafer (2) so as to overlap with the first alignment mark (10) in an inverted state when combining the first semiconductor wafer (1) and the inverted second semiconductor wafer (2).

[0077] Next, as illustrated in FIG. 3, the first semiconductor wafer (1) and the second semiconductor wafer (2) are temporarily aligned so that the surfaces on which the semiconductor elements of the first semiconductor wafer (1) and the second semiconductor wafer (2) are formed face each other. In this step, the coordinates of the first alignment mark (10) and the coordinates of the second alignment mark (20) are individually measured, and temporary alignment can be performed using these coordinates.

[0078] Next, using the camera (5), an alignment mark image (e.g., the image of Fig. 7) in which the first alignment mark (10) and the second alignment mark (20) overlap is acquired.

[0079] And by analyzing the alignment mark image, the alignment error between the first symmetry center (COS1) and the second symmetry center (COS2) of the first alignment mark (10) and the second alignment mark (20) is calculated.

[0080] And using this alignment error, the first alignment mark (10) and the second alignment mark (20) are aligned. If the first symmetry center (COS1) and the second symmetry center (COS2) overlap (if the alignment error is 0), the first alignment mark (10) and the second alignment mark (20) can be considered aligned. If the first alignment mark (10) and the second alignment mark (20) are aligned, the first semiconductor wafer (1) and the second semiconductor wafer (2) are also aligned.

[0081] Next, the aligned first semiconductor wafer (1) and second semiconductor wafer (2) are bonded.

[0082] Fig. 9 is a drawing showing another example of a first alignment mark and a second alignment mark, and Fig. 10 shows an alignment mark image in which the first alignment mark of Fig. 9 and an inverted second alignment mark are overlapped.

[0083] The alignment mark illustrated in FIG. 10 differs from the alignment mark illustrated in FIG. 7 in the position where the bars (111, 113, 115, 117) constituting the first alignment mark (110) and the bars (121, 123, 125, 127) constituting the second alignment mark (120) intersect. In the alignment mark illustrated in FIG. 10, the bars (111, 113, 115, 117) constituting the first alignment mark (110) and the bars (121, 123, 125, 127) constituting the second alignment mark (120) roughly form a square together. The bars (111, 113, 115, 117) forming the first alignment mark (110) and the bars (121, 123, 125, 127) forming the second alignment mark (120) overlap each other at the corners of the square.

[0084] The embodiments described above merely describe preferred embodiments of the present invention, and the scope of the present invention is not limited to the described embodiments, and various changes, modifications, or substitutions may be made by those skilled in the art within the technical spirit and scope of the claims of the present invention, and it should be understood that such embodiments fall within the scope of the present invention.

[0085] [Explanation of symbols]

[0086] 1: First semiconductor wafer

[0087] 2: First semiconductor wafer

[0088] 5: Camera

[0089] 10, 110: First alignment mark

[0090] 11: First alignment mark element

[0091] 13: Second alignment mark element

[0092] 15: Third alignment mark element

[0093] 17: 4th alignment mark element

[0094] 20, 120: Second alignment mark

[0095] 21: Fifth alignment mark element

[0096] 23: 6th alignment mark element

[0097] 25: 7th alignment mark element

[0098] 27: 8th alignment mark element

Claims

1. As an alignment mark used in a wafer bonding process for aligning and bonding a first semiconductor wafer and a flipped second semiconductor wafer, A first alignment mark formed in a predetermined area of ​​the first semiconductor wafer and having a first center of symmetry; A second alignment mark is formed in a predetermined region of the second semiconductor wafer so as to overlap the first alignment mark in a flipped state when combining the first semiconductor wafer and the flipped second semiconductor wafer, and includes a second alignment mark having a second center of symmetry. When the first semiconductor wafer and the flipped second semiconductor wafer are aligned, the first symmetry center and the second symmetry center overlap, The difference between the first symmetry center and the second symmetry center represents an alignment error between the first semiconductor wafer and the flipped second semiconductor wafer, The above first alignment mark is rotationally symmetrical at 90 degrees and 180 degrees with respect to the first symmetry center, and is asymmetrical with respect to the first axis passing through the first symmetry center. The above first alignment mark and the above second alignment mark have the same shape and size, An alignment mark used in a wafer bonding process, wherein the first alignment mark and the second alignment mark include a plurality of bars, and among the quadrants divided by the first axis and the second axis orthogonal to the first axis, the bars of the first alignment mark belonging to the same quadrant and the bars of the second alignment mark that are flipped form a right angle.

2. In paragraph 1, The above first alignment mark is, Among the above quadrants, a first alignment mark element and a third alignment mark element are formed in each of two quadrants arranged diagonally, and a second alignment mark element and a fourth alignment mark element are formed in each of the remaining two quadrants. The first alignment mark element comprises at least one first bar formed elongated in the second axis direction, The second alignment mark element comprises at least one second bar formed elongated in the first axis direction, The third alignment mark element comprises at least one third bar formed elongated in the second axis direction, An alignment mark used in a wafer bonding process, wherein the fourth alignment mark element comprises at least one fourth bar formed long in the first axis direction.

3. In paragraph 2, The above second alignment mark is, The first alignment mark includes a fifth bar, a sixth bar, a seventh bar, and an eighth bar, each corresponding to the first bar, the second bar, the third bar, and the fourth bar, An alignment mark used in a wafer bonding process in which the bars of the first alignment mark belonging to the same quadrant and the bars of the second alignment mark flipped over form a right angle.

4. In paragraph 3, The bars of the first alignment mark belonging to the same quadrant and the bars of the second alignment mark flipped over are alignment marks used in the orthogonal wafer bonding process.

5. A wafer bonding method for aligning and bonding a first semiconductor wafer and a flipped second semiconductor wafer, A step of forming a first alignment mark having a first center of symmetry in a predetermined area of ​​the first semiconductor wafer; A step of forming a second alignment mark having a second center of symmetry in a predetermined area of ​​the second semiconductor wafer so as to overlap the first alignment mark in a flipped state when combining the first semiconductor wafer and the flipped second semiconductor wafer; A step of aligning the first alignment mark and the second alignment mark, A step of bonding the first semiconductor wafer and the second semiconductor wafer is included, When the first semiconductor wafer and the flipped second semiconductor wafer are aligned, the first symmetry center and the second symmetry center overlap, The difference between the first symmetry center and the second symmetry center represents an alignment error between the first semiconductor wafer and the flipped second semiconductor wafer, The above first alignment mark is rotationally symmetrical at 90 degrees and 180 degrees with respect to the first symmetry center, and is asymmetrical with respect to the first axis passing through the first symmetry center. The above first alignment mark and the above second alignment mark have the same shape and size, A wafer bonding method, wherein the first alignment mark and the second alignment mark include a plurality of bars, and among the quadrants divided by the first axis and the second axis orthogonal to the first axis, the bars of the first alignment mark belonging to the same quadrant and the bars of the second alignment mark that are flipped form a right angle.

6. In paragraph 5, The above first alignment mark is, Among the above quadrants, a first alignment mark element and a third alignment mark element are formed in each of two quadrants arranged diagonally, and a second alignment mark element and a fourth alignment mark element are formed in each of the remaining two quadrants. The first alignment mark element comprises at least one first bar formed elongated in the second axis direction, The second alignment mark element comprises at least one second bar formed elongated in the first axis direction, The third alignment mark element comprises at least one third bar formed elongated in the second axis direction, A wafer bonding method, wherein the fourth alignment mark element comprises at least one fourth bar formed long in the first axis direction.

7. In paragraph 6, The above second alignment mark is, The first alignment mark includes a fifth bar, a sixth bar, a seventh bar, and an eighth bar, each corresponding to the first bar, the second bar, the third bar, and the fourth bar, A wafer bonding method in which the bars of the first alignment mark belonging to the same quadrant and the bars of the second alignment mark flipped over form a right angle.

8. In paragraph 7, A wafer bonding method wherein the bars of the first alignment mark belonging to the same quadrant and the bars of the second alignment mark flipped over are orthogonal.

Images