Three-dimensional random access memory with assured memory performance

Abstract

Disclosed are a three-dimensional random access memory that improves the application speed of a bit line voltage, and an operating method thereof. According to the present invention, a three-dimensional random access memory comprises: gate electrodes which are formed on a substrate so as to extend in the horizontal direction and to be stacked spaced apart from each other in the vertical direction; at least one dummy electrode located between the gate electrodes; vertical structures formed so as to penetrate the gate electrodes and the at least one dummy electrode and so as to extend in the vertical direction, wherein each of the vertical structures comprises a data storage pattern and a bit line vertical part, and the data storage patterns form memory cells corresponding to the gate electrodes.

Description

3D random access memory that guarantees memory performance

[0001] The examples below are for a three-dimensional random access memory that guarantees memory performance.

[0002] Semiconductor devices such as DRAM (Dynamic Random Access Memory) have a MOS transistor including a source and a drain, a capacitor electrically connected to the source of the MOS transistor, and wiring such as a bit line electrically connected to the drain of the MOS transistor.

[0003] These DRAMs began to be implemented in a three-dimensional structure, moving away from the two-dimensional structure, in line with the trend toward high integration to secure storage space.

[0004] A 3D DRAM is implemented to support and operate random access based on a semiconductor structure including interlayer insulating layers and gate electrodes that are alternately stacked in a vertical direction and a memory cell string that extends vertically through the semiconductor structure, and a gate electrode and a vertical electrode within the memory cell string.

[0005] However, conventional 3D random access memories have a problem in that the speed of applying bit line voltage to a vertical portion of a bit line of a selected vertical structure including a target memory cell during a memory operation for the target memory cell is reduced due to high-level configuration.

[0006] In addition, since the existing 3D random access memory does not propose a design for a block in which vertical structures of memory cells are arranged, if an excessive number of vertical structures are included in a block, a delay occurs in applying voltage through a word line, which deteriorates memory performance, and if an excessive number of vertical structures are included in a block, the integration density is deteriorated.

[0007] Therefore, there is a need to propose a technology to solve the described problems and shortcomings.

[0008]

[0009] One embodiment proposes a three-dimensional random access memory and an operating method thereof, which uses at least one dummy electrode interposed between gate electrodes for the purpose of improving the application speed of a bit line voltage applied to a bit line vertical portion, to solve the problem of a decrease in the application speed of a bit line voltage applied to a bit line vertical portion.

[0010] One embodiment proposes a three-dimensional random access memory having a structure including at least one string select line slit that separates at least one gate electrode corresponding to a string select line for each string select line block and at least one word line slit that separates at least one gate electrode corresponding to a word line for each word line block to solve the disadvantages of a decrease in memory performance due to a delay in applying voltage through a word line when an excessive number of vertical structures are included in a block and a decrease in integration when an excessive number of vertical structures are included in a block.

[0011] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0012] According to one embodiment, a three-dimensional random access memory may include gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart from each other and stacked; at least one dummy electrode interposed between the gate electrodes; and vertical structures formed to extend vertically through the gate electrodes and the at least one dummy electrode, each of the vertical structures including a data storage pattern and a bit line vertical portion, and the data storage pattern forming memory cells corresponding to the gate electrodes.

[0013] According to one aspect, the at least one dummy electrode may be characterized as being used for the purpose of improving the application speed of the bit line voltage applied through the bit line vertical portion as the dummy voltage is applied.

[0014] According to another aspect, when the at least one dummy electrode is included in multiple numbers, the spacing or number of the dummy electrodes interposed between the gate electrodes may be controlled and determined based on the application speed of the bit line voltage applied through the bit line vertical portion.

[0015] According to another aspect, when the at least one dummy electrode is included in multiple numbers, the plurality of dummy electrodes may be formed such that the gap between the gate electrodes becomes narrower as it goes toward the bottom of the vertical portion of the bit line.

[0016] According to another aspect, when the at least one dummy electrode is included in multiple numbers, the plurality of dummy electrodes may be formed such that the gap between the gate electrodes becomes narrower as it goes toward the top of the vertical portion of the bit line.

[0017] According to another aspect, when the at least one dummy electrode is included in multiple numbers, the plurality of dummy electrodes may be characterized in that the gaps interposed between the gate electrodes are formed uniformly.

[0018] According to one embodiment, a memory operation method of a three-dimensional random access memory including gate electrodes formed horizontally extending on a substrate and spaced apart vertically and stacked; at least one dummy electrode interposed between the gate electrodes; and vertical structures formed vertically extending through the gate electrodes and the at least one dummy electrode, each of the vertical structures including a data storage pattern and a bit line vertical portion, the data storage pattern forming memory cells corresponding to the gate electrodes, may include the steps of: applying a bit line voltage having at least a portion of an operation voltage to the bit line vertical portion included in a selected vertical structure including a target memory cell to be a target of a memory operation among the vertical structures; applying a gate voltage having an opposite polarity to the bit line voltage and having a remaining portion of the operation voltage to a selected gate electrode corresponding to the target memory cell among the gate electrodes; grounding at least one unselected gate electrode, excluding the selected gate electrode, among the gate electrodes; and applying a dummy voltage to the at least one dummy electrode.

[0019] According to one embodiment, a memory operation method of a three-dimensional random access memory including gate electrodes formed to extend horizontally on a substrate and spaced apart vertically and stacked; at least one dummy electrode interposed between the gate electrodes; and vertical structures formed to extend vertically through the gate electrodes and the at least one dummy electrode, each of the vertical structures including a data storage pattern and a bit line vertical portion, the data storage pattern forming memory cells corresponding to the gate electrodes, may include the steps of: grounding the bit line vertical portion included in a selected vertical structure including a target memory cell to be a target of a memory operation among the vertical structures; applying an operation voltage to a selected gate electrode corresponding to the target memory cell among the gate electrodes; applying a pass voltage having at least a portion of the operation voltage to at least one unselected gate electrode, excluding the selected gate electrode, among the gate electrodes; and applying the dummy voltage to the at least one dummy electrode.

[0020]

[0021] According to one embodiment, a three-dimensional random access memory may include gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart from each other and stacked; vertical structures that penetrate the gate electrodes and extend vertically, each of the vertical structures including a data storage pattern and a bit line vertical portion, the data storage pattern forming memory cells corresponding to the gate electrodes; at least one string selection line slit that separates at least one gate electrode corresponding to a string selection line among the gate electrodes by string selection line block; and at least one word line slit that separates at least one gate electrode corresponding to a word line among the gate electrodes by word line block.

[0022] According to one aspect, the word line block may be characterized by including a plurality of string selection line blocks.

[0023] According to another aspect, the word line block may be characterized by including a greater number of the vertical structures than the string selection line block.

[0024] According to another aspect, the number of the vertical structures included in the word line block may be determined and controlled based on a speed at which an operating voltage is applied to a target memory cell of a vertical structure selected from among the vertical structures through the word line within the word line block.

[0025] According to another aspect, the at least one word line slit may be characterized as being used as a passage for removing sacrificial layers and filling a material constituting the gate electrodes during the process of forming the gate electrodes during the manufacturing process of the three-dimensional random access memory.

[0026] According to another aspect, each of the two ends of the gate electrodes may be characterized by having a step structure along the horizontal direction.

[0027] According to another aspect, the three-dimensional random access memory may be characterized in that it performs a memory operation in response to a voltage applied in both directions from word line plugs formed at both ends of the step structure at each end of the gate electrodes toward a selected vertical structure among the vertical structures.

[0028] One embodiment proposes a three-dimensional random access memory and an operating method thereof that uses at least one dummy electrode interposed between gate electrodes for the purpose of improving the speed of applying a bit line voltage applied to a vertical portion of a bit line, thereby solving the problem of a decrease in the speed of applying a bit line voltage applied to a vertical portion of a bit line.

[0029] One embodiment proposes a three-dimensional random access memory having a structure including at least one string select line slit for separating at least one gate electrode corresponding to a string select line for each string select line block and at least one word line slit for separating at least one gate electrode corresponding to a word line for each word line block, thereby resolving a disadvantage that a delay occurs in applying voltage through a word line when an excessive number of vertical structures are included in a block, thereby lowering memory performance, and a disadvantage that a density is lowered when an excessive number of vertical structures are included in a block, thereby achieving a technical effect of promoting high integration while ensuring memory performance.

[0030] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0031] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0032] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to one embodiment.

[0033] FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2.

[0034] Figures 4a to 4d are drawings for explaining dummy electrodes according to one embodiment.

[0035] FIG. 5 is a flowchart illustrating a memory operation method of a three-dimensional random access memory according to one embodiment.

[0036] FIG. 6 is a drawing for explaining an example of a memory operation method of the three-dimensional random access memory illustrated in FIG. 5.

[0037] FIG. 7 is a flowchart illustrating a memory operation method of a three-dimensional random access memory according to another embodiment.

[0038] FIG. 8 is a drawing for explaining an example of a memory operation method of the three-dimensional random access memory illustrated in FIG. 7.

[0039] FIG. 9 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments.

[0040] FIG. 10 is a plan view illustrating a three-dimensional random access memory according to one embodiment.

[0041] FIG. 11 is a plan view illustrating a three-dimensional random access memory according to another embodiment.

[0042] Fig. 12 is a cross-sectional view illustrating a three-dimensional random access memory according to embodiments, corresponding to a cross-section taken along line A-A' of Figs. 10 and 11.

[0043] FIG. 13 is a flow chart illustrating a method for manufacturing a three-dimensional random access memory according to one embodiment.

[0044] FIG. 14 is a flow chart illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment.

[0045] FIG. 15 is a flow chart illustrating an operating method of a three-dimensional random access memory according to embodiments.

[0046] FIG. 16 is a perspective view schematically illustrating an electronic system including a three-dimensional random access memory according to one embodiment.

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0048] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0049] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0050] Hereinafter, with reference to the drawings, a memory operation method of a three-dimensional random access memory having a structure in which each of the gate electrodes is formed in a plate shape extending in a horizontal direction and vertical structures formed to extend vertically while penetrating the gate electrodes form an array composed of a plurality of columns and rows on a horizontal plane will be described in detail.

[0051] The three-dimensional random access memory described below is based on a GAA (Gate-All-Around) based three-terminal selection element-based memory.

[0052]

[0053] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0054] Referring to FIG. 1, a three-dimensional random access memory according to one embodiment includes a plurality of bit line horizontal parts (BL1_horizontal part, BL2_horizontal part, BL3_horizontal part; BLH) and a plurality of bit line vertical parts (BL1_vertical part (BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part (BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part (BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV), and a plurality of word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n), A plurality of memories arranged at the intersections of a plurality of bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV) and a plurality of word lines (WL1(WL1 / 1, WL1 / 2, …, WL1 / n), WL2(WL2 / 1, WL2 / 2, …, WL2 / n), WL3(WL3 / 1, WL3 / 2, …, WL3 / n)) including WL3(WL3 / 1, WL3 / 2, …, WL3 / n)) Cells can be configured.Accordingly, a plurality of memory cells can form a plurality of memory cell strings (CSTR; hereinafter, cell strings) along a plurality of bit line vertical parts (BL1_vertical part (BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part (BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part (BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV).

[0055] The bit line horizontal portions (BLH) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0056] Each of the bit line horizontal portions (BLH) may have a plurality of cell strings (CSTR) connected in parallel. Each of the cell strings (CSTR) includes a bit line vertical portion (BLV), and each of the bit line horizontal portions (BLH) may have a plurality of bit line vertical portions (BLV) connected in parallel.

[0057] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may include memory cell transistors (MCT) arranged corresponding to word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n), WL3 (WL3 / 1, WL3 / 2, …, WL3 / n)) and string select transistors (SST; hereinafter, select transistors) arranged corresponding to string select lines (SSL1, SSL2, SSL3). Each of the memory cell transistors (MCT) may include a data storage element.

[0058] More specifically, one cell string (CSTR) may be composed of one select transistor (SST) located at the top of the string closest to the bit line horizontal portions (BLH) and a plurality of memory cell transistors (MCT) located at different distances from the bit line horizontal portions (BLH). That is, the memory cell transistors (MCT) may be connected in series while being arranged along the third direction (D3).

[0059] The select transistor (SST) can be controlled by a string select line (SSL), and the memory cell transistors (MCT) can be controlled by word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n), WL3 (WL3 / 1, WL3 / 2, …, WL3 / n)).

[0060] Here, the gate electrode (EL-SSL) of the selection transistor (SST) may be connected to the string selection line (SSL) and may be in an equipotential state, and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may be commonly connected to one of the word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n)) and may be in an equipotential state.

[0061] Additionally, between the plurality of word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n)), a plurality of dummy lines (D1 (D1 / 1, D1 / 2, ..., D1 / m), D2 (D2 / 1, D2 / 2, ..., D2 / m), D3 (D3 / 1, D3 / 2, ... D3 / m)) may be interposed.

[0062]

[0063] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to one embodiment, FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIGS. 4a to 4d are drawings for explaining dummy electrodes according to one embodiment.

[0064] The substrate (SUB) may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0065] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0066] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL), at least one dummy electrode (EL-D), and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0067] Referring back to FIG. 1, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n)) sequentially stacked on the substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0068] Each of the gate electrodes (EL-WL, EL-SSL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2), and may have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL-WL, EL-SSL) may be formed of a conductive material. For example, each of the gate electrodes (EL-WL, EL-SSL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL-WL, EL-SSL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0069] At this time, at least one dummy electrode (EL-D) may be interposed between the gate electrodes (EL-WL, EL-SSL). The at least one dummy electrode (EL-D) is formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and may be used for the purpose of improving the application speed of the bit line voltage applied through the bit line vertical portion (BLV) when the dummy voltage is applied. That is, when the dummy voltage is applied to at least one dummy electrode (EL-D), the application speed of the bit line voltage applied through the bit line vertical portion (BLV) can be improved.

[0070] Hereinafter, the improvement in the application speed of the bit line voltage applied through the bit line vertical portion (BLV) means that the speed at which the potential moves within the bit line vertical portion (BLV) as the bit line voltage is applied through the bit line vertical portion (BLV) is improved.

[0071] When at least one dummy electrode (EL-D) is included in multiple numbers, the spacing or number of the dummy electrodes (EL-D) interposed between the gate electrodes (EL-WL, EL-SSL) can affect the application speed of the bit line voltage applied through the bit line vertical portion (BLV).

[0072] For example, as illustrated in FIG. 4a, the closer at least one dummy electrode (EL-D) is positioned to the top of the bit line vertical portion (BLV), the more the delay of the bit line voltage applied through the bit line vertical portion (BLV) is reduced, thereby improving the application speed.

[0073] For another example, as illustrated in FIG. 4b, as the number of at least one dummy electrode (EL-D) increases, the delay of the bit line voltage applied through the bit line vertical portion (BLV) decreases, thereby improving the application speed.

[0074] Based on these characteristics, when at least one dummy electrode (EL-D) is included in multiple numbers, the spacing or number of the dummy electrodes (EL-D) interposed between the gate electrodes (EL-WL, EL-SSL) can be adjusted and determined based on the application speed of the bit line voltage applied through the bit line vertical portion (BLV). That is, the spacing or number of the dummy electrodes (EL-D) interposed between the gate electrodes (EL-WL, SSL) can be adjusted and determined so that the application speed of the bit line voltage applied through the bit line vertical portion (BLV) achieves a designed value.

[0075] In Fig. 3, the spacing between the plurality of dummy electrodes (EL-D) is illustrated as being uniform, but the spacing is not limited thereto and may not be uniform.

[0076] For example, a plurality of dummy electrodes (EL-D) can be formed so that the gap between the gate electrodes (EL-WL, EL-SSL) becomes narrower toward the bottom of the bit line vertical portion (BLV), as illustrated in FIG. 4c.

[0077] As another example, a plurality of dummy electrodes (EL-D) can be formed so that the gap between the gate electrodes (EL-WL, EL-SSL) becomes narrower toward the top of the bit line vertical portion (BLV), as illustrated in FIG. 4d.

[0078] Although not shown, one of the upper and lower ends of each of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL-WL, EL-SSL) and at least one dummy electrode (EL-D) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). For example, the electrode positioned at the top among the gate electrodes (EL-WL, EL-SSL) and the at least one dummy electrode (EL-D) may have the smallest length in the first direction (D1) and the largest distance from the substrate (SUB) in the third direction (D3). On the other hand, the electrode located at the bottom among the gate electrodes (EL-WL, EL-SSL) and at least one dummy electrode (EL-D) may have the longest length in the first direction (D1) and the closest distance from the substrate (SUB) in the third direction (D3).

[0079] Although each of the interlayer insulating layers (ILDs) is illustrated as having the same thickness, it is not limited thereto and may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL-WL, EL-SSL) and at least one dummy electrode (EL-D). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0080] A plurality of holes (H) penetrating a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the holes (H). The vertical structures (VS) may be a plurality of cell strings (CSTR) illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0081] The rows of vertical structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL-WL, EL-SSL) are formed in a plate shape, the vertical structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL-WL, EL-SSL). For example, as illustrated in FIG. 2, twelve vertical structures (VS) may form six columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical structures (VS) forming the array is not limited or restricted thereto.

[0082] As vertical structures (VS) are formed in a plate shape, the three-dimensional random access memory can have a structure in which the integration of memory cell strings is improved by forming an array composed of multiple columns and rows on the horizontal plane of gate electrodes (EL-WL, EL-SSL).

[0083] At this time, the vertical structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on the horizontal plane and to be misaligned with each other. For example, the vertical structures (VS) included in the first column may be arranged in the first and third rows, and the vertical structures (VS) included in the second column may be arranged in the second and fourth rows, such that the vertical structures (VS) included in the pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string may be further improved compared to the case where the vertical structures (VS) included in the pair of adjacent columns are arranged side by side in the same row on the horizontal plane.

[0084] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical structures (VS) is depicted as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0085] These vertical structures (VS) may correspond to the cell strings (CSTR) illustrated in FIG. 1.

[0086] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a bit line vertical portion (BLV), and a selection transistor (SST). In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open top, the bit line vertical portion (BLV) may have a shape that fills a space from the bottom to a certain height among the inner spaces of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP), and the selection transistor (SST) may have a shape that fills a space from the top to a certain depth among the inner spaces of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP). That is, the selection transistor (SST) may be positioned at the uppermost end of the inner spaces of the data storage pattern (DSP) and thus may be arranged on the upper part of the bit line vertical portion (BLV).

[0087] The data storage pattern (DSP) surrounds the outer wall of the bit line vertical portion (BLV) and can be in contact with the outer side walls of the gate electrodes (EL-WL, EL-SSL). Accordingly, regions of the data storage pattern (DSP) corresponding to the gate electrodes (EL-WL) can form memory cells in which a memory operation (a write operation including a program operation and an erase operation, and a read operation) is performed by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the bit line vertical portion (BLV). Hereinafter, applying a voltage to the bit line vertical portion (BLV) means that a voltage is applied to the bit line horizontal portion (BLH) connected to the bit line vertical portion (BLV) and transmitted to the bit line vertical portion (BLV).

[0088] The memory cells correspond to the memory cell transistors (MCT) illustrated in Fig. 1. To this end, the data storage pattern (DSP) may be a polarization-generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through gate electrodes (EL-WL) and a voltage applied to a bit line vertical portion (BLV), thereby representing a data value as a change in voltage, current, or resistance corresponding to the polarization state of charges.

[0089] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx or InOx can be used.

[0090] As another example, antiferroelectric materials can be used as data storage patterns (DSPs), and ZrO is an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge or one of the elements in group 2 of the periodic table) may be used.

[0091] Although the drawing shows the data storage pattern (DSP) as extending in a vertical direction (e.g., a third direction (D3)), it is not limited thereto and may have a structure of multiple segments spaced apart only in areas corresponding to the gate electrodes (EL-WL) on the outer wall of the bit line vertical portion (BLV).

[0092] The bottom surface of the data storage pattern (DSP) may be positioned at a level lower than the bottom surface of the gate electrodes (EL-WL) and at least one dummy electrode (EL-D), and may be formed to be in contact with the substrate (SUB).

[0093] A bit line vertical portion (BLV) (hereinafter, the bit line vertical portion (BLV) may be referred to as a vertical electrode) is a component used as a conductor rather than a channel in a three-dimensional random access memory, and may be connected to each of the bit line horizontal portions (BLH) located on the upper portions of the vertical structures (VS) through a select transistor (SST) included in each of the vertical structures (VS). To this end, the bit line vertical portion (BLV) may be brought into contact with the bit line horizontal portions (BLH) through the select transistor (SST) thereon, and an upper surface of the select transistor (SST) may be substantially coplanar with a data storage pattern (DSP).

[0094] The bit line vertical portion (BLV) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0095] The lower surface of the bit line vertical portion (BLV) may be positioned at a level lower than the lower surface of the lowest one of the gate electrodes (EL-WL, EL-SSL) and at least one dummy electrode (EL-D), and may be spaced apart from the substrate (SUB) by a certain amount or more, but is not limited thereto.

[0096] A select transistor (SST) may be configured to connect the bit line vertical portion (BLV) to the bit line horizontal portion (BLH) while being positioned above the bit line vertical portion (BLV).

[0097] More specifically, the select transistor (SST) may serve as a selector that turns on a selected vertical structure (Sel VS; selected memory cell string) that includes a target memory cell to be the target of a memory operation among vertical structures (VS) connected to the same bit line horizontal portion (BLH) and turns off at least one unselected vertical structure (Unsel VS; unselected memory cell string) that does not include the target memory cell.

[0098] For example, a selection transistor (SST) can be used to apply an operating voltage only to a selected vertical structure (Sel VS) among vertical structures (VS) connected to the same bit line horizontal portion (BLH) during a memory operation for a target memory cell, and to prevent the application of an operating voltage to at least one unselected vertical structure (Unsel VS). In this way, the selection transistor (SST) can prevent parasitic capacitance from being generated in at least one unselected vertical structure (Unsel VS) by preventing the application of an operating voltage to at least one unselected vertical structure (Unsel VS).

[0099] To this end, the selection transistor (SST) may be formed of a semiconductor material (e.g., polycrystalline silicon or an oxide semiconductor material) that selectively forms a channel to be turned on or off depending on an applied voltage. For example, the channel of the selection transistor (SST) may be formed of a semiconductor material that is turned on or off depending on an applied voltage, and the drain and source of the transistor (SST) may be formed by doping the semiconductor material with impurities (N-type impurities) to improve contact resistance with a bit line vertical portion (BLV) or a bit line horizontal portion (BLH).

[0100] The described selection transistor (SST) can be used not only as a selector, but also to pre-charge a vertical structure (VS). Specifically, the selection transistor (SST) can be used to fill a pre-charge voltage to pre-charge a selected vertical structure (Sel VS) including a target memory cell among the vertical structures (VS) during a read operation for the target memory cell.

[0101] Such a selection transistor (SST) is turned on or off under the control of a corresponding gate electrode (EL-SSL), and can activate or deactivate the included vertical structure (VS).

[0102] The selection transistor (SST) is not limited or restricted to the structure described above, and may have a structure further including a dielectric pattern (not shown). For example, the selection transistor (SST) may have a structure further including a dielectric pattern disposed on top of a data storage pattern (DSP) to correspond to the selection transistor (SST).

[0103] Additionally, the selection transistor (SST) may have a structure including a buried pattern (not shown) inside. For example, a buried pattern may be formed inside the selection transistor (SST) using a material that facilitates the diffusion of charges or holes (e.g., an intrinsic semiconductor material or a polycrystalline semiconductor material with excellent charge / hole mobility) to facilitate the formation of a channel by the selection transistor (SST).

[0104] Additionally, the select transistor (SST) may further include a barrier metal layer (not shown) arranged at a contact surface with the bit line vertical portion (BLV). The barrier metal layer may be optionally included or omitted depending on the material forming the bit line vertical portion (BLV). For example, the barrier metal layer may be formed of TiN when the material forming the bit line vertical portion (BLV) is tungsten (W).

[0105] At this time, at least two bit line horizontal parts (BLH) are positioned at the same height on the upper portion of the vertical structures (VS), and the vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS) so as to be connected to different bit line horizontal parts (BLH), respectively. That is, the vertical structures (VS) arranged in the same row in the array may be connected to different bit line horizontal parts (BLH), respectively, through the bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS).

[0106] A separation trench (not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench, thereby isolating the adjacent stacked structures (ST) from each other. For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0107] A capping insulating film (CAP) may be provided on the stacked structures (ST) and the vertical structures (VS). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0108] Bit line horizontal portions (BLH) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending along a second direction (D2) with a conductive material while being spaced apart from each other along a first direction (D2). The conductive material forming the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL-WL, EL-SSL).

[0109] The three-dimensional random access memory described above is not limited or restricted to the described structure, and can be implemented in various structures based on a vertical structure (VS) including a select transistor (SST) and a bit line vertical portion (BLV) according to an implementation example.

[0110] As described, the three-dimensional random access memory can perform memory operations in response to voltages applied between bit line horizontal portions (BLH) and bit line vertical portions (BLV), gate electrodes (EL-WL, EL-SSL), and at least one dummy electrode (EL-D).

[0111] Here, the three-dimensional random access memory can perform a memory operation on the selected target memory cell in response to a voltage applied between the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) and the selected gate electrode (Sel EL-WL, EL-SSL) while turning on (activating) only the selected vertical structure (Sel VS) including the target memory cell among the vertical structures (VS) connected to the same bit line horizontal portion (BLH) using a selection transistor (SST) and turning off (deactivating) at least one unselected vertical structure (Unsel VS). A detailed description thereof will be described below.

[0112] In particular, a three-dimensional random access memory can improve the application speed of a bit line voltage applied through a bit line vertical portion (BLV) by applying a dummy voltage to at least one dummy electrode (EL-D). A detailed description thereof will be provided below.

[0113]

[0114] FIG. 5 is a flow chart illustrating a memory operation method of a three-dimensional random access memory according to one embodiment, and FIG. 6 is a drawing for explaining an example of the memory operation method of the three-dimensional random access memory illustrated in FIG. 5.

[0115] The memory operation method described below performs a memory operation on a target memory cell, and is assumed to be performed by a three-dimensional random access memory having the structure described above with reference to FIGS. 1 to 4a to 4d.

[0116] In step (S510), the 3D random access memory applies an operating voltage (V) through a selected bit line horizontal portion (Sel BLH) connected to a selected vertical structure (Sel VS) including a target memory cell among the vertical structures (VS). OP ) with at least some value of bit line voltage (V BL ) is applied to the bit line vertical portion (Sel BLV) included in the selected vertical structure (Sel VS). OP ) with at least some value of bit line voltage (V BL ) can be applied. For example, a 3D random access memory can be applied with an operating voltage (V OP ) with a bit line voltage (V ) of half the value BL ) can be applied. In this case, the bit line voltage (V BL ) can be expressed as in Equation 1 below.

[0117] <Formula 1>

[0118] V BL=±1 / 2V OP

[0119] In step (S510), the three-dimensional random access memory can ground at least one unselected bit line horizontal portion (Unsel BLH) excluding a selected bit line horizontal portion (Sel BLH) among the bit line horizontal portions (BLH).

[0120] In step (S520), the 3D random access memory applies a bit line voltage (V) to the selected vertical structure (Sel VS). BL ) can turn on the selection transistor (SST) of the selected vertical structure (Sel VS) to be applied.

[0121] Turning on the selection transistor (SST) of the selected vertical structure (Sel VS) can be accomplished by applying a turn-on voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of the selected vertical structure (Sel VS).

[0122] In step (S530), the 3D random access memory applies a bit line voltage (V) to at least one unselected vertical structure (Unsel VS) that is connected to a bit line horizontal portion (Sel BLH) that is identical to a selected vertical structure (Sel VS) among unselected vertical structures (Unsel VS) that do not include a target memory cell. BL ) can be turned off to prevent at least one unselected vertical structure (Unsel VS) from being selected.

[0123] Turning on the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) can be accomplished by floating or grounding the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS), or by applying a turn-off voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS).

[0124] In this way, the 3D random access memory is configured to apply a bit line voltage (V) to at least one unselected vertical structure (Unsel VS) in step (S530). BL ) is turned off so that the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) is not applied, thereby preventing the parasitic capacitance from being generated in at least one unselected vertical structure (Unsel VS).

[0125] In step (S540), the 3D random access memory applies a bit line voltage (V) to a selected gate electrode (Sel EL-WL) corresponding to a target memory cell among the gate electrodes (EL-WL). BL ) and has opposite polarity and operating voltage (V OP ) with the remaining values ​​of the gate voltage (V GATE ) can be applied. For example, a 3D random access memory can be applied by applying a bit line voltage (V BL ) and has opposite polarity and operating voltage (V OP ) with a gate voltage (V ) of half the value GATE ) can be applied. In this case, the gate voltage (V GATE ) can be expressed as in Equation 2 below.

[0126] <Formula 2>

[0127] V GATE =±1 / 2V OP

[0128] For example, at step (S510) +1 / 2V OP This bit line voltage (V BL ) is authorized, -1 / 2V in step (S540) OP This gate voltage (V GATE ) can be authorized. For another example, -1 / 2 V in step (S510) OP This bit line voltage (V BL ) is authorized, +1 / 2V in step (S540) OP This gate voltage (V GATE ) can be authorized. For another example, in step (S510) +1 / 3V OP This bit line voltage (V BL ) is authorized, -2 / 3V in step (S540) OP This gate voltage (V GATE ) can be authorized. For another example, -1 / 3V in step (S510) OP This bit line voltage (V BL ) is authorized, +2 / 3V in step (S540) OP This gate voltage (V GATE ) can be authorized. For another example, in step (S510) +3 / 4V OP This bit line voltage (V BL ) is authorized, -1 / 4V in step (S540) OP This gate voltage (V GATE ) can be authorized. For another example, -3 / 4V in step (S510) OP This bit line voltage (V BL ) is authorized, +1 / 4V in step (S540) OP This gate voltage (V GATE ) can be authorized.

[0129] In this way, the operating voltage (V) has opposite polarity in step (S510) and step (S540). OP ) with at least some value of bit line voltage (V BL ) and operating voltage (V OP) with the remaining values ​​of the gate voltage (V GATE ) are applied to the target memory cell, as shown in Equation 3 below. BL , V GATE ) is the operating voltage (V) OP ) may be authorized.

[0130] <Formula 3>

[0131] (±1 / 2V OP )-(±1 / 2V OP )=V OP

[0132] That is, the 3D random access memory applies the operating voltage (V) to the target memory cell through steps (S510 and S540). OP ) can be used to perform a memory operation on the target memory cell.

[0133] The 3D random access memory is configured such that a gate voltage (V) is applied to a gate electrode (Sel EL-WL) selected through step (S540) while a selection transistor (SST) of at least one unselected vertical structure (Unsel VS) is turned off through step (S530). GATE ), it is possible to prevent a memory operation from occurring for a memory cell corresponding to a selected gate electrode (Sel EL-WL) among memory cells of at least one unselected vertical structure (Unsel VS).

[0134] In step (S550), the three-dimensional random access memory can ground at least one unselected gate electrode (Unsel EL-WL) among the gate electrodes (EL-WL) except for the selected gate electrode (Sel EL-WL).

[0135] In step (S560), the 3D random access memory applies a dummy voltage (V) to at least one dummy electrode (EL-D). DUMMY ) can be authorized.

[0136] At this time, the 3D random access memory is, in step (S560), a dummy voltage (V DUMMY ) is applied to at least one dummy electrode (EL-D), thereby applying a bit line voltage (V) through the bit line vertical portion (BLV). BL ) can improve the authorization speed.

[0137] Here, a dummy voltage (V) is applied to at least one dummy electrode (EL-D). DUMMY ) is a condition in which no memory operation occurs for at least one memory cell corresponding to at least one dummy electrode (EL-D) among data storage patterns (DSP) (a condition in which no significant polarization occurs in at least one memory cell corresponding to at least one dummy electrode (EL-D) among data storage patterns (DSP)) and a bit line voltage (V) applied through a bit line vertical portion (BLV) BL ) can be adjusted and determined to a value that satisfies the condition for improving the application speed of the memory cell. The occurrence of significant polarization in at least one memory cell means that polarization occurs in a state and degree that is not read as if a write operation was performed in a read operation. For example, a dummy voltage (V) applied to at least one dummy electrode (EL-D) DUMMY ) is the bit line voltage (V BL ) can have the same polarity and the same value.

[0138] The described steps (S510 to S560) may be sequentially performed in ascending order of the drawing numbers, but are not limited thereto. For example, after step (S560) is performed first, steps (S510 to S550) may be sequentially performed in ascending order of the drawing numbers. In this way, the order in which steps (S510 to S560) are performed is determined by a dummy voltage (V) applied to at least one dummy electrode (EL-D). DUMMY ), the bit line voltage (V) applied through the bit line vertical portion (BLV) BL) can be freely adjusted, assuming that the approval speed is improved.

[0139] The memory operation described above may be a write operation for a target memory cell (a programming operation that writes data of "1" to the target memory cell or an erase operation that writes data of "0" to the target memory cell).

[0140] Although the gate electrodes (EL-WL) are shown as being divided by block in FIG. 6, the present invention is not limited thereto, and the gate electrodes (EL-WL) may have a structure in which they are connected substantially independently of the blocks. Even in this case, the gate electrode (EL-SSL) of the selection transistor (SST) may have a structure in which the gate electrode (EL-SSL) of the selection transistor (SST) is divided by block in order to turn on or off the selection transistor (SST) by block.

[0141]

[0142] FIG. 7 is a flowchart illustrating a memory operation method of a three-dimensional random access memory according to another embodiment.

[0143] FIG. 8 is a drawing for explaining an example of a memory operation method of the three-dimensional random access memory illustrated in FIG. 7.

[0144] The memory operation method described below performs a memory operation on a target memory cell, and is assumed to be performed by a three-dimensional random access memory having the structure described above with reference to FIGS. 1 to 4a to 4d.

[0145] In step (S710), the three-dimensional random access memory can ground a bit line vertical portion (Sel BLV) included in the selected vertical structure (Sel VS) by grounding a selected bit line horizontal portion (Sel BLH) connected to a selected vertical structure (Sel VS) including a target memory cell among the vertical structures (VS).

[0146] In step (S710), the three-dimensional random access memory can also ground at least one unselected bit line horizontal portion (Unsel BLH) other than the selected bit line horizontal portion (Sel BLH) among the bit line horizontal portions (BLH).

[0147] In step (S720), the 3D random access memory applies an operating voltage (V) to the selected vertical structure (Sel VS). OP ) can turn on the selection transistor (SST) of the selected vertical structure (Sel VS) to be applied.

[0148] Turning on the selection transistor (SST) of the selected vertical structure (Sel VS) can be accomplished by applying a turn-on voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of the selected vertical structure (Sel VS).

[0149] In step (S730), the 3D random access memory applies an operating voltage (V) to at least one unselected vertical structure (Unsel VS) that is connected to a bit line horizontal portion (Sel BLH) that is identical to the selected vertical structure (Sel VS) among the unselected vertical structures (Unsel VS) that do not include a target memory cell. OP ) can be turned off to prevent at least one unselected vertical structure (Unsel VS) from being selected.

[0150] Turning on the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) can be accomplished by floating or grounding the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS), or by applying a turn-off voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS).

[0151] In this way, the 3D random access memory is configured to apply an operating voltage (V) to at least one unselected vertical structure (Unsel VS) in step (S730). OP ) is turned off so that the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) is not applied, thereby preventing the parasitic capacitance from being generated in at least one unselected vertical structure (Unsel VS).

[0152] In step (S740), the 3D random access memory applies an operating voltage (V) to a selected gate electrode (Sel EL-WL) corresponding to a target memory cell among the gate electrodes (EL-WL). OP ) can be applied. Since the selection transistor (SST) of the selected vertical structure (Sel VS) including the target memory cell is turned on in step (S720), the target memory cell is supplied with an operating voltage (V OP ) may be authorized.

[0153] In step (S750), the 3D random access memory applies an operating voltage (V) to at least one unselected gate electrode (Unsel EL-WL) other than the selected gate electrode (Sel EL-WL) among the gate electrodes (EL-WL). OP ) with at least some value of the pass voltage (V PASS ) can be applied. For example, a 3D random access memory can be applied with an operating voltage (V OP) with a pass voltage of half the value of PASS =1 / 2V OP ) can be authorized.

[0154] The 3D random access memory is configured such that a pass voltage (V) is applied to at least one unselected gate electrode (Unsel EL-WL) through a step (S750) while a selection transistor (SST) of at least one unselected vertical structure (Unsel VS) is turned off through a step (S730). PASS ) was applied, so the pass voltage (V PASS ) to a bit line vertical portion (BLV) of at least one unselected vertical structure (Unsel VS), thereby preventing a memory operation from occurring for a memory cell corresponding to a selected gate electrode (Sel EL-WL) among the memory cells of at least one unselected vertical structure (Unsel VS).

[0155] In step (S760), the 3D random access memory applies a dummy voltage (V) to at least one dummy electrode (EL-D). DUMMY ) can be authorized.

[0156] At this time, the 3D random access memory is, in step (S760), a dummy voltage (V DUMMY ) is applied to at least one dummy electrode (EL-D), thereby applying a bit line voltage (V) through the bit line vertical portion (BLV). BL ) can improve the authorization speed.

[0157] Here, a dummy voltage (V) is applied to at least one dummy electrode (EL-D). DUMMY) is a condition in which no memory operation occurs for at least one memory cell corresponding to at least one dummy electrode (EL-D) among data storage patterns (DSP) (a condition in which no significant polarization occurs in at least one memory cell corresponding to at least one dummy electrode (EL-D) among data storage patterns (DSP)) and a bit line voltage (V) applied through a bit line vertical portion (BLV) BL ) can be adjusted and determined to a value that satisfies the condition for improving the application speed of the memory cell. The occurrence of significant polarization in at least one memory cell means that polarization occurs in a state and degree that is not read as if a write operation was performed in a read operation. For example, a dummy voltage (V) applied to at least one dummy electrode (EL-D) DUMMY ) is the aforementioned pass voltage (V PSASS ) can have a value less than .

[0158] The described steps (S710 to S760) may be sequentially performed in ascending order of the drawing numbers, but are not limited thereto. For example, after step (S760) is performed first, steps (S710 to S750) may be sequentially performed in ascending order of the drawing numbers. In this way, the order in which steps (S710 to S760) are performed is determined by applying a dummy voltage (V) to at least one dummy electrode (EL-D). DUMMY ), the bit line voltage (V) applied through the bit line vertical portion (BLV) BL ) can be freely adjusted, assuming that the approval speed is improved.

[0159] The memory operation described above may be a write operation for a target memory cell (a programming operation that writes data of "1" to the target memory cell or an erase operation that writes data of "0" to the target memory cell).

[0160] Although the gate electrodes (EL-WL) are shown as being divided by block in FIG. 8, the present invention is not limited thereto, and the gate electrodes (EL-WL) may have a structure in which they are connected substantially independently of the blocks. Even in this case, the gate electrode (EL-SSL) of the selection transistor (SST) may have a structure in which the gate electrode (EL-SSL) of the selection transistor (SST) is divided by block in order to turn on or off the selection transistor (SST) by block.

[0161]

[0162] Hereinafter, with reference to the drawings, a memory operation method of a three-dimensional random access memory having a structure in which each of the gate electrodes is formed in a plate shape extending in a horizontal direction and vertical structures formed to extend vertically while penetrating the gate electrodes form an array composed of a plurality of columns and rows on a horizontal plane will be described in detail.

[0163] The three-dimensional random access memory described below is based on a GAA (Gate-All-Around) based three-terminal selection element-based memory.

[0164]

[0165] Figure 9 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0166] Referring to FIG. 9, a three-dimensional random access memory according to an embodiment includes a plurality of bit line horizontal parts (BL1_horizontal part, BL2_horizontal part, BL3_horizontal part; BLH) and a plurality of bit line vertical parts (BL1_vertical part (BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part (BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part (BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part), BL4_vertical part (BL4 / 1_Vertical part, BL4 / 2_Vertical part, BL4 / 3_Vertical part); BLV), and a plurality of words. Multiple bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part), BL4_vertical part(BL4 / 1_Vertical part, BL4 / 2_Vertical part, BL4 / 3_Vertical part)) including lines (WL1(WL1 / 1, WL1 / 2, …, WL1 / n), WL2(WL2 / 1, WL2 / 2, …, WL2 / n));A plurality of memory cells can be configured to be arranged at the intersection of a plurality of word lines (BLV) and a plurality of word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)). Accordingly, a plurality of memory cells can form a plurality of memory cell strings (CSTR; hereinafter, cell strings) along a plurality of bit line vertical parts (BL1_vertical part (BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part (BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part (BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part), BL4_vertical part (BL4 / 1_Vertical part, BL4 / 2_Vertical part, BL4 / 3_Vertical part); BLV).

[0167] The bit line horizontal portions (BLH) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0168] Each of the bit line horizontal portions (BLH) may have a plurality of cell strings (CSTR) connected in parallel. Each of the cell strings (CSTR) includes a bit line vertical portion (BLV), and each of the bit line horizontal portions (BLH) may have a plurality of bit line vertical portions (BLV) connected in parallel.

[0169] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may include memory cell transistors (MCT) arranged corresponding to word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) and string select transistors (SST; hereinafter, select transistors) arranged corresponding to string select lines (SSL1, SSL2, SSL3). Each of the memory cell transistors (MCT) may include a data storage element.

[0170] More specifically, one cell string (CSTR) may be composed of one select transistor (SST) located at the top of the string closest to the bit line horizontal portions (BLH) and a plurality of memory cell transistors (MCT) located at different distances from the bit line horizontal portions (BLH). That is, the memory cell transistors (MCT) may be connected in series while being arranged along the third direction (D3).

[0171] The select transistor (SST) can be controlled by a string select line (SSL), and the memory cell transistors (MCT) can be controlled by word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)).

[0172] Here, the gate electrode (EL-SSL) of the selection transistor (SST) may be connected to the string selection line (SSL) and may be in an equipotential state, and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may be commonly connected to one of the word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) and may be in an equipotential state.

[0173] That is, the gate electrode (EL-SSL) of the selection transistor (SST) may mean a string selection line (SSL), and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may mean word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)).

[0174] A string select line (SSL) can be shared by cell strings (CSTR) included in the same string select line block (SB1, SB2, SB3, SB4; SB) (e.g., cell strings (CSTR) located in the same column (Column) as illustrated in the drawing), and word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) can be shared by cell strings (CSTR) included in the same word line block (WB1, WB2; WB) (e.g., cell strings (CSTR) located in two adjacent columns as illustrated in the drawing).

[0175]

[0176] FIG. 10 is a plan view illustrating a three-dimensional random access memory according to one embodiment, FIG. 11 is a plan view illustrating a three-dimensional random access memory according to another embodiment, and FIG. 12 is a cross-sectional view illustrating a three-dimensional random access memory according to embodiments, which corresponds to a cross-section taken along line A-A' of FIGS. 10 and 11.

[0177] The substrate (SUB) may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0178] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0179] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0180] Referring again to FIG. 9, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) sequentially stacked on the substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0181] Each of the gate electrodes (EL-WL, EL-SSL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2), and may have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL-WL, EL-SSL) may be formed of a conductive material. For example, each of the gate electrodes (EL-WL, EL-SSL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL-WL, EL-SSL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0182] As illustrated in FIG. 10, the lower end of each of the stacked structures (ST) may have a stepwise structure (SS) along the first direction (D1). More specifically, the stepwise structure of the gate electrodes (EL-WL, EL-SSL) included in the stacked structures (ST) may be implemented as the length of the gate electrodes (EL-WL, EL-SSL) in the first direction (D1) decreases as they move away from the substrate (SUB). For example, the electrode positioned at the uppermost position among the gate electrodes (EL-WL, EL-SSL) may be the electrode having the largest distance from the substrate (SUB) in the third direction (D3) and thus may have the smallest length in the first direction (D1). On the other hand, the electrode located at the lowest position among the gate electrodes (EL-WL, EL-SSL) is the electrode that is spaced the closest distance from the substrate (SUB) in the third direction (D3) and may have the longest length in the first direction (D1).

[0183] However, the present invention is not limited thereto, and as illustrated in FIG. 11, the upper end of each of the stacked structures (ST) may also have a step structure (SS) along the first direction (D1). Although not illustrated in the drawing, a word line plug (not illustrated) may be formed on the upper surface of each of the step structures (SS) of the gate electrodes (EL-WL, EL-SSL).

[0184] Accordingly, the three-dimensional random access memory can perform a memory operation in response to a voltage applied in both directions from the word line plugs at both ends formed in the step structure (SS) at each end of the gate electrodes (EL-WL, EL-SSL) toward a selected vertical structure (Sel VS) including a target memory cell among the vertical structures (VS).

[0185] Although each of the interlayer insulating layers (ILDs) is illustrated as having the same thickness, it is not limited thereto and may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL-WL, EL-SSL). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0186] A plurality of holes (H) penetrating a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the holes (H). The vertical structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 9, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0187] The rows of vertical structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL-WL, EL-SSL) are formed in a plate shape, the vertical structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL-WL, EL-SSL). For example, as illustrated in FIG. 10, 18 vertical structures (VS) may form 12 columns and 3 rows and penetrate one of the stacked structures (ST). However, the number of vertical structures (VS) forming the array is not limited or restricted thereto.

[0188] As vertical structures (VS) are formed in a plate shape, the three-dimensional random access memory can have a structure in which the integration of memory cell strings is improved by forming an array composed of multiple columns and rows on the horizontal plane of gate electrodes (EL-WL, EL-SSL).

[0189] At this time, the vertical structures (VS) included in a pair of adjacent columns may be arranged in different rows on the horizontal plane and shifted so as to be misaligned with each other. For example, the vertical structures (VS) included in the first column may be arranged in the first and third rows, and the vertical structures (VS) included in the second column may be arranged in the second row, such that the vertical structures (VS) included in the pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string may be further improved compared to the case where the vertical structures (VS) included in the pair of adjacent columns are arranged side by side in the same row on the horizontal plane.

[0190] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical structures (VS) is depicted as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0191] These vertical structures (VS) may correspond to the cell strings (CSTR) illustrated in FIG. 9.

[0192] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a bit line vertical portion (BLV), and a selection transistor (SST). In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open top, the bit line vertical portion (BLV) may have a shape that fills a space from the bottom to a certain height among the inner spaces of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP), and the selection transistor (SST) may have a shape that fills a space from the top to a certain depth among the inner spaces of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP). That is, the selection transistor (SST) may be positioned at the uppermost end of the inner spaces of the data storage pattern (DSP) and thus may be arranged on the upper part of the bit line vertical portion (BLV).

[0193] The data storage pattern (DSP) surrounds the outer wall of the bit line vertical portion (BLV) and can be in contact with the outer side walls of the gate electrodes (EL-WL, EL-SSL). Accordingly, regions of the data storage pattern (DSP) corresponding to the gate electrodes (EL-WL) can form memory cells in which a memory operation (a write operation including a program operation and an erase operation, and a read operation) is performed by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the bit line vertical portion (BLV). Hereinafter, applying a voltage to the bit line vertical portion (BLV) means that a voltage is applied to the bit line horizontal portion (BLH) connected to the bit line vertical portion (BLV) and transmitted to the bit line vertical portion (BLV).

[0194] The memory cells correspond to the memory cell transistors (MCT) illustrated in Fig. 9. To this end, the data storage pattern (DSP) may be a polarization-generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through gate electrodes (EL-WL) and a voltage applied to a bit line vertical portion (BLV), thereby representing a data value as a change in voltage, current, or resistance corresponding to the polarization state of charges.

[0195] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx or InOx can be used.

[0196] As another example, antiferroelectric materials can be used as data storage patterns (DSPs), and ZrO is an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge or one of the elements in group 2 of the periodic table) may be used.

[0197] Although the drawing shows the data storage pattern (DSP) as extending in a vertical direction (e.g., a third direction (D3)), it is not limited thereto and may have a structure of multiple segments spaced apart only in areas corresponding to the gate electrodes (EL-WL) on the outer wall of the bit line vertical portion (BLV).

[0198] The bottom surface of the data storage pattern (DSP) may be positioned at a lower level than the bottom surface of the lowest one among the gate electrodes (EL-WL) and may be formed to be in contact with the substrate (SUB).

[0199] A bit line vertical portion (BLV) (hereinafter, the bit line vertical portion (BLV) may be referred to as a vertical electrode) is a component used as a conductor rather than a channel in a three-dimensional random access memory, and may be connected to each of the bit line horizontal portions (BLH) located on the upper portions of the vertical structures (VS) through a select transistor (SST) included in each of the vertical structures (VS). To this end, the bit line vertical portion (BLV) may be brought into contact with the bit line horizontal portions (BLH) through the select transistor (SST) thereon, and an upper surface of the select transistor (SST) may be substantially coplanar with a data storage pattern (DSP).

[0200] The bit line vertical portion (BLV) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0201] The lower surface of the bit line vertical portion (BLV) may be positioned at a level lower than the lower surface of the lowest one of the gate electrodes (EL-WL, EL-SSL) and may be spaced apart from the substrate (SUB) by a certain amount or more, but is not limited thereto.

[0202] A select transistor (SST) may be configured to connect the bit line vertical portion (BLV) to the bit line horizontal portion (BLH) while being positioned above the bit line vertical portion (BLV).

[0203] More specifically, the select transistor (SST) may serve as a selector that turns on a selected vertical structure (Sel VS; selected memory cell string) that includes a target memory cell to be the target of a memory operation among vertical structures (VS) connected to the same bit line horizontal portion (BLH) and turns off at least one unselected vertical structure (Unsel VS; unselected memory cell string) that does not include the target memory cell.

[0204] For example, a selection transistor (SST) can be used to apply an operating voltage only to a selected vertical structure (Sel VS) among vertical structures (VS) connected to the same bit line horizontal portion (BLH) during a memory operation for a target memory cell, and to prevent the application of an operating voltage to at least one unselected vertical structure (Unsel VS). In this way, the selection transistor (SST) can prevent parasitic capacitance from being generated in at least one unselected vertical structure (Unsel VS) by preventing the application of an operating voltage to at least one unselected vertical structure (Unsel VS).

[0205] To this end, the selection transistor (SST) may be formed of a semiconductor material (e.g., polycrystalline silicon or an oxide semiconductor material) that selectively forms a channel to be turned on or off depending on an applied voltage. For example, the channel of the selection transistor (SST) may be formed of a semiconductor material that is turned on or off depending on an applied voltage, and the drain and source of the transistor (SST) may be formed by doping the semiconductor material with impurities (N-type impurities) to improve contact resistance with a bit line vertical portion (BLV) or a bit line horizontal portion (BLH).

[0206] The described selection transistor (SST) can be used not only as a selector, but also to pre-charge a vertical structure (VS). Specifically, the selection transistor (SST) can be used to fill a pre-charge voltage to pre-charge a selected vertical structure (Sel VS) including a target memory cell among the vertical structures (VS) during a read operation for the target memory cell.

[0207] Such a selection transistor (SST) is turned on or off under the control of a corresponding gate electrode (EL-SSL), and can activate or deactivate the included vertical structure (VS).

[0208] The selection transistor (SST) is not limited or restricted to the structure described above, and may have a structure further including a dielectric pattern (not shown). For example, the selection transistor (SST) may have a structure further including a dielectric pattern disposed on top of a data storage pattern (DSP) to correspond to the selection transistor (SST).

[0209] Additionally, the selection transistor (SST) may have a structure including a buried pattern (not shown) inside. For example, a buried pattern may be formed inside the selection transistor (SST) using a material that facilitates the diffusion of charges or holes (e.g., an intrinsic semiconductor material or a polycrystalline semiconductor material with excellent charge / hole mobility) to facilitate the formation of a channel by the selection transistor (SST).

[0210] Additionally, the select transistor (SST) may further include a barrier metal layer (not shown) arranged at a contact surface with the bit line vertical portion (BLV). The barrier metal layer may be optionally included or omitted depending on the material forming the bit line vertical portion (BLV). For example, the barrier metal layer may be formed of TiN when the material forming the bit line vertical portion (BLV) is tungsten (W).

[0211] Although Fig. 12 illustrates that the bit line horizontal portions (BLH) are positioned at different heights on the upper portions of the vertical structures (VS), this is a three-dimensional illustration to help understand the structure of a three-dimensional random access memory, and in reality, all the bit line horizontal portions (BLH) on the upper portions of the vertical structures (VS) may be positioned at the same height. In this way, since at least two bit line horizontal portions (BLH) are positioned at the same height on the upper portions of the vertical structures (VS), the vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) arranged at a position offset from the center of each of the vertical structures (VS) in order to be respectively connected to different bit line horizontal portions (BLH). That is, vertical structures (VS) arranged in the same row in the array can be connected to different bit line horizontal portions (BLH) through bit line plugs (BLPG) arranged at positions that are offset from the center of each of the vertical structures (VS).

[0212] At least one word line slit (WS) extending in a first direction (D1) and formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant may be provided between adjacent stacked structures (ST). The at least one word line slit (WS) is a component that separates at least one gate electrode (EL-WL) corresponding to a word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) among the gate electrodes (EL-SSL, EL-WL) into word line blocks (WB1, WB2; WB), and may have a depth etched to an upper surface of the substrate (SUB) in a vertical direction (e.g., a third direction (D3)).

[0213] Here, separating at least one gate electrode (EL-WL) by word line block (WB1, WB2; WB) means that at least one gate electrode (EL-WL) has a structure in which it is physically and electrically separated by word line block (WB1, WB2; WB). For example, the word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) may be physically and electrically separated from the word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n)) included in the first word line block (WB1) and the word lines (WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) included in the second word line block (WB2) by at least one word line slit (WS).

[0214] Each of the word line blocks (WB1, WB2; WB) may include a plurality of string select line blocks (SB1, SB2, SB3, SB4; SB4). Such string select line blocks (SB1, SB2, SB3, SB4) may be separated by at least one string select slit (SS). More specifically, at least one string select slit (SS) is provided that extends in a first direction (D1) and is formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant, so that at least one gate electrode (EL-SSL) corresponding to a string select line (SSL) among the gate electrodes (EL-SSL, EL-WL) may be separated for each string select line block (SB1, SB2, SB3, SB4; SB). To this end, at least one string selection slit (SS) may have an etched depth up to a depth of at least one gate electrode (EL-SSL) corresponding to the string selection line (SSL) in the vertical direction (e.g., the third direction (D3)).

[0215] Likewise, separating at least one gate electrode (EL-SSL) by string selection line block (SB1, SB2, SB3, SB4; SB) means that at least one gate electrode (EL-SSL) has a structure in which it is physically and electrically separated by string selection line block (SB1, SB2, SB3, SB4; SB). For example, the string selection lines (SSL1, SSL2, SSL3, SSL4) can be physically and electrically separated by at least one string selection slit (SS) into a string selection line (SSL1) included in a first string selection line block (SB1), a string selection line (SSL2) included in a second string selection line block (SB2), a string selection line (SSL3) included in a third string selection line block (SB3), and a string selection line (SSL4) included in a fourth string selection line block (SB4).

[0216] As each of the word line blocks (WB1, WB2; WB) has a structure including multiple string select line blocks (SB1, SB2, SB3, SB4; SB4), each of the word line blocks (WB1, WB2; WB) can include a larger number of vertical structures (VS) than each of the string select line blocks. For example, as illustrated in FIGS. 10 and 11, each of the string select line blocks (SB1, SB2, SB3, SB4; SB4) can include 9 vertical structures (VS), and each of the word line blocks (WB1, WB2; WB) can include 18 vertical structures (VS).

[0217] The number of vertical structures (VS) included in each of the above described and described string selection line blocks (SB1, SB2, SB3, SB4; SB4) and the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) are merely examples and can be adaptively determined and adjusted.

[0218] For example, the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) can be determined and controlled based on the speed at which an operating voltage is applied to a target memory cell of a selected vertical structure (Sel VS) among the vertical structures (VS) through a word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line block (WB). For a more specific example, the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) can be determined and controlled such that the speed at which the operating voltage is applied to the target memory cell of the selected vertical structure (Sel VS) among the vertical structures (VS) through the word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line block (WB) is equal to or greater than a preset threshold speed value. In terms of practical design, the number of vertical structures (VS) included in each of the word line blocks (WB1, WB2; WB) can be determined and controlled within a range of 9000 to 1000.

[0219] At least one word line slit (WS) described above can be used as a passage for removing sacrificial layers (not shown) and filling a material constituting the gate electrodes (EL-SSL, EL-WL) in the process of forming gate electrodes (EL-SSL, EL-WL) during the manufacturing process of a 3D random access memory. For example, at least one word line slit (WS) can be used as a passage for removing sacrificial layers in the process of forming gate electrodes (EL-SSL, EL-WL), or can be used as a passage for filling a material constituting the gate electrodes (EL-SSL, EL-WL) in spaces from which sacrificial layers have been removed.

[0220] A capping insulating film (not shown) may be provided on the stacked structures (ST) and the vertical structures (VS). The capping insulating film may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD). The capping insulating film may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film. The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0221] Bit line horizontal portions (BLH) may be provided on a capping insulating film and a bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending along a second direction (D2) with a conductive material while being spaced apart from each other along a first direction (D2). The conductive material forming the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL-WL, EL-SSL).

[0222] The three-dimensional random access memory described above can perform a memory operation in response to a voltage applied between bit line horizontal portions (BLH) and bit line vertical portions (BLV) and gate electrodes (EL-WL, EL-SSL) based on the described structure.

[0223] Here, the three-dimensional random access memory can perform a memory operation on the selected target memory cell in response to a voltage applied between the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) and the selected gate electrode (Sel EL-WL, EL-SSL) while turning on (activating) only the selected vertical structure (Sel VS) including the target memory cell among the vertical structures (VS) connected to the same bit line horizontal portion (BLH) using a selection transistor (SST) and turning off (deactivating) at least one unselected vertical structure (Unsel VS).

[0224]

[0225] Fig. 13 is a flowchart illustrating a method for manufacturing a three-dimensional random access memory according to one embodiment. The manufacturing method described below is a manufacturing method based on a gate-first process, and includes steps (S1310 to S1330) for manufacturing a three-dimensional random access memory having the structure described above with reference to Figs. 9 to 12, and is assumed to be performed by an automated and mechanized manufacturing system.

[0226] In step (S1310), the manufacturing system can prepare a semiconductor structure (SEMUI-STR).

[0227] More specifically, the manufacturing system can prepare a semiconductor structure (SEMI-STR) including gate electrodes (EL-SSL, EL-WL) that are formed horizontally and vertically spaced apart from each other on a substrate (SUB) and vertical structures (VS) that extend vertically and penetrate the gate electrodes (EL-SSL, EL-WL). Each of the vertical structures (VS) includes a data storage pattern (DSP) and a bit line vertical portion (BLV), and the data storage pattern (DSP) can configure memory cells corresponding to the gate electrodes (EL-WL).

[0228] At this time, the semiconductor structure (SEMI-STR) may include gate electrodes (EL-SSL, EL-WL) each having a step structure (SS) along the horizontal direction at both ends.

[0229] In step (S1320), the manufacturing system can form at least one string selection line slit (SS) that separates at least one gate electrode (EL-SSL) corresponding to a string selection line (SSL) among the gate electrodes (EL-SSL, EL-WL) by string selection line block (SB1, SB2, SB3, SB4; SB).

[0230] Specifically, the manufacturing system can form at least one string selection slit (SS) by etching to a depth of at least one gate electrode (EL-SSL) corresponding to a string selection line (SSL) in a vertical direction (e.g., a third direction (D3)) and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0231] In step (S1330), the manufacturing system can form at least one word line slit (WS) that separates at least one gate electrode (EL-WL) corresponding to a word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) among the gate electrodes (EL-SSL, EL-WL) by word line block (WB1, WB2; WB).

[0232] More specifically, the manufacturing system can form at least one word line slit (WS) by etching the upper surface of the substrate (SUB) in a vertical direction (e.g., a third direction (D3)) so as to expose the upper surface, and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0233] Additionally, in step (S1330), the manufacturing system can form at least one word line slit (WS) such that the word line blocks (WB1, WB2; WB) include a plurality of string select line blocks (SB1, SB2, SB3, SB4; SB).

[0234] Additionally, in step (S1330), the manufacturing system can form at least one word line slit (WS) such that the word line blocks (WB1, WB2; WB) include a greater number of vertical structures (VS) than the string select line blocks (SB1, SB2, SB3, SB4; SB).

[0235] The position at which at least one string selection slit (SS) is formed in step (S1320) and the position at which at least one word line slit (WS) is formed in step (S1330) can be adaptively determined and adjusted according to the number of vertical structures (VS) to be included in each of the string selection line blocks (SB1, SB2, SB3, SB4; SB) and the number of vertical structures (VS) to be included in each of the word line blocks (WB1, WB2; WB).

[0236] In determining and controlling the position at which at least one word line slit (WS) is formed in step (S1330), the manufacturing system can first determine and control the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the speed at which the operating voltage is applied to the memory cell through the word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line block (SB1, SB2, SB3, SB4; SB). For example, the manufacturing system can determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) such that the speed at which the operating voltage is applied to the memory cells through the word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line blocks (SB1, SB2, SB3, SB4; SB) is greater than a preset threshold speed value.

[0237] That is, the manufacturing system can first determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the speed at which the operating voltage is applied to the memory cell through the word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line block (SB1, SB2, SB3, SB4; SB), and then determine and adjust the position at which at least one word line slit (WS) is formed according to the number of vertical structures (VS) determined and adjusted.

[0238]

[0239] Fig. 14 is a flowchart illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment. The manufacturing method described below is a manufacturing method based on a gate replacement process, and includes steps (S1410 to S1440) for manufacturing a three-dimensional random access memory having the structure described above with reference to Figs. 9 to 12, and is assumed to be performed by an automated and mechanized manufacturing system.

[0240] In step (S1410), the manufacturing system can prepare a semiconductor structure (SEMUI-STR).

[0241] More specifically, the manufacturing system can prepare a semiconductor structure (SEMI-STR) including sacrificial layers (SAC) that are formed horizontally and vertically spaced apart from each other on a substrate (SUB) and vertical structures (VS) that extend vertically through the sacrificial layers (SAC). Each of the vertical structures (VS) includes a data storage pattern (DSP) and a bit line vertical portion (BLV), and the data storage pattern (DSP) can form memory cells corresponding to gate electrodes (EL-WL) to be generated after the sacrificial layers (SAC) are removed.

[0242] At this time, the semiconductor structure (SEMI-STR) may include sacrificial layers (SAC) each having a step structure (SS) along the horizontal direction at both ends.

[0243] In step (S1420), the manufacturing system can form at least one string selection line slit (SS) that separates at least one gate electrode (EL-SSL) corresponding to a string selection line (SSL) among the gate electrodes (EL-SSL, EL-WL) by string selection line block (SB1, SB2, SB3, SB4; SB).

[0244] Specifically, the manufacturing system can form at least one string selection slit (SS) by etching a sacrificial layer (SAC) to a depth where at least one gate electrode (EL-SSL) corresponding to a string selection line (SSL) is to be formed in a vertical direction (e.g., a third direction (D3)) and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0245] In step (S1430), the manufacturing system can form at least one word line slit (WS) that separates at least one gate electrode (EL-WL) corresponding to a word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) among the gate electrodes (EL-SSL, EL-WL) by word line block (WB1, WB2; WB).

[0246] More specifically, the manufacturing system can form at least one word line slit (WS) by etching the upper surface of the substrate (SUB) in a vertical direction (e.g., a third direction (D3)) so as to expose the upper surface, and then filling the etched space with an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0247] Additionally, in step (S1430), the manufacturing system can form at least one word line slit (WS) such that the word line blocks (WB1, WB2; WB) include a plurality of string select line blocks (SB1, SB2, SB3, SB4; SB).

[0248] Additionally, in step (S1430), the manufacturing system can form at least one word line slit (WS) such that the word line blocks (WB1, WB2; WB) include a greater number of vertical structures (VS) than the string select line blocks (SB1, SB2, SB3, SB4; SB).

[0249] The position at which at least one string selection slit (SS) is formed in step (S1420) and the position at which at least one word line slit (WS) is formed in step (S1430) can be adaptively determined and adjusted according to the number of vertical structures (VS) to be included in each of the string selection line blocks (SB1, SB2, SB3, SB4; SB) and the number of vertical structures (VS) to be included in each of the word line blocks (WB1, WB2; WB).

[0250] In determining and controlling the position at which at least one word line slit (WS) is formed in step (S1430), the manufacturing system can first determine and control the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the speed at which the operating voltage is applied to the memory cell through the word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line block (SB1, SB2, SB3, SB4; SB). For example, the manufacturing system can determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) such that the speed at which the operating voltage is applied to the memory cells through the word lines (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line blocks (SB1, SB2, SB3, SB4; SB) is greater than a preset threshold speed value.

[0251] That is, the manufacturing system can first determine and adjust the number of vertical structures (VS) to be included in each of the word line blocks (SB1, SB2, SB3, SB4; SB) based on the speed at which the operating voltage is applied to the memory cell through the word line (WL1 (WL1 / 1, WL1 / 2, …, WL1 / n), WL2 (WL2 / 1, WL2 / 2, …, WL2 / n)) within the word line block (SB1, SB2, SB3, SB4; SB), and then determine and adjust the position at which at least one word line slit (WS) is formed according to the number of vertical structures (VS) determined and adjusted.

[0252] In step (S1440), the manufacturing system can remove sacrificial layers (SAC) through at least one word line slit (WS) and generate gate electrodes (EL-SSL, EL-WL) in spaces where the sacrificial layers (SAC) are removed.

[0253] However, without being limited or restricted thereto, removing the sacrificial layers (SAC) and creating gate electrodes (EL-SSL, EL-WL) in the spaces where the sacrificial layers (SAC) are removed may be performed through a trench other than at least one word line slit (WS).

[0254]

[0255] Fig. 15 is a flowchart illustrating an operating method of a three-dimensional random access memory according to embodiments. The memory operating method described below performs a memory operation on a target memory cell, and is assumed to be performed by a three-dimensional random access memory having the structure described above with reference to Figs. 9 to 12. In addition, the target memory cell below refers to a memory cell that is a target of a memory operation, and the selected vertical structure (Sel VS) refers to a vertical structure that includes a target memory cell among the vertical structures (VS).

[0256] In step (S1510), the three-dimensional random access memory can apply voltage in both directions from word line plugs formed at both ends of the step structure (SS) of each of the gate electrodes (EL-SSL, EL-WL) toward a selected vertical structure (Sel VS) among the vertical structures (VS).

[0257] For example, a three-dimensional random access memory can apply an operating voltage in both directions toward a target memory cell from word line plugs at both ends of a selected gate electrode (Sel EL-WL) corresponding to a target memory cell among the gate electrodes (EL-WL). At least one unselected gate electrode (Unsel EL-WL) among the gate electrodes (EL-WL) other than the selected gate electrode (Sel EL-WL) can be grounded.

[0258] In this step (S1520), the three-dimensional random access memory can perform a memory operation in response to voltages applied in both directions toward the selected vertical structure (Sel VS).

[0259] Although the above memory operation is described as being performed through steps (S1510 to S1520), it can be performed by additionally executing steps performed by a conventional 3D random access memory.

[0260] For example, before or immediately after step (S1510), a step of applying a voltage through a selected bit line horizontal portion (Sel BLH) connected to a selected vertical structure (Sel VS), a step of turning on a selection transistor (SST) of a selected vertical structure (Sel VS) so that the voltage applied through the selected bit line horizontal portion (Sel BLH) is transmitted to a target memory cell of the selected vertical structure (Sel VS), and a step of turning off a selection transistor (SST) of at least one unselected vertical structure (Unsel VS) so that the voltage applied through the selected bit line horizontal portion (Sel BLH) is not transmitted to at least one unselected vertical structure (Unsel VS) connected to the same selected bit line horizontal portion (Sel BLH) as the selected vertical structure (Sel VS) among unselected vertical structures (Unsel VS) that do not include a target memory cell are additionally performed, thereby Step (S1520) may be performed in response to step (S1510) and additionally performed steps.

[0261] The memory operation described above may be a write operation for a target memory cell (a programming operation that writes data of "1" to the target memory cell or an erase operation that writes data of "0" to the target memory cell).

[0262]

[0263] FIG. 16 is a perspective view schematically illustrating an electronic system including a three-dimensional random access memory according to one embodiment.

[0264] Referring to FIG. 16, an electronic system (1600) including a three-dimensional random access memory according to embodiments may include a main substrate (1601), a controller (1602) mounted on the main substrate (1601), one or more semiconductor packages (1603), and a DRAM (1604).

[0265] The semiconductor package (1603) and DRAM (1604) can be interconnected with the controller (1602) by wiring patterns (1605) provided on the main substrate (1601).

[0266] The main board (1601) may include a connector (1606) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1606) may vary depending on the communication interface between the electronic system (1600) and the external host.

[0267] The electronic system (1600) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (1600) may operate by power supplied from an external host, for example, through a connector (1606). The electronic system (1600) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (1602) and a semiconductor package (1603).

[0268] The controller (1602) can write data to the semiconductor package (1603) or read data from the semiconductor package (1603), and can improve the operating speed of the electronic system (1600).

[0269] The DRAM (1604) may be a buffer memory to mitigate the speed difference between the semiconductor package (1603), which is a data storage space, and an external host. The DRAM (1604) included in the electronic system (1600) may also function as a type of cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package (1603). When the electronic system (1600) includes the DRAM (1604), the controller (1602) may further include a DRAM controller for controlling the DRAM (1604) in addition to the NAND controller for controlling the semiconductor package (1603).

[0270] A semiconductor package (1603) may include first and second semiconductor packages (1603a, 1603b) that are spaced apart from each other. The first and second semiconductor packages (1603a, 1603b) may each be a semiconductor package including a plurality of semiconductor chips (1620). Each of the first and second semiconductor packages (1603a, 1603b) may include a package substrate (1610), semiconductor chips (1620) on the package substrate (1610), adhesive layers (1630) disposed on a lower surface of each of the semiconductor chips (1620), connection structures (1640) that electrically connect the semiconductor chips (1620) and the package substrate (1610), and a molding layer (1650) that covers the semiconductor chips (1620) and the connection structures (1640) on the package substrate (1610).

[0271] The package substrate (1610) may be a printed circuit board including package upper pads (1611). Each of the semiconductor chips (1620) may include input / output pads (1621). Each of the semiconductor chips (1620) may include the three-dimensional random access memory described above with reference to FIGS. 1 to 4D or FIGS. 9 to 12. More specifically, each of the semiconductor chips (1620) may include gate stack structures (1622) and memory structures (1623). The gate stack structures (1622) may correspond to the stack structures (ST) described above, and the memory structures (1623) may correspond to the vertical structures (VS) described above.

[0272] The connection structures (1640) may be, for example, bonding wires that electrically connect the input / output pads (1621) and the package upper pads (1611). Accordingly, in each of the first and second semiconductor packages (1603a, 1603b), the semiconductor chips (1620) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (1611) of the package substrate (1610). According to embodiments, in each of the first and second semiconductor packages (1603a, 1603b), the semiconductor chips (1620) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (1640).

[0273] Unlike the illustration, the controller (1602) and the semiconductor chips (1620) may be included in a single package. The controller (1602) and the semiconductor chips (1620) may be mounted on a separate interposer substrate different from the main substrate (1601), and the controller (1602) and the semiconductor chips (1620) may be connected to each other by wiring provided on the interposer substrate.

[0274]

[0275] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0276] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Gate electrodes that are formed extending horizontally on the substrate and are spaced apart vertically and laminated; At least one dummy electrode interposed between the gate electrodes; and Vertical structures formed to extend in the vertical direction and penetrate the gate electrodes and at least one dummy electrode, each of the vertical structures including a data storage pattern and a bit line vertical portion, the data storage pattern forming memory cells corresponding to the gate electrodes. A three-dimensional random access memory containing .

2. In paragraph 1, At least one dummy electrode, A three-dimensional random access memory characterized in that it is used for the purpose of improving the application speed of a bit line voltage applied through the bit line vertical portion as a dummy voltage is applied.

3. In paragraph 1, When the at least one dummy electrode is included in multiple numbers, the spacing or number of the multiple dummy electrodes interposed between the gate electrodes is, A three-dimensional random access memory characterized in that the speed of applying a bit line voltage applied through the vertical portion of the bit line is controlled and determined based on the speed of applying the bit line voltage.

4. In paragraph 1, When the above at least one dummy electrode is included in multiple numbers, the multiple dummy electrodes are, A three-dimensional random access memory characterized in that the gap between the gate electrodes is formed to become narrower toward the bottom of the vertical portion of the bit line.

5. In paragraph 1, When the above at least one dummy electrode is included in multiple numbers, the multiple dummy electrodes are, A three-dimensional random access memory characterized in that the gap between the gate electrodes is formed to become narrower toward the top of the vertical portion of the bit line.

6. In paragraph 1, When the above at least one dummy electrode is included in multiple numbers, the multiple dummy electrodes are, A three-dimensional random access memory characterized in that the gaps interposed between the gate electrodes are uniformly formed.

7. A memory operation method of a three-dimensional random access memory including gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart and stacked; at least one dummy electrode interposed between the gate electrodes; and vertical structures that penetrate the gate electrodes and the at least one dummy electrode and extend in the vertical direction, each of the vertical structures including a data storage pattern and a bit line vertical portion, and the data storage pattern forming memory cells corresponding to the gate electrodes, A step of applying a bit line voltage having at least a portion of an operating voltage value to a bit line vertical portion included in a selected vertical structure including a target memory cell to be a target of a memory operation among the above vertical structures; A step of applying a gate voltage having a polarity opposite to the bit line voltage and having a remaining portion of the operating voltage to a selected gate electrode corresponding to the target memory cell among the gate electrodes; A step of grounding at least one unselected gate electrode, excluding the selected gate electrode among the gate electrodes; and A step of applying a dummy voltage to at least one dummy electrode A memory operation method of a three-dimensional random access memory including a .

8. A memory operation method of a three-dimensional random access memory, comprising: gate electrodes formed to extend horizontally on a substrate and spaced apart in a vertical direction and stacked; at least one dummy electrode interposed between the gate electrodes; and vertical structures formed to extend in the vertical direction while penetrating the gate electrodes and the at least one dummy electrode, each of the vertical structures including a data storage pattern and a bit line vertical portion, and the data storage pattern forming memory cells corresponding to the gate electrodes; A step of grounding a vertical portion of the bit line included in a selected vertical structure including a target memory cell to be the target of a memory operation among the vertical structures; A step of applying an operating voltage to a selected gate electrode corresponding to the target memory cell among the gate electrodes; A step of applying a pass voltage having at least a portion of the operating voltage to at least one unselected gate electrode, excluding the selected gate electrode among the gate electrodes; and A step of applying a dummy voltage to at least one dummy electrode A memory operation method of a three-dimensional random access memory including a .

9. Gate electrodes that are formed extending horizontally on the substrate and are spaced apart vertically and laminated; Vertical structures formed to extend in the vertical direction and penetrate the gate electrodes, each of the vertical structures including a data storage pattern and a bit line vertical portion, the data storage pattern forming memory cells corresponding to the gate electrodes; At least one string selection line slit for separating at least one gate electrode corresponding to a string selection line among the above gate electrodes by string selection line block; and At least one word line slit separating at least one gate electrode corresponding to a word line among the above gate electrodes for each word line block A three-dimensional random access memory containing .

10. In paragraph 9, The above word line block is, A three-dimensional random access memory characterized by including a plurality of the above string selection line blocks.

11. In paragraph 9, The above word line block is, A three-dimensional random access memory characterized by including a greater number of said vertical structures than said string selection line blocks.

12. In paragraph 11, The number of vertical structures included in the above word line block is A three-dimensional random access memory, characterized in that the operating voltage within the word line block is determined and controlled based on the speed at which the operating voltage is applied to a target memory cell of a selected vertical structure among the vertical structures through the word line.

13. In paragraph 9, At least one word line slit is, A three-dimensional random access memory characterized in that, during the manufacturing process of the three-dimensional random access memory, sacrificial layers are removed in the process of forming the gate electrodes and are used as passages for filling the material constituting the gate electrodes.

14. In paragraph 9, Each of the two ends of the above gate electrodes, A three-dimensional random access memory characterized by having a step structure along the horizontal direction.

15. In paragraph 14, The above three-dimensional random access memory is, A three-dimensional random access memory characterized in that it performs a memory operation in response to a voltage applied in both directions from word line plugs formed at both ends of the step structure having each end of the gate electrodes toward a selected vertical structure among the vertical structures.

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