Display device

Abstract

A display device according to an embodiment comprises: a substrate including a display area and a non-display area; a transistor disposed on the display area of the substrate and including a semiconductor layer; and at least one inspection pattern disposed on the non-display area of the substrate and including a semiconductor pattern, wherein: the inspection pattern includes a first conductive pattern and a second conductive pattern spaced apart in a thickness direction with the semiconductor pattern interposed therebetween, an inspection source electrode connected to a portion of the semiconductor pattern, and an inspection drain electrode connected to another portion of the semiconductor pattern; and the second conductive pattern is in contact with the semiconductor pattern.

Description

display device

[0001] The present invention relates to a display device.

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being used in various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light emitting display device. The light emitting display device includes an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element such as an inorganic semiconductor, and an ultra-small light emitting display device including an ultra-solid light emitting element.

[0004] An organic light-emitting device may include two opposing electrodes and a light-emitting layer interposed therebetween. The light-emitting layer receives electrons and holes from the two electrodes, recombines them, and generates excitons. The generated excitons change from an excited state to a ground state, thereby emitting light.

[0005] Organic light-emitting display devices that include organic light-emitting elements are attracting attention as next-generation display devices because they do not require a light source such as a backlight unit, so they can be configured as thin, lightweight devices with low power consumption, and have high-quality characteristics such as a wide viewing angle, high brightness and contrast, and fast response speed.

[0006] The problem to be solved by the present invention is to provide a display device capable of managing the characteristics of a thin film transistor in a display area by using an inspection pattern placed in a non-display area.

[0007] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0008] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate including a display area and a non-display area, a transistor disposed on the display area of ​​the substrate and including a semiconductor layer, and at least one inspection pattern disposed on the non-display area of ​​the substrate and including a semiconductor pattern, wherein the inspection pattern includes a first conductive pattern and a second conductive pattern spaced apart in a thickness direction with the semiconductor pattern therebetween, and an inspection source electrode connected to one portion of the semiconductor pattern and an inspection drain electrode connected to another portion of the semiconductor pattern, wherein the second conductive pattern can contact the semiconductor pattern.

[0009] The first conductive pattern is disposed on the substrate, and may further include a first insulating layer and a second insulating layer interposed between the semiconductor pattern and the first conductive pattern.

[0010] The semiconductor pattern may include a pattern channel region, a first conductive region and a second conductive region spaced apart from each other with the pattern channel region interposed therebetween.

[0011] The above first challenge pattern may overlap with the pattern channel region.

[0012] The above inspection source electrode can be connected to the first conducting region, and the above inspection drain electrode can be connected to the second conducting region.

[0013] The second conductive pattern is arranged on the semiconductor pattern and can overlap with the first conductive pattern.

[0014] It further includes a third insulating layer disposed between the second conductive pattern and the semiconductor pattern, wherein the second conductive pattern can contact the semiconductor pattern through a first via hole penetrating the third insulating layer.

[0015] It further includes a fourth insulating layer disposed between the inspection source electrode and the inspection drain electrode and the second conductive pattern, wherein the inspection source electrode and the inspection drain electrode can be connected to the semiconductor pattern through a second via hole and a third via hole penetrating the fourth insulating layer.

[0016] It may further include a fourth insulating layer disposed on the second conductive pattern, and a first inspection electrode, a second inspection electrode, a third inspection electrode, and a fourth inspection electrode disposed on the fourth insulating layer and spaced apart from each other.

[0017] The first inspection electrode may be connected to the first conductive pattern, and the second inspection electrode may be connected to the second conductive pattern.

[0018] The third inspection electrode may extend from the inspection source electrode, and the fourth inspection electrode may extend from the inspection drain electrode.

[0019] The semiconductor layer of the transistor of the display area may include the same material as the semiconductor pattern of the inspection pattern.

[0020] The semiconductor layer of the transistor of the display area and the semiconductor pattern of the inspection pattern may include an oxide semiconductor.

[0021] It further includes a connection pattern arranged between the first conductive pattern and the semiconductor pattern, wherein the first conductive pattern can be electrically connected to the semiconductor pattern through the connection pattern.

[0022] In addition, a display device according to one embodiment includes a substrate including a display area and a non-display area, a transistor disposed on the display area of ​​the substrate and including a semiconductor layer, and an inspection pattern disposed on the non-display area of ​​the substrate and including a semiconductor pattern, wherein the inspection pattern includes a first conductive pattern and a second conductive pattern spaced apart in a thickness direction with the semiconductor pattern therebetween, an inspection source electrode connected to one portion of the semiconductor pattern and an inspection drain electrode connected to another portion of the semiconductor pattern, and a connection pattern disposed between the first conductive pattern and the semiconductor pattern, wherein the connection pattern can contact the first conductive pattern and the semiconductor pattern.

[0023] The semiconductor layer of the transistor of the display area and the semiconductor pattern of the inspection pattern may include an oxide semiconductor.

[0024] It further includes a first insulating layer and a second insulating layer interposed between the semiconductor pattern and the first conductive pattern, wherein the connection pattern is arranged in a first via hole penetrating the first insulating layer and the second insulating layer, and the first via hole can overlap the first conductive pattern and the semiconductor pattern.

[0025] The semiconductor pattern includes a pattern channel region, a first conductive region and a second conductive region spaced apart from each other with the pattern channel region interposed therebetween, and the connection pattern can contact the pattern channel region.

[0026] The first conductive pattern, the second conductive pattern, and the connection pattern may overlap with the pattern channel region of the semiconductor pattern.

[0027] It further includes a third insulating layer disposed between the semiconductor pattern and the second conductive pattern, wherein the second conductive pattern can be spaced apart from the semiconductor pattern.

[0028] Specific details of other embodiments are included in the detailed description and drawings.

[0029] According to one embodiment, a display device can infer a hydrogen content in a semiconductor layer of a pixel transistor in a display area by forming a test pattern including a semiconductor pattern in a non-display area and measuring the capacitance of the semiconductor pattern. Accordingly, the characteristics of the pixel transistor of the display device can be monitored, thereby improving the quality of the display device.

[0030] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0031] Figure 1 is a plan view showing a display device according to one embodiment.

[0032] Figure 2 is a plan view showing the display panel of Figure 1.

[0033] Figure 3 is a circuit diagram showing a pixel according to one embodiment.

[0034] FIG. 4 is a circuit diagram showing a pixel (PX) according to one embodiment.

[0035] FIG. 5 is a cross-sectional view showing a display panel (110) according to one embodiment.

[0036] Fig. 6 is a plan view showing an inspection pattern according to one embodiment.

[0037] Figure 7 is a cross-sectional view taken along line Q1-Q1' of Figure 6.

[0038] Figure 8 is a graph showing changes in the characteristics of a transistor depending on the hydrogen content of the semiconductor layer.

[0039] Figure 9 is a graph showing the change in characteristics of a transistor having a semiconductor layer without hydrogen.

[0040] Figure 10 is a graph showing the change in characteristics of a transistor having a semiconductor layer containing hydrogen.

[0041] Figure 11 is a graph showing the capacitance of a semiconductor pattern according to frequency.

[0042] Fig. 12 is a cross-sectional view showing an inspection pattern of a display device according to another embodiment.

[0043] Fig. 13 is a cross-sectional view showing an inspection pattern of a display device according to another embodiment.

[0044] Fig. 14 is a plan view showing a display panel according to another embodiment.

[0045] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0046] When an element or layer is referred to as "on" another element or layer, it includes both cases where it is directly above the other element or layer or where there is another layer or material intervening therebetween. Similarly, when an element or layer is referred to as "below," "left," and "right," it includes both cases where it is directly adjacent to the other element or where there is another layer or material intervening therebetween. Like reference numerals throughout the specification refer to like elements.

[0047] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0048] Hereinafter, embodiments will be described with reference to the attached drawings.

[0049] Fig. 1 is a plan view illustrating a display device according to one embodiment. Fig. 2 is a plan view illustrating the display panel of Fig. 1.

[0050] Referring to FIGS. 1 and 2, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and Ultra Mobile PCs (UMPCs), as well as televisions, laptops, monitors, billboards, and Internet of Things (IOT). These are presented only as examples, and the display device (10) can also be employed in other electronic devices.

[0051] In one embodiment, the display device (10) may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device using an ultra-small light-emitting diode such as a micro or nano light emitting diode (micro LED or nano LED), but is not limited thereto. For example, the display device (10) may be a type of display device other than a light-emitting display device. Hereinafter, embodiments in which the display device (10) is an organic light-emitting display device are disclosed.

[0052] The display device (10) may include a display panel (110) including pixels (PX), and a first driving unit (120) and a second driving unit (130) that supply driving signals to the pixels (PX). The display device (10) may further include additional components. For example, the display device (10) may further include a power supply unit for supplying power voltages to the pixels (PX), the first driving unit (120) and the second driving unit (130), and a timing control unit for controlling the operations of the first driving unit (120) and the second driving unit (130).

[0053] The display panel (110) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be an area that displays an image by including pixels (PX). The non-display area (NDA) is an area excluding the display area (DA), and an image may not be displayed in the non-display area (NDA). In one embodiment, the non-display area (NDA) may be located around the display area (DA) and may surround the display area (DA).

[0054] In FIGS. 1 and 2, a first direction (DR1), a second direction (DR2), and a third direction (DR3) may be defined. In one embodiment, the first direction (DR1) and the second direction (DR2) may be perpendicular to each other, the first direction (DR1) and the third direction (DR3) may be perpendicular to each other, and the second direction (DR2) and the third direction (DR3) may be perpendicular to each other. For example, the first direction (DR1) may be a horizontal direction of the display panel (110), the second direction (DR2) may be a vertical direction of the display panel (110), and the third direction (DR3) may be a thickness direction of the display panel (110).

[0055] In one embodiment, the display panel (110) may be formed in a rectangular shape on a plane. For example, the display panel (110) may include two first sides extending in a first direction (DR1) and two second sides extending in a second direction (DR2) intersecting the first direction (DR1). In FIGS. 1 and 2 , the display panel (110) is illustrated in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel (110) is not limited thereto. For example, the display panel (110) may have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or may have a shape in which the lengths of the first side and the second side are substantially the same.

[0056] In one embodiment, the display panel (110) may include, but is not limited to, an angled corner where the first side and the second side meet. For example, the display panel (110) may also include a rounded corner where the first side and the second side meet.

[0057] The planar shape of the display panel (110) is not limited to the rectangular shape illustrated, and may be applied in other shapes. For example, the display panel (110) may have a planar square shape, a non-square polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes.

[0058] In one embodiment, the display panel (110) may be substantially flat on a plane defined by the first direction (DR1) and the second direction (DR2), and may have a uniform thickness in the third direction (DR3). In another embodiment, the display panel (110) may be provided in a three-dimensional shape having a curved surface, etc.

[0059] The display panel (110) may be provided as a rigid panel that is substantially not deformed, or may be provided as a flexible panel that can be deformed in a form such as by folding, bending, or rolling at least in one portion. The display panel (110) may be provided to the display device (10) in an unbent state, or may be provided to the display device (10) in a bent state in some sections.

[0060] A display panel (110) may include a substrate (SUB) and pixels (PX) arranged on the substrate (SUB). The pixels (PX) may be arranged in a display area (DA) on the substrate (SUB).

[0061] The substrate (SUB) is a base member for manufacturing or providing a display panel (110) and may constitute a base surface of the display panel (110). The substrate (SUB) may include a display area (DA) and a non-display area (NDA) located around the display area (DA).

[0062] The display area (DA) may have various shapes depending on the embodiments. For example, the display area (DA) may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes. In one embodiment, the display area (DA) may have a shape that matches the shape of the display panel (110), but is not limited thereto.

[0063] The display area (DA) may include pixel areas in which pixels (PX) are provided and / or arranged. For example, each pixel (PX) may be arranged in a respective pixel area located in the display area (DA). In one embodiment, the display device (10) may be a light-emitting display device, and each pixel (PX) may include a light-emitting element located in a respective light-emitting area and a pixel circuit connected to the light-emitting element. In describing the embodiments, “connection” may include the meaning of electrical connection and / or physical connection.

[0064] Each pixel area may include a light-emitting area where the light-emitting element of the corresponding pixel is positioned and the pixel emits light, and a pixel circuit area where circuit elements constituting the pixel circuit of the corresponding pixel are positioned. In one embodiment, the light-emitting area and the pixel circuit area of ​​each pixel (PX) may overlap each other, but are not limited thereto.

[0065] Pixels (PX) may be arranged in a display area (DA). For example, the pixels (PX) may be arranged in a stripe structure, a delta structure, a pentile structure, or another arrangement structure.

[0066] A non-display area (NDA) may include a driving circuit area located at least on one side of a display area (DA) and a pad area (PA) where pads (PD) are arranged. At least one driving unit, pads (PD), and / or wiring may be arranged in the non-display area (NDA).

[0067] At least one driving unit, or a portion of the driving unit, for driving pixels (PX) may be disposed in the driving circuit area. For example, circuit elements constituting the first driving unit (120) may be disposed in the driving circuit area on the substrate (SUB). In one embodiment, the circuit elements of the first driving unit (120) may be formed on the display panel (110) together with the pixels (PX).

[0068] Pads (PD) may be arranged in the pad area (PA). At least one circuit board (140) may be arranged and / or bonded on the pad area (PA). In one embodiment, a plurality of circuit boards (140) connected to different pads (PD) may be arranged on the pad area (PA). The pads (PD) may include signal pads and power pads for transmitting driving signals and power voltages required for driving the pixels (PX) and / or the first driving unit (120) to the inside of the display panel (110).

[0069] The first driving unit (120) and the second driving unit (130) can generate driving signals for controlling the operation timing and brightness of the pixels (PX) and supply the driving signals to the pixels (PX). For example, the first driving unit (120) can be a gate driving unit including a scan driving unit and can be connected to the pixels (PX) through respective gate lines. The first driving unit (120) can supply respective gate signals (for example, driving signals for controlling the operation timing of the pixels (PX) including the first gate signal (GW) of FIG. 3) to the pixels (PX). The second driving unit (130) can be a data driving unit including source driving circuits and can be connected to the pixels (PX) through respective data lines. The second driving unit (130) can supply respective data signals to the pixels (PX).

[0070] In one embodiment, at least one of the first driving unit (120) and the second driving unit (130), or a portion of the at least one driving unit, may be built into the display panel (110). For example, the first driving unit (120) or a portion of the first driving unit (120) may be disposed on the substrate (SUB) of the display panel (110) and may be disposed and / or formed in a non-display area (NDA).

[0071] In Fig. 1, the first driving unit (120) is exemplified as being formed on one side of the display area (DA) (for example, the non-display area (NDA) on the right side of the display area (DA), but the embodiments are not limited thereto. For example, the first driving unit (120) may be positioned only on the other side of the display area (DA) (for example, the non-display area (NDA) on the left side of the display area (DA)) or on both sides of the display area (DA) (for example, the non-display areas (NDA) on the left and right sides of the display area (DA). Alternatively, a part of the first driving unit (120) (for example, some of the circuit elements constituting the first driving unit (120)) may be located in a non-display area (NDA), and another part of the first driving unit (120) (for example, the remaining circuit elements constituting the first driving unit (120)) may be located in a non-emitting area (for example, an area between the emitting areas of the pixels (PX)) within the display area (DA).

[0072] In one embodiment, the other of the first driving unit (120) and the second driving unit (130), or a part of the other driving unit, may be disposed or formed outside the display panel (110) and electrically connected to the display panel (110). For example, the second driving unit (130) or a part of the second driving unit (130) may be implemented with a plurality of integrated circuit chips and may be disposed on a circuit board (140) electrically connected to the pixels (PX) of the display panel (110). In one embodiment, the second driving unit (130) may be integrated with the timing controller as a separate integrated circuit chip, or may be integrated with the timing controller as a separate integrated circuit chip. The second driving unit (130) may also be implemented with at least one integrated circuit chip and mounted on a non-display area (NDA) of the display panel (110).

[0073] The circuit board (140) may be connected to the display panel (110) via pads (PD). In one embodiment, the circuit board (140) may be, but is not limited to, a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF). In one embodiment, the circuit board (140) may be connected to a timing control unit and / or a power supply unit via another circuit board or a connector.

[0074] In one embodiment, a test pattern (TAG) may be placed in a non-display area (NDA). The test pattern (TAG) is used to test the characteristics of a thin film transistor, and the test can be performed by connecting a measuring device to the test pattern (TAG). Accordingly, the characteristics of the thin film transistor can be tested from the test pattern (TAG), and the hydrogen content of the thin film transistor, etc. can be inferred. Through this, the quality of the display device can be improved through evaluation and compensation for the process.

[0075] At least one inspection pattern (TAG) may be placed in the non-display area (NDA). For example, the inspection pattern (TAG) may be placed in the space between the first driving unit (120) and the pad area (PA). In some embodiments, multiple inspection patterns (TAG) may be placed.

[0076] The inspection pattern (TAG) can be used to infer the characteristics of thin film transistors within the display area (DA), for example, the hydrogen content of a semiconductor layer. Since the inspection pattern (TAG) is placed in the non-display area (NDA), it remains even after the display device (10) is completed. Accordingly, the evaluation of the thin film transistors is possible not only during the manufacturing process but also after the display device is completed, and the quality of the display device (10) can be improved through compensation accordingly. A detailed description of the inspection pattern (TAG) will be provided later.

[0077] Fig. 3 is a circuit diagram illustrating a pixel according to one embodiment. The pixel (PX) of Fig. 3 is presented as only one embodiment, and the structure and type of the pixel (PX) may be varied in various ways according to embodiments.

[0078] In addition to FIGS. 1 and 2, referring to FIG. 3, a pixel (PX) may include a light-emitting element (ED) and a pixel circuit (PC) connected to the light-emitting element (ED). The light-emitting element (ED) is a light source of the pixel (PX), and may be, for example, an organic light-emitting diode, but is not limited thereto. The pixel circuit (PC) may control the light-emitting timing and brightness of the light-emitting element (ED).

[0079] The pixel circuit (PC) may include pixel transistors (TRS) and at least one pixel capacitor (CST). For example, the pixel circuit (PC) may include first to fifth transistors (T1 to T5) and first and second capacitors (C1, C2). The structure of the pixel circuit (PC) or the types of circuit elements constituting the pixel circuit (PC) may vary depending on embodiments. In FIG. 3, an embodiment in which the pixel transistors (TRS) are N-type transistors is exemplified, but the types of the pixel transistors (TRS) are not limited thereto. For example, at least one pixel transistor (TRS) may be formed as a P-type transistor.

[0080] The pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to driving signals supplied from the first driving unit (120) and the second driving unit (130). For example, the pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to each of the gate signals (GS) supplied from the first driving unit (120) through each of the gate lines (GL) and the data signal (DATA) supplied from the second driving unit (130) through the data line (DL).

[0081] The second transistor (T2) may be a driving transistor of a pixel (PX), in which the magnitude of the drain-source current (e.g., driving current (Id)) is determined according to the gate-source voltage. The first, third, fourth, and fifth transistors (T1, T3, T4, and T5) may be switching transistors that are turned on or off according to their respective gate-source voltages (substantially, their respective gate voltages). Depending on the type (e.g., P-type or N-type transistor) and / or operating conditions of each of the first to fifth transistors (T1 to T5), the first electrode of each of the first to fifth transistors (T1 to T5) may be a drain electrode (or a drain region) or a source electrode (or a source region), and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a drain electrode, the second electrode may be a source electrode.

[0082] A pixel (PX) may be connected to a first gate line (GWL) that transmits a first gate signal (GW) (e.g., a scan signal), a second gate line (GIL) that transmits a second gate signal (GI), a third gate line (GRL) that transmits a third gate signal (GR), an emission control line (ECL) that transmits an emission control signal (EM), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel (PX) may be connected to a first pixel power line (VDL) that transmits a first pixel voltage (ELVDD) (also referred to as a “first pixel power voltage”), and a second pixel power line (VSL) that transmits a second pixel voltage (ELVSS) (also referred to as a “second pixel power voltage”). In one embodiment, the pixel (PX) may be further connected to an initialization power line (VIL) that carries an initialization voltage (VINT) (also referred to as a "third pixel power voltage") and a reference power line (VRL) that carries a reference voltage (VREF) (also referred to as a "fourth pixel power voltage").

[0083] In one embodiment, the first to fifth transistors (T1 to T5) may be positioned in respective pixel areas (for example, a pixel area (PXA) of a pixel (PX) provided in a display area (DA) of FIG. 5) and may be oxide transistors (also referred to as “oxide semiconductor transistors”) including an oxide semiconductor (for example, an oxide semiconductor material). For example, the semiconductor layer of each of the first to fifth transistors (T1 to T5) may be formed of an oxide semiconductor. However, the embodiments are not limited thereto. For example, at least one pixel transistor (TRS) may be formed of a semiconductor material other than an oxide semiconductor (for example, amorphous silicon or polysilicon).

[0084] Oxide semiconductors have high carrier mobility (for example, high electron mobility in the case of an N-type transistor) and low leakage current, and thus, even if the driving time of the oxide transistor is long, a large voltage drop may not occur. For example, in the case of a pixel (PX) including an oxide transistor, since the brightness and / or color of the image does not change significantly due to the voltage drop even when driven at a low frequency, the pixel can be driven at a low frequency. In the case of a display device (10) in which the first to fifth pixel transistors (T1 to T5) include an oxide semiconductor, the leakage current of the pixel (PX) can be reduced or prevented and power consumption can be reduced.

[0085] Oxide semiconductors are sensitive to light, and thus, the amount of current, etc., may vary depending on external light. In one embodiment, a light-shielding pattern or a lower electrode (e.g., a bottom gate electrode) may be disposed below a semiconductor layer constituting at least one pixel transistor (TRS) (e.g., at least one transistor among the first to fifth pixel transistors (T1 to T5)). Accordingly, the amount of current of the pixel transistor (TRS) may be prevented or reduced due to light, and the operating characteristics of the pixel transistor (TRS) may be stabilized.

[0086] A first transistor (T1) (also referred to as a “first pixel transistor”) may include a gate electrode connected to a first gate line (GWL), a first electrode connected to a data line (DL), and a second electrode connected to a first node (N1). The first transistor (T1) may be turned on by a first gate signal (GW) transmitted to the first gate line (GWL) (for example, a first gate signal (GW) of a gate-on voltage) to connect the data line (DL) and the first node (N1). Accordingly, a data signal (DATA) transmitted to the data line (DL) may be transmitted to the first node (N1).

[0087] A second transistor (T2) (also referred to as a “second pixel transistor”) may include a gate electrode connected to a first node (N1) (or gate node), a first electrode (e.g., a drain electrode or a drain region) connected to a second node (N2), and a second electrode (e.g., a source electrode or a source region) connected to a third node (N3). The first electrode of the second transistor (T2) may be connected to the first pixel power line (VDL) via a fifth transistor (T5), and the second electrode may be connected to the light-emitting element (ED). The second transistor (T2) may function as a driving transistor of the pixel (PX), and may control the size (e.g., the amount of current) of a driving current (Id) flowing to the light-emitting element (ED) in response to a data signal (DATA) transmitted according to a switching operation of the first transistor (T1).

[0088] In one embodiment, the second transistor (T2) may further include a bottom gate electrode (BG) (also referred to as a “back-gate electrode of the second transistor (T2)” or a “second bottom gate electrode”) connected to a third node (N3). When the bottom gate electrode (BG) of the second transistor (T2) is connected to a third node (N3) to which the second electrode (e.g., a source electrode) of the second transistor (T2) is connected, thereby forming the second transistor (T2) into a double-gate structured transistor (e.g., a double-gate transistor having a source-sink structure), the operating characteristics of the second transistor (T2) can be improved.

[0089] A third transistor (T3) (also referred to as a “third pixel transistor”) may include a gate electrode connected to a third gate line (GRL), a first electrode connected to a reference power line (VRL), and a second electrode connected to a first node (N1). The third transistor (T3) may be turned on by a third gate signal (GR) transmitted to the third gate line (GRL) and may transmit a reference voltage (VREF) transmitted to the reference power line (VRL) to the first node (N1).

[0090] A fourth transistor (T4) (also referred to as a “fourth pixel transistor”) may include a gate electrode connected to a second gate line (GIL), a first electrode connected to a third node (N3), and a second electrode connected to an initialization power line (VIL). The fourth transistor (T4) may be turned on by a second gate signal (GI) transmitted to the second gate line (GIL) and may transmit an initialization voltage (VINT) transmitted to the initialization power line (VIL) to the third node (N3).

[0091] A fifth transistor (T5) (also referred to as a “fifth pixel transistor”) may include a gate electrode connected to a light emission control line (ECL), a first electrode connected to a first pixel power line (VDL), and a second electrode connected to a second node (or, a first electrode of a second transistor (T2)). The fifth transistor (T5) may be turned on by a light emission control signal (EM) transmitted to the light emission control line (ECL) (for example, a light emission control signal (EM) of a gate-on voltage), thereby controlling a light emission timing of the pixel (PX).

[0092] The first capacitor (C1) may be connected between the first node (N1) and the third node (N3). For example, the first capacitor (C1) may be connected between the gate electrode and the second electrode of the second transistor (T2). The first capacitor (C1) may serve as a storage capacitor of the pixel (PX) and may store a voltage corresponding to the threshold voltage of the second transistor (T2) and a data signal (DATA) (e.g., a data voltage).

[0093] A second capacitor (C2) may be connected between the first pixel power line (VDL) and the third node (N3). In one embodiment, the capacitance of the second capacitor (C2) may be smaller than the capacitance of the first capacitor (C1).

[0094] The light emitting element (ED) may be connected between the third node (N3) and the second pixel power line (VSL). For example, the light emitting element (ED) may include a first electrode (e.g., an anode electrode or a pixel electrode) connected to the third node (N3), a second electrode (e.g., a cathode electrode or a counter electrode) facing the first electrode and connected to the second pixel power line (VSL), and a light emitting layer interposed between the first electrode and the second electrode. In one embodiment, the first electrode of the light emitting element (ED) may be an individual electrode individually provided to each pixel (PX), and the second electrode of the light emitting element (ED) may be a common electrode shared by a plurality of pixels (PX). The light emitting element (ED) may emit light with a brightness corresponding to the driving current (Id) during a period in which the driving current (Id) is supplied from the pixel circuit (PC).

[0095] FIG. 4 is a circuit diagram showing a pixel (PX) according to one embodiment. For example, FIG. 4 shows an additional embodiment related to switching transistors among the pixel transistors (TRS) of FIG. 3.

[0096] In addition to FIGS. 1 to 3, referring to FIG. 4, at least one of the switching transistors provided in the pixel (PX) may include a bottom gate electrode (BG) (or back-gate electrode) facing a gate electrode (e.g., a top gate electrode) with a semiconductor layer therebetween. For example, at least one of the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may include a bottom gate electrode (BG).

[0097] In Fig. 4, an embodiment is disclosed in which bottom gate electrodes (BG) are provided to each of the pixel transistors (TRS), and reference numerals are given only to the bottom gate electrode (BG) provided to one pixel transistor (TRS) (e.g., the second transistor (T2)). However, the embodiments are not limited thereto. For example, at least one pixel transistor (TRS) may not include a bottom gate electrode (BG), and / or may not be formed in a gate-sink structure or a source-sink structure.

[0098] In one embodiment, the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may each include bottom gate electrodes (BG). In one embodiment, the bottom gate electrode (BG) of each of the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may be connected to the gate electrode of the corresponding pixel transistor (TRS). For example, each of the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may be formed as a double gate transistor having a gate-sink structure.

[0099] By providing bottom gate electrodes (BG) to the first, third, fourth and fifth transistors (T1, T3, T4, T5), respectively, current fluctuations of the first, third, fourth and fifth transistors (T1, T3, T4, T5) due to light can be prevented or reduced. In addition, when the bottom gate electrodes (BG) of the first, third, fourth and fifth transistors (T1, T3, T4, T5) are connected to the gate electrodes (also referred to as “top gate electrodes”) of the first, third, fourth and fifth transistors (T1, T3, T4, T5), the operating characteristics (e.g., switching characteristics) of the first, third, fourth and fifth transistors (T1, T3, T4, T5) can be improved and / or stabilized. For example, by forming at least one switching transistor with a double gate structure of a gate-sink structure, the off characteristics and switching speed of the switching transistor can be improved, an additional voltage tolerance range can be secured, leakage current can be reduced, and voltage stability can be improved. For example, by forming a small-sized switching transistor formed with an oxide transistor having a short channel length with a double gate structure such as a gate-sink structure, the operating characteristics of the switching transistor can be improved.

[0100] FIG. 5 is a cross-sectional view showing a display panel (110) according to one embodiment.

[0101] FIG. 5 shows a first transistor (T1) and a second transistor (T2) arranged in one pixel area (PXA) as examples of circuit elements that can be provided or arranged in a panel circuit layer (PCL) of a display panel (110). In addition, FIG. 5 shows a light-emitting display panel including a light-emitting element (ED) (for example, an organic light-emitting diode) as an example of a display panel (110) to which embodiments can be applied. However, the type and / or structure of the display panel (110) according to the embodiments is not limited thereto. For example, the display panel (110) may include a light-emitting element of a different type and / or structure, or may be a display panel of a different type and / or structure other than a light-emitting display panel.

[0102] Referring to FIG. 5 in conjunction with FIGS. 1 to 4, the display panel (110) may include a substrate (SUB), a panel circuit layer (PCL), a light emitting element layer (LEL), and a thin film encapsulation layer (TFEL). A panel circuit layer (PCL), a light emitting element layer (LEL), and a thin film encapsulation layer (TFEL) may be arranged or provided on a substrate (SUB) to overlap each other. For example, based on the display area (DA), the panel circuit layer (PCL), the light emitting element layer (LEL), and the thin film encapsulation layer (TFEL) may be arranged or formed sequentially on the substrate (SUB) along a third direction (DR3). However, the embodiments are not limited thereto, and the mutual positions of the panel circuit layer (PCL), the light emitting element layer (LEL), and the thin film encapsulation layer (TFEL) may be changed. For example, the panel circuit layer (PCL) and the light emitting element layer (LEL) may be integrated with each other, or the light emitting element layer (LEL) may be arranged on top of the panel circuit layer (PCL).

[0103] In one embodiment, the display panel (110) may further include additional elements provided on top and / or bottom of the thin film encapsulation layer (TFEL). For example, the display panel (110) may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and / or the protective layer may be provided on top of the thin film encapsulation layer (TFEL) or between the light emitting element layer (LEL) and the thin film encapsulation layer (TFEL). In one embodiment, the sensor layer, the optical layer, and / or the protective layer may be provided on the display panel (110). For example, the sensor layer, the optical layer, and / or the protective layer may be manufactured integrally with the display panel (110). In another embodiment, the sensor layer, optical layer, and / or protective layer may be manufactured separately from the display panel (110) and attached to the display panel (110) via an adhesive layer or the like.

[0104] The substrate (SUB) is a base member for forming the display panel (110), and may be a substrate (or film) having rigid or flexible characteristics. In one embodiment, the substrate (SUB) may be a substrate having rigid characteristics including an insulating material such as glass, and may not be bent. In another embodiment, the substrate (SUB) may be a flexible substrate including polyimide or another insulating material, and may be deformable by bending, folding, rolling, etc., and may or may not be bent. The type and / or material of the substrate (SUB) may vary depending on the embodiments.

[0105] The substrate (SUB) may include at least a display area (DA). In one embodiment, the display area (DA) may include pixel areas (PXA) corresponding to each pixel (PX). For example, the display area (DA) may define respective pixel areas (PXA) in which each pixel (PX) is arranged.

[0106] In one embodiment, a buffer layer (BUF) may be disposed on the substrate (SUB). In another embodiment, the display panel (110) may not include a buffer layer (BUF), in which case a panel circuit layer (PCL) may be disposed directly on the substrate (SUB).

[0107] The buffer layer (BUF) may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). The buffer layer (BUF) may protect the pixels (PX) from moisture permeating through the substrate (SUB) that is vulnerable to moisture permeation. The material of the buffer layer (BUF) may vary depending on the embodiments.

[0108] A panel circuit layer (PCL) may be disposed on a buffer layer (BUF). The panel circuit layer (PCL) may include circuit elements including pixel transistors (TRS) and pixel capacitors (CST), and wires (e.g., signal lines and power lines).

[0109] The panel circuit layer (PCL) may further include insulating layers arranged on the substrate (SUB). For example, the panel circuit layer (PCL) may include a first insulating layer (INS1), a second insulating layer (INS2), a third insulating layer (INS3), a fourth insulating layer (INS4), and a first passivation layer (PVX1) sequentially arranged on the substrate (SUB) along a third direction (DR3).

[0110] In one embodiment, the panel circuit layer (PCL) may further include a connection electrode (CNE) and a second passivation layer (PVX2) disposed on the first passivation layer (PVX1), as illustrated in FIG. 5.

[0111] In one embodiment, each of the first insulating layer (INS1), the second insulating layer (INS2), the third insulating layer (INS3), and the fourth insulating layer (INS4) may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating material).

[0112] Each of the first via layer (VIA1) and the second via layer (VIA2) may include at least one organic insulating layer including an organic insulating material (e.g., an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or another organic insulating material). The surfaces (e.g., upper surfaces) of the first via layer (VIA1) and the second via layer (VIA2) may be substantially flat. The types, materials, shapes, and / or structures of the insulating layers provided on the panel circuit layer (PCL) may vary depending on embodiments.

[0113] Pixel transistors (TRS) may be included in a pixel circuit (PC) of each pixel (PX) and may be positioned in a display area (DA). For example, a first transistor (T1) and a second transistor (T2) provided to each pixel (PX) may be positioned in each pixel area (PXA) where the corresponding pixel (PX) is positioned. In addition, at least one other pixel transistor (TRS) and / or at least one pixel capacitor (CST) may be further positioned in each pixel area (PXA).

[0114] In one embodiment, at least one pixel transistor (TRS) may include a bottom gate electrode (BG). For example, a first transistor (T1) may include a first bottom gate electrode (BG1), and a second transistor (T2) may include a second bottom gate electrode (BG2). In one embodiment, the first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) may be disposed in the same layer within a panel circuit layer (PCL).

[0115] A first transistor (T1) may include a first bottom gate electrode (BG1) disposed on a substrate (SUB), a first semiconductor layer (ACT1) disposed on the first bottom gate electrode (BG1) and including a first channel region (CH1), a first drain region (DR1), and a first source region (SR1), and a first gate electrode (GE1) (hereinafter, referred to as “first top gate electrode (GE1)”) disposed on the first semiconductor layer (ACT1).

[0116] The first semiconductor layer (ACT1) may be disposed on at least a portion of the first bottom gate electrode (BG1). For example, at least a portion of the first semiconductor layer (ACT1) including the first channel region (CH1) may overlap the first bottom gate electrode (BG1). The first top gate electrode (GE1) may be disposed on a portion of the first semiconductor layer (ACT1) including the first channel region (CH1), and a third insulating layer (INS3) may be disposed between the first top gate electrode (GE1) and the first semiconductor layer (ACT1).

[0117] In one embodiment, the first transistor (T1) may further include a first drain electrode (DE1) and a first source electrode (SE1) connected to different portions of the first semiconductor layer (ACT1). Alternatively, the first transistor (T1) may not include a separate drain electrode and / or source electrode, and the first drain region (DR1) and / or the first source region (SR1) of the first semiconductor layer (ACT1) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the drain electrode and / or the source electrode of the first transistor (T1).

[0118] The first bottom gate electrode (BG1) may be disposed between the substrate (SUB) and the first insulating layer (INS1). For example, the first bottom gate electrode (BG1) may be disposed on the buffer layer (BUF) and covered by the first insulating layer (INS1).

[0119] The first bottom gate electrode (BG1) may overlap the first semiconductor layer (ACT1). For example, the first bottom gate electrode (BG1) may be disposed under the first semiconductor layer (ACT1) so as to overlap at least the first channel region (CH1). A first insulating layer (INS1) and a second insulating layer (INS2) may be disposed between the first bottom gate electrode (BG1) and the first semiconductor layer (ACT1). The first bottom gate electrode (BG1) and the first semiconductor layer (ACT1) may be spaced apart from each other by a distance corresponding to the thicknesses of the first insulating layer (INS1) and the second insulating layer (INS2). The first bottom gate electrode (BG1) may face the first top gate electrode (GE1) with the first semiconductor layer (ACT1) therebetween.

[0120] The first bottom gate electrode (BG1) may or may not be connected to another electrode of the first transistor (T1). In one embodiment, the first bottom gate electrode (BG1) may be electrically connected to the first top gate electrode (GE1) and may be utilized as a back-gate electrode for adjusting the characteristics of the first transistor (T1).

[0121] The first semiconductor layer (ACT1) may be disposed on the second insulating layer (INS2). In one embodiment, the first semiconductor layer (ACT1) may be disposed on the second insulating layer (INS2) and may be covered by a third insulating layer (INS3).

[0122] The first semiconductor layer (ACT1) may include a first channel region (CH1) overlapping the first top gate electrode (GE1), and a first drain region (DR1) and a first source region (SR1) spaced apart from each other with the first channel region (CH1) therebetween. For example, the first drain region (DR1) and the first source region (SR1) may be located on both sides of the first channel region (CH1). The first channel region (CH1) may be a region that is not conductive and maintains semiconductor characteristics, and the first drain region (DR1) and the first source region (SR1) may be conductive regions.

[0123] The first semiconductor layer (ACT1) may overlap the first bottom gate electrode (BG1) and the first top gate electrode (GE1). For example, the first channel region (CH1) of the first semiconductor layer (ACT1) may be positioned between the first bottom gate electrode (BG1) and the first top gate electrode (GE1), and may overlap the first bottom gate electrode (BG1) and the first top gate electrode (GE1).

[0124] The first semiconductor layer (ACT1) may be entirely covered by the third insulating layer (INS3). For example, the first semiconductor layer (ACT1) may be covered by the third insulating layer (INS3) except for a portion where at least one contact hole (e.g., a first contact hole (CNT1) and a second contact hole (CNT2)) for connection with the first drain electrode (DE1) and / or the first source electrode (SE1) is formed. Accordingly, the amount of hydrogen flowing into the first semiconductor layer (ACT1) in a process for forming a panel circuit layer (PCL) or the like can be reduced, thereby appropriately controlling the conductivity (e.g., carrier concentration) of the first semiconductor layer (ACT1) and / or the formation length of the first channel region (CH1).

[0125] The first top gate electrode (GE1) may be disposed on the third insulating layer (INS3). In one embodiment, the first top gate electrode (GE1) may be disposed on the third insulating layer (INS3) and covered by a fourth insulating layer (INS4).

[0126] The first top gate electrode (GE1) may be disposed on the first semiconductor layer (ACT1) so as to overlap the first channel region (CH1). The first top gate electrode (GE1) and the first semiconductor layer (ACT1) may be spaced apart from each other with a third insulating layer (INS3) interposed therebetween.

[0127] A first drain electrode (DE1) and a first source electrode (SE1) may be disposed on a fourth insulating layer (INS4). The first drain electrode (DE1) may be connected to a portion of the first semiconductor layer (ACT1). For example, the first drain electrode (DE1) may be connected to the first drain region (DR1) by a first contact hole (CNT1) penetrating the third insulating layer (INS3) and the fourth insulating layer (INS4). The first source electrode (SE1) may be connected to another portion of the first semiconductor layer (ACT1). For example, the first source electrode (SE1) may be connected to the first source region (SR1) by a second contact hole (CNT2) penetrating the third insulating layer (INS3) and the fourth insulating layer (INS4).

[0128] The second transistor (T2) may include a second bottom gate electrode (BG2) disposed on a substrate (SUB), a second gate electrode (GE2) (hereinafter referred to as “second top gate electrode (GE2)”) disposed on a second semiconductor layer (ACT2) disposed on the second bottom gate electrode (BG2) and including a second channel region (CH2), a second drain region (DR2), and a second source region (SR2). The second semiconductor layer (ACT2) may be disposed on at least a portion of the second bottom gate electrode (BG2). For example, at least a portion of the second semiconductor layer (ACT2) including the second channel region (CH2) may overlap the second bottom gate electrode (BG2). A second top gate electrode (GE2) may be disposed on a portion of a second semiconductor layer (ACT2) including a second channel region (CH2), and a third insulating layer (INS3) may be disposed between the second top gate electrode (GE2) and the second semiconductor layer (ACT2).

[0129] In one embodiment, the second transistor (T2) may further include a second drain electrode (DE2) and a second source electrode (SE2) connected to different portions of the second semiconductor layer (ACT2). Alternatively, the second transistor (T2) may not include a separate drain electrode and / or source electrode, and the second drain region (DR2) and / or the second source region (SR2) of the second active layer (ACT2) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the drain electrode and / or the source electrode of the second transistor (T2).

[0130] The second bottom gate electrode (BG2) is disposed on the buffer layer (BUF) and may be disposed on the same layer as the first bottom gate electrode (BG1). The second bottom gate electrode (BG2) may overlap the second semiconductor layer (ACT2). For example, the second bottom gate electrode (BG2) may be disposed under the second semiconductor layer (ACT2) so as to overlap at least the second channel region (CH2). A first insulating layer (INS1) and a second insulating layer (INS2) may be disposed between the second bottom gate electrode (BG2) and the second semiconductor layer (ACT2). The second bottom gate electrode (BG2) and the second semiconductor layer (ACT2) may be spaced apart from each other by a distance corresponding to the thicknesses of the first insulating layer (INS1) and the second insulating layer (INS2). The second bottom gate electrode (BG2) may face the second top gate electrode (GE2) with the second semiconductor layer (ACT2) therebetween.

[0131] The second bottom gate electrode (BG2) may or may not be connected to one electrode of the second transistor (T2). In one embodiment, the second bottom gate electrode (BG2) may be connected to the second source electrode (SE2) of the second transistor (T2) and may be utilized as a back-gate electrode for adjusting the characteristics of the second transistor (T2).

[0132] The second semiconductor layer (ACT2) is disposed on the second insulating layer (INS2), and may be disposed on the same layer as the first semiconductor layer (ACT1) and may include the same oxide semiconductor.

[0133] The second semiconductor layer (ACT2) may include a second channel region (CH2) overlapping the second top gate electrode (GE2), and a second drain region (DR2) and a second source region (SR2) spaced apart from each other with the second channel region (CH2) interposed therebetween. For example, the second drain region (DR2) and the second source region (SR2) may be located on both sides of the second channel region (CH2). The second channel region (CH2) may be a region that is not conductive and maintains semiconductor characteristics, and the second drain region (DR2) and the second source region (SR2) may be conductive regions.

[0134] The second semiconductor layer (ACT2) may overlap the second bottom gate electrode (BG2) and the second top gate electrode (GE2). For example, the second channel region (CH2) of the second semiconductor layer (ACT2) may be positioned between the second bottom gate electrode (BG2) and the second top gate electrode (GE2), and may overlap the second bottom gate electrode (BG2) and the second top gate electrode (GE2).

[0135] The second semiconductor layer (ACT2) may be entirely covered by the third insulating layer (INS3). For example, the second semiconductor layer (ACT2) may be covered by the third insulating layer (INS3) except for a portion where at least one contact hole (e.g., the third contact hole (CNT3) and the fourth contact hole (CNT4)) for connection with the second drain electrode (DE2) and / or the second source electrode (SE2) is formed. Accordingly, the amount of hydrogen flowing into the second semiconductor layer (ACT2) in a process for forming a panel circuit layer (PCL) or the like can be reduced, thereby appropriately controlling the conductivity (e.g., carrier concentration) of the second semiconductor layer (ACT2) and / or the formation length of the second channel region (CH2).

[0136] The second top gate electrode (GE2) is disposed on the third insulating layer (INS3) and may be disposed on the same layer as the first top gate electrode (GE1).

[0137] The second top gate electrode (GE2) may be disposed on the second semiconductor layer (ACT2) so as to overlap the second channel region (CH2). The second top gate electrode (GE2) and the second semiconductor layer (ACT2) may be spaced apart from each other with a third insulating layer (INS3) interposed therebetween.

[0138] The second drain electrode (DE2) and the second source electrode (SE2) may be disposed on the fourth insulating layer (INS4) and covered by the first passivation layer (PVX1).

[0139] The second drain electrode (DE2) may be connected to a portion of the second semiconductor layer (ACT2). For example, the second drain electrode (DE2) may be connected to the second drain region (DR2) by a third contact hole (CNT3) penetrating the third insulating layer (INS3) and the fourth insulating layer (INS4).

[0140] The second source electrode (SE2) may be connected to another portion of the second semiconductor layer (ACT2). For example, the second source electrode (SE2) may be connected to the second source region (SR2) by a fourth contact hole (CNT4) penetrating the third insulating layer (INS3) and the fourth insulating layer (INS4). In one embodiment, the second source electrode (SE2) may be further connected to the second bottom gate electrode (BG2). For example, the second source electrode (SE2) may be connected to the second bottom gate electrode (BG2) by a fifth contact hole (CNT5) penetrating the first insulating layer (INS1), the second insulating layer (INS2), the third insulating layer (INS3), and the fourth insulating layer (INS4).

[0141] The pixel transistors (TRS) including the first transistor (T1) and the second transistor (T2) may be covered by at least one passivation layer. For example, the pixel transistors (TRS) may be covered by the first passivation layer (PVX1) and the second passivation layer (PVX2) as illustrated in FIG. 5.

[0142] In the embodiment of FIG. 5, the second transistor (T2) of each pixel (PX) can be connected to the light emitting element (ED) of the corresponding pixel (PX) via a connection electrode (CNE). The connection electrode (CNE) can be disposed on the first via layer (VIA1) and covered by the second passivation layer (PVX2). For example, the connection electrode (CNE) can be disposed between the first via layer (VIA1) and the second passivation layer (PVX2).

[0143] The connecting electrode (CNE) may be connected to one electrode of the second transistor (T2). For example, the connecting electrode (CNE) may be disposed on the second source electrode (SE2) and connected to the second source electrode (SE2) through at least one contact hole or via hole penetrating the first passivation layer (PVX1) and the first via layer (VIA1).

[0144] Each of the electrodes, conductive patterns and / or wires provided on the conductive layers of the panel circuit layer (PCL) may include at least one conductive material, and may each have a single-layer or multi-layer structure. For example, the first and second bottom gate electrodes (BG1, BG2), the first and second top gate electrodes (GE1, GE2), the first and second source electrodes (SE1, SE2), the first and second drain electrodes (DE1, DE2), and the connection electrode (CNE3) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials, and may each have a single-layer or multi-layer structure.

[0145] In one embodiment, the first and second semiconductor layers (ACT1, ACT2) may include oxide semiconductors. For example, the first and second semiconductor layers (ACT1, ACT2) may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors. The oxide semiconductors used in forming the oxide transistors, including the first transistor (T1) and the second transistor (T2), are not limited to the materials exemplified above, and may vary depending on embodiments. In one embodiment, the first and second semiconductor layers (ACT1, ACT2) may include the same oxide semiconductor.

[0146] In one embodiment, the semiconductor layers of the pixel transistors (TRS) are high-mobility oxide semiconductors (e.g., high electron concentration, high mobility (e.g., about 50 cm)), such as indium-tin-gallium-zinc oxide (ITGZO) or indium-gallium oxide (IGO). 2 / Vs or higher mobility) of the oxide semiconductor). When the pixel transistors (TRS) are formed with a high-mobility oxide semiconductor, each transistor can be formed in a fine size (for example, a size including an active layer having a width and / or length in the range of approximately several micrometers to several tens of micrometers) while appropriately securing the mobility of each transistor. Accordingly, even in a high-resolution display device with a relatively narrow pixel area (PXA), the pixel transistors (TRS) can be easily arranged and / or formed, and the device characteristics and / or operating characteristics of the pixel transistors (TRS) can be appropriately secured. For example, even if the channel length of at least one switching transistor provided in the pixel (PX) is reduced, the operating characteristics (for example, appropriate switching characteristics) of the switching transistor can be secured. Accordingly, the area occupied by the pixel transistors (TRS) can be appropriately and / or easily reduced, and design space for other circuit elements or wiring can be secured. In addition, by forming pixel transistors (TRS) with high-mobility oxide semiconductors, the power consumption of the display device (10) can be reduced.

[0147] The light emitting element layer (LEL) can be disposed on the panel circuit layer (PCL) and can be located in the display area (DA). For example, the light emitting element layer (LEL) can be disposed on the panel circuit layer (PCL) in the display area (DA).

[0148] The light emitting element layer (LEL) may include light emitting elements (ED) of the pixels (PX). For example, the light emitting element layer (LEL) may include a pixel defining layer (PDL) (also referred to as a “bank”) that defines a light emitting area of ​​each of the pixels (PX) and a light emitting element (ED) positioned in each light emitting area. In one embodiment, the light emitting element layer (LEL) may further include a spacer (SPC) disposed on a portion of the pixel defining layer (PDL).

[0149] Each light emitting element (ED) may include a first electrode (PE) (e.g., an anode electrode) connected to at least one pixel transistor (TRS) (e.g., a second transistor (T2)) included in a corresponding pixel (PX), and an emission layer (EML) and a second electrode (CE) (e.g., a cathode electrode) sequentially disposed on the first electrode (PE). In one embodiment, the light emitting element (ED) may further include a first functional layer (e.g., a hole layer including a hole transport layer) interposed between the first electrode (PE) and the emission layer (EML), and a second functional layer (e.g., an electron layer including an electron transport layer) interposed between the emission layer (EML) and the second electrode (CE).

[0150] A first electrode (PE) of a light emitting element (ED) may be disposed on a panel circuit layer (PCL). In the embodiment of FIG. 5, the first electrode (PE) may be disposed on a second via layer (VIA2) corresponding to each light emitting region, and may be connected to a connection electrode (CNE) through at least one contact hole or via hole penetrating the second passivation layer (PVX2) and the second via layer (VIA2).

[0151] The first electrode (PE) may include a conductive material. In one embodiment, the first electrode (PE) may include a metal material having high reflectivity. For example, the first electrode (PE) may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or a multi-layer structure (e.g., ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, etc.) including indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni).

[0152] An emission layer (EML) of a light-emitting element (ED) may include a polymer material or a low-molecular material. Light emitted from the emission layer (EML) may contribute to image display. In one embodiment, the emission layer (EML) may be provided for each pixel (PX), and the emission layer (EML) of each pixel (PX) may emit visible light of a color corresponding to the pixel (PX). In another embodiment, the emission layer (EML) may be a common layer shared by pixels (PX) of different colors, and wavelength conversion layers and / or color filters corresponding to the color (or wavelength band) of light to be emitted from each pixel (PX) may be arranged in emission areas of at least some of the pixels (PX).

[0153] The second electrode (CE) of the light emitting element (ED) may include a conductive material. In one embodiment, the second electrode (CE) may be a common film formed over the entire display area (DA) in a form that covers the light emitting layer (EML) and the pixel defining layer (PDL). In one embodiment, the second electrode (CE) may be made of a transparent conductive material (TCO) such as ITO, IZO, ZnO, ITZO, etc. that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0154] The pixel defining layer (PDL) has an opening corresponding to each light-emitting area and can surround the light-emitting area. For example, the pixel defining layer (PDL) can be formed to cover an edge of a first electrode (PE) of a light-emitting element (ED) and can include an opening that exposes the remaining portion of the first electrode (PE). An area where the exposed first electrode (PE) and the light-emitting layer (EML) overlap (or an area including the same) can be defined as the light-emitting area of ​​each pixel (PX).

[0155] In one embodiment, the pixel defining layer (PDL) may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer (PDL) may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB), or other organic insulating materials.

[0156] A spacer (SPC) may be disposed on a portion of a pixel defining layer (PDL). The spacer (SPC) may include at least one organic insulating layer including an organic insulating material. The spacer (SPC) may include the same material as the pixel defining layer (PDL) or a different material from the pixel defining layer (PDL). In one embodiment, the pixel defining layer (PDL) and the spacer (SPC) may be sequentially formed through separate mask processes. In another embodiment, the pixel defining layer (PDL) and the spacer (SPC) may be simultaneously formed using a halftone mask. In this case, the pixel defining layer (PDL) and the spacer (SPC) may also be viewed as a single insulating film that is integral with each other.

[0157] A thin film encapsulation layer (TFEL) may be disposed on the light emitting element layer (LEL). The thin film encapsulation layer (TFEL) may cover the light emitting element layer (LEL) in the display area (DA) and extend to the non-display area (NDA) to be in contact with the panel circuit layer (PCL). For example, the thin film encapsulation layer (TFEL) may be disposed in the display area (DA) to cover the light emitting element layer (LEL), and an end of the thin film encapsulation layer (TFEL) may be located in a part of the non-display area (NDA) adjacent to the display area (DA). The thin film encapsulation layer (TFEL) may block the penetration of oxygen or moisture into the light emitting element layer (LEL) and mitigate electrical and / or physical impacts on the panel circuit layer (PCL) and the light emitting element layer (LEL).

[0158] In one embodiment, the thin film encapsulation layer (TFEL) may have a multilayer structure including a first encapsulation layer (TFE1), a second encapsulation layer (TFE2), and a third encapsulation layer (TFE3) sequentially arranged on a light emitting element layer (LEL). Each of the first encapsulation layer (TFE1) and the third encapsulation layer (TFE3) may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer (TFE2) may be an organic encapsulation layer including an organic material. The structure and / or material of the thin film encapsulation layer (TFEL) may vary depending on the embodiments.

[0159] Fig. 6 is a plan view showing an inspection pattern according to one embodiment. Fig. 7 is a cross-sectional view taken along line Q1-Q1' of Fig. 6.

[0160] Referring to FIGS. 6 and 7, an inspection pattern (TAG) according to one embodiment may include a first conductive pattern (COP1), a first inspection electrode (INE1) connected to the first conductive pattern (COP1), a semiconductor pattern (SCP), a second conductive pattern (COP2), a second inspection electrode (INE2) connected to the second conductive pattern (COP2), an inspection source electrode (IPS) connected to a part of the semiconductor pattern (SCP), a third inspection electrode (INE3) connected to the inspection source electrode (IPS), an inspection drain electrode (IPD) connected to another part of the semiconductor pattern (SCP), and a fourth inspection electrode (INE4) connected to the inspection drain electrode (IPD).

[0161] The first conductive pattern (COP1) may be disposed on the substrate (SUB). For example, the first conductive pattern (COP1) may be disposed on the substrate (SUB) on which the buffer layer (BUF) is formed, and may be disposed directly on the buffer layer (BUF).

[0162] The first conductive pattern (COP1) may be arranged on the same layer as the bottom gate electrode (BG) of the panel circuit layer (PCL) illustrated in FIG. 5. For example, the first conductive pattern (COP1) may be formed simultaneously with the bottom gate electrode (BG) through the same process.

[0163] A first insulating layer (INS1) and a second insulating layer (INS2) may be disposed on a first conductive pattern (COP1). The first insulating layer (INS1) may be a first insulating layer (INS1) of a panel circuit layer (PCL), and the second insulating layer (INS2) may be a second insulating layer (INS2) of the panel circuit layer (PCL). For example, the first insulating layer (INS1) and the second insulating layer (INS2) may be disposed on the first conductive pattern (COP1) so as to extend from the display area (DA) to the non-display area (NDA).

[0164] A semiconductor pattern (SCP) may be disposed on the second insulating layer (INS2). The semiconductor pattern (SCP) may be disposed directly on the second insulating layer (INS2). The semiconductor pattern (SCP) may be disposed on the same layer as the first semiconductor layer (ACT1) and the second semiconductor layer (ACT2) of the panel circuit layer (PCL). For example, the semiconductor pattern (SCP) may be simultaneously formed by the same process as the first semiconductor layer (ACT1) and the second semiconductor layer (ACT2).

[0165] The semiconductor pattern (SCP) may include an oxide semiconductor. For example, the semiconductor pattern (SCP) may include an oxide semiconductor as exemplified in the first semiconductor layer (ACT1) and the second semiconductor layer (ACT2) of the panel circuit layer (PCL).

[0166] A semiconductor pattern (SCP) may include a first conductive region (COR1), a patterned channel region (PCH), and a second conductive region (COR2). The patterned channel region (PCH) may overlap with a second conductive pattern (COP2). The first conductive region (COR1) and the second conductive region (COR2) may be spaced apart from each other with the patterned channel region (PCH) therebetween. For example, the first conductive region (COR1) and the second conductive region (COR2) may be located on both sides of the patterned channel region (PCH). The patterned channel region (PCH) may be a region that is not conductive and maintains semiconductor characteristics, and the first conductive region (COR1) and the second conductive region (COR2) may be conductive regions.

[0167] A third insulating layer (INS3) may be disposed on the semiconductor pattern (SCP). The third insulating layer (INS3) may be the third insulating layer (INS3) of the panel circuit layer (PCL). For example, the third insulating layer (INS3) may be disposed on the semiconductor pattern (SCP) and extend from the display area (DA) to the non-display area (NDA).

[0168] A second conductive pattern (COP2) may be disposed on a third insulating layer (INS3). For example, the second conductive pattern (COP2) may be disposed on the third insulating layer (INS3) and covered by a fourth insulating layer (INS4).

[0169] The second conductive pattern (COP2) may be arranged on the same layer as the top gate electrodes (GE1, GE2) of the panel circuit layer (PCL) illustrated in FIG. 5. For example, the second conductive pattern (COP2) may be formed simultaneously with the top gate electrodes (GE1, GE2) by the same process. The second conductive pattern (COP2) may overlap the first conductive pattern (COP1) and may be arranged to overlap the pattern channel region (PCH) of the semiconductor pattern (SCP).

[0170] The second conductive pattern (COP2) may be connected to a portion of the semiconductor pattern (SCP). For example, the second conductive pattern (COP2) may be connected to the semiconductor pattern (SCP) by a first via hole (VH1) penetrating the third insulating layer (INS3). In some embodiments, the second conductive pattern (COP2) may be in direct contact with the upper surface of the semiconductor pattern (SCP). In some embodiments, the second conductive pattern (COP2) may be in direct contact with the pattern channel region (PCH) of the semiconductor pattern (SCP).

[0171] A fourth insulating layer (INS4) may be disposed on the second conductive pattern (COP2). The fourth insulating layer (INS4) may be the fourth insulating layer (INS4) of the panel circuit layer (PCL). For example, the fourth insulating layer (INS4) may extend from the display area (DA) to the non-display area (NDA) and be disposed on the second conductive pattern (COP2).

[0172] A first inspection electrode (INE1), a second inspection electrode (INE2), a third inspection electrode (INE3), a fourth inspection electrode (INE4), an inspection source electrode (IPS), and an inspection drain electrode (IPD) may be disposed on a fourth insulating layer (INS4). The first inspection electrode (INE1), the second inspection electrode (INE2), the third inspection electrode (INE3), the fourth inspection electrode (INE4), the inspection source electrode (IPS), and the inspection drain electrode (IPD) are disposed on the same layer as the first and second source electrodes (SE1, SE2) and the first and second drain electrodes (DE1, DE2) of the panel circuit layer (PCL) illustrated in FIG. 5, and may be simultaneously formed by the same process.

[0173] The first inspection electrode (INE1) may be arranged to overlap a portion of the first conductive pattern (COP1). The first inspection electrode (INE1) may be connected to a portion of the first conductive pattern (COP1). For example, the first inspection electrode (INE1) may be connected to the first conductive pattern (COP1) through a second via hole (VH2) penetrating the first insulating layer (INS1), the second insulating layer (INS2), the third insulating layer (INS3), and the fourth insulating layer (INS4).

[0174] The second inspection electrode (INE2) may be arranged to overlap a portion of the second conductive pattern (COP2). The second inspection electrode (INE2) may be connected to a portion of the second conductive pattern (COP2). For example, the second inspection electrode (INE2) may be connected to the second conductive pattern (COP2) through a third via hole (VH3) penetrating the fourth insulating layer (INS4).

[0175] The inspection source electrode (IPS) may be arranged to overlap a portion of the semiconductor pattern (SCP). The inspection source electrode (IPS) may be connected to a portion of the semiconductor pattern (SCP). For example, the inspection source electrode (IPS) may be connected to a first conductive region (COR1) of the semiconductor pattern (SCP) through a fourth via hole (VH3) penetrating the third insulating layer (INS3) and the fourth insulating layer (INS4).

[0176] The third inspection electrode (INE3) may be connected to the inspection source electrode (IPS). For example, the third inspection electrode (INE3) may be formed integrally with the inspection source electrode (IPS). However, this is not limited to the third inspection electrode (INE3), and the third inspection electrode (INE3) may be formed separately from the inspection source electrode (IPS) and connected through a via hole.

[0177] The inspection drain electrode (IPD) may be arranged to overlap with another portion of the semiconductor pattern (SCP). The inspection drain electrode (IPD) may be connected to another portion of the semiconductor pattern (SCP). For example, the inspection drain electrode (IPD) may be connected to the second conductive region (COR2) of the semiconductor pattern (SCP) through a fifth via hole (VH5) penetrating the third insulating layer (INS3) and the fourth insulating layer (INS4).

[0178] The fourth inspection electrode (INE4) may be connected to the inspection drain electrode (IPD). For example, the fourth inspection electrode (INE4) may be formed integrally with the inspection drain electrode (IPD). However, this is not limited thereto, and the fourth inspection electrode (INE4) may be formed separately from the inspection drain electrode (IPD) and connected through a via hole.

[0179] The above-described inspection pattern (TAG) can be formed by including a semiconductor pattern (SCP) identical to the first and second semiconductor layers (ACT1, ACT2) of the first and second transistors (T1, T2) of the display area (DA). Accordingly, by inspecting the characteristics of the inspection pattern (TAG), the characteristics of the pixel transistors (TRS) can be inferred.

[0180] Fig. 8 is a graph showing the change in the characteristics of a transistor depending on the hydrogen content of the semiconductor layer. For example, Fig. 8 shows the electrical characteristics of a transistor formed when hydrogen was not supplied during the formation of the semiconductor layer, and when hydrogen was supplied at 3 sccm (standard cubic centimeters per minute) and 10 sccm, through the drain current (Id) according to the gate voltage (Vg).

[0181] Fig. 9 is a graph showing the change in characteristics of a transistor having a semiconductor layer without hydrogen. Fig. 10 is a graph showing the change in characteristics of a transistor having a semiconductor layer containing hydrogen. For example, Fig. 9 shows the hysteresis curve of a transistor formed without supplying hydrogen during the formation of the semiconductor layer of Fig. 8, and Fig. 10 shows the hysteresis curve of a transistor formed when hydrogen was supplied at 3 sccm during the formation of the semiconductor layer of Fig. 8.

[0182] Referring to Fig. 8, when hydrogen was supplied, the threshold voltage (Vth) was approximately 3.82 and the subthreshold swing (SS) was approximately 1.89, and when hydrogen was supplied at 3 sccm, the threshold voltage was approximately 1.88 and the subthreshold swing was approximately 1.28. In addition, when hydrogen was supplied at 10 sccm, the semiconductor layer was found to be conductive.

[0183] Referring to FIGS. 9 and 10, it was found that the hysteresis of a transistor including hydrogen in a semiconductor layer is reduced compared to a transistor not including hydrogen in a semiconductor layer.

[0184] Through Figures 8 to 10, it was confirmed that the hydrogen content of the semiconductor layer has a great influence on the characteristics of the transistor.

[0185] Through this, the inventors of the present invention inspect the characteristics of pixel transistors (TRS) through an inspection pattern (TAG) to confirm the hydrogen content of a semiconductor layer, thereby inspecting and monitoring the characteristics of pixel transistors (TRS) within a display area (DA) even when they change according to manufacturing process conditions, thereby maintaining uniform display quality.

[0186] Hereinafter, with reference to the above-described drawings 1 to 7, a method for inspecting a display device including an inspection pattern (TAG) will be described.

[0187] Since the inspection pattern (TAG) includes an oxide pattern (SCP), which is the same semiconductor layer as the pixel transistors (TRSs) of the display area (DA), it represents the pixel transistors (TRSs) of the display area (DA) and can be used to check the characteristics of the pixel transistors (TRSs) of the display area (DA). For example, the characteristic of the transistor may be the capacitance value of the semiconductor layer.

[0188] In one embodiment, during the manufacturing process of the display device (10), the manufacturing process of the inspection pattern (TAG) may be performed simultaneously with the manufacturing process of the pixel transistor (TRS) of the panel circuit layer (PCL). For example, the bottom gate electrode (BG) of the pixel transistor (TRS) and the first conductive pattern (COP1) of the inspection pattern (TAG), the semiconductor layers (ACT1, ACT2) of the pixel transistor (TRS) and the semiconductor pattern (SCP) of the inspection pattern (TAG), the top gate electrodes (GE1, GE2) of the pixel transistor (TRS) and the second conductive pattern (COP2) of the inspection pattern (TAG), the source and drain electrodes (SE1, SE2, DE1, DE2) of the pixel transistor (TRS) and the first to fourth inspection electrodes (INE1, INE2, INE3, IN4) of the inspection pattern (TAG) may each be formed simultaneously through the same process.

[0189] After the pixel transistor (TRS) and inspection pattern (TAG) are formed, inspection can be performed by connecting a measuring device to the inspection pattern (TAG). The measuring device can be equipped with terminals capable of applying an electric signal to the first to fourth inspection electrodes (INE1, INE2, INE3, IN4).

[0190] In one embodiment, the capacitance of the back channel of the semiconductor pattern (SCP) of the inspection pattern (TAG) can be measured. Here, the back channel of the semiconductor pattern (SCP) can refer to a channel formed on the lower side of the semiconductor pattern (SCP) adjacent to the first conductive pattern (COP1). The capacitance of the back channel can be obtained by measuring the capacitance of the semiconductor pattern (SCP) while the back channel is formed in the semiconductor pattern (SCP).

[0191] A method for forming a back channel in a semiconductor pattern (SCP) of an inspection pattern (TAG) can be formed by applying an AC signal (e.g., frequency) to a first conductive pattern (COP1) through a first inspection electrode (INE1) in a measuring device and applying a DC signal to a second conductive pattern (COP2) through a second inspection electrode (INE2).

[0192] As described above, the second conductive pattern (COP2) can be connected by directly contacting the upper surface of the semiconductor pattern (SCP). A third insulating layer (INS3) is interposed between the second conductive pattern (COP2) and the semiconductor pattern (SCP). Since the third insulating layer (INS3) is thick, even if an electric signal is applied to the second conductive pattern (COP2) and the first conductive pattern (COP1), a tunneling effect does not occur between the second conductive pattern (COP2) and the first conductive pattern (COP1). In the present embodiment, by directly contacting the second conductive pattern (COP2) with the semiconductor pattern (SCP), a tunneling effect can be generated between the second conductive pattern (COP2) and the first conductive pattern (COP1). In a state where there is an electron trap due to hydrogen present in the semiconductor pattern (SCP), a current can move along the trap according to the tunneling effect.

[0193] That is, when an electric signal is applied to the first conductive pattern (COP1) and the second conductive pattern (COP2), a current flows between the first conductive pattern (COP1) and the second conductive pattern (COP2), and the current and capacitance within the semiconductor pattern (SCP) can be measured through the third inspection electrode (INE3) and the fourth inspection electrode (INE4).

[0194] Figure 11 is a graph showing the capacitance of a semiconductor pattern according to frequency. For example, it shows the capacitance of a semiconductor pattern (SCP) according to the frequency of an AC signal applied to a second conductive pattern (COP2).

[0195] Referring to FIG. 11, it shows a characteristic in which the capacitance (Qcp) of the semiconductor pattern (SCP) decreases as the frequency of the AC signal applied to the second challenge pattern (COP2) increases.

[0196] In this embodiment, the capacitance value of a semiconductor pattern (SCP) having a back channel formed therein can be measured using the aforementioned inspection pattern (TAG). Using this capacitance value, the hydrogen content of the semiconductor pattern (SCP) can be determined by comparing it with a reference table in which the hydrogen content according to the capacitance value is analyzed.

[0197] Therefore, during the manufacturing of the display device (10), the hydrogen content of the semiconductor pattern (SCP) can be measured using the inspection pattern (TAG) at regular intervals to monitor the characteristics of the pixel transistors (TRS).

[0198] Fig. 12 is a cross-sectional view showing an inspection pattern of a display device according to another embodiment. Fig. 12 shows another embodiment of Fig. 7 described above.

[0199] Referring to FIG. 12, the present embodiment differs from the aforementioned FIG. 7 in that it further includes a connection pattern (CNP) connecting the first conductive pattern (COP1) and the semiconductor pattern (SCP) and the second conductive pattern (COP2) is spaced apart from the semiconductor pattern (SCP). Hereinafter, descriptions of the same configuration as the aforementioned embodiment will be omitted, and the differences will be described.

[0200] According to one embodiment, an inspection pattern (TAG) may include a first conductive pattern (COP1), a first inspection electrode (INE1) connected to the first conductive pattern (COP1), a connection pattern (CNP) connecting the first conductive pattern (COP1) and a semiconductor pattern (SCP), a semiconductor pattern (SCP), a second conductive pattern (COP2), a second inspection electrode (INE2) connected to the second conductive pattern (COP2), an inspection source electrode (IPS) connected to a part of the semiconductor pattern (SCP), a third inspection electrode (INE3) connected to the inspection source electrode (IPS), an inspection drain electrode (IPD) connected to another part of the semiconductor pattern (SCP), and a fourth inspection electrode (INE4) connected to the inspection drain electrode (IPD).

[0201] A connection pattern (CNP) may be arranged on a first conductive pattern (COP1). For example, the connection pattern (CNP) may be arranged in direct contact with the first conductive pattern (COP1). The connection pattern (CNP) may overlap with a semiconductor pattern (SCP) and may be arranged to overlap with a pattern channel region (PCH) of the semiconductor pattern (SCP). The connection pattern (CNP) may be arranged in a sixth via hole (VH6) penetrating a first insulating layer (INS1) and a second insulating layer (INS2). The sixth via hole (VH6) may be arranged to overlap with the first conductive pattern (COP1), the second conductive pattern (COP2), and the semiconductor pattern (SCP). The connection pattern (CNP) may be connected to the first conductive pattern (COP1) and the semiconductor pattern (SCP) through the sixth via hole (VH6). For example, the connection pattern (CNP) may be in direct contact with a lower surface of the pattern channel region (PCH). The first challenge pattern (COP1), the second challenge pattern (COP2), and the connection pattern (CNP) can be arranged to overlap with the pattern channel region (PCH) of the semiconductor pattern (SCP).

[0202] The connection pattern (CNP) may be arranged in contact with the side surfaces of the first insulating layer (INS1) and the second insulating layer (INS2). In some embodiments, the upper surface of the connection pattern (CNP) may be aligned with and coincide with the upper surface of the second insulating layer (INS2). However, the present invention is not limited thereto, and at least a portion of the connection pattern (CNP) may be arranged to extend to the upper surface of the second insulating layer (INS2).

[0203] The connecting pattern (CNP) may include a conductive material. For example, the connecting pattern (CNP) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials, and each may have a single-layer or multi-layer structure.

[0204] A semiconductor pattern (SCP) may be disposed on a connection pattern (CNP) and a second insulating layer (INS2), and a third insulating layer (INS3) may be disposed on the semiconductor pattern (SCP). A second conductive pattern (COP2) may be disposed on the third insulating layer (INS3) overlapping the semiconductor pattern (SCP). Unlike in FIG. 7, the second conductive pattern (COP2) may be disposed spaced apart from the semiconductor pattern (SCP).

[0205] In one embodiment, the capacitance of the front channel of the semiconductor pattern (SCP) of the inspection pattern (TAG) can be measured. Here, the front channel of the semiconductor pattern (SCP) can refer to a channel formed on the upper side of the semiconductor pattern (SCP) adjacent to the second conductive pattern (COP2). Accordingly, the front channel can be formed by contacting the first conductive pattern (COP1) to the semiconductor pattern (SCP) through the connection pattern (CNP) and disposing the second conductive pattern (COP2) apart from the semiconductor pattern (SCP).

[0206] The capacitance of the front channel can be obtained by measuring the capacitance of the semiconductor pattern (SCP) while a back channel is formed in the semiconductor pattern (SCP). As a method of forming a front channel in the semiconductor pattern (SCP) of the inspection pattern (TAG), a measurement device may apply a direct current signal to the first conductive pattern (COP1) through the first inspection electrode (INE1) and apply an alternating current signal (e.g., frequency) to the second conductive pattern (COP2) through the second inspection electrode (INE2). In the present embodiment, by directly connecting the first conductive pattern (COP1) to the semiconductor pattern (SCP) through the connection pattern (CNP), a tunneling effect can be generated between the second conductive pattern (COP2) and the first conductive pattern (COP1).

[0207] Therefore, when an electric signal is applied to the first conductive pattern (COP1) and the second conductive pattern (COP2), a current flows between the first conductive pattern (COP1) and the second conductive pattern (COP2), and the current and capacitance within the semiconductor pattern (SCP) can be measured through the third inspection electrode (INE3) and the fourth inspection electrode (INE4).

[0208] Fig. 13 is a cross-sectional view showing an inspection pattern of a display device according to another embodiment. Fig. 13 shows an embodiment different from the above-described Figs. 7 and 12.

[0209] Referring to FIG. 13, the present embodiment shows an inspection pattern (TAG) having the structures of the embodiments of FIGS. 7 and 12 together. For example, it differs from the above-described embodiments in that it has a connection pattern (CNP) connecting a first conductive pattern (COP1) and a semiconductor pattern (SCP), and the conductive pattern (COP2) is in contact with the semiconductor pattern (SCP).

[0210] In one embodiment, the capacitance of a dual channel of a semiconductor pattern (SCP) of a test pattern (TAG) can be measured. Here, the dual channel of the semiconductor pattern (SCP) may refer to a front channel formed on an upper side of the semiconductor pattern (SCP) adjacent to a second conductive pattern (COP2), and a back channel formed on a lower side of the semiconductor pattern (SCP) adjacent to a first conductive pattern (COP1). Accordingly, the first conductive pattern (COP1) may be brought into contact with the semiconductor pattern (SCP) through a connection pattern (CNP), and the second conductive pattern (COP2) may be brought into contact with the semiconductor pattern (SCP), thereby forming a dual channel.

[0211] The capacitance of the dual channel can be obtained by measuring the capacitance of the semiconductor pattern (SCP) while forming a front channel and a back channel on the semiconductor pattern (SCP). As a method of forming a dual channel in the semiconductor pattern (SCP) of the inspection pattern (TAG), the measurement device can form the dual channel by applying an AC signal (e.g., frequency) to the first conductive pattern (COP1) through the first inspection electrode (INE1), and applying an AC signal (e.g., frequency) to the second conductive pattern (COP2) through the second inspection electrode (INE2).

[0212] In the present embodiment, by directly connecting the first conductive pattern (COP1) to the semiconductor pattern (SCP) through the connection pattern (CNP) and connecting the second conductive pattern (COP2) to the semiconductor pattern (SCP), a tunneling effect can be generated between the second conductive pattern (COP2) and the first conductive pattern (COP1). Therefore, when an electric signal is applied to the first conductive pattern (COP1) and the second conductive pattern (COP2), a current flows between the first conductive pattern (COP1) and the second conductive pattern (COP2), and the current and capacitance within the semiconductor pattern (SCP) can be measured through the third inspection electrode (INE3) and the fourth inspection electrode (INE4).

[0213] Therefore, by measuring the capacitance of the semiconductor pattern (SCP) using the inspection pattern (TAG) at regular intervals during the manufacturing of the display device (10) to check the hydrogen content, the characteristics of the pixel transistors (TRS) can be monitored.

[0214] Fig. 14 is a plan view showing a display panel according to another embodiment.

[0215] Referring to FIG. 14, this embodiment differs from the above-described FIG. 2 in that it includes multiple inspection patterns (TAG1, TAG2, TAG3).

[0216] A plurality of inspection patterns (TAG1, TAG2, TAG3) may be arranged in the non-display area (NDA). For example, a first inspection pattern (TAG1) may be arranged in the space between the first driving unit (120) and the pad area (PA), and a second inspection pattern (TAG2) may be arranged adjacent to the first inspection pattern (TAG1) with the pad area (PA) therebetween. A third inspection pattern (TAG3) may be arranged on the upper left side of the display panel (110). However, the present invention is not limited thereto, and the plurality of inspection patterns (TAG1, TAG2, TAG3) may be arranged anywhere in the non-display area (NDA). In addition, the plurality of inspection patterns (TAG1, TAG2, TAG3) may all be arranged in the space between the first driving unit (120) and the pad area (PA).

[0217] In one embodiment, the first inspection pattern (TAG1) may be the inspection pattern illustrated in FIG. 7, the second inspection pattern (TAG2) may be the inspection pattern illustrated in FIG. 11, and the third inspection pattern (TAG3) may be the inspection pattern illustrated in FIG. 13. For example, the first inspection pattern (TAG1) may be a inspection pattern capable of measuring back channel capacitance, the second inspection pattern (TAG2) may be a inspection pattern capable of measuring front channel capacitance, and the third inspection pattern (TAG3) may be a inspection pattern capable of measuring dual channel capacitance.

[0218] In this embodiment, the hydrogen content of a semiconductor pattern (SCP) can be analyzed by measuring the capacitance of various channels of the inspection patterns, including a plurality of inspection patterns (TAG1, TAG2, TAG3).

[0219] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. A substrate including a display area and a non-display area; A transistor disposed on the display area of ​​the substrate and including a semiconductor layer; and At least one inspection pattern is disposed on the non-display area of ​​the substrate and includes a semiconductor pattern, The above inspection pattern is, A first conductive pattern and a second conductive pattern spaced apart in the thickness direction with the semiconductor pattern interposed therebetween; and It comprises an inspection source electrode connected to a part of the semiconductor pattern and an inspection drain electrode connected to another part of the semiconductor pattern, The above second challenge pattern is a display device that contacts the above semiconductor pattern.

2. In paragraph 1, A display device wherein the first conductive pattern is disposed on the substrate, and further includes a first insulating layer and a second insulating layer interposed between the semiconductor pattern and the first conductive pattern.

3. In paragraph 1, A display device wherein the semiconductor pattern includes a pattern channel region, a first conductive region and a second conductive region spaced apart from each other with the pattern channel region interposed therebetween.

4. In paragraph 3, A display device in which the first challenge pattern overlaps the pattern channel region.

5. In paragraph 3, A display device wherein the inspection source electrode is connected to the first conducting region, and the inspection drain electrode is connected to the second conducting region.

6. In paragraph 1, A display device in which the second challenge pattern is arranged on the semiconductor pattern and overlaps the first challenge pattern.

7. In paragraph 1, Further comprising a third insulating layer disposed between the second challenge pattern and the semiconductor pattern, A display device in which the second challenge pattern contacts the semiconductor pattern through a first via hole penetrating the third insulating layer.

8. In paragraph 1, Further comprising a fourth insulating layer disposed between the inspection source electrode and the inspection drain electrode and the second conductive pattern, A display device in which the above-described inspection source electrode and the above-described inspection drain electrode are connected to the semiconductor pattern through a second via hole and a third via hole penetrating the fourth insulating layer.

9. In paragraph 1, A fourth insulating layer disposed on the second challenge pattern; and A display device further comprising a first test electrode, a second test electrode, a third test electrode, and a fourth test electrode, which are arranged on the fourth insulating layer and are spaced apart from each other.

10. In paragraph 9, A display device wherein the first inspection electrode is connected to the first conductive pattern, and the second inspection electrode is connected to the second conductive pattern.

11. In paragraph 9, A display device wherein the third inspection electrode extends from the inspection source electrode, and the fourth inspection electrode extends from the inspection drain electrode.

12. In paragraph 1, A display device wherein the semiconductor layer of the transistor in the display area includes the same material as the semiconductor pattern of the inspection pattern.

13. In paragraph 12, A display device wherein the semiconductor layer of the transistor of the display area and the semiconductor pattern of the inspection pattern include oxide semiconductors.

14. In paragraph 1, Further comprising a connection pattern arranged between the first challenge pattern and the semiconductor pattern, The above first challenge pattern is a display device electrically connected to the semiconductor pattern through the connection pattern.

15. A substrate including a display area and a non-display area; A transistor disposed on the display area of ​​the substrate and including a semiconductor layer; and A test pattern is disposed on the non-display area of ​​the above substrate and includes a semiconductor pattern, The above inspection pattern is, A first conductive pattern and a second conductive pattern spaced apart in the thickness direction with the semiconductor pattern interposed therebetween; an inspection source electrode connected to a portion of the semiconductor pattern and an inspection drain electrode connected to another portion of the semiconductor pattern; and A connection pattern disposed between the first challenge pattern and the semiconductor pattern, The above connection pattern is a display device in contact with the first challenge pattern and the semiconductor pattern.

16. In paragraph 15, A display device wherein the semiconductor layer of the transistor of the display area and the semiconductor pattern of the inspection pattern include oxide semiconductors.

17. In paragraph 15, Further comprising a first insulating layer and a second insulating layer interposed between the semiconductor pattern and the first conductive pattern, The above connection pattern is arranged in a first via hole penetrating the first insulating layer and the second insulating layer, A display device in which the first via hole overlaps the first conductive pattern and the semiconductor pattern.

18. In paragraph 15, The semiconductor pattern includes a pattern channel region, a first conductive region and a second conductive region spaced apart from each other with the pattern channel region interposed therebetween, The above connection pattern is a display device that contacts the above pattern channel area.

19. In paragraph 18, A display device in which the first challenge pattern, the second challenge pattern, and the connection pattern overlap with the pattern channel region of the semiconductor pattern.

20. In paragraph 15, Further comprising a third insulating layer disposed between the semiconductor pattern and the second conductive pattern, The second challenge pattern is a display device spaced apart from the semiconductor pattern.

Images