Increasing density of semiconductor devices on a substrate

Abstract

Structures that maximize the utilization of a substrate are disclosed. A device of these teachings includes a substrate having two opposing surfaces, at least one semiconductor heterostructure epitaxially grown on one surface of the two opposing surfaces of the substrate, and at least another semiconductor heterostructure epitaxially grown on a surface of the substrate opposite to the one surface. Methods for fabricating the device are also disclosed.

Description

Docket No.: 10966-02 INCREASING DENSITY OF SEMICONDUCTOR DEVICES ON A SUBSTRATE CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 548,460, entitled INCREASING DENSITY OF SEMICONDUCTOR DEVICES ON A SUBSTRATE, filed November 14, 2023, which is incorporated herein by reference in its entirety and for all purposes. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with U.S. Government support from the U.S. Army Research Laboratory - Army Research Office under Grant No. W911NF-22-2-0177 and National Science Foundation under Grants No.2139899, and 2039380. The U.S. Government has certain rights in the invention. BACKGROUND

[0003] These teachings relate generally to increasing density of semiconductor devices on a substrate and, particularly, to at least one semiconductor heterostructure grown on each of the two faces of a substrate.

[0004] Epitaxy is a transformative process that facilitates the controlled growth of crystalline layers on a substrate, leading to the synthesis of advanced semiconductor materials and devices. Techniques such as Molecular Beam Epitaxy (MBE) and Metal-Organic Chemical Vapor Deposition (MOCVD) provide the means for precise manipulation of material properties at the atomic level, enabling the formation of highly engineered multilayer thin films. Epitaxy empowers researchers to exercise precise control over key parameters such as thickness, alloy composition, doping levels, and interface characteristics, resulting in the creation of advanced heterostructures. These heterostructures are meticulously designed to possess specific energy landscapes, thereby offering a detailed control over carrier transport. By leveraging the chemical, structural, and symmetry properties of different crystals, epitaxy has opened up an expansive application space.

[0005] At present, epitaxy involves the growth of materials on a single substrate face, each with a specific crystallographic orientation. As the density of structures of a surface grows, there is a need for maximizing the utilization of a substrate.Docket No.: 10966-02 BRIEF SUMMARY

[0006] Structures that maximize the utilization of a substrate are disclosed below. In one instantiation of these teachings, a device of these teachings includes a substrate having two opposing surfaces, at least one semiconductor heterostructure epitaxially grown on one surface of the two opposing surfaces of the substrate, and at least another semiconductor heterostructure epitaxially grown on a surface of the substrate opposite to the one surface. In one instance, the substrate is a double-sided polished crystalline substrate. In one instance, heterostructures are epitaxially grown by at least one of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor-phase epitaxy (HVPE), ultra-high vacuum chemical vapor deposition (UHVCVD), atomic layer deposition (ALD), atomic layer epitaxy (ALE), or reactive sputtering. In another instance, the device also includes wire bonding or through-hole contacts connecting heterostructures on the one surface to heterostructures on the surface of the substrate opposite to the one surface.

[0007] Methods for fabricating the device of these teachings are also disclosed.

[0008] For a better understanding of the present teachings, together with other and further objects thereof, reference is made to the accompanying drawings and detailed description and its scope will be pointed out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1a-1c show a schematic representation of epitaxially grown instantiation of a device of these teachings;

[0010] Figures 2a-2d show a schematic representation of an instantiation of a device of these teachings and measurements from that instantiation;

[0011] Figures 2e-2g show the schematic representation of the instantiation of a device of these teachings and other measurements from that instantiation;

[0012] Figures 2h-2k show further measurements from that instantiation;

[0013] Figures 3a-3c show device processing flow for an instantiation of the device of these teachings, a 3D representation of the completed instantiation, an optical image from the instantiation;

[0014] Figure 3d-3h is a schematic representation of a setup for measurements on the instantiation of the device of these teachings;

[0015] Figures 3e-3h show two device processing flows (labeled roman numeral i or ii) for an instantiation of the device of these teachings including through-hole contacts;

[0016] Figures 4a-4d show a graphical representation of measurement results for the instantiation, shown in Figures 2a-2d, of the device of these teachings;Docket No.: 10966-02

[0017] Figures 5a-d show energy bands for the instantiation of the device of these teachings, a circuit schematic for the instantiation of the device of these teachings, and measurements for that instantiation;

[0018] Figures 6a-6b show measurements on an instantiation of a sub-device of these teachings grown on one of two opposing surface of the substrate, the measurements taken before and after growing another sub-device grown on the other of the two opposing surfaces; and

[0019] Figures 7a-7d represent measurements on a sub-device of the instantiation shown in Fig.3d. DETAILED DESCRIPTION

[0020] The advantages and other features of the technology disclosed herein will become more readily apparent to those having ordinary skill in the art from the following detailed description of certain preferred embodiments taken in conjunction with the drawings which set forth representative embodiments of the present technology and wherein like reference numerals identify similar structural elements. Directional indications such as upward, downward, right, left, bottom, top, and the like are used with respect to the figures and are not meant in a limiting manner.

[0021] Structures that maximize the utilization of a substrate are disclosed below. In one instantiation of these teachings, a device of these teachings includes a substrate having two opposing surfaces, at least one semiconductor heterostructure epitaxially grown on one of the two opposing surfaces of the substrate, and at least another semiconductor heterostructure epitaxially grown on a surface of the substrate opposite to the one surface. In one instance, heterostructures are epitaxially grown by at least one of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor-phase epitaxy (HVPE), ultra-high vacuum chemical vapor deposition (UHVCVD), atomic layer deposition (ALD), atomic layer epitaxy (ALE) or reactive sputtering. In another instance, the substrate is a double-sided polished crystalline substrate. Substrates may include GaN, AlN, SiC, Si, Sapphire, ZnO, and any polytype thereof. The substrate faces on which epitaxy is performed may be polar, semi-polar, or non-polar. The substrate can be conductive or semi- insulating.

[0022] An actual cut at a surface will most likely differ from a completely straight cut at the surface. A ”miscut,” as used herein, refers to the error incurred when cutting the surface. The miscut is characterized by angle(s) between the miscut direction and the ideal direction.

[0023] In one instance, the miscut in the substrate is between about 0 degrees and about 20 degrees.Docket No.: 10966-02

[0024] In another instance, the substrate has the two opposing surfaces that are substantially nonparallel. Substantially, as used in substantially nonparallel, refers to surfaces that are nonparallel to a degree higher than the usually accepted error in surfaces that are considered parallel (see, for example, Parallelism of a Surface at www.engineeringessentials.com / gdt / parallelism / parallelism- surf.htm).

[0025] Gallium bonding , asrefers to using gallium to mount near room temperature, then at higher temperatures gallium is still liquid and adhesive forces hold it in place (see, for example, https: / / www.mdpi.com / 1996-1944 / 13 / 24 / 5590 or releases / 768113 ). of material (for example, GaN / sapphire) used asthe Merriam-Webster dictionary, at www.merriam-webster.com / dictionary / wafer .) herein, is the slice of material referred to as a wafer.

[0028] A “holder,” as used herein, refers to a carrier wafer (or slice of material or equivalent) on which the substrate is mounted.

[0029] In one or more instantiations, the system of these teachings includes a substrate having two opposing surfaces, at least one slice of material, the material selected such that one surface of the two opposing surfaces of the substrate can bonded to one of the at least one slice of material with a detachable bond. At least one semiconductor heterostructure epitaxially is grown on one surface of the two opposing surfaces of the substrate. At least another semiconductor heterostructure is epitaxially grown on a surface of the substrate opposite to the one surface.

[0030] In another instance, the device and system of these teachings include at least one of wire bonds or through-hole contacts. Through-holes may be achieved by substrate-via etching by dry etching, wet etching, laser drilling, or by any combination of such techniques. Through-holes are holes, extending vertically from one layer to another layer. in some instances, an inner surface of the hole has an electrically insulating layer (in order to electrically isolate from intervening layers).

[0031] In one instance, the at least one semiconductor heterostructure and the at least another semiconductor heterostructure include optical or acoustic components.

[0032] In another instance, the at least one semiconductor heterostructure and the at least another semiconductor heterostructure include at least one of transistors, diodes, LEDs, laser diodes, Schottky diodes, resonant tunneling diodes, avalanche diodes, waveguides, reflectors, photonic crystals, integrated circuits, or any combinations thereof.Docket No.: 10966-02

[0033] In yet another instance, the at least one semiconductor heterostructure includes Microwave and RF amplifiers, rectifiers, and corresponding circuit components and the at least another semiconductor heterostructure includes digital electronics and circuits.

[0034] In a further instance, the at least one semiconductor heterostructure includes at least one of LED or laser diodes and the at least another semiconductor heterostructure includes electronic sub-devices and circuits.

[0035] In still another instance, the at least one semiconductor heterostructure includes p- channel metal-polar III-N heterojunction field effect transistors (FETs) and the at least another semiconductor heterostructure includes n-channel nitrogen-polar III-N heterojunction FETs. In a related instance, the at least one semiconductor heterostructure includes p-channel nitrogen-polar III- N heterojunction field effect transistors (FETs) and the at least another semiconductor heterostructure includes n-channel metal-polar III-N heterojunction FETs. In one instance, III-N heterojunction FETs are GaN / Al(Ga)N heterojunction FETs.

[0036] In one or more instantiations, the method of these teachings includes epitaxially growing at least one semiconductor heterostructure on one surface of two opposing surfaces of a substrate, and epitaxially growing at least another semiconductor heterostructure on a surface of the substrate opposite to the one surface.

[0037] In one instance, epitaxially growing the at least one semiconductor heterostructure on the one surface of two opposing surfaces of the substrate includes bonding the one surface to a holder, and epitaxially growing the at least another semiconductor heterostructure on the surface of the substrate opposite to the one surface includes releasing the one surface from the holder and bonding the surface of the substrate opposite to the one surface to the holder.

[0038] In another instance, the method of these teachings also includes further includes polishing both of the two opposing surfaces.

[0039] In another instance, the method of these teachings also includes forming through holes in the substrate at predetermined locations.

[0040] The method of these teachings can be applied to fabricating the instantiations disclosed above.

[0041] In order to further elucidate these teachings, an illustrative instantiation is disclosed hereinbelow. It should be noted that these teachings are not only limited to only this instantiation.

[0042] With over three decades of extensive research, (Al, Ga)N based HEMTs have demonstrated outstanding performances both in high-power and high-speed applications. The broken inversion symmetry along the c-axis of wurtzite GaN and AlN and the difference in electronegativityDocket No.: 10966-02 between the metal and nitrogen atoms lead to spontaneous polarization, of which its amplitude strongly depends on group-III composition for alloys. Together with the piezoelectric polarization induced by the tensile strain formed in heteroepitaxial layers, dense two-dimensional electron gases (2DEGs) with high electron mobility can be formed at (Al, Ga)N heterointerfaces despite the large carrier masses and dopant activation energies associated with ultra-wide bandgap semiconductors.

[0043] Furthermore, as a consequence of the lack of inversion symmetry, the polarization of nitrogen-polar (N-polar) GaN and its alloys are opposite in direction to that of their metal-polar counterparts, leading to the formation of a 2DEG at the GaN / AlGaN interface closer to sample surface for a N-polar heterostructure. While most of the HEMT studies to date have focused on metal- polar heterostructures, such as AlGaN / GaN HEMTs, N-polar heterostructures bring several unique advantages which include a stronger back barrier, the absence of a wide-bandgap top-barrier, and easier formation of ohmic contacts.

[0044] The versatility of (Al, Ga, In)N semiconductors extends far beyond the realm of electronics. One of their exceptional characteristics is the direct bandgap in the wurtzite phase across their entire compositional range. This unique property makes (Al, Ga, In)N alloys and heterostructures highly advantageous for a wide range of optoelectronic applications. The breakthroughs achieved in the late 1980s and early 1990s, such as the development of high internal quantum efficiency (IQE) InGaN quantum wells and the demonstration of conductive p-type Mg- doped GaN, have laid the foundation for significant advancements in various fields. These advancements include solid-state lighting, where (In, Ga)N-based LEDs and LDs have revolutionized energy-efficient lighting solutions, full-color displays enabling vibrant and immersive visual experiences, and high-density optical data storage, providing large storage capacities and fast access speeds, to name just a few. Recently, (Al, Ga, In)N based optoelectronic devices are being explored for the use of visible light as an alternative band for wireless communication, as the visible spectrum has a bandwidth larger than 2000 times that of the entire RF spectrum. For such technology, often coined Li-Fi, high-speed modulation of light-emission is desirable through the use of current or voltage drivers. Since technologically mature (Al, Ga)N based HEMTs are based on the same materials family, monolithic integration of transistors as voltage drivers for the LED light sources is a great candidate for achieving such a setup.

[0045] Despite these capabilities, to the inventors’ knowledge, no N-polar heterostructure has been used for monolithic integration of HEMTs and LEDs. In fact, challenges associated with a high impurity incorporation efficiency and reduced formation energy of nitrogen vacancies for N- polar (In, Ga)N growth which restricts the internal quantum efficiency of visible emitters, currently limit the growth of useful optoelectronic devices to those with metal polarity. Moreover, whenDocket No.: 10966-02 monolithically integrating HEMTs and LEDs on a single growth front, multiple epitaxial layers need to be either selectively removed or regrown in order to expose the LED heterostructure buried underneath the HEMT structure or vice versa. Exposing the buried heterostructure by dry etching induces plasma damage, leading to diminished light emission and degradation of contacts. Similarly, with a selective growth method, the ex-situ nature of regrowth technique results in a poor growth interface, increasing the leakage pathways.

[0046] On the other hand, clean growth interfaces, low dislocation-densities, and superior crystallinity of both HEMT and LED heterostructures can be achieved without any external damage by leveraging the recent development of double-side epitaxy-ready polar single-crystal substrates. The present teachings use molecular beam epitaxial growth on both sides of 2-plane GaN substrates with a dislocation density less than or about equal to 104cm-2to monolithically integrate N-polar (Al,Ga)N / GaN HEMTs with metal-polar blue (Al,In,Ga)N LEDs. This double-side monolithic integration scheme reduces the chip area by directly growing and processing the drive circuits on the opposite face of the substrate, overcoming the physical density limit of lateral monolithic integration without the added complexity of mass transfer techniques that are needed for heterogeneous integration.

[0047] The illustrative sample was grown on a bulk Si-doped GaN substrate grown by the ammonothermal synthesis method with a carrier concentration reaching 1019cm-3and threading dislocation density on the order of 104cm-2. Both Ga-polar and N-polar surfaces were prepared for growth by mechanical and chemo-mechanical polishing to obtain atomically smooth surfaces with a miscut angle of 0.5°. Before each growth, substrates were cleaned in an ultrasonic bath using a piranha etch, rinsed with water, and dried in N2 flow. During each epitaxial process, the sample was gallium-mounted to a GaN / sapphire wafer. The growth of the LED was conducted first on the Ga- polar face, followed by the same cleaning procedure and gallium-mounting up-side-down for the HEMT epitaxial process on the N-polar face. Before processing, the same cleaning procedure was conducted to remove metal used for mounting. This growth procedure is depicted in Figures 1a-1c. Figs.1a-1c show a schematic of plasma-assisted molecular beam epitaxial growth of the HEMT- LED. The gray arrows indicate the chronological order of the growth procedure, with the N-polar HEMT being grown after the metal-polar LED.

[0048] The N-polar surface of the GaN substrate was gallium-bonded to a GaN / sapphire carrier wafer as shown in Fig.1a. Because the surface bonded to the carrier wafer needs to be used again, gallium bonding was used to bond to the GaN surface of a GaN / sapphire carrier wafer (slice of material) to ensure desired elements (Ga, N) at this bonding interface. Using molecular-beam epitaxy (MBE), a blue (In,Ga,Al)N LED structure consisting of a quantum well active region inside a p–nDocket No.: 10966-02 heterojunction on the Ga-polar face of GaN was first grown . The wafer was then detached from the carrier wafer and flipped (rotated) as shown in Fig.1b. The Ga was removed from the N-polar side and the metal-polar p-type GaN surface of the LED side was gallium-bonded on to a clean GaN / sapphire carrier wafer (slice of material labeled Carrier wafer2). Subsequently, a N-polar GaN / AlGaN / GaN heterostructure was grown on the N-polar face again by MBE to create a high- electron-mobility 2DEG to serve as the conduction channel of the HEMT, as shown in Fig.1c.

[0049] In the instantiation shown in Figs.1a-1c, the starting wafer is a high-transparency bulk n-type O-doped GaN substrate grown by the ammonothermal method (see Grabianska, K., Kucharski, R., Puchalski, A., Sochacki, T. & Bockowski, M. Recent progress in basic ammonothermal GaN crystal growth. J. Cryst. Growth 547, 125804 (2020) or Hashimoto, T., Wu, F., Speck, J. S. & Nakamura, S. A GaN bulk crystal with improved structural quality grown by the ammonothermal method. Nat. Mater.6, 568–571 (2007), both of which are incorporated by reference herein in their entirety and for all purposes) with mobile electron concentration of about 1018cm−3and threading dislocation density of about 104cm−2with both the Ga-polar and N-polar sides chemo- mechanically polished to obtain atomically smooth surfaces. The N-polar surface of the GaN substrate was gallium-bonded to a GaN / sapphire carrier wafer as shown in Fig.1a. Because the surface bonded to the carrier wafer needs to be used again, we chose gallium bonding to the GaN surface of a GaN / sapphire carrier wafer to ensure desired elements (Ga, N) at this bonding interface. Using molecular-beam epi-taxy (MBE), a blue (In,Ga,Al)N LED structure consisting of a quantum well active region inside a p–n heterojunction on the Ga-polar face of GaN was grown . The wafer was then detached from the carrier wafer and flipped as shown in Fig.1b. The Ga was removed from the N-polar side and the metal-polar p-type GaN surface of the LED side was gallium-bonded on to a clean GaN / sapphire carrier wafer. Subsequently, a N-polar GaN / AlGaN / GaN heterostructure was grown on the N-polar face again by MBE to create a high-electron-mobility 2DEG to serve as the conduction channel of the HEMT, as shown in Fig.1c.

[0050] In one instance, the epitaxial processes on both crystal planes were conducted using a plasma-assisted molecular beam epitaxy reactor. GaN and AlGaN layers on both polarities were grown at the same substrate temperature around 740°C thermocouple temperature while InGaN layers were grown at a thermocouple temperature of 660°C, as confirmed by gallium and indium desorption, respectively. The Ga-polar and N-polar structures were both grown using metal-rich growth conditions similar to recipes described elsewhere for laser diode growth. ( See G. Muziol, M. Hajdel, M. Siekacz, H. Turski, K. Pieniak, A. Bercha, W. Trzeciakowski, R. Kudrawiec, T. Suski, and C. Skier-biszewski, “III-nitride optoelectronic devices containing wide quantum wells—unexpectedly efficient light sources,” Jpn. J. Appl. Phys.61, SA0801 (2021) and M. Siekacz, A. Feduniewicz-Docket No.: 10966-02 Żmuda, G. Cywiński, M. Kryśko, I. Grze-gory, S. Krukowski, K. E. Waldrip, W. Jantsch, Z. R. Wasilewski, R. Porowski, and C. Skierbiszewski, “Growth of InGaN and InGaN / InGaN quantum wells by plasma-assisted molecular beam epitaxy,” Journal of Crystal Growth Special Issue IWBNS- 5, 310, 3983–3986 (2008).)

[0051] In one instance, the LED heterostructure was grown starting with a 150 nm GaN:Si buffer layer followed by an In0.17 Ga0.83N / In0.04Ga0.96N active region with a single 2.6 nm thick In0.17Ga0.83N quantum well. The active region was followed by p-type doped layers starting with an Al0.06Ga0.94N electron blocking layer with Mg concentration of 1 x 1019cm-3followed by 150 nm thick GaN layer with Mg concentration of 4 ⇥ 1018cm-3finally capped with p-InGaN contact layers consisting of 40 nm thick In0.03Ga0.97N and 5 nm thick In0.15Ga0.85N doped with Mg at the level of 4 x1019cm-3and 5 x1020cm-3, respectively. The N-polar structure started with the growth of a 2 µm thick un-doped GaN buffer layer followed by 5 nm GaN:Si and 10 nm Al0.40Ga0.60N:Si with a Si concentration of 3 x1018cm-3capped with undoped 20 nmAl0.40Ga0.60Nand 10 nm GaN. Silicon doping in the preceding layers was used to prevent formation of two-dimensional hole gas at the bottom interface. The two-dimensional electron gas (2DEG) in such structure forms in the top-most unintentionally doped GaN layer. (See Fig.1c.)

[0052] To investigate the surface morphology of the as-grown heterostructures, atomic force microscopy (AFM) was performed on an Asylum Cypher AFM microscope in tapping mode for sample areas of 5 x 5 µm2and 2 x 2 µm2. Furthermore, scanning transmission electron microscopy (STEM) was performed on samples, which were prepared using a Thermo Fisher Helios G4 UX Focused Ion Beam with a final milling step of 5 keV. STEM measurements were taken on both faces independently with an aberration-corrected Thermo Fisher Spectra 300 CFEG operated at 300 keV. The concentrations of Mg, O, C, and Si were measured by time-of-flight secondary ion mass spectrometry (ToF-SIMS) performed by Evans Analytical Group.

[0053] Figures 2a-2d show a schematic of the HEMT-LED heterostructures aligned with HAADF-STEM images taken along the [112¯0] projection axis. Fig.2b shows that all the illustrative layers in the HEMT (top) and LED (bottom) are implemented with illustrative thickness and composition. Increased contrast / brightness in the images correlates to atoms with higher atomic number (Z). The brighter regions highlight incorporated regions, and darker regions highlight Al incorporation in the film. The middle column shows atomic resolution HAADF-STEM images of the GaN / Al0.6Ga0.4N heterojunction of the HEMT which hosts the 2DEG, and the In0.04Ga0.96N / In0.17Ga0.83N / In0.04Ga0.96N quantum well. The HEMT structure shows an atomically clean and sharp interface. The AlGaN layer shows half a unit cell periodicity of Al rich and Ga rich layer structure. In the LED quantum well, minimal interdiffusion of different layers is observed, indicatingDocket No.: 10966-02 that the device heterostructures can withstand the thermal load of the secondary growth of the HEMT. Furthermore, in Fig.2d, the rightmost column of integrated differential phase contrast (iDPC) images of GaN near the surface on each end of the device heterostructure shown in Figure 2a indicate that the polarity of the MBE-grown layers follows that of the substrate to the topmost layers. Hence, these teachings enable the exploitation of the built-in polarization fields with both nitrogen-polar and metal- polar alignment stemming from both of the polar faces of the GaN substrate.

[0054] Figure 2e shows the as-grown illustrative heterostructure. Figure 2f-2g show 5 x5 µm2and 2 x 2 µm2atomic force topographs of the +c and -c surfaces of the as-grown heterostructures after completion of both growths. Sub-nanometer roughness and the observation of trains of well- resolved undulations are characteristic of step-flow growth for both growth fronts.

[0055] ToF-SIMS performed on both heterostructures is shown in Figures 2h-2k, inferring the depth-resolved Al, Ga, and In atomic fraction as well as the Mg, O, Si, and C densities. FIG.2h-2k show Time-of-Flight Secondary-ion Mass Spectrometry (ToF-SIMS). The top row, Figs.2h, 2i. shows the group III element ratios in the LED (left) and HEMT (right) heterostructures, whereas the bottom row, Figs.2j, 2k, shows the Mg, O, Si, and C impurity densities in the same. The detection limits for the impurity densities are [Mg] is about 1 - 2 x 1016cm-3, [O] is about 3-4 x 1016cm-3, [Si] is about 7-8 x 1015cm-3, and [C] is about 1 x 1016cm-3. There is no noticeable interdiffusion of dopants or group-III broadening of the metal-polar LED layers after growth of the N-polar HEMT, indicating interface and doping control is not affected by secondary growth.

[0056] Device fabrication began with processing the N-polar side of the double-sided sample. First, source and drain ohmic contacts were defined by patterning the N-polar heterostructure with a 200 / 30 nm SiO2 / Cr hard mask. After removing the Cr and SiO2layers in the contact regions via a selective dry etch to expose the GaN channel layer, the sample was reloaded into the MBE chamber and 50 nm n++GaN (ND~ 1020cm-3) was regrown at a thermocouple temperature of 660°C. The excess n++GaN was lifted off by removing the SiO2 / Cr hard mask in diluted HF, and a 6 / 2 nm Al2O3 / SiO2gate dielectric was blanket deposited by thermal ALD, followed by post deposition annealing at 400°C in O2. Next, mesa isolation was achieved by a BCl3inductively coupled plasma etch, which extended into the GaN buffer layer. Source and drain non-alloyed ohmic metallization regions were then defined by photolithography, and prior to the e-beam evaporation of 50 / 100 nm Ti / Au, a gate dielectric, and a few nanometers of regrown n++GaN layer were removed by a diluted HF dip and lower power ICP etch, respectively, to expose the fresh surface. Lastly, rectangular gates were defined by photolithography and metallized by e-beam evaporation of 50 / 100 nm Ti / Au. The overall process flow for N-polar HEMTs is illustrated in the top row (from left to right) of Figure 3a, and protection of the metal-polar LED heterostructure was not performed throughout.Docket No.: 10966-02

[0057] Next, the metal-polar face was processed into light-emitting diodes (LEDs) in the manner as described in the bottom row (from right to left) of Figure 3a. First, before each photolithography step, a positive photoresist was spun and baked on the nitrogen-polar face to protect and preserve the features of the HEMTs. Then, a Pd / Au / Ni metallization stack with thicknesses of 20 / 100 / 50 nm was deposited by electron beam evaporation, forming the anode (p-side electrode) for the LEDs. This stack was subsequently used for self-aligned etching and formation of the device mesas by inductively coupled reactive ion etching (ICP-RIE), resulting in an etch depth of approximately 540 nm. The device mesas are circular with a diameter ranging between about 20 and about 400 µm. Finally, a Ti / Au cathode (n-side electrode) metallization stack was deposited at thicknesses of about 20 / 100 nm by electron beam evaporation, completing the LED formation. A three-dimensional representation of the complete device structure, including a HEMT (top), substrate, and LED (bottom), is shown in Figure 3b. Optical microscope images of the fully processed sample are shown in Figure 3c, where both images are taken with the N-polar side of the sample facing up. The image on the left is focused on the top surface of the sample where four fully processed N-polar HEMTs are shown, whereas the image on the right is focused on the bottom surface of the sample and shows circular diodes of various sizes.

[0058] Current-voltage characteristics of the LEDs and transfer and output curves for the HEMTs, operating independently from each other, were measured using a Cascade Microtech Summit 11000 probe system. Electroluminescence measurements were performed by collecting light emission from the LED surface (mostly k k c) by using an Ocean Optics integrating sphere. After device fabrication of both the HEMTs and LEDs, monolithic switching measurements were performed by wire bonding the source of the HEMTs to the anode of a corresponding LED with an aluminum wire with 25 µm diameter. A customized probe setup was fabricated to probe both HEMTs and LEDs without the need to flip the sample, as schematized in Figure 3d. Figure 3d shows a schematic of top-side probing setup used for HEMT back-gating and HEMT-LED switching measurements. The HEMT-LED sample was bonded with the LED face down to two Ti / Au double- side coated glass slides with thermal glue. The cathode and anode contacts of a 400 µm diameter LED were subsequently wire-bonded to the Ti / Au coated slide with a 25 µm diameter Al wire. Finally, the coated slides were bonded to two additional uncoated glass slides and the sample was oriented as schematized to allow all the contacts of both the HEMT and the LED to be probed from the top. Additionally, to study the back-gating effect of the HEMT or to set the body voltage during switching measurements, Indium was soldered to an edge of the sample to make an electrical contact to the bulk n-GaN substrate. To facilitate the access of both device fronts by establishing a reliable electrical connectivity between both substrate faces, through-hole contacts can be used.Docket No.: 10966-02

[0059] Figures 3e-3h show two device processing flows (labeled roman numeral i or ii) for an instantiation of the device of these teachings including through-hole contacts. Referring to Figures 3e-3h, in the first processing flow, the epi-structure is etched to define the through hole (Fig.3fi). Then, the through hole contact is deposited (Fig.3gi). (Although, in the instantiation shown, the through hole contact completely fills the through hole, other instantiations are also within the scope of these teachings. In one instance, the through all contact can be deposited on the surface of the through hole.) Finally, as shown in Fig.3h, the devices are defined in structure 1 and in structure 2. Referring again to Figures 3e-3h, in the second processing flow, as shown in Fig.3fii, the devices are defined in structure 1 and in structure 2. Then, the epi-structure is etched to define the through hole (Fig.3gii). Finally, the through hole contact is deposited, the end result being shown in Fig.3h.

[0060] It is confirmed that both heterostructures consist of their intended group III ratio and doping profiles. Importantly, there is no noticeable interdiffusion of dopants or group-III broadening of the metal-polar LED layers, indicating interface and doping control is not affected by secondary growth.

[0061] On-wafer van der Pauw patterns were used for Hall-effect measurements following the completion of N-polar HEMTs fabrication (and before the metal-polar LED fabrication began). A measured room-temperature electron density of 1.26 x 1013, electron mobility of 1970 cm2 / (V·s), and a corresponding sheet resistance of 252 Ω / sq were measured. The observed sheet resistance is the lowest and the electron mobility is one of the highest among all N-polar HEMT heterostructures reported in the literature, demonstrating high quality epitaxy on double-side polished bulk substrates. Next, current-voltage curves obtained from the linear transfer-length method patterns were used to extract the sheet resistance and contact resistance (from a metal pad to 2DEG). The extracted values revealed a contact resistance of 0.21 Ωmm and a sheet resistance of 290 Ω / sq, which closely aligns with the result obtained through Hall-effect measurements.

[0062] Figures 4a and 4b show the linear- and log-scale transfer curves of a HEMT, respectively, with dimensions of source-drain length LSD = 4 µm, gate length LG = 1.5 µm, and gate width WG = 50 µm. The peak extrinsic transconductance of 16 mS (0.32 S / mm) was extracted at a drain bias of 5 V. Most HEMTs of similar dimensions across the sample exhibited sharp pinch-off characteristics with an on / off ratio exceeding 5 ⇥ 103. The main limitation of the on / off ratio is largely attributed to the gate leakage through the gate dielectric layer. Therefore, in order to achieve further improvements in gate control, careful control of bulk and interface traps in the gate dielectric layer will be needed. As shown in Figure 3d, the devices of the same dimensions showed drain currents up to 50 mA (1 A / mm) with repeatable current saturation over the large range of gate voltages. The on-resistance extracted at a gate bias of 1.75 V was 57 (2.85 ·mm).Docket No.: 10966-02

[0063] After the metal-polar LED fabrication, its current-voltage (IV) characteristics were measured leaving the HEMT contacts floated. Semi-log and linear plots corresponding to a 400 µm diameter LED are shown in Figures 4b and 4d, respectively, indicated by the blue solid line. The diodes turn on at a forward bias of 2.1 V. The corresponding electroluminescence spectra for current densities ranging from 1 to 100 A / cm2are shown in Figures 4a-4c. The observed blueshift of the peak emission wavelength of 470 nm at 1 A / cm2to 450 nm at 100 A / cm2is ascribed to the screening of the internal polarization field as more carriers are injected into the quantum well, leading to the suppression of the quantum confined Stark effect (QCSE). The top right inset shows a camera image of a 400 µm diameter LED in its on state.

[0064] To evaluate the processability of the double side epitaxy, the HEMT performance was analyzed again after the fabrication of the LED. The corresponding output and transfer characteristics of the HEMTs before and after the processing of the LEDs is shown in Figures 6a-6b. It was confirmed that after the LED processing, the HEMT performance degraded minimally, with a threshold voltage shift less than 0.3 V and a negligible change in the output and gate leakage current. This minimal degradation highlights the feasibility of using double-side epitaxy and processing for reliable heterogeneous device integration on both crystal faces.

[0065] Next, switching measurements were performed where the HEMTs were used to drive the LEDs monolithically. As depicted in Figure 5a, during an off-state, a negative gate bias elevates the conduction energy band of a transistor to deplete free carriers, which subsequently bends the energy band of a LED to block the electron diffusion into the quantum well, suppressing the radiative recombination. Similarly, a positive gate bias pulls down the conduction energy band of a transistor, allowing electric current to flow, and lowers the diffusion barrier for electrons on the LED side. Therefore, by changing the gate voltage, the light output from the LED quantum well can be modulated between bright, dim, and off.

[0066] In the configuration schematically shown in Figure 5b, the source of the HEMT was shorted to the anode of the LED. In the monolithic device scheme, it is important to consider the effect of the n-GaN substrate. Particularly, due to its highly conductive nature, the potential of the substrate which is set by the cathode of the LED can act as a back-gate for the HEMT. This effect was studied by fabricating a separate contact to the n-GaN substrate and performing transfer and output measurements of the HEMTs for various substrate potentials, acting as the back-gate VBS.It is found that two orders of magnitude current modulation can be achieved by a three-terminal depletion-mode HEMT defined by the back-gate and leaving the top gate, VGS,floating. Transfer curves of a transistor with a back-gate (top gate still floating) also revealed a sharp exponential increase in gate leakage for VBS- VDSis less than or about -4 V, possibly due to band-to-band tunneling. The back gating effect isDocket No.: 10966-02 expected to be eliminated by simply replacing the conductive substrates with semi-insulating substrates. Transfer and output curves of a back-gated transistor with a floating top gate are shown in Figures 7a- 7d.

[0067] Figures 7a-7b show (a) Log scale and (b) linear scale transfer curves of a three-terminal N-polar HEMT gated by the substrate contact made with Indium as shown in Figure 3d, with the top gate left floating. Each curve represents the dependency of the drain (solid) and gate (dashed) current as a function of the back gate voltage (VBS), with a fixed drain bias. Drain bias increases from 0.5 V to 5 V at a 0.5 V step in the direction the arrow points, with the last curve taken at a drain bias (VDS) of 0.2 V. Figure 7c shows the output characteristics of a back-gated N-polar HEMT. The maximum drain current is comparable to the value measured on top-gated HEMT. For VBS - VDS less than or about -4 V, the drain current is dominated by the high gate leakage current. Figure 7d shows Log scale transfer curves of a four-terminal N-polar HEMT measurement with fixed VBS and VDS. The blue curve represents the transfer curve with a back gate. No drain current modulation is observed for VDS - VBS about 5 V, and up to six orders of drain current modulation is observed for VDS - VBS = 0 V.

[0068] In a four-terminal setup, it was found that by varying both VGS and VBS, the current modulation can be extended from 3.5 to 6 orders by altering the leakage pathways from gate-source to gate-back gate. On the other end, as the potential difference between the drain and the back gate (or the cathode of the LED), VDS - VBS, increases, a reduction in current modulation was noted, ultimately reaching a point where no current modulation is observed (VDS - VBS ⇠ 5 V). For the switching measurements, a photodiode was placed directly on top of the device, and the drain and the cathode were biased at 5.8 V and 1 V. The biasing condition was chosen to ensure sufficient drive current through the LED for light emission while simultaneously achieving adequate current modulation to turn the LED off. With the sinusoidal signal swinging between -3.2 V and 3.6 V applied to the gate, the current modulation was sufficient to modulate the LED between on and off. Figure 5c shows the 1 kHz sinusoidal input signal (red), the output photodiode voltage (blue), and the background photodiode voltage (black). The photodiode voltage closely followed the gate voltage for 1.6 V < VGS < 3.6 V and stayed at the background level (LED is off) for VGS < 1.6 V, indicating a full control of the LED by the transistor gate voltage modulation. In Figure 5d, it is shown that the dimmability of the LED light output, where the input voltage is limited to the range over which the LED is expected to be on with a different brightness. The photodiode voltage again closely followed the 1 kHz input gate signal, demonstrating the successful integration of two devices with opposing polarities that were grown and fabricated on separate growth fronts of the polar substrates.

[0069] As used herein, the singular forms “a,” “an,” and “the” include the plural reference unless the context clearly dictates otherwise. Except where otherwise indicated, all numbersDocket No.: 10966-02 expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

[0070] For the purpose of better describing and defining the present invention, it is noted that terms of degree (e.g., “substantially,” “about,” and the like) may be used in the specification and / or in the claims. Such terms of degree are utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, and / or other representation. The terms of degree may also be utilized herein to represent the degree by which a quantitative representation may vary (e.g., ±10%) from a stated reference without resulting in a change in the basic function of the subject matter at issue.

[0071] It will be appreciated by those of ordinary skill in the pertinent art that the functions of several elements may, in alternative embodiments, be carried out by fewer elements or a single element. Similarly, in some embodiments, any functional element may perform fewer, or different, operations than those described with respect to the illustrated embodiment. While the subject technology has been described with respect to preferred embodiments, those skilled in the art will readily appreciate that various changes and / or modifications can be made to the subject technology without departing from the spirit or scope of the subject technology.

[0072] Although the invention has been described with respect to various embodiments, it should be realized these teachings are also capable of a wide variety of further and other embodiments within the spirit and scope of the appended claims.

Claims

Docket No.: 10966-02 WHAT IS CLAIMED IS:

1. A system comprising; a substrate having two opposing surfaces; at least one slice of material, the material selected such that one surface of the two opposing surfaces of the substrate can bonded to one of the at least one slice of material with a detachable bond; wherein at least one semiconductor heterostructure epitaxially is grown on one surface of the two opposing surfaces of the substrate; and at least another semiconductor heterostructure is epitaxially grown on a surface of the substrate opposite to the one surface.

2. The system of claim 1, wherein heterostructures are epitaxially grown by at least one of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor-phase epitaxy (HVPE), ultra-high vacuum chemical vapor deposition (UHVCVD), atomic layer deposition (ALD), atomic layer epitaxy (ALE), or reactive sputtering.

3. The system of claim 1, wherein the substrate is a double-side polished crystalline substrate.

4. The system of claim 1, wherein a miscut in the substrate is between about 0 degrees and about 20 degrees.

5. The system of claim 1, wherein the substrate comprises one of GaN, AlN, SiC, Si, Sapphire, ZnO.

6. The system of claim 1, wherein the one surface is one of polar, semi-polar, or non- polar; and wherein the surface of the substrate opposite to the one surface is one of polar, semi-polar, or non-polar.

7. The system of claim 6, wherein the one surface is a surface of a structure that is polar; and wherein the surface of the substrate opposite to the one surface is a surface of a structure that is polar.Docket No.: 10966-02 8. The system of claim 1 further comprising at least one of wire bonds or through-hole contacts.

9. The system of claim 1, wherein at least one of the at least one semiconductor heterostructure and the at least another semiconductor heterostructure comprises optical or acoustic components.

10. The system of claim 1, wherein the at least one semiconductor heterostructure and the at least another semiconductor heterostructure comprise at least one of transistors, diodes, LEDs, laser diodes, Schottky diodes, resonant tunneling diodes, avalanche diodes, waveguides, reflectors, photonic crystals, integrated circuits, or any combinations thereof.

11. The system of claim 1, wherein the at least one semiconductor heterostructure include Microwave and RF amplifiers, rectifiers, and corresponding circuit components and the at least another semiconductor heterostructure includes digital electronics and circuits.

12. The system of claim 1, wherein the at least one semiconductor heterostructure includes at least one of LED or laser diodes and the at least another semiconductor heterostructure includes electronic sub-systems and circuits.

13. The system of claim 1, wherein the at least one semiconductor heterostructure includes metal-polar III-N heterojunction field effect transistors (FETs) and the at least another semiconductor heterostructure includes nitrogen-polar III-N heterojunction FETs.

14. The system of claim 13, wherein the III-N heterojunction FETs are GaN / Al(Ga)N heterojunction FETs.

15. The system of claim 1, wherein the two opposing surfaces are nonparallel.Docket No.: 10966-02 16. A device comprising; a substrate having two opposing surfaces; at least one semiconductor heterostructure epitaxially grown on one surface of the two opposing surfaces of the substrate; and at least another semiconductor heterostructure epitaxially grown on a surface of the substrate opposite to the one surface; the two opposing surfaces being nonparallel.

17. The device of claim 16, wherein a miscut in the substrate is between about 0 degrees and about 20 degrees.

18. The device of claim 16, wherein the substrate is a double-sided polished crystalline substrate.

19. The device of claim 16, wherein the one surface is one of polar, semi-polar, or non- polar; and wherein the surface of the substrate opposite to the one surface is one of polar, semi-polar, or non-polar.

20. A method for increasing density of semiconductor devices on a substrate, the method comprising: epitaxially growing at least one semiconductor heterostructure on one surface of two opposing surfaces of a substrate; epitaxially growing the at least one semiconductor heterostructure on the one surface of two opposing surfaces of the substrate comprising releasably bonding the one surface to a holder; and epitaxially growing at least another semiconductor heterostructure on a surface of the substrate opposite to the one surface; epitaxially growing the at least another semiconductor heterostructure on the surface of the substrate opposite to the one surface comprising releasing the one surface from the holder and releasably bonding an outermost surface of the at least one semiconductor heterostructure to another holder.

21. The method of claim 20 further comprising polishing both of the two opposing surfaces of the substrate.

22. The method of claim 20 wherein bonding comprises gallium bonding.Docket No.: 10966-02 23. The method of claim 20 further comprising, after releasing the one surface from the holder, positioning the substrate with the at least one semiconductor heterostructure epitaxially grown on the one surface of the two opposing surfaces of the substrate so that the outermost surface of the at least one semiconductor heterostructure can be releasably bonded to another holder.

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