Circuit board, communication device, and chip

Abstract

Provided in the embodiments of the present application are a circuit board, a communication device, and a chip. The circuit board is used for connecting an electronic device, and the circuit board is used for suppressing the mismatch of coefficients of thermal expansion between the circuit board and the electronic device, which can effectively reduce an insertion loss of the circuit board. In a direction perpendicular to the surface of the circuit board, the circuit board comprises M sequentially arranged sub-boards, M being any integer not less than 2, and the M sub-boards comprising a first sub-board and a second sub-board. A coefficient of thermal expansion of the first sub-board is smaller than that of the second sub-board, and a dielectric loss factor of the second sub-board is smaller than that of the first sub-board.

Description

Circuit board, communication device and chip

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 21, 2023, with application number 202311568114.1 and invention name “A circuit board, communication equipment and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a circuit board, a communication device, and a chip. Background Art

[0003] Communication equipment includes a circuit board and electronic devices connected to the surface of the circuit board. To improve the reliability of the communication equipment and the reliability of the circuit board's electrical connections, it is necessary to suppress the coefficient of thermal expansion (CTE) mismatch between the circuit board and the electronic devices.

[0004] The existing circuit board includes a first sub-board and a plurality of second sub-boards, wherein the first sub-board is located between the plurality of second sub-boards. To suppress CTE mismatch, the CTE of the first sub-board is smaller than the CTE of the second sub-board.

[0005] However, when the CTE of the first sub-board is reduced, the insertion loss of the first sub-board will be increased, and thus the insertion loss of the circuit board cannot be suppressed. A circuit board with high insertion loss cannot meet the demand for increasingly higher information transmission rates.

[0006] Summary of the Invention

[0007] An embodiment of the present application provides a circuit board, a communication device, and a chip. The circuit board is used to connect electronic devices, suppress the mismatch of thermal expansion coefficients between the circuit board and the electronic devices, and can effectively reduce the insertion loss of the circuit board.

[0008] In a first aspect, the present application provides a circuit board, which is used to connect electronic devices. The circuit board includes M sub-boards arranged in sequence along a direction perpendicular to the surface of the circuit board, where M is an arbitrary integer not less than 2, and the M sub-boards include a first sub-board and a second sub-board. Among the M sub-boards, the first sub-board and the second sub-board are adjacent to each other along a direction perpendicular to the surface of the circuit board, or at least one sub-board is spaced between the first sub-board and the second sub-board. The low thermal expansion coefficient performance and low dielectric loss factor performance shown in this aspect are decomposed into different sub-boards among the M sub-boards. Therefore, the thermal expansion coefficient of the first sub-board is smaller than that of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than that of the first sub-board.

[0009] With the circuit board described in this aspect, when the thermal expansion coefficient of the first sub-board is smaller than that of the second sub-board, the thermal expansion coefficient of the circuit board is effectively reduced, thereby effectively suppressing the thermal expansion coefficient mismatch between the circuit board and the electronic device, ensuring a stable electrical connection of the communication device and improving the lifespan of the communication device. When the dielectric loss factor of the second sub-board is smaller than that of the first sub-board, the insertion loss of the circuit board is effectively reduced, thereby enabling the circuit board described in this aspect to meet the requirements of both a low thermal expansion coefficient and low insertion loss.

[0010] Based on the first aspect, in an optional implementation, the Young's modulus of the second sub-plate is smaller than the Young's modulus of the first sub-plate.

[0011] This implementation minimizes the negative impact of the second daughter board's high thermal expansion coefficient on the overall thermal expansion coefficient of the circuit board due to the second daughter board's high Young's modulus. Furthermore, the second daughter board's low Young's modulus allows for a smaller via pitch on the circuit board.

[0012] Based on the first aspect, in an optional implementation, the M sub-boards include a plurality of second sub-boards, and the plurality of second sub-boards are symmetrically distributed around the first sub-board.

[0013] With this implementation, multiple second sub-boards are symmetrically distributed with the first sub-board as the center, so as to improve the overall flatness of the circuit board and improve the overall warping of the circuit board.

[0014] Based on the first aspect, in an optional implementation, the M sub-boards also include a third sub-board, and the second sub-board is located between the first sub-board and the second sub-board; the thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the third sub-board.

[0015] With this implementation, when the thermal expansion coefficient of the third sub-board is smaller than that of the second sub-board, the thermal expansion coefficient of the circuit board is effectively reduced, thereby effectively suppressing thermal expansion coefficient mismatch of the circuit board, ensuring the stability of the electrical connection of the communication device and improving the lifespan of the communication device. When the dielectric loss factor of the second sub-board is smaller than that of the third sub-board, the insertion loss of the circuit board is effectively reduced, thereby enabling the circuit board shown in this aspect to meet the requirements of both low thermal expansion coefficient and low insertion loss. Furthermore, because the second sub-board is located between the first and third sub-boards, the reliability of the circuit board structure is improved.

[0016] Based on the first aspect, in an optional implementation, the Young's modulus of the second sub-plate is smaller than the Young's modulus of the third sub-plate.

[0017] With this implementation, the third sub-board is located in the outermost layer of the circuit board. Therefore, the Young's modulus of the third sub-board is greater than that of the second sub-board, thereby effectively improving the overall rigidity of the circuit board and reducing the footprint when mounting components on the circuit board surface.

[0018] Based on the first aspect, in an optional implementation, the M sub-boards include a plurality of the third sub-boards, and the plurality of the third sub-boards are symmetrically distributed around the first sub-board.

[0019] With this implementation, multiple third sub-boards are symmetrically distributed with the first sub-board as the center, so as to improve the overall flatness of the circuit board and improve the overall warping of the circuit board.

[0020] Based on the first aspect, in an optional implementation, within a target plane, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the target plane is parallel to the surface of the circuit board.

[0021] As shown in this implementation, within the target plane, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the second sub-board, and, within the target plane, the thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, effectively suppressing the thermal expansion coefficient mismatch between the circuit board and the electronic device.

[0022] Based on the first aspect, in an optional implementation, the thickness of the first sub-board along the target direction is greater than the thickness of the second sub-board along the target direction, and the thickness of the first sub-board along the target direction is greater than the thickness of the third sub-board along the target direction, wherein the target direction is a direction perpendicular to the surface of the circuit board.

[0023] In this implementation, the first sub-board is thicker than the second sub-board, and thicker than the third sub-board, effectively reducing the circuit board's coefficient of thermal expansion. Furthermore, the second sub-board's smaller thickness mitigates its negative impact on the overall thermal expansion coefficient of the circuit board, reducing the overall thickness of the circuit board.

[0024] Based on the first aspect, in an optional implementation, the M sub-boards include a fourth sub-board, and the fourth sub-board is located between the first sub-board and the second sub-board in a direction perpendicular to the surface of the circuit board; the thermal expansion coefficient of the fourth sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the fourth sub-board.

[0025] With this implementation, when the fourth sub-board has a lower thermal expansion coefficient than the second sub-board, the circuit board's thermal expansion coefficient is effectively reduced, thereby effectively suppressing thermal expansion coefficient mismatch, ensuring a secure electrical connection for the communication device and improving the lifespan of the communication device. When the second sub-board has a lower dielectric loss factor than the fourth sub-board, the circuit board's insertion loss is effectively reduced, enabling the circuit board shown in this aspect to meet both low thermal expansion coefficient and low insertion loss requirements.

[0026] Based on the first aspect, in an optional implementation, the Young's modulus of the second sub-plate is smaller than the Young's modulus of the fourth sub-plate.

[0027] This implementation minimizes the negative impact of the second daughter board's high thermal expansion coefficient on the overall thermal expansion coefficient of the circuit board due to the second daughter board's high Young's modulus. Furthermore, the second daughter board's low Young's modulus allows for a smaller via pitch on the circuit board.

[0028] Based on the first aspect, in an optional implementation, the second sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; the second sub-board also includes a second dielectric layer, along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface positioned opposite to each other, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

[0029] By adopting this implementation method, the thermal expansion coefficient and insertion loss of the circuit board can be effectively reduced.

[0030] Based on the first aspect, in an optional implementation, the first dielectric layer and the second dielectric layer meet at least one of the following conditions:

[0031] The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

[0032] By adopting this implementation method, the circuit board can meet the requirements of low thermal expansion coefficient and low insertion loss.

[0033] Based on the first aspect, in an optional implementation, the third sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; the third sub-board also includes a second dielectric layer, along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface positioned opposite to each other, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

[0034] By adopting this implementation method, the thermal expansion coefficient and insertion loss of the circuit board can be effectively reduced.

[0035] Based on the first aspect, in an optional implementation, the first dielectric layer and the second dielectric layer meet at least one of the following conditions:

[0036] The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

[0037] By adopting this implementation method, the circuit board can meet the requirements of low thermal expansion coefficient and low insertion loss.

[0038] Based on the first aspect, in an optional implementation, the first sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; the first sub-board also includes a second dielectric layer, along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface positioned opposite to each other, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

[0039] By adopting this implementation method, the thermal expansion coefficient and insertion loss of the circuit board can be effectively reduced.

[0040] Based on the first aspect, in an optional implementation, the first dielectric layer and the second dielectric layer meet at least one of the following conditions:

[0041] The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

[0042] By adopting this implementation method, the circuit board can meet the requirements of low thermal expansion coefficient and low insertion loss.

[0043] Based on the first aspect, in an optional implementation, the first sub-board or the third sub-board serves as a power layer or a ground layer, and the second sub-board serves as a signal layer.

[0044] In a second aspect, an embodiment of the present application provides a communication device, comprising a circuit board and an electronic device connected to the circuit board, wherein the circuit board is as described in any one of the first aspects above. For a description of the beneficial effects of the circuit board in this aspect, please refer to the description in the first aspect, and the details are not repeated here.

[0045] In a third aspect, embodiments of the present application provide a chip, comprising a package housing, wherein the package housing includes a circuit board and a bare chip connected to the circuit board, wherein the circuit board is as described in any one of the first aspects above. For a description of the beneficial effects of the circuit board in this aspect, please refer to the description in the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a structural diagram of a communication device;

[0047] FIG2 is a structural diagram of an existing circuit board;

[0048] FIG3 is a structural diagram of a first embodiment of a circuit board provided in this application;

[0049] FIG4 is a structural diagram of a second embodiment of a circuit board provided in this application;

[0050] FIG5 is another structural example diagram of an existing circuit board;

[0051] FIG6 is a structural diagram of a third embodiment of a circuit board provided in this application;

[0052] FIG7 is a structural diagram of a fourth embodiment of a circuit board provided in this application;

[0053] FIG8 is a structural diagram of a fifth embodiment of a circuit board provided in this application;

[0054] FIG9 is a structural diagram illustrating a sixth embodiment of the circuit board provided in this application. DETAILED DESCRIPTION

[0055] The present application provides a communication device, which includes a circuit board and an electronic device connected to the surface of the circuit board. The communication device provided in an embodiment of the present application can effectively suppress the CTE mismatch between the circuit board and the electronic device.

[0056] For example, as shown in Figure 1, Figure 1 is a structural example diagram of a communication device. The communication device includes a printed circuit board (PCB) 101. The communication device also includes an electronic device connected to the surface of the PCB 101, and the electronic device can be a chip. The chip specifically includes a packaging shell 111, and the packaging shell 111 includes a substrate (Substrate) 112 and a bare chip (die) 113 connected to the surface of the substrate 112. The substrate 112 is connected to the surface of the PCB 101 through a ball grid array (BGA). In this embodiment, the type of circuit board included in the chip packaging shell 111 is a substrate. In other examples, the type of circuit board included in the packaging shell 111 can also be a PCB, then the die 113 is connected to the surface of the PCB. The example shown in FIG1 takes the electronic device connected to the surface of PCB 101 as a chip. In other examples, the electronic device packaged on the surface of PCB 101 can be any type of electronic component, such as a resistor, capacitor, inductor, connector, laser device, power supply, etc. The electronic device can also be a die, that is, the die is directly connected to the surface of PCB 101. This example does not limit the type of device used by the communication device. For example, the communication device can be applied to optical transmission equipment, optical access equipment, routers, switches, wireless base stations, wireless remote access equipment, wireless baseband signal processing equipment, etc. It can also be a computing server (usually referred to as a server), a high performance computer (HPC), a storage server, or a memory resource pool, etc. The devices used by the communication device can also be various types of terminal devices, such as cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices, wearable devices, any communication networks, such as terminal devices in the fifth generation mobile communication technology (5G), terminal devices in the sixth generation mobile communication technology (6G), terminal devices in the future evolved public land mobile communication network (PLMN), etc., without specific limitation.

[0057] In this example, the target plane XY is parallel to the surface of PCB 101, while the target direction Z is perpendicular to the target plane. In this example, the electrical connection between PCB 101 and substrate 112 in package housing 111 is achieved through solder balls or solder paste soldering. During the assembly and soldering process, the solder balls or solder paste soldering require heating, which heats and causes dimensional changes in both PCB 101 and package housing 111. PCB 101 has a first CTE within target plane XY, while package housing 111 has a second CTE within target plane XY. CTE mismatch in communication devices refers to a significant difference between the first and second CTEs. When CTE mismatch occurs in communication devices, the PCB 101 and package housing 111 deform inconsistently during temperature increases and decreases, leading to internal stress at the solder joints between them when the temperature returns to room temperature. The greater the difference between the first CTE of PCB 101 and the second CTE of package housing 111, the greater the internal stress. When the internal stress exceeds the connection force of the solder joint, problems such as solder joint cracking will occur, resulting in failure of the electrical connection between PCB101 and the packaging shell 111. In addition, during the actual use of the communication equipment, if there is a large CTE gap between PCB101 and the packaging shell 111, due to factors such as changes in ambient temperature or heat generated during the use of the communication equipment, the solder joint will also be subjected to long-term thermal fatigue stress (also known as creep fatigue), and eventually the solder joint will crack and fail. In particular, when there are large cyclic fluctuations in ambient temperature and the communication equipment is repeatedly powered on and off, there will be cyclic stress at the solder joint, resulting in failure of the electrical connection, affecting the service life of the communication equipment. There is also a CTE mismatch problem between the substrate 112 and the bare chip 113 shown in this example. For details, please refer to the description of the CTE mismatch between PCB101 and the packaging shell 111, and the details will not be repeated here.

[0058] Therefore, if the CTE mismatch of communication equipment can be effectively suppressed, the stability of the electrical connection of the communication equipment can be effectively guaranteed, and the life of the communication equipment can be improved. Taking the CTE mismatch between PCB101 and packaging shell 111 as an example, the dielectric material used to make PCB101 is composed of polymer resin, filler, fiber cloth, etc., and the CTE of polymer resin is generally greater than 50 parts per million per degree Celsius (ppm / °C). The packaging shell 111 is generally made of inorganic materials such as ceramics and silicon. Therefore, the CTE of PCB101 in the target plane XY is greater than the CTE of the packaging shell 111 in the target plane XY. Generally speaking, the CTE of the packaging shell 111 in the target plane XY is approximately 2 to 10 ppm / °C, and the CTE of the dielectric material of PCB101 in the target plane XY is generally 15 to 25 ppm / °C. Therefore, to suppress the CTE mismatch between PCB 101 and package housing 111, thereby improving the problem of solder joint cracking, electrical connection failure, and reduced life of the communication device caused by CTE mismatch, the CTE of the dielectric material of PCB 101 within the target plane XY can be reduced, thereby reducing the difference between the first CTE and the second CTE, thereby achieving the purpose of suppressing the CTE mismatch between PCB 101 and package housing 111. Similarly, to suppress the CTE mismatch between substrate 112 and bare chip 113, the CTE of substrate 112 within the target plane XY can also be reduced. For details, please refer to the description of suppressing the CTE mismatch between PCB 101 and package housing 111, and the details are not repeated here.

[0059] The structure of an existing circuit board is specifically described with reference to FIG2 , wherein FIG2 is an example diagram of an existing circuit board structure. FIG2 shows an example of a circuit board as a flip chip ball grid array (FCBGA) package substrate. The circuit board includes a first sub-board 201. The first sub-board 201 is a copper-clad core board (Core) covered with copper foil on both sides. The first sub-board 201 is located between two second sub-boards 202. The second sub-board 202 is a multi-layer ajinomoto build-up film (ABF). A copper layer (i.e., a seed layer) is deposited using a semi-additive process (SAP) to achieve electrical connection between two adjacent second sub-boards 202. The thickness of the first sub-board 201 shown in FIG2 along the target direction Z is greater than the thickness of each second sub-board 202. To reduce the CTE of the entire circuit board within the target plane XY, the CTE of the first sub-board 201 is smaller than the CTE of the second sub-board 202 within the target plane XY, thereby reducing the CTE of the entire circuit board within the target plane XY. First sub-board 201 can be a copper-clad laminate (CCL) with copper cladding on both sides. A CCL is a dielectric material with copper cladding on both sides. The dielectric material is generally composed of glass fiber, polymer resin, and fillers.

[0060] As communication equipment transmission rates increase, the information capacity required is also increasing. This places increasing demands on circuit boards for high-speed signal transmission performance. To address this, circuit boards must simultaneously suppress CTE mismatch between the board and electronic components and reduce insertion loss. Using a PCB as an example, this article will explain existing solutions for reducing PCB insertion loss.

[0061] PCB insertion loss primarily stems from dielectric loss and conductor loss in the dielectric material. Dielectric loss is primarily determined by the dielectric material's dissipation factor (Df), dielectric constant (Dk), and frequency. The lower the Df and Dk of the dielectric material, the better the PCB's insertion loss performance. It's understandable that effectively reducing the PCB's Df and Dk can effectively reduce the PCB's insertion loss.

[0062] To improve the performance of communication equipment, it is necessary to ensure that the PCB can simultaneously suppress the CTE mismatch between the PCB and electronic devices and reduce insertion loss. To achieve this, the dielectric material used to make the first sub-board 201 in the existing PCB shown in Figure 2 must simultaneously suppress the CTE mismatch between the PCB and electronic devices and reduce insertion loss. For example, the first sub-board 201 is a CCL. The CTE of the CCL is primarily affected by the polymer resin, filler, reinforcement material, and copper foil, as shown in the following formula 1:

[0063] Formula 1:

[0064] In formula 1, a CCL is the CTE of the first sub-board 201, α is the coefficient of thermal expansion, K is the Young's modulus, φ is the volume percentage, r is the polymer resin, f is the filling material, g is the reinforcing material, and c is the copper foil. For example, a r Refers to the thermal expansion coefficient of polymer resin, K r Refers to the Young's modulus of polymer resin, Refers to the volume percentage of polymer resin.

[0065] Since the copper foil used in CCLs is mostly electrolytic or rolled copper with a purity exceeding 99.5%, the CTE of different types of copper foil varies slightly, generally around 17ppm / °C. The primary factors influencing the CTE of CCLs are the polymer resin, followed by the reinforcement material (such as fiberglass cloth) and the filler. The CTE of the reinforcement material is the key factor affecting the CTE of the dielectric material within the target XY plane.

[0066] Similarly, the main factors affecting the Df performance of CCL are polymer resin, reinforcement material and filler material, as shown in the following formula 2:

[0067] Formula 2: Dfccl = VA*DfA+VB*DfB+VC*DfC

[0068] In Formula 2, Dfccl refers to the Df of CCL. V refers to the volume percentage, and A / B / C represent the different components. For example, VA refers to the volume percentage of the polymer resin, DfA refers to the Df of the polymer resin, VB refers to the volume percentage of the filler, DfB refers to the Df of the filler, VC refers to the volume percentage of the reinforcement, and DfC refers to the Df of the reinforcement.

[0069] However, it's difficult for the dielectric material of the first sub-board 201 to simultaneously achieve low insertion loss and low CTE within the target plane XY. For example, if the dielectric material used for the first sub-board 201 needs to have both low insertion loss and low CTE within the target plane XY, for example, the CTE of the first sub-board 201 within the target plane XY must be ≤10ppm / °C and the Df must be ≤0.002@10GHz. The Df value of the first sub-board 201 is positively correlated with the board loss; that is, the lower the Df value, the lower the insertion loss. It can be understood that reducing the Df value can achieve low insertion loss. However, reconciling the CTE and Df of the first sub-board 201 within the target plane XY is challenging. This is because dielectric materials with low CTE within the target plane XY typically have a large Df. Dielectric materials with a low Df also have a high CTE within the target plane XY. For example, to achieve a low CTE for the first sub-plate 201 within the target plane XY, the dielectric material of the first sub-plate 201 can be a polymer resin with a low CTE. However, polymer resins with a low CTE typically have a large Df, meaning that polymer resins with a low CTE typically do not exhibit low Df performance. If the dielectric material of the first sub-plate 201 is made of quartz cloth, the cost of the dielectric material will increase significantly, as will the difficulty of processing, making it impossible to achieve a small via pitch. To reduce the CTE of the first sub-plate 201 within the target plane XY, the proportion of fiber cloth can be increased in the dielectric material, thereby enabling the first sub-plate 201 to simultaneously achieve low CTE and low insertion loss performance. However, increasing the fiber cloth ratio in the first sub-board 201 can lead to fiber cloth interfaces, making conductive anodic filament (CAF) failure between vias very likely. This is especially true when the via pitch is ≤200μm. The proportion of fillers with low CTE and low insertion loss can affect the interface impregnation performance. Furthermore, microcracks in the fiber cloth interface caused by high-density via drilling can degrade CAF reliability and easily lead to CAF failure. If the first sub-board 201 has a low CTE within the target plane XY, the cost of the first sub-board 201 can be significantly increased, or the processing difficulty can be significantly increased (e.g., if quartz cloth is used as the dielectric material for the first sub-board 201). High fillers used to reduce the CTE of the first sub-board 201 within the target plane XY can affect the wetting properties between the polymer resin and the filler, and between the polymer resin and the glass fiber cloth, leading to poor heat resistance, CAF resistance, and highly accelerated stress test (HAST) resistance of the vias.

[0070] The present application provides a communication device, which includes a circuit board and an electronic device electrically connected to the surface of the circuit board. For the description of the type of electronic device, please refer to the corresponding description of Figure 1 and will not be described in detail. The circuit board of the communication device has both low insertion loss and low CTE performance. The circuit board shown in this embodiment can effectively suppress the CTE mismatch between the circuit board and the electronic device, improve the reliability of the circuit board, and at the same time effectively reduce the insertion loss of the circuit board to meet the increasingly higher demand for information transmission rate of the circuit board. For example, the CTE of the circuit board provided in this embodiment is ≤15ppm / ℃ and Df ≤0.002@10GHz.

[0071] Figure 3 is a structural example diagram of the first embodiment of the circuit board provided in this application. Figure 3 takes the structural example diagram of the circuit board in the coordinate system XYZ as an example. For the description of the XYZ coordinate system, please refer to the corresponding description of Figure 1, and the details are not repeated here. The circuit board shown in this embodiment includes M sub-boards arranged in sequence along the target direction Z, where M is an arbitrary integer not less than 2. The M sub-boards specifically include one or more first sub-boards 301. This embodiment does not limit the number of first sub-boards 301. This embodiment takes the circuit board including one first sub-board 301 as an example. The M sub-boards also include one or more second sub-boards. This embodiment does not limit the number of second sub-boards. This embodiment takes the circuit board including multiple second sub-boards as an example. Multiple second sub-boards are symmetrically distributed along the target direction Z with the first sub-board 301 as the center. For example, the circuit board includes two second sub-boards, namely, the second sub-board 302 and the second sub-board 303. Along the target direction Z, the first sub-board 301 is located between the second sub-board 302 and the second sub-board 303. The circuit board also includes a conductive layer (such as the copper foil shown in Figure 2) located between the first sub-board 301 and the second sub-board 302. It should be noted that this embodiment does not limit the number of second sub-boards included in the circuit board. For example, if the circuit board includes four second sub-boards, then two second sub-boards are superimposed on the upper surface of the first sub-board 301, and two second sub-boards are superimposed on the lower surface of the first sub-board 302. The circuit board shown in this example also includes a conductive layer located between two adjacent second sub-boards. It should be noted that this embodiment takes multiple second sub-boards symmetrically distributed around the first sub-board 301 as an example to improve the overall flatness of the circuit board and the reliability of the circuit board structure. In other examples, the multiple second sub-boards can also be asymmetrically distributed around the first sub-board 301. This embodiment does not limit the positional relationship between the first sub-board 301 and the second sub-board. In other examples, the positional relationship between the first sub-board and the second sub-board in the circuit board can be interchangeable. For example, the second sub-board is located between multiple first sub-boards.

[0072] The M sub-boards shown in this embodiment may also include one or more third sub-boards. This embodiment does not limit the number of third sub-boards; instead, this embodiment uses a circuit board including multiple third sub-boards as an example. The multiple third sub-boards are symmetrically distributed along the target direction Z, centered around the first sub-board 301, to improve the overall flatness of the circuit board and enhance the reliability of the circuit board structure. For example, the circuit board includes two third sub-boards, namely, a third sub-board 304 and a third sub-board 305. Along the target direction Z, the first sub-board 301, the second sub-board 302, and the second sub-board 303 are located between the third sub-board 304 and the third sub-board 305. That is, the third sub-board 304 is connected to the surface of the second sub-board 302 facing away from the first sub-board 301, and the third sub-board 305 is connected to the surface of the second sub-board 303 facing away from the first sub-board 301. The circuit board also includes a conductive layer located between the second sub-board 302 and the third sub-board 304, and a conductive layer located between the second sub-board 303 and the third sub-board 305. It should be clarified that this embodiment does not limit the number of third sub-boards included in the circuit board. For the description of the number and distribution form of the third sub-boards included in the circuit board, please refer to the description of the number and distribution form of the second sub-boards included in the circuit board. The details will not be repeated here.

[0073] As can be seen from the above description, it is difficult for the same dielectric material to have both low CTE and low Df properties. As shown in this embodiment, in order to reduce the overall CTE and Df of the circuit board, the two properties of low CTE and low Df are decomposed into different sub-boards included in the circuit board. In this embodiment, the first sub-board has the low CTE property, while the second sub-board has the low Df property. It can be understood that in order to suppress the CTE mismatch between the circuit board and the electronic device, the CTE of the circuit board needs to be reduced. The method of reducing the CTE of the circuit board shown in this embodiment is to ensure that the CTE of the first sub-board 301 is smaller than the CTE of the second sub-board. Specifically, in the target XY plane, the CTE of the first sub-board 301 is smaller than the CTE of the second sub-board. The CTE of the third sub-board shown in this embodiment is smaller than the CTE of the second sub-board. Specifically, in the target XY plane, the CTE of the third sub-board is smaller than the CTE of the second sub-board. It should be noted that the CTE of each sub-panel shown in this embodiment is based on the CTE within the target plane. In other examples, the CTE of each sub-panel can also be the CTE of each sub-panel along the target direction Z, and this is not limited in this embodiment. It is understood that the CTE of the second sub-panel shown in this embodiment is the highest among the M sub-panels. This embodiment does not limit the magnitude relationship between the CTE of the first sub-panel and the CTE of the third sub-panel.

[0074] Among the M sub-boards included in the circuit board, if the CTE of the first sub-board and the third sub-board are respectively smaller than the CTE of the second sub-board, the overall CTE of the circuit board can be effectively reduced. For details, please refer to the following formula 3:

[0075] Taking the circuit board shown in this embodiment as a PCB as an example, it should be clear that the description of the circuit board type in this embodiment is not limited. For example, the circuit board can also be a substrate. The description of the circuit board type can refer to the corresponding description of Figure 1, and the details will not be repeated. The CTE of the PCB is affected by the dielectric material and thickness used in the PCB. When the proportion of copper foil in the PCB is certain and the design of the PCB is certain, the lower the CTE of the dielectric material, the lower the CTE of the PCB. The design of the PCB includes vias, plug holes, solder mask, residual copper rate of the pattern, etc., which are not specifically limited. The CTE of the PCB can be obtained by formula 3:

[0076] Formula 3:

[0077] In formula 3, 1 to n are the codes of each sub-board on the PCB. The PCB includes sub-board 1, sub-board 2, and so on, to sub-board n. αn is the CTE of sub-board n, En is the Young's modulus of sub-board n, and φn is the volume ratio of sub-board n. As can be seen from the above, if the CTE of the first sub-board 301 and the third sub-board is reduced, the overall CTE of the PCB can be effectively reduced, where the overall CTE of the PCB is a in formula 3. PCB .

[0078] As can be seen from the above description, it is difficult for a sub-board to have both low CTE and low insertion loss performance. In order to enable the circuit board to have both low CTE and low insertion loss performance, this embodiment decomposes the performance of low CTE and the performance of low insertion loss into different sub-boards included in the circuit board. Specifically, when the CTE of the second sub-board is the highest among the M sub-boards, then the Df of the second sub-board is the smallest among the M sub-boards, thereby reducing the overall CTE and insertion loss of the circuit board. To this end, in order to ensure that the insertion loss of the second sub-board is the lowest among the M sub-boards, then the Df of the second sub-board is smaller than the Df of the first sub-board, and the Df of the second sub-board is smaller than the Df of the third sub-board. This embodiment does not limit the size relationship between the Df of the first sub-board and the Df of the third sub-board. It can be understood that when the CTE of the second sub-board is the highest among the M sub-boards and the Df of the second sub-board is the smallest among the M sub-boards, then this embodiment decomposes the performance of low CTE and low insertion loss into two different sub-boards, that is, the first sub-board and the third sub-board have low CTE performance, and the second sub-board has low insertion loss performance.

[0079] In order to effectively reduce the overall CTE of the circuit board in this embodiment, the Young's modulus of the second sub-board is smaller than that of the first sub-board, and / or the Young's modulus of the second sub-board is smaller than that of the third sub-board. In this embodiment, the Young's modulus of the second sub-board is the lowest among the M sub-boards as an example. Then, due to the low Young's modulus of the second sub-board, the negative impact of the high CTE of the second sub-board on the CTE of the entire circuit board can be reduced as much as possible. As shown in the above formula 3, in order to reduce the overall CTE of the circuit board, under the condition that the CTE and volume ratio of the M circuit boards are constant, the lower the Young's modulus of the second sub-board, the lower the overall CTE of the circuit board. Optionally, in the circuit board shown in this embodiment, the third sub-board is located in the outermost layer. Then, the Young's modulus of the third sub-board is the highest among the multiple sub-boards included in the circuit board, thereby effectively improving the overall rigidity of the circuit board and reducing the imprint when the circuit board surface is mounted. The following is a detailed description of each sub-board of the circuit board:

[0080] The first sub-board 301 can serve as a power layer or ground layer with lower electrical requirements. The power layer houses power and ground lines to ensure a stable and reliable power supply for the entire circuit board. The ground layer houses ground and power lines to ensure a stable and reliable ground connection for the entire circuit board. The Young's modulus of the first sub-board 301 is greater than that of the second sub-board. The high Young's modulus of the first sub-board 301 improves the reliability of the circuit board, and the low CTE of the first sub-board 301 effectively reduces the overall CTE of the circuit board. It is understood that the dielectric material of the first sub-board 301 should be selected from a dielectric material with a low CTE and without consideration for insertion loss. For example, the dielectric material of the first sub-board 301 can be bismaleimide triazine resin (BT resin) or a high-rigidity epoxy resin. The dielectric material of the first sub-board 301 also includes glass cloth with a low CTE, thereby ensuring that the first sub-board 301 has a low CTE and a high Young's modulus. Among them, glass cloth with low CTE includes but is not limited to high-strength glass (T-glass) glass cloth, high-strength glass fiber (S-glass) glass cloth and any other type of reinforcing material with low CTE and high Young's modulus. The copper foil on both sides of the first sub-board 301 can be reverse (RTF) copper foil, RTF2, RTF3, high-frequency ultra-low profile copper foil (HVLP), ultra-thin detachable copper foil with a thickness of ≤5μm along the target direction Z, etc. based on the minimum line width requirement. The interface treatment agent between the glass cloth and the copper foil is selected based on the resin system, such as silane coupling agents containing amino or epoxy groups, etc., and is not specifically limited. The first sub-board 301 shown in this example has a CTE of ≤10ppm / ℃ and a Young's modulus of ≥10 gigapascals (GPa) in the target plane XY. Optionally, the first sub-board 301 can be a fiber-reinforced composite material with a glass transition temperature (Tg) ≥220℃. This embodiment does not limit the number of layers of the first sub-board 301. For example, the first sub-board 301 is designed to be a double-layer or multi-layer structure based on performance requirements such as power supply, thermal conductivity, and shielding. The overall thickness of the first sub-board is ≥400μm. The thickness of the first sub-board 301 along the target direction Z shown in this embodiment is greater than the thickness of the second sub-board along the target direction Z, and the thickness of the first sub-board 301 along the target direction Z is greater than the thickness of the third sub-board along the target direction Z. It can be understood that the thickness of the first sub-board 301 along the target direction Z is the highest among the M sub-boards. Then, when the first sub-board 301 has a lower CTE in the target plane XY, the CTE of the entire circuit board is effectively reduced.

[0081] Taking the second sub-board 302 as an example, the second sub-board 302 can be used as a signal layer with higher electrical requirements. The second sub-board 302 uses a dielectric material with low Young's modulus and low insertion loss. That is, the Young's modulus of the second sub-board 302 is the lowest among the M sub-boards, and the Df of the second sub-board 302 is the lowest among the M sub-boards. For example, to achieve low insertion loss for the second sub-board 302, the Df of the second sub-board 302 is ≤ 0.002. To achieve a low Young's modulus for the second sub-board 302, the Young's modulus of the second sub-board 302 is ≤ 5 GPa. The CTE of the second sub-board 302 shown in this example within the target plane XY is greater than the CTE of the first sub-board 301 within the target plane XY. Therefore, the CTE of the second sub-board 302 shown in this example within the target plane XY is ≤ 35 ppm / °C, the Young's modulus is ≤ 3 GPa, and the Dk is ≤ 3.5. Optionally, the second sub-board 302 may be in the form of a film, sheet, or resin coated copper foil (RCC). Optionally, if the second sub-board 302 is in the form of RCC, the selection of its copper foil is based on the circuit manufacturing process and line width requirements. If it is a modified semi-addition process (mSAP) process with a line width of ≤40μm, it can be used with a 1-5μm carrier copper foil. If it is a negative film (tenting) process, it can be used with RTF, RTF2, RTF3, or HVLP copper foil. The second sub-board 302 may not use continuously woven fiber cloth as a reinforcement material to reduce the overall Young's modulus. The dielectric material of the second sub-board 302 may be a thermosetting resin or a thermoplastic resin. Among them, the thermosetting resin may be a modified epoxy resin, a low-polarity resin, or polyphenylene oxide (PPO), which may also be referred to as polypheylene ether (PPE). The thermoplastic resin may be liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), or polyimide (PI).

[0082] As the information transmission rate of communication equipment increases, the capacity of transmitted information also increases, prompting the circuit boards used in communication equipment to develop towards higher speed and higher density. Accordingly, the requirements for high-speed signal transmission performance of circuit boards are becoming increasingly stringent. Furthermore, the increasingly dense routing and / or via pitches, and the increasing size of electronic devices (such as chips), lead to an increasing risk of reliability failures such as solder joint cracking, CAF, and HAST. To improve the reliability of communication equipment and achieve the goal of reducing via pitch, the dielectric material used in the circuit board must have low insertion loss, small via pitch, and low CTE within the target XY plane. In the circuit board shown in this embodiment, the second sub-board has low Df and low Young's modulus, enabling the second sub-board to achieve a small via pitch. Pitch generally refers to the center-to-center distance between vias or pads on a circuit board. Specifically, because the second sub-board does not use continuously woven fiber cloth as a reinforcement material, it can improve the reliability of small-pitch CAF and HAST resistance in ultra-dense, small via pitch scenarios, especially in scenarios with pitch ≤ 200μm. Impedance control requirements can be met at a relatively low thickness. Since the second sub-board is relatively thin, the negative impact of the second sub-board on the overall CTE of the circuit board can be reduced, and the overall thickness of the circuit board can be reduced.

[0083] Taking the third sub-board 304 as an example, the third sub-board 304 is the outermost layer of the PCB. Due to the need to consider operations such as surface mounted technology (SMT) for pad mounting, this embodiment takes the third sub-board 304 having the highest Young's modulus among the M sub-boards included in the circuit board as an example. Specifically, the Young's modulus of the third sub-board 304 is ≥7GPa and Df is ≤0.004@10GHz. The CTE of the third sub-board 304 within the target plane XY is ≤30ppm / °C. To reduce the conductor loss of the third sub-board 304, its copper foil uses low-roughness copper foil with a micro-roughness ten-point height (Rz) of ≤3μm, and the thickness is determined based on the minimum line width requirement. The thicknesses of the second sub-board 302 and the third sub-board 304 shown in this embodiment are ≤100μm, respectively.

[0084] The Young's modulus of the circuit board can be obtained by the following formula 4:

[0085] Formula 4:

[0086] Among them, E PCBis the Young's modulus of the entire PCB, and 1-n are the designations of the sub-boards on the PCB. The PCB includes sub-board 1, sub-board 2, and so on, up to sub-board n. En is the Young's modulus of sub-board n, and φn is the volume fraction of sub-board n. This embodiment can be used based on Equation 4 to design the Young's modulus of M circuit boards, ensuring that the second sub-board has the highest Young's modulus among the M sub-boards.

[0087] It will be appreciated that the circuit board structure shown in this embodiment can be used to adjust the overall CTE and Young's modulus of the circuit board by using dielectric materials with different CTE and Young's modulus properties on different sub-boards, and by adjusting the thickness of the sub-boards to suit the overall CTE and Young's modulus requirements. In this embodiment, the overall CTE of the circuit board is reduced by reducing the CTE of the first and third sub-boards within the target plane XY. Therefore, the CTE requirement for the second sub-board within the target plane XY can be relaxed. Because the CTE requirement for the second sub-board within the target plane XY is relaxed, a dielectric material with a relatively low Df can be used for the second sub-board, thereby ensuring that the circuit board provided by this embodiment achieves both low CTE and low insertion loss performance.

[0088] The following describes the structure of the circuit board with a specific example:

[0089] Figure 4 is a structural diagram of a second embodiment of a circuit board provided by the present application, wherein the circuit board shown in Figure 4 is a high-density interconnector (HDI) circuit board as an example.

[0090] FIG4 shows an example diagram of the structure of a circuit board in a coordinate system XYZ. For an explanation of the XYZ coordinate system, please refer to the corresponding explanation of FIG1 , which will not be described in detail. The circuit board shown in this embodiment specifically includes a first sub-board 401. For an explanation of the structure of the first sub-board 401, please refer to the explanation of the first sub-board corresponding to FIG3 , which will not be described in detail. The circuit board also includes a plurality of second sub-boards. In this embodiment, the circuit board includes six second sub-boards, that is, along the target direction Z, the circuit board includes, from top to bottom, a second sub-board 411, a second sub-board 412, a second sub-board 413, a second sub-board 414, a second sub-board 415, and a second sub-board 416. This embodiment does not limit the number of second sub-boards. The circuit board may also include two third sub-boards, that is, along the target direction Z, the circuit board includes, from top to bottom, a third sub-board 421 and a third sub-board 422. This embodiment does not limit the number of third sub-boards. In this embodiment, a plurality of second sub-boards are symmetrically distributed around the first sub-board 401 as the center, and a plurality of third sub-boards are symmetrically distributed around the first sub-board 401 as the center. For the description of the positional relationship between the first sub-board, the second sub-board, and the third sub-board shown in this embodiment, please refer to the embodiment corresponding to Figure 3, and the details are not repeated here. The M sub-boards shown in this embodiment may also include at least one fourth sub-board. In this embodiment, the circuit board includes two fourth sub-boards as an example, namely, a fourth sub-board 431 and a fourth sub-board 432. The plurality of fourth sub-boards are also symmetrically distributed around the first sub-board 401 as the center. Specifically, the fourth sub-board 431 is located between the second sub-board 412 and the first sub-board 401, and the fourth sub-board 432 is located between the second sub-board 414 and the first sub-board 401.

[0091] The dielectric material of the fourth sub-board shown in the embodiment may be the same as the dielectric material of the first sub-board, and / or the dielectric material of the fourth sub-board may be the same as the dielectric material of the third sub-board. In order to suppress the CTE mismatch between the circuit board and the electronic device in this embodiment, it is necessary to reduce the CTE of the circuit board. The method of reducing the CTE of the circuit board shown in this embodiment is that, in the XY plane, the CTE of the first sub-board 401 is smaller than the CTE of the second sub-board, the CTE of the third sub-board is smaller than the CTE of the second sub-board, and the CTE of the fourth sub-board is smaller than the CTE of the second sub-board. The CTEs of the first sub-board, the third sub-board, and the fourth sub-board are respectively smaller than the CTE of the second sub-board, thereby effectively reducing the overall CTE of the circuit board. Please refer to the description of the embodiment corresponding to Figure 3 and no further details will be given.

[0092] In order to make the circuit board have both low CTE and low insertion loss performance, this embodiment has the Df of the second sub-board as the smallest among the M sub-boards, that is, the Df of the first sub-board 401 is greater than the Df of the second sub-board, the Df of the third sub-board is greater than the Df of the second sub-board, and the DF of the fourth sub-board is greater than the DF of the second sub-board. It can be understood that when the Df of the second sub-board is the lowest among the M circuit boards, the insertion loss of the circuit board is effectively reduced. In the circuit board shown in this embodiment, the third sub-board is located in the outermost layer, so the Young's modulus of the third sub-board is the highest among the M sub-boards included in the circuit board, thereby effectively improving the overall rigidity of the circuit board and reducing the footprint of the circuit board when mounting components on the surface. The Young's modulus of the second sub-board shown in this embodiment is the lowest among the M sub-boards. Therefore, due to the low Young's modulus of the second sub-board, the negative impact of the high CTE of the second sub-board on the CTE of the entire circuit board can be reduced as much as possible. The following is a detailed description of each sub-board of the circuit board:

[0093] The first sub-board 401 can be used as a power layer or a ground layer. For the description of the power layer and the ground layer, please refer to the description of the first sub-board corresponding to Figure 3, and the details are not repeated here. The first sub-board 401 shown in this embodiment has a high Young's modulus and a low CTE in the target plane XY, thereby improving the stability of the circuit board structure, reducing the overall CTE of the circuit board, and improving the overall warpage of the circuit board. The dielectric material of the first sub-board 401 is selected from a material with a CTE of ≤10ppm / ℃, a Young's modulus ≥10GPa in the target plane XY, and no consideration of Df. For specific details, please refer to the description of the dielectric material of the first sub-board 301 corresponding to Figure 3, and the details are not repeated here. Based on the actual board thickness and mechanical performance control requirements, the thickness of the first sub-board 401 is designed to be 100~1600μm. This embodiment takes the thickness of the first sub-board 401 ≥200μm as an example.

[0094] Taking the second sub-board 411 as an example, the second sub-board 411 can be in the form of a film, sheet, or RCC. The second sub-board 411 does not use continuously woven fiber cloth as a reinforcement material to reduce the overall Young's modulus. The dielectric material of the second sub-board 411 can be selected from thermosetting resin or thermoplastic resin. For the description of thermosetting resin or thermoplastic resin, please refer to the description of the second sub-board corresponding to Figure 3, and the details are not repeated here. The Df of the second sub-board 411 is ≤ 0.002 and the Young's modulus is ≤ 5 GPa. The CTE of the second sub-board 411 in the target plane XY is ≤ 35 ppm / °C. In this embodiment, the Young's modulus of the second sub-board 411 is ≤ 3 GPa, Dk ≤ 3.5, and the thickness is ≤ 50 μm. If the second sub-board 411 is made in the form of RCC, its thickness and copper foil selection are determined by the circuit manufacturing process and line width requirements; if it is an mSAP process (line width 20-50 μm), it can be used with a 1-3 μm carrier copper foil, etc. If the tenting process (line width ≥ 40μm) is used, RTF, RTF2, RTF3, HVLP and other copper foils can be used. For the description of any second sub-board included in the circuit board, please refer to the description of the second sub-board 411, and the details will not be repeated here.

[0095] Taking the third sub-board 421 as an example, it can achieve both low CTE and low insertion loss performance. The dielectric material for the third sub-board 421 can be a material with a relatively low CTE that also achieves low insertion loss performance. Specifically, the CTE of the third sub-board 421 within the target plane XY is smaller than the CTE of the second sub-board within the target plane XY. The Df of the third sub-board 421 is greater than the Df of the second sub-board 411. For example, the dielectric material for the third sub-board 421 can be a modified high-rigidity epoxy + BT resin. The dielectric material of the third sub-board 421 can also partially incorporate low-polarity CH resin, and the overall performance is controlled through pre-polymerization. Optionally, the dielectric material of the third sub-board 421 can also be combined with glass cloth with low Dk to achieve good electrical performance. For example, the glass cloth can include NE-glass, NER-glass, low-loss glass cloth (L-glass), L2-glass, and other glass cloths with low Dk. Optionally, to reduce conductor loss, the copper foil of the third sub-board 421 uses low-roughness copper foil with an Rz ≤ 3μm, with a thickness determined based on the minimum line width requirement. Because the third sub-board 421 uses a fiberglass-reinforced dielectric material, high-density via pitch is not provided on this layer. The third sub-board 421 has a CTE ≤ 17ppm / °C, a Young's modulus ≥ 7GPa, a Df ≤ 0.004@10GHz, and a thickness ≤ 100μm within the target XY plane. For details about the fourth sub-board, refer to the descriptions of the first or third sub-board 421; details are not repeated here.

[0096] The following table shows the thickness of the copper foil on each daughter board of the circuit board, the thickness of each daughter board itself, and the copper foil coating process:

[0097] Table 1

[0098] It can be understood that Layer L1 is the copper foil covering the surface of the third sub-board 421 , Layer L2 is the copper foil covering the surface of the second sub-board 411 , and so on. Layer 12 is the copper foil covering the surface of the third sub-board 422 .

[0099] Based on the overall CTE and Young's modulus requirements of the PCB, the CTE and Young's modulus of the PCB can be adjusted by using dielectric materials with different CTE and Young's modulus properties on different daughter boards. For details, see Table 2 below:

[0100] Table 2

[0101] The structures of the circuit boards shown in Examples 1 to 8 in Table 2 all adopt the embodiment shown in Figure 4, that is, the CTE of the first sub-board in the XY plane is the lowest among the multiple sub-boards included in the circuit board. The Young's modulus of the second sub-board is the lowest among the multiple sub-boards included in the circuit board. In the examples described in Table 2, taking the dielectric material of the third sub-board as the same as the dielectric material of the fourth sub-board as an example, the CTE and Young's modulus of the third sub-board and the fourth sub-board in the target plane XY are between the first sub-board and the second sub-board. Specifically, in Example 1, the dielectric material of the first sub-board is a glass fiber cloth reinforced dielectric material, and the CTE in the target plane XY is 8ppm / ℃, the Young's modulus is 30GPa, Df≥0.008 / 10GHz, and the thickness is 410μm. The third sub-board and the fourth sub-board use the same dielectric material. The third and fourth sub-boards both use glass fiber cloth-reinforced dielectric materials, and have a CTE of 15ppm / °C, a Young's modulus of 20GPa, a Df of 0.004 / 10GHz, and a thickness of 40μm within the target plane XY. The second sub-board uses a non-fiber-reinforced membrane material, and has a CTE of 35ppm / °C, a Young's modulus of 2GPa, a Df of 0.0012 / 10GHz, a thickness of 30μm, and a Dk of 3.0 within the target plane XY. Therefore, in Example 1, the CTE of the entire PCB within the target plane XY is 25.4ppm / °C, and the Young's modulus is 11.9GPa. The Dk of the PCB is 3.0, and the Df is 0.012. Examples 2 to 8 are analogous and will not be described in detail.

[0102] The performance of each sub-board of the circuit board shown in Figure 2 can be seen in Table 3:

[0103] Table 3

[0104] For a detailed description of the circuit board corresponding to Table 3, please refer to Figure 2 and will not be elaborated on in detail. In Comparative Example 1, the CTE of the dielectric material of the first sub-board in the target plane XY is 8ppm / ℃, the Young's modulus is 30GPa, and the thickness is 410μm. The CTE of the second sub-board in the target plane XY is 15ppm / ℃, the Young's modulus is 20GPa, and the thickness is 40μm. Because the dielectric material of the second sub-board in the existing circuit board cannot have both low CTE and low insertion loss performance, the Df of the second sub-board is relatively large, which is 0.0038@10GHz. That is, in the circuit board shown in Figure 2, the CTE of the first sub-board in the target plane XY is the lowest among all the sub-boards included in the circuit board, and the Young's modulus of the first sub-board is the highest among all the sub-boards included in the circuit board. Then, the CTE of the corresponding circuit board as a whole in the target plane XY is 28.7, and the Young's modulus is 12.1.

[0105] From Tables 2 and 3, it can be seen that the structure of the circuit board shown in FIG4 makes the CTE of the circuit board in the target plane XY lower than that of the circuit board corresponding to FIG2. At the same time, the circuit board shown in FIG4 can achieve the performance of ultra-low Df and low Dk for the second sub-board, can be made into a high-speed signal layer transmission, and effectively reduce the insertion loss.

[0106] The circuit board structure shown in this embodiment includes multiple dielectric materials with different properties. Different properties, such as low CTE, high Young's modulus, and low insertion loss, within the target plane XY are decomposed into different sub-boards within the circuit board. For example, the CTE of the first sub-board within the target plane XY is lower than that of the second sub-board within the target plane XY. The second sub-board has the lowest Young's modulus among the M sub-boards. The second sub-board also has the lowest Df among the M sub-boards. It can be understood that the lower CTE and lower Df within the target plane XY are decomposed into the first and second sub-boards, respectively. Because the first sub-board has a lower CTE within the target plane XY, the overall CTE of the circuit board within the target plane XY is effectively reduced. Because the second sub-board has a lower Df, the insertion loss of the circuit board is effectively reduced. Furthermore, the second sub-board has the lowest Young's modulus among the M sub-boards, effectively suppressing the negative impact of the second sub-board's high CTE on reducing the overall CTE of the circuit board. By reducing the CTE of the circuit board within the target plane XY, the CTE mismatch between the circuit board and electronic components is effectively suppressed. The Young's modulus of the first sub-board and the Young's modulus of the third sub-board are both higher than that of the second sub-board, which effectively improves the reliability of the overall structure of the circuit board.

[0107] Because the first sub-panel shown in this embodiment has a low CTE within the target plane XY and does not need to have low insertion loss (i.e., low Df), the dielectric material of the first sub-panel does not need to simultaneously achieve low CTE and low insertion loss, effectively reducing the cost and manufacturing difficulty of the first sub-panel. The circuit board shown in this embodiment can achieve the following goals: CTE ≤ 15ppm / °C and Df ≤ 0.001 within the target plane XY. This ensures that the entire circuit board has low CTE and low insertion loss within the target plane XY, ensuring the reliability of the circuit board structure.

[0108] FIG4 shows an example of a circuit board including 12 layers of copper foil. It should be noted that this embodiment does not limit the number of copper foil layers included in the circuit board. For example, the circuit board may include 16 layers of copper foil. First, the structure of a conventional circuit board including 16 layers of copper foil will be described with reference to FIG5 , which is another exemplary structure of a conventional circuit board.

[0109] The circuit board includes a first sub-board 501 coated with copper foil on both sides. For a description of the first sub-board 501, please refer to the description corresponding to FIG2 , and the details are not repeated here. The circuit board also includes 14 second sub-boards stacked sequentially from top to bottom along the Z direction, namely, second sub-board 511, second sub-board 512, second sub-board 513, second sub-board 514, second sub-board 515, second sub-board 516, second sub-board 517, second sub-board 518, second sub-board 519, second sub-board 520, second sub-board 521, second sub-board 522, second sub-board 523, and second sub-board 524. The 14 second sub-boards are symmetrically distributed around the first sub-board 501. For a description of each second sub-board, please refer to the description of the corresponding second sub-board in FIG2 , and the details are not repeated here. The circuit board corresponding to FIG5 includes 15 layers of copper foil, namely, L1, L2, and so on, to L16. Among them, L1 is the copper foil covering the surface of the second sub-board 511, and so on, L16 is the copper foil covering the surface of the second sub-board 524. The performance of the circuit board corresponding to Figure 5 can be seen in Table 4:

[0110] Table 4

[0111] Using the structure of an existing circuit board as shown in FIG5 , the first sub-board 501 is covered on both sides with copper foils L8 and L9, respectively. The thickness of the first sub-board 501 along the target direction Z is 400 μm, and the thickness of each of the 14 second sub-boards along the target direction Z is 70 μm. In the circuit board corresponding to FIG5 , the Young's modulus of the entire circuit board is 30.2 GPa, and the CTE in the target plane XY is 13.2 ppm / °C.

[0112] FIG6 is a structural example diagram of the third embodiment of the circuit board provided in this application. The circuit board shown in FIG6 also includes 15 layers of copper foil. The circuit board shown in this embodiment is a structural example diagram within the coordinate system XYZ. For the description of the coordinate system XYZ, please refer to the corresponding description of FIG3 , and the details are not repeated here. The circuit board shown in this embodiment includes sub-boards 601, 602, 603 to 615 stacked in sequence along the target direction Z. The performance of the circuit board corresponding to FIG6 can be seen in Table 5:

[0113] Table 5

[0114] In Example 1 of the circuit board corresponding to Figure 6 , sub-board 608 is the first sub-board, sub-boards 601, 603, 604, 605, 606, 609, 610, 611, 612, and 613 are the third sub-boards, and sub-boards 602 and 614 are the second sub-boards. For descriptions of the first, second, and third sub-boards, please refer to the descriptions corresponding to Figure 3 , and details are omitted here. In the circuit board corresponding to Example 1, the performance of the first sub-board is as follows: the CTE of first sub-board 608 within the target plane XY is 10 ppm / °C, the Young's modulus is 20 GPa, and the thickness along the target direction Z is 400 μm. Each third sub-board has a CTE within the target plane XY of 13 ppm / °C, a Young's modulus of 15 GPa, and a thickness along the target direction Z of 70 μm. The second sub-board can be in the form of RCC, and each second sub-board has a CTE of 30ppm / °C, a Young's modulus of 3GPa, and a thickness of 50μm along the target direction Z in the target plane XY. As shown in Table 5, the CTE of the first sub-board in the XY plane is the lowest among all the sub-boards included in the circuit board. The Young's modulus of the second sub-board is the lowest among all the sub-boards included in the circuit board. For specific details, please refer to the corresponding description of Figure 3, and the details will not be repeated. Then, the CTE of the entire circuit board shown in Example 1 in the target plane XY is 13.4 and the Young's modulus is 28.4GPa.

[0115] In Example 2, sub-board 608 is the first sub-board, sub-boards 601, 604, 605, 606, 609, 610, 611, and 612 are the third sub-board, and sub-boards 602, 603, 614, and 613 are the second sub-board. For descriptions of the first, second, and third sub-boards, please refer to the corresponding descriptions in FIG3 , and detailed descriptions are omitted. For descriptions of the performance of the first, second, and third sub-boards, please refer to Example 1, and detailed descriptions are omitted. Using the circuit board shown in Example 2, the CTE of the entire circuit board within the target plane XY is 13.6, and the Young's modulus is 26.7 GPa.

[0116] In Example 3, sub-board 608 is the first sub-board, sub-boards 601, 604, 606, 607, 609, 610, 612, and 615 are the third sub-board, and sub-boards 602, 603, 605, 611, 613, and 614 are the second sub-board. For the description of the first, second, and third sub-boards, please refer to the corresponding description of Figure 3, and the details are not repeated here. For the description of the performance of the first, second, and third sub-boards, please refer to Example 1, and the details are not repeated here. Using the circuit board shown in Example 3, the CTE of the entire circuit board in the target plane XY is 13.8 and the Young's modulus is 24.9 GPa.

[0117] In Example 4, sub-board 608 is the first sub-board, sub-boards 601, 604, 606, 607, 609, 610, 612, and 615 are the third sub-board, and sub-boards 602, 603, 605, 611, 613, and 614 are the second sub-board. For descriptions of the first, second, and third sub-boards, please refer to the corresponding descriptions in FIG3 , and no further details are given here. For descriptions of the performance of the first, second, and third sub-boards, please refer to Example 1 , and no further details are given here. Using the circuit board shown in Example 4, the CTE of the entire circuit board in the target plane XY is 14.1, and the Young's modulus is 23.1 GPa.

[0118] Comparing Examples 1 to 4 in Table 4 and Table 5, it can be seen that the structure of the circuit board corresponding to FIG6 is closer to or equivalent to the CTE of the existing circuit board compared to the result of using the existing circuit board corresponding to FIG5 . However, the structure of the circuit board shown in FIG6 can effectively reduce the insertion loss.

[0119] In Example 5 shown in Table 5, sub-board 608 is the first sub-board, sub-boards 601, 604, 606, 607, 609, 610, 612, and 615 are the third sub-boards, and sub-boards 602, 603, 605, 611, 613, and 614 are the second sub-boards. For the description of the first, second, and third sub-boards, please refer to the corresponding description of Figure 3, and no further details are given. The difference between Example 4 and Example 5 is that the thickness of the first sub-board shown in Example 5 along the target direction Z is 500um. For the description of the performance of the first, second, and third sub-boards, please refer to Example 1, and no further details are given. Using the circuit board shown in Example 4, the CTE of the entire circuit board in the target plane XY is 13.8 and the Young's modulus is 25.1GPa. By comparing Example 4 and Example 5, it can be seen that when the thickness of the first sub-board along the target direction Z is increased, the CTE in the target plane XY will be reduced. For example, when the thickness of the first sub-board shown in Example 5 is greater than the thickness of the first sub-board shown in Example 4 along the target direction Z, the CTE of the circuit board shown in Example 5 in the target plane XY is less than the CTE of the circuit board shown in Example 4 in the target plane XY.

[0120] Table 5 shows a circuit board with a different number of second sub-board layers in different examples. For example, Example 1 in Table 5 includes two second sub-board layers, Example 2 includes four second sub-board layers, and Example 3 includes six second sub-board layers. Table 6 shows a performance table in which the circuit board corresponding to Figure 6 includes a fixed number of first, second, and third sub-boards, but the different examples have different Young's moduli for the second sub-boards.

[0121] Table 6

[0122] In Examples 1 and 2 shown in Table 6, the first sub-board is sub-board 608, and the second sub-board is sub-board 602, 603, 605, 611, 613, and 614. The third sub-board is sub-board 601, 604, 606, 607, 609, 610, 612, and 615. For a description of the performance of each sub-board, please refer to the corresponding description in Table 5, and the details are not repeated here. The difference between Example 1 and Example 2 included in Table 6 is that the Young's modulus of the second sub-board shown in Example 1 is 1 GPa, and the Young's modulus of the second sub-board shown in Example 2 is 2 GPa. Comparing Examples 1 and 2 included in Table 6, it can be seen that when the Young's modulus of the second sub-board of Example 2 is greater than the Young's modulus of the first sub-board of Example 1, the Young's modulus of the entire circuit board of Example 2 is greater than the Young's modulus of the entire circuit board of Example 1. The CTE of the circuit board shown in Example 2 within the target plane XY is greater than the CTE of the circuit board shown in Example 1 within the target plane XY.

[0123] FIG7 is a structural example diagram of the fourth embodiment of the circuit board provided in this application. FIG7 shows an example diagram of the structure of the circuit board in the coordinate system XYZ. For the description of the coordinate system XYZ, please refer to the corresponding description of FIG3 , which will not be described in detail. The circuit board shown in FIG7 has multiple layers of first sub-boards distributed along the target direction Z. For example, the circuit board shown in this embodiment includes seven layers of first sub-boards, namely, the first sub-board 701, the first sub-board 702, the first sub-board 703, the first sub-board 704, the first sub-board 705, the first sub-board 706 and the first sub-board 707. This embodiment can design the number of layers of the first sub-board included in the circuit board based on performance requirements such as power supply, thermal conductivity and shielding. Among them, the first sub-board 702, the first sub-board 704 and the first sub-board 706 are CCLs, while the first sub-board 701, the first sub-board 703, the first sub-board 705 and the first sub-board 707 are prepregs (PP). It is understood that among the multiple first sub-boards, of two adjacent first sub-boards along the target direction Z, one first sub-board is CCL and the other first sub-board is PP. Optionally, the overall thickness of the multi-layer first sub-boards along the target direction Z is ≥ 400 μm. The circuit board also includes multi-layer second and third sub-boards. For a description of the second and third sub-boards, please refer to the above embodiment and will not be repeated here.

[0124] The second sub-panel shown in this embodiment can be in the form of a film, sheet, or RCC. For example, if the second sub-panel is in the form of a film or RCC, then the second sub-panel specifically includes a first dielectric layer. The CTE of the first dielectric layer within the target plane XY is greater than the CTE of the first sub-panel and the CTE of the third sub-panel, respectively, and the Df of the first dielectric layer is less than the Df of the first sub-panel and the Df of the third sub-panel, respectively. For a description of the CTE, Df, and Young's modulus of the first dielectric layer, please refer to the description of the CTE, Df, and Young's modulus of the second sub-panel shown in the above embodiment, and the details are not repeated here. For example, the first dielectric layer shown in this example has a Df ≤ 0.002, a Young's modulus ≤ 5 GPa, a CTE ≤ 35 ppm / °C within the target plane XY, and a thickness ≤ 50 μm. The first dielectric layer has a first surface and a second surface positioned opposite each other, and the first and second surfaces of the first dielectric layer are aligned along the target direction Z. That is, along the target direction Z, the first surface is the upper surface of the first dielectric layer, and the second surface is the lower surface of the first dielectric layer. At least one of the first surface or the second surface is covered with at least one second dielectric layer. For example, the first surface is covered with one, two, or any number of second dielectric layers, and / or the second surface is covered with one, two, or any number of second dielectric layers. The second dielectric layer is used to enhance the bonding strength between the second sub-board and the copper foil, or to enhance the glue filling performance of the second sub-board, or to improve the indentation resistance of the surface layer of the second sub-board. The thickness of the second dielectric layer shown in this example along the target direction Z is ≤10μm. The dielectric material of the first dielectric layer shown in this example is different from the dielectric material of the second dielectric layer.

[0125] The first dielectric layer and the second dielectric layer shown in this example meet at least one of the following conditions:

[0126] The Df of the second dielectric layer is smaller than the Df of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the CTE of the second dielectric layer is smaller than the CTE of the first dielectric layer.

[0127] For example, as shown in Figure 8, Figure 8 is an example diagram of the structure of the fifth embodiment of the circuit board provided in this application. Taking the second sub-board as a film material as an example, specifically, the second sub-board includes a first dielectric layer 801 and a second dielectric layer 802 covering the first surface of the first dielectric layer 801. The circuit board may specifically include two second sub-boards 800, and the two second sub-boards 800 are symmetrically distributed with the first sub-board 810 as the center. For the specific description of the first sub-board 810 and the second sub-board 800 included in the circuit board, please refer to the above embodiment, and no further details will be given. It can be understood that since the second sub-board shown in this example includes the first dielectric layer and the second dielectric layer, the second sub-board includes multiple layers of dielectric material. This embodiment does not limit the number of dielectric material layers included in the second sub-board. This embodiment takes the circuit board including two second sub-boards as an example. In other examples, the circuit board may include any integer number of second sub-boards, and the number of second sub-boards included in the circuit board is not limited. The first sub-board, the third sub-board and the fourth sub-board provided in this embodiment may also include a first dielectric layer and a second dielectric layer. For the description of the first dielectric layer and the second dielectric layer, please refer to the description of the first dielectric layer and the second dielectric layer included in the first sub-board, and the details are not repeated here.

[0128] In the above embodiment, taking the circuit board as HDI as an example, the electrical interconnection between different sub-boards of the circuit board is through micro-buried blind vias. Specifically, HDI uses a laser to directly drill holes in each sub-board to form conductive through-holes, buried vias, and blind vias for realizing electrical interconnection between different sub-boards. In the embodiment shown in Figure 9, the sub-boards included in the circuit board are electrically interconnected through through-holes, wherein Figure 9 is an example diagram of the structure of the sixth embodiment of the circuit board provided in this application. As shown in Figure 9, the circuit board includes 15 layers of sub-boards as an example, that is, the circuit board shown in this embodiment arranges sub-boards 901, 902 to 915 in order from top to bottom according to the target direction Z. The circuit board includes 16 layers of copper foil, and Layer L1, Layer L2 to Layer L16 are arranged in order from top to bottom according to the target direction Z. Layer L1 is the copper foil covering the surface of daughter board 901, Layer L2 is the copper foil covering the surface of daughter board 902, and so on, Layer 116 is the copper foil covering the surface of daughter board 915. It should be noted that this embodiment does not limit the number of daughter boards and copper foils included in the circuit board.

[0129] Specifically, the first sub-board included in the circuit board is sub-board 908, sub-board 901 and sub-board 915 are respectively the third sub-board, and sub-board 902, sub-board 903, sub-board 904, sub-board 905, sub-board 906, sub-board 907, sub-board 909, sub-board 910, sub-board 911, sub-board 912, sub-board 913 and sub-board 914 are respectively the second sub-board. For the description of the first sub-board, the second sub-board and the third sub-board, please refer to the above embodiment and the details will not be repeated. The sub-board 901 and sub-board 915 included in the circuit board shown in this embodiment are located on both sides of the outermost surface. The circuit board includes a plurality of through holes 920, and the through holes 920 pass through the various sub-boards included in the circuit board from one side of the sub-board 901, so that the through holes 920 pass through the entire circuit board along the target direction Z to pass through the sub-board 915. The through holes 920 can realize electrical connection between the various sub-boards included in the circuit board, providing electrical connection and mechanical support. This embodiment does not limit the number of through-holes included in the circuit board. It is understood that the second sub-board has the highest CTE within the target plane XY among all the sub-boards included in the circuit board. The second sub-board also has the lowest Young's modulus among all the sub-boards included in the circuit board. The second sub-board also has the lowest Df among all the sub-boards included in the circuit board.

[0130] The performance of each sub-board included in the circuit board shown in this embodiment is shown in Table 7:

[0131] Table 7

[0132] Sub-board 908, which serves as the first sub-board, can be used as a power layer or a ground layer. The first sub-board has a high Young's modulus, which can improve the reliability of the circuit board. The low CTE of the first sub-board effectively reduces the overall CTE of the circuit board. It can be understood that the dielectric material of the first sub-board is selected from a material with a small CTE and without considering the loss. For the description of the specific dielectric material, please refer to the description of the dielectric material used to make the first sub-board shown in the above embodiment, and the details will not be repeated. The first sub-board shown in this embodiment has a CTE ≤ 10ppm / ℃ in the target plane XY, a Young's modulus ≥ 10GPa, and a thickness of 100 to 1600μm. For example, this embodiment takes the thickness of the first sub-board ≥ 200μm as an example.

[0133] Sub-board 901 and sub-board 915, which serve as the third sub-board, are the outermost layer of the circuit board. The third sub-board shown in this embodiment can take into account both the requirements of low CTE and low loss within the target plane XY. That is, the dielectric material of the third sub-board can be selected from materials with relatively small CTE and taking into account insertion loss performance. For a description of the dielectric material of the third sub-board, please refer to the above embodiment and the details will not be repeated. The copper foil covering the third sub-board is a low-roughness copper foil with Rz ≤ 3μm, and the thickness is determined based on the minimum line width requirement. The CTE of the third sub-board within the target plane XY is ≤ 17ppm / ℃, the Young's modulus is ≥ 7GPa, the Df is ≤ 0.004@10GHz, and the thickness is ≤ 100μm.

[0134] Sub-boards 902, 903, 904, 905, 906, 907, 909, 910, 911, 912, 913, and 914 serve as second sub-boards. The multiple second sub-boards included in the circuit board can adopt two different structural forms. The second sub-boards of the two structural forms can be arranged at intervals. For example, sub-boards 902, 904, 906, 910, 912, and 914 have a first structural form. Sub-boards 903, 905, 907, 909, 911, and 913 have a second structural form. The first structural form refers to a semi-cured adhesive film, and the second structural form refers to a fully cured adhesive film. The second sub-plate is constructed to reduce the Young's modulus and is made of a dielectric material without continuous coded fiber cloth reinforcement. For details on the dielectric material, refer to the dielectric material used to make the second sub-plate in the above embodiment. For example, the second sub-plate has a Df ≤ 0.002, a Young's modulus ≤ 5 GPa, a CTE within the target plane XY ≤ 35 ppm / °C, and a Dk ≤ 3.5. Preferably, its thickness is ≤ 50 μm.

[0135] The performance of the circuit board shown in this embodiment is shown in Table 8:

[0136] Table 8

[0137] The circuit boards shown in Table 8 include three examples. In Example 1, the first sub-board of the circuit board has a CTE of 8, a Young's modulus of 30 GPa, and a thickness of 400 μm within the target plane XY. The third sub-board has a CTE of 15, a Young's modulus of 20, and a thickness of 100 μm within the target plane XY. The second sub-board has a CTE of 35, a Young's modulus of 2, and a thickness of 50 μm within the target plane XY. In Example 1, the entire circuit board has a CTE of 20.7 and a Young's modulus of 14.5 within the target plane XY. In Example 2, the first sub-board of the circuit board has a CTE of 8, a Young's modulus of 30, and a thickness of 400 μm within the target plane XY. The third sub-board has a CTE of 15, a Young's modulus of 20, and a thickness of 100 μm within the target plane XY. The second sub-board has a CTE of 30, a Young's modulus of 2, and a thickness of 50 μm within the target plane XY. In Example 2, the overall CTE of the circuit board within the target plane XY is 20.7, and the Young's modulus is 14.3. In Example 3, the first sub-board of the circuit board within the target plane XY has a CTE of 8, a Young's modulus of 30, and a thickness of 400 μm. The third sub-board within the target plane XY has a CTE of 15, a Young's modulus of 20, and a thickness of 100 μm. The second sub-board within the target plane XY has a CTE of 25, a Young's modulus of 2, and a thickness of 50 μm. In Example 3, the overall CTE of the circuit board within the target plane XY is 20.7, and the Young's modulus is 14.1.

[0138] The performance of existing circuit boards is shown in Table 9:

[0139] Table 9

[0140] For the description of the existing circuit board structure, please refer to the corresponding description of Figure 2, and the details will not be repeated here. It can be understood that the CTE of the first sub-board of the existing circuit board in the target plane XY is 8, the Young's modulus is 30, and the thickness is 200um. The CTE of the second sub-board in the target plane XY is 15, the Young's modulus is 20, and the thickness is 100. The CTE of the existing circuit board as a whole in the target plane XY is 26.2, and the Young's modulus is 14.9. Comparing Table 8 and Table 9, it can be seen that the structure of the circuit board shown in this embodiment can effectively reduce the CTE of the circuit board as a whole in the target plane XY, and can ensure that the Young's modulus of the circuit board is close to that of the existing circuit board. It can be understood that the circuit board shown in this embodiment can take into account the requirements of low CTE and high Young's modulus of the circuit board.

[0141] An embodiment of the present application also provides a circuit board, which may be a PCB or a substrate. For specific descriptions, please refer to any embodiment shown in Figures 3, 4, 6, 7, 8 or 9, and the details will not be repeated here.

[0142] An embodiment of the present application also provides a communication system, which includes at least two connected communication devices. For specific descriptions of the communication devices, please refer to any embodiment shown in Figures 1, 3, 4, 6, 7, 8 or 9, and the details will not be repeated here.

[0143] The embodiment of the present application also provides a chip. For the description of the chip, please refer to the corresponding description of Figure 1 and the details will not be repeated here.

[0144] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit board, characterized in that: Along a direction perpendicular to the surface of the circuit board, the circuit board includes M sub-boards arranged in sequence, where M is an arbitrary integer not less than 2, and the M sub-boards include a first sub-board and a second sub-board, wherein the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the first sub-board.

2. The circuit board according to claim 1, characterized in that: The Young's modulus of the second sub-plate is smaller than that of the first sub-plate.

3. The circuit board according to claim 1 or 2, characterized in that: The M sub-boards include a plurality of the second sub-boards, and the plurality of the second sub-boards are symmetrically distributed with the first sub-board as the center.

4. The circuit board according to any one of claims 1 to 3, characterized in that: The M sub-boards further include a third sub-board, and the second sub-board is located between the first sub-board and the second sub-board; The thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the third sub-board.

5. The circuit board according to claim 4, characterized in that: The Young's modulus of the second sub-plate is smaller than the Young's modulus of the third sub-plate.

6. The circuit board according to claim 4 or 5, characterized in that: The M sub-boards include a plurality of the third sub-boards, and the plurality of the third sub-boards are symmetrically distributed with the first sub-board as the center.

7. The circuit board according to any one of claims 4 to 6, characterized in that: In a target plane, the thermal expansion coefficient of the first sub-board is smaller than that of the second sub-board, and the thermal expansion coefficient of the third sub-board is smaller than that of the second sub-board, and the target plane is parallel to the surface of the circuit board.

8. The circuit board according to any one of claims 4 to 7, characterized in that: The thickness of the first sub-board along the target direction is greater than the thickness of the second sub-board along the target direction, and the thickness of the first sub-board along the target direction is greater than the thickness of the third sub-board along the target direction, wherein the target direction is a direction perpendicular to the surface of the circuit board.

9. The circuit board according to any one of claims 4 to 8, characterized in that: The M sub-boards include a fourth sub-board, and along a direction perpendicular to the surface of the circuit board, the fourth sub-board is located between the first sub-board and the second sub-board; The thermal expansion coefficient of the fourth sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the fourth sub-board.

10. The circuit board according to claim 9, characterized in that: The Young's modulus of the second sub-plate is smaller than the Young's modulus of the fourth sub-plate.

11. The circuit board according to any one of claims 1 to 10, characterized in that: The second sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; The second sub-board also includes a second dielectric layer. Along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface that are located opposite to each other, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

12. The circuit board according to claim 11, characterized in that: The first dielectric layer and the second dielectric layer satisfy at least one of the following conditions: The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

13. A communication device, characterized in that: The invention comprises a circuit board and an electronic device connected to the circuit board, wherein the circuit board is as claimed in any one of claims 1 to 12.

14. A chip, characterized in that: The chip comprises a packaging shell, wherein the packaging shell comprises a circuit board and a bare chip connected to the circuit board, and the circuit board is as described in any one of claims 1 to 12.

Images