Radiation-resistant semiconductor device having dynamically adjustable threshold, process, circuit, and chip

Abstract

The present application relates to the technical field of semiconductors, and discloses a radiation-resistant semiconductor device having a dynamically adjustable threshold, a process, a circuit, and a chip. The radiation-resistant semiconductor device having a dynamically adjustable threshold comprises a substrate, a bottom gate layer, a bottom gate dielectric layer, an epitaxial layer, a top gate dielectric layer, and a top gate layer which are sequentially stacked; the epitaxial layer comprises a source region, a body region, and a drift region which are sequentially arranged in the transverse direction; the bottom gate layer is located directly below the body region and the drift region; the top gate layer is located directly above the body region and the drift region; and the bottom gate layer and the top gate layer form electric fields having opposite directions in the body region and the drift region. When the device is in an on state, a conductive channel is formed in the device and far away from the surface of the device, and therefore is not prone to be interfered by external radiation, and thus the device is more stable. In addition, a double-gate structure is used to achieve dynamic regulation of double gates to obtain different threshold voltages required by the circuit by means of device design, so that the costs of adjusting process parameters and the process are reduced.

Description

Radiation-resistant dynamic threshold modulation semiconductor devices, processes, circuits and chips Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a radiation-resistant dynamic threshold modulation semiconductor device, process, circuit and chip. Background Art

[0002] LDMOS (Lateral Double-Diffused Metal-Oxide-Semiconductor), as a power device, is widely used in various power conversion integrated circuits, such as power management circuits, LDO circuits, switching power supply circuits, and driver circuits.

[0003] LDMOS applications are often exposed to electromagnetic radiation. The presence of large numbers of charged particles and radiation can easily cause degradation of LDMOS's electrical parameters, a phenomenon known as the total dose effect. This can lead to a decrease in device threshold voltage, an increase in subthreshold current, increased noise, and increased leakage current, leading to device failure and, ultimately, chip failure.

[0004] Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a radiation-resistant dynamic threshold modulation semiconductor device, process, circuit, and chip. These devices have strong radiation resistance, meet the application requirements of power chips in complex electromagnetic interference environments, and can also dynamically adjust the threshold.

[0006] In the first aspect, the present application provides a radiation-resistant dynamic threshold modulation semiconductor device, comprising a substrate, a bottom gate layer, a bottom gate dielectric layer, an epitaxial layer, a top gate dielectric layer and a top gate layer stacked in sequence, the epitaxial layer comprising a source region, a body region, a drift region and a drain region arranged in sequence along the horizontal direction, the bottom gate layer is located directly below the body region and the drift region, the top gate layer is located directly above the body region and the drift region, and the bottom gate layer and the top gate layer form electric fields in opposite directions in the body region and the drift region.

[0007] In the second aspect, the present application also provides a radiation-resistant dynamic threshold modulation semiconductor device, comprising a substrate, a bottom gate layer, a bottom gate dielectric layer, an epitaxial layer, a top gate dielectric layer and a top gate layer stacked in sequence, the epitaxial layer comprising a source region, a body region, a drift region and a drain region arranged in sequence along the horizontal direction, the bottom gate layer is located directly below the body region and the drift region, the bottom gate dielectric layer forms a field oxide region above the bottom gate layer, the thickness of the field oxide region is greater than the thickness of other regions of the bottom gate dielectric layer, at least part of the drift region is located directly above the field oxide region, the top gate layer is located directly above the body region and the drift region, and the bottom gate layer and the top gate layer form electric fields in opposite directions in the body region and the drift region.

[0008] On the third aspect, the present application also provides a radiation-resistant dynamic threshold modulation semiconductor device, comprising a substrate, a bottom gate layer, a bottom gate dielectric layer, an epitaxial layer, a top gate dielectric layer and a top gate layer stacked in sequence, the epitaxial layer comprising a source region, a body region, a drift region and a drain region arranged in sequence along the horizontal direction, the bottom gate layer is located directly below the body region and the drift region, the bottom gate dielectric layer forms a first field oxidation region above the bottom gate layer, the thickness of the first field oxidation region is greater than the thickness of other regions of the bottom gate dielectric layer, at least part of the drift region is located directly above the first field oxidation region, the top gate dielectric layer forms a second field oxidation region above at least part of the drift region, the thickness of the second field oxidation region is greater than the thickness of other regions of the top gate dielectric layer, the top gate layer is located directly above the body region and the drift region, and the bottom gate layer and the top gate layer form electric fields in opposite directions in the body region and the drift region.

[0009] Fourthly, the present application also provides a radiation-resistant dynamic threshold modulation semiconductor device, comprising a substrate, a bottom gate layer, a bottom gate dielectric layer, an epitaxial layer, a top gate dielectric layer and a top gate layer stacked in sequence, the epitaxial layer comprising a source region, a body region, a drift region and a drain region arranged in sequence along the horizontal direction, the bottom gate layer is located directly below the body region and the drift region, an inversion region is formed in the drift region, the conductivity type of the inversion region is opposite to the conductivity type of the drift region, the top gate layer is located directly above the body region and the drift region, the bottom gate layer and the top gate layer form electric fields of opposite directions in the body region and the drift region.

[0010] In the fifth aspect, the present application also provides a radiation-resistant dynamic threshold modulation semiconductor device, comprising a substrate, a bottom gate layer, a bottom gate dielectric layer, an epitaxial layer, a top gate dielectric layer and a top gate layer stacked in sequence, the epitaxial layer comprising a source region, a body region, a drift region and a drain region arranged in sequence along the horizontal direction, the bottom gate layer is located directly below the body region and the drift region, the bottom gate dielectric layer forms a field oxidation region above the bottom gate layer, the thickness of the field oxidation region is greater than the thickness of other regions of the bottom gate dielectric layer, at least part of the drift region is located directly above the field oxidation region, an inversion region is formed in the drift region, the conductivity type of the inversion region is opposite to the conductivity type of the drift region, the top gate layer is located directly above the body region and the drift region, the bottom gate layer and the top gate layer form electric fields of opposite directions in the body region and the drift region.

[0011] In a sixth aspect, the present application also provides a process for a radiation-resistant dynamic threshold modulation semiconductor device, comprising: providing a substrate; forming a bottom gate layer on the substrate; forming a bottom gate dielectric layer on the substrate and the bottom gate layer; forming an epitaxial layer on the bottom gate dielectric layer, the epitaxial layer comprising a source region, a body region, a drift region and a drain region arranged in sequence along the horizontal direction, the bottom gate layer being located directly below the body region and the drift region; forming a top gate dielectric layer on the epitaxial layer; forming a top gate layer on the top gate dielectric layer, the top gate layer being located directly above the body region and the drift region.

[0012] In a seventh aspect, the present application also provides a circuit comprising the aforementioned radiation-resistant dynamic threshold modulation semiconductor device.

[0013] In the eighth aspect, the present application also provides an electrostatic protection circuit, including the aforementioned anti-radiation dynamic threshold modulation semiconductor device, the drain of the anti-radiation dynamic threshold modulation semiconductor device is coupled to the electrostatic protection node, the source of the anti-radiation dynamic threshold modulation semiconductor device is coupled to the ground node, and the gate and source of the anti-radiation dynamic threshold modulation semiconductor device are short-circuited.

[0014] In a ninth aspect, the present application also provides a chip comprising the aforementioned radiation-resistant dynamic threshold modulation semiconductor device.

[0015] In a tenth aspect, the present application also provides an electronic device, which includes the aforementioned radiation-resistant dynamic threshold modulation semiconductor device.

[0016] The radiation-resistant dynamic threshold modulation semiconductor device, process, circuit, chip, and electronic device of the present application have at least one of the following beneficial effects:

[0017] (1) The traditional device structure has only one electrode, the top gate, and the conductive channel is on the upper surface, which is easily affected by external radiation. The field oxide is exposed to the outside world and easily captures a large number of holes to generate new electric field effects. The radiation-resistant dynamic threshold modulation semiconductor device of the present application adopts a dual-gate structure consisting of a bottom gate electrode and a top gate electrode. When the bottom gate electrode is used for control, the conductive channel is on the lower surface and is not easily affected by external radiation. When the top gate and bottom gate electrodes are used for control at the same time, the conductive channel is in the middle and is also not easily affected by external radiation. In addition, the top gate electrode can be a polysilicon or metal gate electrode, which effectively shields the body region and drift region of the device and is not easily affected by external radiation.

[0018] (2) Under the dual-gate control, the conductive channel is formed between the body region and the drift region, achieving high mobility and low on-resistance. In traditional device structures, since the conductive channel exists on the surface of the body region, and the body and dielectric materials are in contact with each other, a large number of interface defect states are easily generated, causing surface scattering of the conductive channel and reducing the carrier mobility. By changing the position of the channel, the surface scattering effect of the interface state is avoided;

[0019] (3) In traditional device structures, since the conductive channel exists on the surface of the body region, and the body and dielectric materials are in contact at the interface, a large number of interface defect states are easily generated. Under the influence of the electrical, magnetic, and thermal multi-physical field stress environment, the carriers in the conductive channel on the surface are easily captured by the interface state, or tunnel into the oxide and are captured by the trap state, causing the threshold voltage and saturation current to drift, leading to circuit function disorder and chip failure. However, the conductive channel of the structure of the present application is located in the middle, and the carriers are not easily captured by the interface defects, thereby improving the reliability of the device.

[0020] (4) The gate control capability of the structure of the present application is strong, and the device characteristics are still very good at a small size. It helps to improve the subthreshold characteristics of the device, the turn-on speed is fast, and the response speed of the circuit will also become faster; it helps to improve the device mobility and on-state current, thereby reducing the on-resistance;

[0021] (5) Due to the introduction of the inverse ion implantation layer, it helps to form a depletion region in the drift region, which can withstand voltage and improve the withstand voltage characteristics of the device;

[0022] (6) Since the voltages of the top gate and bottom gate can be adjusted independently, the threshold voltage of the device can be dynamically and flexibly adjusted. Devices with different threshold voltages can be obtained without making complex process changes, which can flexibly meet circuit requirements and save process development costs.

[0023] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0025] FIG1 is a schematic diagram of a structure of a radiation-resistant semiconductor device according to an embodiment of the present application;

[0026] FIG2 is a second structural schematic diagram of a radiation-resistant semiconductor device provided in an embodiment of the present application;

[0027] FIG3 is a third structural schematic diagram of a radiation-resistant semiconductor device provided in an embodiment of the present application;

[0028] FIG4 is a fourth structural schematic diagram of a radiation-resistant semiconductor device provided in an embodiment of the present application;

[0029] FIG5 is a fifth structural diagram of a radiation-resistant semiconductor device provided in an embodiment of the present application;

[0030] FIG6 is a schematic flow chart of a process for producing a radiation-resistant semiconductor device according to an embodiment of the present application.

[0031] Reference numerals:

[0032] Substrate 10 , bottom gate layer 30 , bottom gate dielectric layer 20 , first field oxide region 31 , epitaxial layer 40 , source region 41 , body region 42 , drift region 43 , drain region 44 , spacer region 45 , inversion region 46 , top gate dielectric layer 50 , second field oxide region 51 , top gate layer 60 . DETAILED DESCRIPTION

[0033] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0034] In the following description, a "circuit" refers to a conductive loop consisting of at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "coupled to" or "connected to" another element, or when an element / circuit is said to be "coupled to" or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements between the two elements.

[0035] In the description, the terms "first," "second," etc. are used to distinguish similar objects, not to describe a particular order or precedence. It should be understood that the numerical descriptors used in this manner are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," etc. are generally of a class and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0036] In addition, descriptions with reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0037] In related technologies, the gate of an LDMOS is located above the device. When in the on state, a conductive channel forms within the device just below the gate, meaning it also forms above the device. Consequently, when the LDMOS is exposed to electromagnetic radiation, the total dose effect can cause a decrease in the LDMOS threshold voltage, an increase in subthreshold current, increased noise, and increased leakage current, leading to device failure.

[0038] The embodiments of the present application propose radiation-resistant semiconductor devices, processes, circuits, chips and electronic devices. The gate structure in the radiation-resistant semiconductor device includes a bottom gate layer. When the device is in the on state, a conductive channel is formed inside the device, away from the surface of the device, so that it is not easily affected by external radiation interference and the device is more stable.

[0039] Referring to Figure 1 , one embodiment of the present application also provides a radiation-hardened semiconductor device. In this embodiment, the radiation-hardened semiconductor device includes a substrate 10, a bottom gate layer 30, a bottom gate dielectric layer 20, an epitaxial layer 40, a top gate dielectric layer 50, and a top gate layer 60, which are stacked in sequence. The epitaxial layer 40 includes a source region 41, a body region 42, a drift region 43, and a drain region 44 arranged in a laterally arranged manner. The bottom gate layer 30 is located directly below the body region 42 and the drift region 43, and the top gate layer 60 is located directly above the body region 42 and the drift region 43. The bottom gate layer 30 and the top gate layer 60 form electric fields in opposite directions within the body region 42 and the drift region 43.

[0040] It should be noted that the shapes and sizes of the regions shown in FIG1 are merely examples and do not limit the radiation-hardened semiconductor device of the embodiment of the present application. The actual size can be set as required and is not limited in this embodiment.

[0041] In some embodiments, the radiation-hardened semiconductor device may be an LDMOS transistor, which may be an N-channel or a P-channel transistor. Of course, the radiation-hardened semiconductor device may also be formed into other types of MOSFET devices or IGBT devices.

[0042] As an example, the LDMOS transistor is an N-channel transistor. The substrate 10 and the body region 42 have P-type conductivity, while the source region 41, the drift region 43, and the drain region 44 have N-type conductivity. The drift region 43 can have a relatively low doping concentration, while the source region 41 and the drain region 44 can have a relatively high doping concentration.

[0043] As another example, the LDMOS transistor is a P-channel transistor. The substrate 10 and body region 42 have N-type conductivity, while the source region 41, drift region 43, and drain region 44 have P-type conductivity. The drift region 43 can have a lower doping concentration, while the source region 41 and drain region 44 can have a higher doping concentration.

[0044] The bottom gate dielectric layer 20 is used to isolate the bottom gate layer 30 from the epitaxial layer 40 , so as to prevent the bottom gate layer 30 from drawing electrons out of the epitaxial layer 40 and prevent leakage.

[0045] It is understood that the bottom gate layer 30 and the top gate layer 60 are used to connect the gate voltage, thereby forming an electric field in the epitaxial layer 40. The bottom gate dielectric layer 20 is used to isolate the bottom gate layer 30 from the epitaxial layer 40, and the top gate dielectric layer 50 is used to isolate the top gate layer 60 from the epitaxial layer 40, thereby preventing the bottom gate layer 30 or the top gate layer 60 from extracting electrons from the epitaxial layer 40 and preventing leakage.

[0046] Because the body region 42 is located between the bottom gate layer 30 and the top gate layer 60, when the gate voltage meets the device's conduction requirements, an inversion layer forms in the middle of the body region 42, which then forms a conductive channel. Because the conductive channel is formed inside the device, away from the device surface, and because the top gate dielectric layer 50 and the top gate layer 60 themselves can also provide a certain degree of shielding, the conductive channel is not easily affected by external radiation.

[0047] In some embodiments, the bottom gate layer 30 may also be located below a portion of the drift region 43. Under the action of the electric field, carriers in the drift region 43 gather on the side close to the bottom gate layer 30, thereby improving the conductivity. Of course, the vertical projection of the bottom gate layer 30 can completely cover the vertical projection of the drift region 43. When the bottom gate layer 30 completely covers the drift region 43, the conductivity is further improved.

[0048] The embodiments of the present application propose a radiation-resistant semiconductor device, wherein the gate structure includes a bottom gate layer 30 and a top gate layer 60. When the device is in the on state, a conductive channel is formed inside the device, away from the device surface, thereby being less susceptible to interference from external radiation and making the device more stable. In addition, by adopting a dual-gate structure, different threshold voltages required by the circuit can be obtained through device design and dynamic control of the dual gate, thereby saving the cost of adjusting process parameters and procedures.

[0049] In some embodiments, the substrate 10 may be a single crystal silicon substrate, a silicon-doped substrate, or an SOI (Silicon On Insulator) substrate.

[0050] In some embodiments, the bottom gate layer 30 is a polysilicon electrode or a metal electrode.

[0051] The material of the metal electrode can be copper, aluminum, gold, tin, etc.

[0052] In some embodiments, the bottom gate dielectric layer 20 and the top gate dielectric layer 50 are made of silicon oxide or high-K oxide.

[0053] Silicon oxide can be silicon dioxide, and high-K oxide can be aluminum oxide. As an insulating material, silicon oxide can effectively form electrical isolation between the bottom gate layer 30 and the epitaxial layer 40. High-K oxide refers to an oxide with a high dielectric constant. Due to its low conductivity, it can also be used to isolate the bottom gate layer 30 and the epitaxial layer 40.

[0054] In some embodiments, a spacer region 45 is provided between the body region 42 and the drift region 43 .

[0055] It is understood that when the device's source region 41 and drain region 44 are connected to an electronic circuit and the device is not conducting, the device will be subjected to the voltage applied between the source region 41 and the drain region 44, thereby forming a transverse electric field within the device. When the voltage between the source region 41 and the drain region 44 is very high, carriers will be driven between the source region 41 and the drain region 44 by the transverse electric field, causing the device to break down. Therefore, by adding the spacer region 45, the device is less susceptible to breakdown, thereby improving its voltage resistance.

[0056] As an example, the spacer region 45 may have the same conductivity type as the drift region 43, and the doping concentration of the spacer region 45 may be lower than the doping concentration of the drift region 43. Alternatively, the spacer region 45 may have the same conductivity type as the body region 42, and the doping concentration of the spacer region 45 may be higher than the doping concentration of the body region 42.

[0057] Of course, in other embodiments, the body region 42 and the drift region 43 may also be in direct contact with each other.

[0058] In some embodiments, the top surfaces of the body region 42 and the drift region 43 are at a first height, the top surfaces of the source region 41 and the drain region 44 are at a second height, and the first height is lower than the second height.

[0059] In this embodiment, the heights of the body region 42 and the drift region 43 are lower than those of the source region 41 and the drain region 44. Since the upper surface of the top gate dielectric layer 50 is generally planar when the device is packaged, when the heights of the body region 42 and the drift region 43 are relatively low, the portion of the top gate dielectric layer 50 above the body region 42 and the drift region 43 in the packaged device is relatively thick, thereby providing better isolation and protecting the conductive channel from external radiation.

[0060] In some embodiments, the bottom gate layer 30 and the top gate layer 60 can be connected to different gate voltages. By adjusting the magnitudes of the two gate voltages, the height of the conductive channel can be adjusted.

[0061] In some embodiments, the bottom gate layer 30 may be located below a portion of the drift region 43, and the top gate layer 60 may be located above a portion of the drift region 43. The vertical projections of the bottom gate layer 30 and the top gate layer 60 may completely cover the vertical projections of the drift region 43. The bottom gate layer 30 and the top gate layer 60 completely cover the drift region 43, thereby improving the conductive performance.

[0062] In some embodiments, the thickness of the top gate dielectric layer 50 is greater than the thickness of the bottom gate dielectric layer 20 .

[0063] In this embodiment, the radiation-hardened semiconductor device uses the bottom gate layer 30 as the main driving gate and the top gate layer 60 as the auxiliary driving gate, with the bottom gate layer 30 providing the primary driving capability. A thicker top gate dielectric layer 50 provides greater isolation from the top gate layer 60. However, since the top gate layer 60 serves as the auxiliary driving gate, a reduced driving capability does not affect device operation, but does enhance shielding against external radiation and improve device stability.

[0064] In some embodiments, the bottom gate layer 30 and the top gate layer 60 are symmetrically distributed on the upper and lower sides of the body region 42 and the drift region 43 .

[0065] It is understood that in the manufacturing process of a radiation-hardened semiconductor device, the bottom gate layer 30 and the top gate layer 60 are formed using a photolithography process, which involves the use of a mask for exposure. Using the same pattern for the bottom gate layer 30 and the top gate layer 60 allows the manufacturing processes of the bottom gate layer 30 and the top gate layer 60 to share the same mask, thereby reducing the number of masks.

[0066] In some embodiments, the bottom gate layer 30 and the top gate layer 60 are polysilicon electrodes or metal electrodes.

[0067] The material of the metal electrode can be copper, aluminum, gold, tin, etc.

[0068] In some embodiments, the bottom gate dielectric layer 20 and the top gate dielectric layer 50 are made of silicon oxide or high-K oxide.

[0069] The silicon oxide may be silicon dioxide, and the high-K oxide may be aluminum oxide.

[0070] Referring to FIG2 , one embodiment of the present application further provides a radiation-hardened semiconductor device. In this embodiment, the radiation-hardened semiconductor device includes a substrate 10, a bottom gate layer 30, a bottom gate dielectric layer 20, an epitaxial layer 40, a top gate dielectric layer 50, and a top gate layer 60 stacked in sequence. The epitaxial layer 40 includes a source region 41, a body region 42, a drift region 43, and a drain region 44 arranged in a laterally arranged manner. The bottom gate layer 30 is located directly below the body region 42 and the drift region 43. The bottom gate dielectric layer 20 forms a first field oxide region 31 above the bottom gate layer 30. The first field oxide region 31 is thicker than the thickness of other regions of the bottom gate dielectric layer 20. At least a portion of the drift region 43 is located above the first field oxide region 31. The top gate layer 60 is located directly above the body region 42 and the drift region 43. The bottom gate layer 30 and the top gate layer 60 form oppositely directed electric fields in the body region 42 and the drift region 43.

[0071] One difference between the radiation-hardened semiconductor device proposed in this embodiment and the radiation-hardened semiconductor device shown in FIG1 is that a first field oxide region 31 is provided between the bottom gate layer 30 and the drift region 43. The thickness of the first field oxide region 31 is greater than that of other regions in the bottom gate layer 30. Thus, the first field oxide region 31 can weaken the surface electric field formed by the bottom gate layer 30 in the drift region 43, thereby improving the breakdown voltage of the device.

[0072] It should be noted that the radiation-resistant semiconductor device proposed in this embodiment has a partially identical structure with the radiation-resistant semiconductor device shown in the aforementioned embodiments. The relevant content of this partially identical structure can refer to the aforementioned embodiments, that is, the radiation-resistant semiconductor device proposed in this embodiment also has the corresponding technical effects, which will not be repeated here in this embodiment.

[0073] 3 , an embodiment of the present application further provides a radiation-resistant semiconductor device. In this embodiment, the radiation-resistant semiconductor device includes a substrate 10, a bottom gate layer 30, a bottom gate dielectric layer 20, an epitaxial layer 40, a top gate dielectric layer 50, and a top gate layer 60 stacked in sequence. The epitaxial layer 40 includes a source region 41, a body region 42, a drift region 43, and a drain region 44 arranged in sequence along the transverse direction. The bottom gate layer 30 is located directly below the body region 42 and the drift region 43. The bottom gate dielectric layer 20 forms a first field oxide region 31 above the bottom gate layer 30. The thickness of the first field oxide region 31 is 100 nm. The thickness of the drift region 43 is greater than the thickness of other regions of the bottom gate dielectric layer 20. At least a portion of the drift region 43 is located above the first field oxidation region 31. The top gate dielectric layer 50 forms a second field oxidation region 51 above at least a portion of the drift region 43. The thickness of the second field oxidation region 51 is greater than the thickness of other regions of the top gate dielectric layer 50. The top gate layer 60 is located directly above the body region 42 and the drift region 43. The bottom gate layer 30 and the top gate layer 60 form electric fields in opposite directions in the body region 42 and the drift region 43.

[0074] In some embodiments, the first field oxide region 31 , other regions of the bottom gate dielectric layer 20 , the second field oxide region 51 and other regions of the top gate dielectric layer 50 may be made of the same or different materials, such as silicon dioxide or aluminum oxide.

[0075] One difference between the radiation-hardened semiconductor device proposed in this embodiment and the radiation-hardened semiconductor device shown in FIG1 is that a first field oxidation region 31 is provided between the bottom gate layer 30 and the drift region 43, and a second field oxidation region 51 is provided between the top gate layer 60 and the drift region 43. Thus, the first field oxidation region 31 weakens the electric field formed by the bottom gate layer 30 on the lower surface of the drift region 43, and the second field oxidation region 51 weakens the electric field formed by the top gate layer 60 on the upper surface of the drift region 43, thereby improving the breakdown voltage of the device.

[0076] It should be noted that the radiation-resistant semiconductor device proposed in this embodiment has a partially identical structure with the radiation-resistant semiconductor device shown in the aforementioned embodiments. The relevant content of this partially identical structure can refer to the aforementioned embodiments, that is, the radiation-resistant semiconductor device proposed in this embodiment also has the corresponding technical effects, which will not be repeated here in this embodiment.

[0077] In some embodiments, the first field oxide region 31 and the second field oxide region 51 are symmetrically distributed above and below the body region and the drift region.

[0078] It should be noted that the first field oxidation region 31 and the second field oxidation region 51 may also be manufactured using a photolithography process. Therefore, the first field oxidation region 31 and the second field oxidation region 51 use the same pattern to achieve mask sharing.

[0079] In some embodiments, the thickness of the second field oxide region 51 is less than the thickness of the first field oxide region 31 .

[0080] As previously mentioned, since the radiation-hardened semiconductor device with a dual-gate structure can use the bottom gate layer 30 as the main driving gate and the top gate layer 60 as the auxiliary driving gate, the electric field formed by the top gate layer 60 on the upper surface of the drift region 43 is relatively weak, so a relatively thin second field oxide region 51 can be provided to reserve more space.

[0081] Referring to Figure 4 , one embodiment of the present application further provides a radiation-hardened semiconductor device. In this embodiment, the radiation-hardened semiconductor device includes a substrate 10, a bottom gate layer 30, a bottom gate dielectric layer 20, an epitaxial layer 40, a top gate dielectric layer 50, and a top gate layer 60, which are sequentially stacked. The epitaxial layer 40 includes a source region 41, a body region 42, a drift region 43, and a drain region 44 arranged in a laterally arranged manner. An inversion region 46 is formed within the drift region 43. The conductivity type of the inversion region 46 is opposite to that of the drift region 43. The bottom gate layer 30 is located directly below the body region 42 and the drift region 43, and the top gate layer 60 is located directly above the body region 42 and the drift region 43. The bottom gate layer 30 and the top gate layer 60 form electric fields in opposite directions within the body region 42 and the drift region 43.

[0082] One difference between the radiation-hardened semiconductor device proposed in this embodiment and the radiation-hardened semiconductor device shown in FIG1 is that an inversion region 46 is provided in the drift region 43. The inversion region 46 can effectively deplete the carriers in the drift region 43, thereby more effectively withstanding voltage and increasing the breakdown voltage.

[0083] It should be noted that the radiation-resistant semiconductor device proposed in this embodiment has a partially identical structure with the radiation-resistant semiconductor device shown in the aforementioned embodiments. The relevant content of this partially identical structure can refer to the aforementioned embodiments, that is, the radiation-resistant semiconductor device proposed in this embodiment also has the corresponding technical effects, which will not be repeated here in this embodiment.

[0084] 5 , an embodiment of the present application further provides a radiation-resistant semiconductor device. In this embodiment, the radiation-resistant semiconductor device includes a substrate 10, a bottom gate layer 30, a bottom gate dielectric layer 20, an epitaxial layer 40, a top gate dielectric layer 50, and a top gate layer 60 stacked in sequence. The epitaxial layer 40 includes a source region 41, a body region 42, a drift region 43, and a drain region 44 arranged in sequence along the horizontal direction. The bottom gate layer 30 is located directly below the body region 42 and the drift region 43. The bottom gate dielectric layer 20 forms a first field oxide region 31 above the bottom gate layer 30. The thickness of the first field oxide region 31 is greater than the thickness of other regions of the bottom gate dielectric layer 20. At least a portion of the drift region 43 is located above the first field oxide region 31. An inversion region 46 is formed in the drift region 43. The conductivity type of the inversion region 46 is opposite to that of the drift region 43. The top gate layer 60 is located directly above the body region 42 and the drift region 43. The bottom gate layer 30 and the top gate layer 60 form electric fields in opposite directions in the body region 42 and the drift region 43.

[0085] One difference between the radiation-hardened semiconductor device proposed in this embodiment and the radiation-hardened semiconductor device shown in FIG5 is that a first field oxide region 31 is provided between the bottom gate layer 30 and the drift region 43, and an inversion region 46 is provided within the drift region 43. Both the first field oxide region 31 and the inversion region 46 can increase the breakdown voltage and improve device reliability.

[0086] It should be noted that the radiation-resistant semiconductor device proposed in this embodiment has a partially identical structure with the radiation-resistant semiconductor device shown in the aforementioned embodiments. The relevant content of this partially identical structure can refer to the aforementioned embodiments, that is, the radiation-resistant semiconductor device proposed in this embodiment also has the corresponding technical effects, which will not be repeated here in this embodiment.

[0087] 6 , an embodiment of the present application further provides a process for producing a radiation-resistant semiconductor device. In this embodiment, the process includes the following steps:

[0088] Step 100: providing a substrate 10;

[0089] Step 200: forming a bottom gate layer 30 on the substrate 10;

[0090] Step 300 , forming a bottom gate dielectric layer 20 on the substrate 10 and the bottom gate layer 30 ;

[0091] Step 400: forming an epitaxial layer 40 on the bottom gate dielectric layer 20. The epitaxial layer 40 includes a source region 41, a body region 42, a drift region 43, and a drain region 44 arranged in sequence along the transverse direction. The bottom gate layer 30 is located directly below the body region 42 and the drift region 43.

[0092] Step 500: forming a top gate dielectric layer 50 on the epitaxial layer;

[0093] Step 600 : forming a top gate layer 60 on the top gate dielectric layer 50 . The top gate layer 60 is located directly above the body region 42 and the drift region 43 .

[0094] It should be noted that the structure of the radiation-resistant semiconductor device manufactured by the process of the radiation-resistant semiconductor device proposed in the embodiments of the present application can refer to the aforementioned embodiments.

[0095] In some embodiments, the substrate 10 may be a single crystal silicon substrate, a silicon-doped substrate, or an SOI (Silicon On Insulator) substrate.

[0096] The bottom gate layer 30 may be made of a conductive material for accessing a gate voltage. Since the material of the bottom gate layer 30 is different from that of the substrate 10 , the bottom gate layer 30 may be manufactured using a deposition process.

[0097] In some embodiments, the specific process of step 200 may be: first, polysilicon or metal material is deposited on the substrate 10 by a sputtering process to form a gate electrode film; and then the gate electrode film is photolithographically processed to form a bottom gate layer 30 .

[0098] The material of the metal electrode can be copper, aluminum, gold, tin, etc.

[0099] A thin film that completely covers the substrate 10 can be formed by a sputtering process, and then a portion of the thin film is removed by a photolithography process, with the remaining portion serving as the bottom gate layer 30 .

[0100] In other embodiments, the specific process of step 200 may also be: forming a mask layer on the substrate 10, wherein the mask layer has a blank area, and the blank area exposes the substrate 10; then depositing polysilicon or metal material in the blank area to form a bottom gate layer 30; and then removing the mask layer.

[0101] It should be noted that the bottom gate dielectric layer 20 is made of insulating material or low-conductivity material to isolate the bottom gate layer 30 and the epitaxial layer 40 to prevent the bottom gate layer 30 from extracting electrons from the epitaxial layer 40 and prevent leakage.

[0102] In some embodiments, the specific process of step 300 can be: using a plasma enhanced chemical vapor deposition process to deposit silicon dioxide on the substrate 10 and the bottom gate layer 30 to form the bottom gate dielectric layer 20; or using an atomic layer deposition process to deposit high-K oxide on the substrate 10 and the bottom gate layer 30 to form the bottom gate dielectric layer 20.

[0103] It is understood that the deposited bottom gate dielectric layer 20 covers the upper surface of the substrate 10 and the upper surface of the bottom gate layer 30, and has the same thickness in the region. Because the bottom gate layer 30 is formed on the substrate 10, the bottom gate dielectric layer 20 has a stepped structure formed at a position corresponding to the bottom gate layer 30.

[0104] In some embodiments, the specific process of step 400 may be: growing a single crystal silicon layer on the bottom gate dielectric layer 20; defining a source region 41, a body region 42, a drift region 43 and a drain region 44 in the single crystal silicon layer, and performing ion implantation.

[0105] In this embodiment, the epitaxial layer 40 is grown once, and then different ions are implanted into different regions to form the source region 41 , the body region 42 , the drift region 43 and the drain region 44 .

[0106] In some embodiments, the source region 41, the body region 42, the drift region 43 and the drain region 44 are defined in the single crystal silicon layer, and the specific process of ion implantation can be as follows: the source region 41 and the drain region 44 are defined at both ends of the single crystal silicon layer in the horizontal direction; ions are implanted into the source region 41 and the drain region 44; the body region 24 and the drift region 43 are defined in the middle of the single crystal silicon layer; the body region 42 and the drift region 43 are etched to remove the target thickness; and ion implantation is performed on the etched body region 42 and the drift region 43.

[0107] In this embodiment, the height of the body region 42 and the drift region 43 is lower than that of the source region 41 and the drain region 44. This facilitates the formation of a thicker top gate dielectric layer 50 above the body region 42 and the drift region 43, thereby improving isolation. Etching of the body region 42 and the drift region 43 can be performed after or before ion implantation of the region 41 and the drain region 44.

[0108] Taking an N-channel LDMOS transistor as an example, the radiation-hardened semiconductor device has a P-type conductivity. N-type conductive ions are implanted in the source region 41, the drift region 43, and the drain region 44, while P-type conductive ions are implanted in the body region 42. The drift region 43 can have a relatively low doping concentration, while the source region 41 and the drain region 44 can have a relatively high doping concentration.

[0109] Taking a P-channel LDMOS transistor as an example, the radiation-hardened semiconductor device has an N-type conductivity. P-type conductive ions are implanted in the source region 41, the drift region 43, and the drain region 44, while N-type conductive ions are implanted in the body region 42. The drift region 43 can have a relatively low doping concentration, while the source region 41 and the drain region 44 can have a relatively high doping concentration.

[0110] The P-type conductive ions may be boron, manganese, nickel, etc., and the N-type conductive ions may be arsenic, phosphorus, etc.

[0111] In other embodiments, the specific process of step 300 may also be: growing a silicon dioxide layer on the substrate 10 ; growing a silicon nitride layer on the bottom gate layer 30 , and the silicon dioxide layer and the silicon nitride layer form the bottom gate dielectric layer 20 .

[0112] In this embodiment, considering the subsequent formation process of the epitaxial layer 40, both materials are used to form the bottom gate dielectric layer 20. The silicon dioxide layer is used to form the source region 41 and the drain region 44, and the corresponding area of ​​the silicon nitride layer is used to form the body region 42 and the drift region 43.

[0113] In some other embodiments, the silicon nitride layer may also be grown above the region adjacent to the substrate 10 and the bottom gate layer 30 , so that part of the drift region 43 formed subsequently may be located outside the bottom gate layer 30 .

[0114] In this embodiment, the thickness of silicon nitride may be greater than the thickness of silicon dioxide.

[0115] The specific process of forming the epitaxial layer 40 based on the bottom gate dielectric layer 20 including silicon dioxide and silicon nitride can be as follows: growing a single crystal silicon layer on the bottom gate dielectric layer 20, the single crystal silicon layer being located above and protruding from the bottom gate layer 30; performing mechanical chemical polishing on the protruding portion of the single crystal silicon layer to expose the silicon nitride layer; performing ion implantation on the retained single crystal silicon layer to form a source region 41 and a drain region 44; etching the silicon nitride layer and retaining a silicon nitride layer having a first thickness; growing an active region on the silicon nitride layer; and performing ion implantation on the active region to form a body region 42 and a drift region 43.

[0116] It is understood that during the growth of the single-crystalline silicon layer, the growth rate at each location is substantially similar, and therefore the thickness of the formed single-crystalline silicon layer at each location is substantially the same. However, because the bottom gate layer 30 is formed on the substrate 10, and the thickness of the silicon nitride layer on the bottom gate layer 30 can be greater than the thickness of the silicon dioxide layer on the substrate 10, the portion of the single-crystalline silicon layer located above the silicon nitride layer is raised relative to the portion located above the silicon dioxide layer.

[0117] It should be noted that silicon nitride is not easy to grind flat. Therefore, when grinding the single-crystal silicon layer flat, when the depth reaches the silicon nitride layer, it is not easy to continue grinding down. At this point, the single-crystal silicon layer above the silicon nitride layer is ground away, leaving the single-crystal silicon layers on both sides unconnected, which can be used to form the source region 41 and the drain region 44.

[0118] By etching the silicon nitride layer, a space for forming the body region 42 and the drift region 43 can be formed. Retaining the silicon nitride layer with a first thickness can isolate the bottom gate layer 30. The first thickness can be the same as the thickness of the silicon dioxide layer.

[0119] In this embodiment, the types of ions implanted into the source region 41 , the body region 42 , the drift region 43 and the drain region 44 during ion implantation can refer to the above description and will not be further elaborated in this embodiment.

[0120] In some embodiments, the height of the active region grown on the silicon nitride is lower than the heights of the source region 41 and the drain region 44 .

[0121] The heights of the body region 42 and the drift region 43 are lower than those of the source region 41 and the drain region 44 , so that a thicker top gate dielectric layer 50 can be formed above the body region 42 and the drift region 43 to improve isolation.

[0122] In some embodiments, when forming the body region 42 and the drift region 43, a spacer region 45 may be further formed between the body region 42 and the drift region 43. The spacer region 45 may have the same conductivity type as the drift region 43, and the doping concentration of the spacer region 45 may be lower than the doping concentration of the drift region 43. Alternatively, the spacer region 45 may have the same conductivity type as the body region 42, and the doping concentration of the spacer region 45 may be higher than the doping concentration of the body region 42.

[0123] In some embodiments, the steps for forming the top gate dielectric layer 50 are the same as the steps for forming the bottom gate dielectric layer.

[0124] It is understandable that the top gate dielectric layer 50 can be made of the same material as the bottom gate dielectric layer 20 , and both are used to cover the underlying structure, so the process used for the top gate dielectric layer 50 can also be the same as that of the bottom gate dielectric layer 20 .

[0125] It should be noted that after the various structures of the radiation-resistant semiconductor device are formed, the radiation-resistant semiconductor device needs to be annealed to restore the crystal structure and eliminate defects.

[0126] In some embodiments, step 300 may also include: forming a bottom gate dielectric layer 20 having a first field oxide region 31 on the substrate 10 and the bottom gate layer 30 , wherein the first field oxide region 31 is located above the bottom gate layer 30 and below the drift region 43 .

[0127] The thickness of the first field oxide region 31 is thicker than that of other regions in the bottom gate layer 30. Therefore, the first field oxide region 31 can weaken the surface electric field formed by the bottom gate layer 30 in the drift region 43, which is beneficial to improving the breakdown voltage of the device.

[0128] In some embodiments, the specific process of forming the bottom gate dielectric layer 20 having the first field oxidation region 31 on the substrate 10 and the bottom gate layer 30 may be: forming a bottom gate dielectric layer 20 having a second thickness on the substrate 10 and the bottom gate layer 30; defining a target portion in the bottom gate dielectric layer 20, the target portion being located above the bottom gate layer 30 and below the drift region 43; etching the portion of the bottom gate dielectric layer 20 except the target portion so that the etched portion retains the third thickness, and the target portion forms the first field oxidation region 31.

[0129] It should be noted that the second thickness is the desired thickness of the first field oxidation region 31 , and the third thickness is the desired thickness of the bottom gate dielectric layer 20 excluding the first field oxidation region 31 .

[0130] In this embodiment, before etching the bottom gate dielectric layer 20 , a mask layer may be formed on the bottom gate dielectric layer 20 . The mask layer has a blank area that exposes the bottom gate dielectric layer 20 to define a target portion.

[0131] In some embodiments, after step 400 , the method further includes forming an inversion region 46 in the drift region 43 , where the conductivity type of the inversion region 46 is opposite to that of the drift region 43 .

[0132] In this embodiment, the inversion region 46 can effectively deplete the carriers in the drift region 43 , thereby more effectively withstanding the voltage and increasing the breakdown voltage.

[0133] In some embodiments, the specific process for forming the inversion region 46 in the drift region 43 may include: sequentially implanting inversion ions into the drift region 43 using an ion implantation process, where the conductivity type of the inversion ions is opposite to that of the drift region 43, and then annealing the radiation-resistant semiconductor device. The energy can be controlled to control the ions' arrival at the desired location, and the dose can be controlled to ensure that the implanted inversion region has a doping type opposite to that of the drift region.

[0134] In other embodiments, to prevent the inverse ion implantation from remaining in the upper layer of the drift region 43 , the same type of ions may be implanted in the upper layer of the drift region 43 , and the conductivity type of the same type of ions is the same as that of the drift region 43 .

[0135] As an example, the drift region 43 has N-type conductivity. First, P-type conductivity is injected into the drift region 43 to convert a portion of the region above the drift region 43 (e.g., the upper two-thirds of the drift region 43) to P-type conductivity. Then, N-type conductivity is injected into the drift region 43 to convert a portion of the region above the drift region 43 with P-type conductivity (e.g., the upper one-third of the drift region 43) to N-type conductivity. As a result, the vertical conductivity distribution of the drift region 43 is NPN. The middle portion with P-type conductivity serves as the inversion region 46.

[0136] In some embodiments, annealing may be performed using a rapid thermal annealing (RTA) process or an annealing process, which allows the implanted ions to further diffuse and distribute more uniformly and stably.

[0137] In some embodiments, step 500 may further include: forming a top gate dielectric layer 50 having a second field oxide region 51 on the epitaxial layer 40 , where the second field oxide region 51 is located above the drift region 43 and below the top gate layer 60 .

[0138] In this embodiment, a second field oxidation region 51 is provided between the top gate layer 60 and the drift region 43 . The second field oxidation region 51 weakens the electric field formed by the top gate layer 60 on the upper surface of the drift region 43 , which is beneficial to improving the breakdown voltage of the device.

[0139] It should be noted that the specific formation method of the second field oxidation region 51 can refer to the formation method of the first field oxidation region 31 described above, and will not be further described in this embodiment.

[0140] In step 600, the process for forming the top gate layer 60 can refer to the process for forming the bottom gate layer 30 in step 200. The bottom gate layer 30 and the top gate layer 60 are symmetrically distributed on the upper and lower sides of the body region and the drift region, and can be made of the same material and use the same process, which will not be further described in this embodiment.

[0141] An embodiment of the present application further provides a circuit including the aforementioned radiation-resistant semiconductor device. The specific structure and principle of the radiation-resistant semiconductor device can be referred to the aforementioned embodiments, and will not be described in detail in this embodiment.

[0142] In some embodiments, radiation-resistant semiconductor devices can be used as switches in circuits to form switching circuits or switching circuits, etc. The structures of switching power supply circuits and switching circuits are already mature technologies, and will not be described in detail in this embodiment.

[0143] One embodiment of the present application further provides an electrostatic protection circuit, comprising the aforementioned radiation-resistant semiconductor device, wherein the drain of the radiation-resistant semiconductor device is coupled to an electrostatic protection node, the source of the radiation-resistant semiconductor device is coupled to a ground node, and the gate and source of the radiation-resistant semiconductor device are short-circuited. The specific structure and principle of the radiation-resistant semiconductor device can be referred to in the aforementioned embodiments and will not be further described in this embodiment.

[0144] In this embodiment, the gate of the radiation-hardened semiconductor device is grounded GGNMOS, which serves as an electrostatic protection device. When an electrostatic current is generated at the electrostatic protection node, the radiation-hardened semiconductor device can discharge the electrostatic current.

[0145] An embodiment of the present application further provides a chip including the aforementioned radiation-resistant semiconductor device. The specific structure and principle of the radiation-resistant semiconductor device can be referred to the aforementioned embodiments, and will not be described in detail in this embodiment.

[0146] In some embodiments, the chip may be a power chip, which may be configured with a switching power circuit or a switching circuit, etc. The switching power circuit and the switching tube in the switching circuit adopt the aforementioned radiation-resistant semiconductor device.

[0147] An embodiment of the present application further provides an electronic device, comprising the aforementioned radiation-resistant semiconductor device. The structure and principle of the radiation-resistant semiconductor device can be referred to above, and this embodiment will not be described in detail here.

[0148] In some embodiments, the electronic device may be a system-level application such as a power supply, a power management unit, a mobile radio frequency device, a smart meter, an IoT meter, a converged terminal, a feeder unit, a fault indicator, etc. Multiple radiation-hardened semiconductor devices may be used in the electronic device.

[0149] Taking a mobile radio frequency device as an example, a circuit for amplifying communication signals is added to the mobile radio frequency device. The amplifier circuit may include amplifier stages having a driver stage and an amplifier output stage. Each amplifier stage includes one or more transistors configured in various ways to amplify the communication signal. The transistors may be the radiation-hardened semiconductor devices proposed in this application.

[0150] According to the circuit, chip and electronic device of the present application, the reliability is improved by adopting radiation-resistant semiconductor devices with strong voltage resistance.

[0151] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A radiation-resistant dynamic threshold modulation semiconductor device, characterized in that: The invention comprises a substrate, a bottom gate layer, a bottom gate dielectric layer, an epitaxial layer, a top gate dielectric layer and a top gate layer which are stacked in sequence, wherein the epitaxial layer comprises a source region, a body region, a drift region and a drain region which are arranged in sequence in the lateral direction, the bottom gate layer is located directly below the body region and the drift region, the top gate layer is located directly above the body region and the drift region, and the bottom gate layer and the top gate layer form electric fields in opposite directions in the body region and the drift region.

2. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The thickness of the top gate dielectric layer is greater than the thickness of the bottom gate dielectric layer.

3. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The bottom gate layer and the top gate layer are symmetrically distributed on upper and lower sides of the body region and the drift region.

4. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The bottom gate layer and the top gate layer are polysilicon electrodes or metal electrodes.

5. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The bottom gate dielectric layer and the top gate dielectric layer are made of silicon oxide or high-K oxide.

6. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The substrate is a single crystal silicon substrate, a silicon doped substrate or an SOI substrate.

7. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: A spacer region is provided between the body region and the drift region.

8. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The top surface of the body region and the top surface of the drift region are at a first height, the top surface of the source region and the top surface of the drain region are at a second height, and the first height is lower than the second height.

9. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The bottom gate dielectric layer forms a field oxide region above the bottom gate layer, the thickness of the field oxide region is greater than the thickness of other regions of the bottom gate dielectric layer, and at least a portion of the drift region is located directly above the field oxide region.

10. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: The bottom gate dielectric layer forms a first field oxidation region above the bottom gate layer, the thickness of the first field oxidation region is greater than the thickness of other regions of the bottom gate dielectric layer, at least a portion of the drift region is located directly above the first field oxidation region, and the top gate dielectric layer forms a second field oxidation region above at least a portion of the drift region, the thickness of the second field oxidation region is greater than the thickness of other regions of the top gate dielectric layer.

11. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 10, characterized in that: The first field oxidation region and the second field oxidation region are symmetrically distributed on upper and lower sides of the body region and the drift region.

12. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 10, characterized in that: The thickness of the second field oxide region is smaller than the thickness of the first field oxide region.

13. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 1, characterized in that: An inversion zone is formed in the drift region, and the conductivity type of the inversion zone is opposite to the conductivity type of the drift region.

14. The radiation-resistant dynamic threshold modulation semiconductor device according to claim 9, characterized in that: An inversion zone is formed in the drift region, and the conductivity type of the inversion zone is opposite to the conductivity type of the drift region.

15. A process for a radiation-resistant dynamic threshold modulation semiconductor device, characterized in that: include: providing a substrate; forming a bottom gate layer on the substrate; forming a bottom gate dielectric layer on the substrate and the bottom gate layer; forming an epitaxial layer on the bottom gate dielectric layer, wherein the epitaxial layer comprises a source region, a body region, a drift region and a drain region sequentially arranged in a lateral direction, and the bottom gate layer is located directly below the body region and the drift region; forming a top gate dielectric layer on the epitaxial layer; A top gate layer is formed on the top gate dielectric layer, and the top gate layer is located directly above the body region and the drift region.

16. The process according to claim 15, characterized in that A bottom gate layer is formed, comprising: Depositing polysilicon or metal material on the substrate by sputtering process to form a gate electrode film; The gate electrode film is subjected to photolithography to form the bottom gate layer.

17. The process according to claim 15, characterized in that Forming a bottom gate dielectric layer or a top gate dielectric layer, comprising: Depositing silicon dioxide by plasma enhanced chemical vapor deposition to form a bottom gate dielectric layer or a top gate dielectric layer; or, A high-K oxide is deposited on the substrate and the bottom gate layer by an atomic layer deposition process to form a bottom gate dielectric layer or a top gate dielectric layer.

18. The process according to claim 17, characterized in that Forming an epitaxial layer, comprising: growing a single crystal silicon layer on the bottom gate dielectric layer; A source region, a body region, a drift region and a drain region are defined in the single crystal silicon layer, and ion implantation is performed.

19. The process according to claim 18, characterized in that The step of defining a source region, a body region, a drift region and a drain region in the single crystal silicon layer and performing ion implantation comprises: A source region and a drain region are defined at two lateral ends of the single crystal silicon layer; Performing ion implantation into the source region and the drain region: A body region and a drift region are defined in the middle of the single crystal silicon layer; Etching the body region and the drift region to remove target thickness; Ion implantation is performed on the etched body region and the drift region.

20. The process according to claim 15, characterized in that Forming a bottom gate dielectric layer, comprising: growing a silicon dioxide layer on the substrate; A silicon nitride layer is grown on the bottom gate layer, and the silicon dioxide layer and the silicon nitride layer form a bottom gate dielectric layer.

21. The process according to claim 20, characterized in that Forming an epitaxial layer, comprising: Growing a single crystal silicon layer on the bottom gate dielectric layer, wherein the single crystal silicon layer is located at a protruding portion above the bottom gate layer; Performing mechanical chemical polishing on the raised portion of the single crystal silicon layer to expose the silicon nitride layer; Performing ion implantation on the retained single crystal silicon layer to form a source region and a drain region; Etching the silicon nitride layer and retaining the silicon nitride layer having a first thickness; growing an active region on the silicon nitride layer; Ion implantation is performed on the active region to form a body region and a drift region.

22. The process according to claim 21, characterized in that The height of the active region grown on the silicon nitride is lower than that of the source region and the drain region.

23. The process according to any one of claims 15 to 22, characterized in that forming a bottom gate dielectric layer, further comprising: A bottom gate dielectric layer having a first field oxide region is formed on the substrate and the bottom gate layer, wherein the first field oxide region is located above the bottom gate layer and directly below the drift region.

24. The process according to claim 23, characterized in that The step of forming a bottom gate dielectric layer having a first field oxide region on the substrate and the bottom gate layer comprises: forming a bottom gate dielectric layer having a second thickness on the substrate and the bottom gate layer; A target portion is defined in the bottom gate dielectric layer, wherein the target portion is located above the bottom gate layer and directly below the drift region; The bottom gate dielectric layer is etched except for the target portion so that the etched portion retains a third thickness, and the target portion forms a first field oxidation region.

25. The process according to claim 23, characterized in that forming a top gate dielectric layer, further comprising: A top gate dielectric layer having a second field oxidation region is formed on the epitaxial layer, wherein the second field oxidation region is located above the drift region and directly below the top gate layer.

26. The process according to any one of claims 15 to 22, characterized in that After forming the epitaxial layer, it also includes: An inversion region is formed in the drift region, and the conductivity type of the inversion region is opposite to the conductivity type of the drift region.

27. The process according to claim 26, characterized in that The inversion zone is formed, including: Using an ion implantation process to sequentially implant counter-type ions and homo-type ions into the drift region, wherein the conductivity type of the counter-type ions is opposite to that of the drift region, and the conductivity type of the homo-type ions is the same as that of the drift region; Annealing of radiation-resistant dynamic threshold modulation semiconductor devices.

28. A circuit, characterized in that: The invention comprises a radiation-resistant dynamic threshold modulation semiconductor device according to any one of claims 1 to 14.

29. An electrostatic protection circuit, characterized in that: It comprises a radiation-resistant dynamic threshold modulation semiconductor device according to any one of claims 1-14, wherein the drain of the radiation-resistant dynamic threshold modulation semiconductor device is coupled to an electrostatic protection node, the source of the radiation-resistant dynamic threshold modulation semiconductor device is coupled to a ground node, and the gate and source of the radiation-resistant dynamic threshold modulation semiconductor device are short-circuited.

30. A chip, characterized in that: The invention comprises a radiation-resistant dynamic threshold modulation semiconductor device according to any one of claims 1 to 14.

31. An electronic device, characterized in that: The electronic device comprises the radiation-resistant dynamic threshold modulation semiconductor device according to any one of claims 1-14.

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