Resistive random-access memory and preparation method for resistive random-access memory

Abstract

Disclosed in the present application are a resistive random-access memory and a preparation method for a resistive random-access memory. The resistive random-access memory comprises: a bottom electrode layer (1) and a top electrode layer (2); a resistive layer (3), which is provided between the bottom electrode layer (1) and the top electrode layer (2); and a suppression layer (4), wherein the suppression layer (4) is provided in the resistive layer (3), and the suppression layer (4) is used for suppressing ion diffusion in the resistive layer (3). By using the resistive random-access memory, ion diffusion in a resistive layer can be effectively suppressed, so that the resistive layer having high uniformity and component controllability is effectively ensured, thereby improving the performance and stability of the resistive random-access memory.

Description

Resistive random access memory and method for preparing the same

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed on November 24, 2023, with application number 202311588542.0 and titled “Resistive Memory and Method for Preparing Resistive Memory”. Technical Field

[0003] The embodiments of the present disclosure relate to the technical field of resistive random access memory, and in particular to a resistive random access memory and a method for preparing the resistive random access memory. Background Art

[0004] Existing resistive random access memories (RRAMs) include oxygen vacancy RRAMs. In RRAMs, oxygen ions migrate within the RRAM layer under the influence of an electric field, ultimately forming a conductive channel (filament) composed of oxygen vacancies. To better control the performance of RRAMs, it is necessary to form a RRAM with uniformity and composition modulation.

[0005] In the related art, the resistive switching layer of the existing resistive random access memory is directly formed by physical vapor deposition (PVD) of metal oxides and complex thin film combinations with different component ratios, wherein the metal oxides are HfOx (hafnium oxide), TaOx (tantalum oxide) and TiOx (titanium oxide), and the complex thin film combinations are HfOx1, HfOx2 and HfOx3. In addition, during the deposition process, the thickness and composition of the resistive switching layer can be adjusted by parameters, or the uniformity of the resistive switching layer can be improved by forming a buffer layer on the bottom electrode layer of the resistive random access memory, or a barrier layer can be formed on the resistive random access layer by ALD (atomic layer deposition) to block ion diffusion. However, the above methods cannot effectively block the diffusion of ions in the resistive random access layer, resulting in the resistive random access layer not having high uniformity and composition controllability, thereby reducing the performance and stability of the resistive random access memory.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the embodiments of the present disclosure is to provide a resistive random access memory (RRAM) that effectively suppresses ion diffusion within the RRAM layer, thereby effectively ensuring high uniformity and controllable composition of the RRAM layer, thereby improving the performance and stability of the RRAM.

[0008] A second objective of the embodiments of the present disclosure is to provide a method for preparing a resistive random access memory.

[0009] In order to solve the above problems, an embodiment of the first aspect of the present disclosure provides a resistive memory, including: a bottom electrode layer and a top electrode layer; a resistive layer, wherein the resistive layer is arranged between the bottom electrode layer and the top electrode layer; and an inhibition layer, wherein the inhibition layer is arranged in the resistive layer, and the inhibition layer is used to inhibit ion diffusion in the resistive layer.

[0010] According to the resistive random access memory of the embodiment of the present disclosure, an inhibition layer is arranged in the resistive random access layer. The inhibition layer limits the movement of ions by forming an electric potential barrier in the resistive random access layer. Therefore, in the present application, by arranging the inhibition layer in the resistive random access layer, the inhibition layer can effectively inhibit the diffusion of ions in the resistive random access layer, thereby improving the off-state resistance of the resistive random access memory and effectively ensuring that the resistive random access layer has high uniformity and controllable components, thereby improving the performance and stability of the resistive random access memory.

[0011] In some embodiments, the inhibition layer includes a saturated oxide layer of the first metal or a nitride layer of the first metal.

[0012] In some embodiments, the first metal is Al, Mg, Ti, Ni, or Si.

[0013] In some embodiments, the resistive layer includes a first oxide layer and a second oxide layer, and the inhibition layer is disposed between the first oxide layer and the second oxide layer.

[0014] In some embodiments, the first oxide layer includes an unsaturated oxide layer of the second metal.

[0015] In some embodiments, the second oxide layer comprises a saturated oxide layer of a second metal.

[0016] In some embodiments, the first oxide layer is disposed on the bottom electrode layer, and the top electrode layer is disposed on a side of the second oxide layer away from the inhibition layer.

[0017] In some embodiments, the thickness of the inhibitory layer is less than 2 nm.

[0018] In some embodiments, the thickness of the first oxide layer is in the range of 10 nm < h2 < 20 nm, the thickness of the second oxide layer is in the range of 1 nm < h1 < 5 nm, and the thickness of the inhibition layer is less than 2 nm.

[0019] In some embodiments, the resistive layer includes a third oxide layer, a fourth oxide layer, and a fifth oxide layer, and the inhibition layer includes a first inhibition layer and a second inhibition layer; wherein the first inhibition layer is arranged between the third oxide layer and the fourth oxide layer, and the second inhibition layer is arranged between the fourth oxide layer and the fifth oxide layer.

[0020] In some embodiments, the third oxide layer includes an unsaturated oxide layer of the second metal, and the fourth oxide layer includes an unsaturated oxide layer of the second metal.

[0021] In some embodiments, the molecular saturation of the fourth oxide layer is greater than the molecular saturation of the third oxide layer.

[0022] In some embodiments, the fifth oxide layer comprises a saturated oxide layer of the second metal.

[0023] In some embodiments, the third oxide layer is disposed on the bottom electrode layer, and the top electrode layer is disposed on a side of the fifth oxide layer away from the second inhibition layer.

[0024] In some embodiments, the thickness of the first inhibiting layer is less than 2 nm, and the thickness of the second inhibiting layer is less than 2 nm.

[0025] In some embodiments, the first metal is Al, the thickness range of the third oxide layer is 5nm<h3<20nm, the thickness range of the fourth oxide layer is 5nm<h4<15nm, the thickness range of the fifth oxide layer is 1nm<h5<5nm, the thickness of the first inhibition layer is less than 2nm, and the thickness of the second inhibition layer is less than 2nm.

[0026] In some embodiments, the first metal is Mg, the thickness range of the third oxide layer is 5nm<h3<20nm, the thickness range of the fourth oxide layer is 5nm<h4<15nm, the thickness range of the fifth oxide layer is 1nm<h5<5nm, the thickness of the first inhibition layer is less than 1nm, and the thickness of the second inhibition layer is less than 1nm.

[0027] In some embodiments, the inhibitory layer has an insulating band gap greater than an insulating band gap of the saturated oxide layer.

[0028] In some embodiments, the metal activity of the inhibition layer is greater than the metal activity of the saturated oxide layer.

[0029] In some embodiments, the second metal is Hf or Ta.

[0030] In some embodiments, the second metal is Ta, and the molecular saturation range of the unsaturated oxide layer is 1<Ω<1.7.

[0031] In some embodiments, the second metal is Ta, and the molecular saturation of the saturated oxide layer is 2.5.

[0032] A second aspect of the present disclosure provides a method for preparing a resistive memory, comprising: preparing a bottom electrode layer; preparing a resistive layer on the bottom electrode layer, and preparing an inhibition layer within the resistive layer, wherein the inhibition layer is used to inhibit ion diffusion within the resistive layer; and preparing a top electrode layer on the resistive layer.

[0033] According to the method for preparing a resistive random access memory in an embodiment of the present disclosure, a resistive random access layer is prepared on a bottom electrode layer and an inhibition layer is prepared within the resistive random access layer. The inhibition layer limits ion movement by forming an electric potential barrier within the resistive random access layer. Therefore, in the present application, by arranging the inhibition layer within the resistive random access layer, the inhibition layer effectively inhibits ion diffusion within the resistive random access layer, thereby improving the off-state resistance of the resistive random access memory and effectively ensuring that the resistive random access layer has high uniformity and controllable components, thereby improving the performance and stability of the resistive random access memory.

[0034] In some embodiments, the resistive layer includes a first oxide layer and a second oxide layer, the resistive layer is prepared on the bottom electrode layer, and the inhibition layer is prepared within the resistive layer, including: preparing the first oxide layer on the bottom electrode layer; preparing the inhibition layer on the first oxide layer; and preparing the second oxide layer on the inhibition layer.

[0035] In some embodiments, the resistive layer includes a third oxide layer, a fourth oxide layer and a fifth oxide layer, the inhibition layer includes a first inhibition layer and a second inhibition layer, the resistive layer is prepared on the bottom electrode layer, and the inhibition layer is prepared within the resistive layer, including: preparing a third oxide layer on the bottom electrode layer; preparing the first inhibition layer on the third oxide layer; preparing a fourth oxide layer on the first inhibition layer; preparing a second inhibition layer on the fourth oxide layer; and preparing a fifth oxide layer on the second inhibition layer.

[0036] In some embodiments, forming the resistive switching layer on the bottom electrode layer includes: forming the resistive switching layer on the bottom electrode layer by physical vapor deposition.

[0037] In some embodiments, preparing the inhibition layer in the resistive layer includes: preparing the inhibition layer in the resistive layer by physical vapor deposition; or preparing the inhibition layer in the resistive layer by atomic layer deposition.

[0038] Additional aspects and advantages of the embodiments of the present disclosure will be given in part in the description below and in part will become apparent from the description below or will be learned through practice of the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the embodiments of the present disclosure will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0040] FIG1 is a schematic diagram of the structure of an existing resistive random access memory;

[0041] FIG2 is a schematic structural diagram of a resistive random access memory according to an embodiment of the present disclosure;

[0042] FIG3 is a flow chart of a method for preparing a resistive random access memory according to an embodiment of the present disclosure.

[0043] Reference numerals:

[0044] Resistive random access memory 100;

[0045] Bottom electrode layer 1; top electrode layer 2; resistive layer 3; inhibition layer 4; first oxide layer 31; second oxide layer 32. DETAILED DESCRIPTION

[0046] Embodiments of the present disclosure will be described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present disclosure will be described in detail below.

[0047] Current resistive random-access memory (ReRAM) is mainly divided into CBRAM (Conductive-Bridge Random Access Memory) and OxRAM (Oxygen-vacancy Random Access Memory), namely oxygen vacancy resistive random access memory. Its basic structure is shown in Figure 1. The resistive random-access memory includes a top electrode layer TE, a resistive switching layer SL and a bottom electrode layer BE.

[0048] In the related art, the resistive switching layer of existing resistive random access memories is directly formed by physical vapor deposition (PVD) to form a combination of metal oxides and complex thin films with different composition ratios. During the deposition process, the thickness and composition of the resistive switching layer can be adjusted through parameters. Alternatively, a buffer layer is formed on the bottom electrode layer of the resistive random access memory to improve the uniformity of the resistive switching layer, or a barrier layer is formed on the resistive random access layer through ALD (atomic layer deposition) to block ion diffusion. However, these methods cannot effectively block ion diffusion in the resistive random access layer, resulting in the resistive random access layer lacking high uniformity and composition controllability, which in turn reduces the performance and stability of the resistive random access memory.

[0049] In order to solve the above problems, the first embodiment of the present disclosure provides a resistive random access memory, which can effectively suppress ion diffusion within the resistive random access layer, thereby effectively ensuring that the resistive random access layer has high uniformity and component controllability, thereby improving the performance and stability of the resistive random access memory.

[0050] The resistive memory 100 according to an embodiment of the present disclosure will be described below with reference to FIG2 . As shown in FIG2 , the resistive memory 100 includes: a bottom electrode layer 1 , a top electrode layer 2 , a resistive layer 3 , and an inhibitory layer 4 .

[0051] The resistive layer 3 is disposed between the bottom electrode layer 1 and the top electrode layer 2 ; the inhibition layer 4 is disposed in the resistive layer 3 , and is used to inhibit ion diffusion in the resistive layer 3 .

[0052] Specifically, the existing resistive random access memory cannot effectively block the diffusion of ions in the resistive random access layer 3, resulting in the resistive random access layer 3 not having high uniformity and component controllability, thereby reducing the performance and stability of the resistive random access memory. In order to solve this problem, the present application suppresses the diffusion of ions in the resistive random access layer 3 by setting an inhibition layer 4 in the resistive random access layer 3. That is, when the oxygen ions in the resistive random access layer 3 migrate under the action of the electric field, a conductive channel composed of oxygen vacancies is formed. In the present application, the inhibition layer 4 is set in the resistive random access layer 3, wherein the inhibition layer 4 acts as an ultra-thin barrier layer to provide an inhibitory effect on ion diffusion, that is, the inhibition layer 4 forms an electric barrier in the resistive random access layer 3 to limit the movement of ions. For example, if the resistive random access memory is an oxygen vacancy resistive random access memory, an inhibition layer 4 is constructed in the oxygen vacancy resistive random access memory to control the ion exchange of oxygen-deficient metal oxides and saturated metal oxides in the oxygen vacancy resistive random access memory, so as to suppress the ion diffusion of the resistive random access layer 3 in the oxygen vacancy resistive random access memory through the inhibition layer 4. Therefore, in this application, by disposing the inhibition layer 4 within the resistive switching layer 3, the inhibition layer 4 effectively inhibits the ion diffusion within the resistive switching layer 3, thereby improving the off-state resistance of the resistive switching memory, and effectively ensuring that the resistive switching layer 3 has high uniformity and component controllability, thereby improving the durability and retention performance and stability of the resistive switching memory, and the performance controllability of the resistive switching memory is stronger, which makes the production cost of the resistive switching memory lower, more convenient to use, and safer. In addition, the resistive switching memory 100 in this application can be CBRAM or oxygen vacancy resistive switching memory, without limitation.

[0053] According to the resistive random access memory 100 of the present disclosure, the inhibition layer 4 is disposed within the resistive random access layer 3. The inhibition layer 4 forms an electric potential barrier within the resistive random access layer 3 to restrict ion movement. Therefore, in the present application, by disposing the inhibition layer 4 within the resistive random access layer 3, the inhibition layer 4 effectively inhibits ion diffusion within the resistive random access layer 3, thereby improving the off-state resistance of the resistive random access memory and effectively ensuring that the resistive random access layer 3 has high uniformity and controllable composition, thereby improving the performance and stability of the resistive random access memory.

[0054] In some embodiments, the inhibition layer 4 includes a saturated oxide layer of the first metal or a nitride layer of the first metal. Because the saturated oxide layer of the first metal or the nitride layer of the first metal in the inhibition layer 4 has high stability, the inhibition layer 4 is disposed within the resistive switching layer 3 to effectively block ion diffusion within the resistive switching layer 3, thereby enhancing the inhibitory effect on ion diffusion within the resistive switching layer 3.

[0055] In some embodiments, the first metal is Al (aluminum), Mg (magnesium), Ti (titanium), Ni (nickel) or Si (silicon), and the inhibition layer 4 includes a saturated oxide layer of Al, Mg, Ti, Ni or Si, or a nitride layer of Al, Mg, Ti, Ni or Si, so as to effectively block the diffusion of ions in the resistive layer 3 through the inhibition layer 4, thereby enhancing the inhibition effect on the diffusion of ions in the resistive layer 3.

[0056] In an embodiment, the suppression layer 4 includes TiO 2 (titanium dioxide), HfO 2 (hafnium dioxide), AlN (aluminum nitride), SiN (silicon nitride), Al 2 O 3 (aluminum oxide), and MgO (magnesium oxide).

[0057] In some embodiments, as shown in FIG. 2 , the resistive layer 3 includes a first oxide layer 31 and a second oxide layer 32 , and the inhibition layer 4 is disposed between the first oxide layer 31 and the second oxide layer 32 .

[0058] Specifically, since the first oxide layer 31 of the resistive layer 3 is grown by PVD DC (direct current) or Impulse growth, the growth rate of the first oxide layer 31 is relatively fast and the oxygen saturation is relatively low. If the first oxide layer 31 is covered on the inhibition layer 4 or the second oxide layer 32, it will cause significant damage to the interface of the inhibition layer 4 or the second oxide layer 32 and destroy the saturation of the inhibition layer 4 or the second oxide layer 32. Therefore, as shown in Figure 2, the inhibition layer 4 is disposed between the first oxide layer 31 and the second oxide layer 32. In addition, since ions in the resistive layer 3 migrate from the second oxide layer 32 to the first oxide layer 31, the inhibition layer 4 is disposed between the first oxide layer 31 and the second oxide layer 32. The inhibition layer 4 acts as an ultra-thin barrier layer to inhibit ion diffusion, that is, the inhibition layer 4 inhibits the migration of ions from the second oxide layer 32 to the first oxide layer 31. Therefore, in the present application, the inhibition layer 4 is disposed between the first oxide layer 31 and the second oxide layer 32 , so that the inhibition layer 4 can effectively inhibit the ion diffusion in the resistive switching layer 3 , thereby improving the off-state resistance of the resistive switching memory.

[0059] In some embodiments, the first oxide layer 31 includes an unsaturated oxide layer of the second metal. For example, the unsaturated oxide layer of the second metal is TaO 1.0-1.7 .

[0060] In some embodiments, the second oxide layer 32 includes a saturated oxide layer of the second metal. For example, the saturated oxide layer of the second metal is TaO. 2.5 .

[0061] In some embodiments, the first oxide layer 31 is disposed on the bottom electrode layer 1 , and the top electrode layer 2 is disposed on the side of the second oxide layer 32 away from the inhibition layer 4 . This structure can help the resistive random access memory achieve better switching ratio, stability, and controllability.

[0062] In some embodiments, the thickness of the first oxide layer 31 is in the range of 10 nm < h2 < 20 nm, wherein the thickness of the first oxide layer 31 is any value between (10 nm, 20 nm), and the thickness of the first oxide layer 31 can be 11 nm, 13 nm, 15 nm, 17 nm, or 19 nm. The thickness of the first oxide layer 31 is within this range, which can ensure that the length of the conductive filament is maintained within a preferred range, so that the resistive random access memory has a better switching ratio and durability, and can also improve the stability and controllability of the resistive random access memory. The thickness of the second oxide layer 32 is in the range of 1 nm < h1 < 5 nm, and the thickness of the second oxide layer 32 can be in the range of 2 nm, 3 nm, or 4 nm. The thickness of the second oxide layer 32 is within this range, which can ensure that the length of the conductive filament is maintained within a preferred range, so that the resistive random access memory has a better switching ratio and durability, and can also improve the stability and controllability of the resistive random access memory. Since the inhibition layer 4 is an active metal oxide, its oxygen ion dissociation ability is significantly weaker than that of the second oxide layer 32. Therefore, the thickness of the inhibition layer 4 needs to be less than 2 nm. The thickness of the inhibition layer 4 can be 1 nm, 0.1 nm, 0.3 nm, 1.5 nm, or 1.9 nm, etc., without limitation. The preferred thickness of the inhibition layer 4 is within the range of (0.3 nm, 1 nm).

[0063] In some embodiments, the resistive layer 3 includes a third oxide layer, a fourth oxide layer, and a fifth oxide layer, and the inhibition layer 4 includes a first inhibition layer and a second inhibition layer; wherein the first inhibition layer is arranged between the third oxide layer and the fourth oxide layer, and the second inhibition layer is arranged between the fourth oxide layer and the fifth oxide layer.

[0064] Specifically, the existing resistive random access memory cannot effectively block the diffusion of ions in the resistive random access layer 3, resulting in the resistive random access layer 3 not having high uniformity and composition controllability, thereby reducing the performance and stability of the resistive random access memory. In order to solve this problem, the present application suppresses the diffusion of ions in the resistive random access layer 3 by setting a multi-layer inhibition layer 4 in the resistive random access layer 3. That is, since the ions in the resistive random access layer 3 migrate from the third oxide layer to the fourth oxide layer, the first inhibition layer is set between the third oxide layer and the fourth oxide layer, and the first inhibition layer acts as an ultra-thin barrier layer to provide an inhibitory effect on ion diffusion, that is, the first inhibition layer is used to inhibit the migration of ions from the third oxide layer to the fourth oxide layer, and the second inhibition layer is set between the fourth oxide layer and the fifth oxide layer, and the second inhibition layer acts as an ultra-thin barrier layer to provide an inhibitory effect on ion diffusion, that is, the second inhibition layer is used to inhibit the migration of ions from the fourth oxide layer to the fifth oxide layer. Therefore, in the present application, by setting two layers of inhibition layers 4 in the resistive random access layer 3, the ion diffusion in the resistive random access layer 3 can be effectively suppressed by the two layers of inhibition layers 4, thereby improving the off-state resistance of the resistive random access memory.

[0065] In some embodiments, the third oxide layer includes an unsaturated oxide layer of the second metal, and the fourth oxide layer includes an unsaturated oxide layer of the second metal. For example, the unsaturated oxide layer of the second metal is TaO 1.0-1.7 .

[0066] In some embodiments, the molecular saturation of the fourth oxide layer is greater than that of the third oxide layer, thereby improving the storage performance of the resistive random access memory.

[0067] In some embodiments, the fifth oxide layer includes a saturated oxide layer of the second metal. For example, the saturated oxide layer of the second metal is TaO 2.5 .

[0068] In some embodiments, the third oxide layer is disposed on the bottom electrode layer 1, and the top electrode layer 2 is disposed on the side of the fifth oxide layer away from the second inhibition layer. This structure can help the resistive random access memory achieve better switching ratio, stability and controllability.

[0069] In some embodiments, the first metal is Al, and the thickness of the third oxide layer is in the range of 5nm<h3<20nm, wherein the thickness of the third oxide layer is any value between (5nm, 20nm), and the thickness of the third oxide layer can be 6nm, 10nm, 13nm, 15nm, 17nm, or 19nm. The thickness of the third oxide layer within this range can ensure that the length of the conductive filament is maintained within a preferred range, so that the resistive random access memory has a better switching ratio and durability, and can also improve the stability and controllability of the resistive random access memory. The thickness of the fourth oxide layer is in the range of 5nm<h4<15nm, wherein the thickness of the fourth oxide layer is any value between (5nm, 15nm), and the thickness of the fourth oxide layer can be 6nm, 10nm, 13nm, or 14nm. The thickness of the fourth oxide layer within this range can ensure that the length of the conductive filament is maintained within a preferred range, so that the resistive random access memory has a better switching ratio and durability. The thickness range of the fifth oxide layer is 1nm<h5<5nm, wherein the thickness of the fifth oxide layer is any value between (1nm, 5nm), and the thickness of the fifth oxide layer can be 1nm, 2nm, 3nm or 4nm. The thickness of the fifth oxide layer is within this range, which can ensure that the length of the conductive filament is maintained within a better range, so that the resistive random access memory has a better switching ratio and durability. The thickness of the first inhibition layer is less than 2nm, and the thickness of the second inhibition layer is less than 2nm, wherein the thickness of the first inhibition layer or the second inhibition layer can be 1nm, 0.1nm, 0.3nm, 1.5nm or 1.9nm, etc., without limitation.

[0070] In some embodiments, the first metal is Mg, the thickness range of the third oxide layer is 5nm<h3<20nm, the thickness range of the fourth oxide layer is 5nm<h4<15nm, the thickness range of the fifth oxide layer is 1nm<h5<5nm, the thickness of the first inhibition layer is less than 1nm, and the thickness of the second inhibition layer is less than 1nm, wherein the thickness of the first inhibition layer or the second inhibition layer can be 0.1nm, 0.3nm, 0.5nm or 0.9nm, etc., without limitation.

[0071] In some embodiments, the insulating bandgap of the inhibition layer 4 is greater than the insulating bandgap of the saturated oxide layer, wherein the saturated oxide layer is the fifth oxide layer. For example, the insulating bandgap of the inhibition layer 4 is greater than the insulating bandgap of Ta2O5 (tantalum pentoxide). Thus, the insulating bandgap of the inhibition layer 4 is designed to prevent ions from migrating from the fifth oxide layer through the inhibition layer 4. Alternatively, the insulating bandgap of the inhibition layer 4 is greater than the insulating bandgap of the saturated oxide layer, wherein the saturated oxide layer is the second oxide layer 32. Thus, the insulating bandgap of the inhibition layer 4 is designed to prevent ions from migrating from the second oxide layer 32 through the inhibition layer 4.

[0072] In some embodiments, the metal activity of the inhibition layer 4 is greater than that of the saturated oxide layer, where metal activity is ionization energy or electron affinity. For example, the metal activity of the inhibition layer 4 is greater than that of Ta2O5 (tantalum pentoxide), and the saturated oxide layer is the second oxide layer 32 or the fifth oxide layer. In other words, when the metal activity of the inhibition layer 4 is higher, it is more easily adsorbed and fixed on the inhibition layer 4, thereby facilitating the inhibition of ion transmission and diffusion.

[0073] In some embodiments, the second metal is Hf (hafnium) or Ta (tantalum), then the first oxide layer 31 includes an unsaturated oxide layer of Hf or Ta, the second oxide layer 32 can be a saturated oxide layer of Hf or Ta, the third oxide layer includes an unsaturated oxide layer of Hf or Ta, the fourth oxide layer includes an unsaturated oxide layer of Hf or Ta, and the fifth oxide layer can be a saturated oxide layer of Hf or Ta.

[0074] In some embodiments, the second metal is Ta, and the molecular saturation range of the unsaturated oxide layer is 1<Ω<1.7, wherein the molecular saturation of the unsaturated oxide layer is any value in the range of (1, 1.7), and the molecular saturation of the unsaturated oxide layer can be 1.1, 1.3, 1.5 or 1.6. The unsaturated oxide layer of Ta can be TaO 1.0-1.7 The first oxide layer 31 includes an unsaturated oxide layer of Ta, the fourth oxide layer includes an unsaturated oxide layer of Ta, and the third oxide layer includes an unsaturated oxide layer of Ta. The molecular saturation range of the unsaturated oxide layer of Ta is 1<Ω<1.7. Therefore, the molecular saturation of the unsaturated oxide layer is within this range, so that the stability of the first oxide layer 31, the third oxide layer or the fourth oxide layer is improved.

[0075] In some embodiments, the second metal is Ta, the molecular saturation of the saturated oxide layer is 2.5, and the saturated oxide layer of Ta can be TaO 2.5 The second oxide layer 32 is a saturated oxide layer of Ta, for example, the second oxide layer 32 is TaO 2.5 The fifth oxide layer is a saturated oxide layer of Ta, for example, the fifth oxide layer is TaO 2.5 .

[0076] A second embodiment of the present disclosure provides a method for preparing a resistive random access memory, as shown in FIG3 . The method at least includes steps S1 to S3 .

[0077] Step S1, preparing a bottom electrode layer.

[0078] Specifically, the resistive random access memory includes a substrate, and a bottom electrode layer is prepared on the substrate, such as depositing a metal or semiconductor material or an electrode material on the substrate to form a bottom electrode layer, wherein the electrode material can be a relatively inert electrode material such as TiN (titanium nitride), W (tungsten), Ru (ruthenium), Ir (iridium), Pt (platinum), etc. In addition, the bottom electrode layer can also be prepared by electron beam vacuum evaporation (E-beam evaporation), sputtering, or physical vapor deposition.

[0079] Step S2 : preparing a resistive switching layer on the bottom electrode layer, and preparing an inhibition layer in the resistive switching layer, wherein the inhibition layer is used to inhibit ion diffusion in the resistive switching layer.

[0080] Specifically, the existing resistive random access memory cannot effectively block the diffusion of ions in the resistive random access layer, resulting in the resistive random access layer not having high uniformity and component controllability, thereby reducing the performance and stability of the resistive random access memory. In order to solve this problem, the present application suppresses the diffusion of ions in the resistive random access layer by setting an inhibition layer in the resistive random access layer. That is, when the oxygen ions in the resistive random access layer migrate under the action of an electric field, a conductive channel composed of oxygen vacancies is formed. In the present application, a resistive random access layer is prepared on the bottom electrode layer and an inhibition layer is prepared in the resistive random access layer, wherein the inhibition layer acts as an ultra-thin barrier layer to provide an inhibitory effect on ion diffusion, that is, the inhibition layer forms an electric barrier in the resistive random access layer to limit the movement of ions. Exemplarily, if the resistive random access memory is an oxygen vacancy resistive random access memory, an inhibition layer is constructed in the oxygen vacancy resistive random access memory to control the ion exchange of oxygen-deficient metal oxides and saturated metal oxides in the oxygen vacancy resistive random access memory, so as to suppress the ion diffusion of the resistive random access layer in the oxygen vacancy resistive random access memory through the inhibition layer. Therefore, in this application, by setting the inhibition layer in the resistive switching layer, the inhibition layer can effectively inhibit the ion diffusion in the resistive switching layer, thereby improving the off-state resistance of the resistive switching memory, and effectively ensuring that the resistive switching layer has high uniformity and component controllability, thereby improving the performance and stability of the resistive switching memory.

[0081] Step S3: preparing a top electrode layer on the resistive switching layer.

[0082] Specifically, a top electrode layer is prepared on the resistive layer, such as depositing a gold electrode material on the resistive layer to form a top electrode layer, wherein the electrode material can be relatively inert electrode materials such as TiN (titanium nitride), W (tungsten), Ru (ruthenium), Ir (iridium), Pt (platinum), etc. In addition, a physical vapor deposition method such as a magnetron sputtering process can be used to deposit the top electrode layer on the resistive layer. When the top electrode layer is prepared, the resistive memory is completed.

[0083] According to the method for preparing a resistive random access memory (RRAM) in the disclosed embodiment, a resistive random access layer is formed on a bottom electrode layer, and an inhibitory layer is formed within the RRAM. The inhibitory layer forms an electrical barrier within the RRAM to restrict ion movement. Thus, by disposing the inhibitory layer within the RRAM, the inhibitory layer effectively inhibits ion diffusion within the RRAM, thereby increasing the off-state resistance of the RRAM and effectively ensuring high uniformity and controllable composition of the RRAM, thereby improving the performance and stability of the RRAM.

[0084] In some embodiments, as shown in Figure 2, the resistive layer includes a first oxide layer and a second oxide layer, the resistive layer is prepared on the bottom electrode layer, and the inhibition layer is prepared within the resistive layer, including: preparing the first oxide layer on the bottom electrode layer; preparing the inhibition layer on the first oxide layer; and preparing the second oxide layer on the inhibition layer.

[0085] Specifically, since the ions in the resistive layer migrate from the second oxide layer to the first oxide layer, an inhibition layer is disposed between the first oxide layer and the second oxide layer, so that the inhibition layer acts as an ultra-thin barrier layer to inhibit ion diffusion, that is, the migration of ions from the second oxide layer to the first oxide layer is inhibited by the inhibition layer. Based on this, a first oxide layer is prepared on the bottom electrode layer. For example, the first oxide layer can be prepared on the bottom electrode layer by physical vapor deposition, and then the inhibition layer is prepared on the first oxide layer, and then the second oxide layer is prepared on the inhibition layer, wherein the second oxide layer can be prepared by physical vapor deposition. Thus, the inhibition layer is disposed between the first oxide layer and the second oxide layer, so that the inhibition layer can effectively inhibit the diffusion of ions in the resistive layer, thereby improving the off-state resistance of the resistive memory.

[0086] In some embodiments, the resistive layer includes a third oxide layer, a fourth oxide layer, and a fifth oxide layer, the inhibition layer includes a first inhibition layer and a second inhibition layer, the resistive layer is prepared on the bottom electrode layer, and the inhibition layer is prepared within the resistive layer, including: preparing a third oxide layer on the bottom electrode layer; preparing a first inhibition layer on the third oxide layer; preparing a fourth oxide layer on the first inhibition layer; preparing a second inhibition layer on the fourth oxide layer; and preparing a fifth oxide layer on the second inhibition layer.

[0087] Specifically, existing resistive memory cannot effectively block the diffusion of ions in the resistive layer, which results in the resistive layer not having high uniformity and composition controllability, thereby reducing the performance and stability of the resistive memory. In order to solve this problem, the present application suppresses the diffusion of ions in the resistive layer by setting a multi-layer inhibition layer in the resistive layer. That is, since the ions in the resistive layer migrate from the third oxide layer to the fourth oxide layer, a third oxide layer is prepared on the bottom electrode layer. For example, the third oxide layer can be prepared on the bottom electrode layer by physical vapor deposition, and then a first inhibition layer is prepared on the third oxide layer, and a fourth oxide layer is prepared on the first inhibition layer. Therefore, the first inhibition layer is set between the third oxide layer and the fourth oxide layer, and the first inhibition layer is used as an ultra-thin barrier layer to provide an inhibitory effect on ion diffusion, that is, through the first inhibition layer. The layer inhibits ions from migrating from the third oxide layer to the fourth oxide layer. After the fourth oxide layer is prepared, a second inhibition layer is prepared on the fourth oxide layer, and then a fifth oxide layer is prepared on the second inhibition layer, so that the second inhibition layer is arranged between the fourth oxide layer and the fifth oxide layer. The second inhibition layer serves as an ultra-thin barrier layer to provide an inhibitory effect on ion diffusion, that is, the migration of ions from the fourth oxide layer to the fifth oxide layer is inhibited by the second inhibition layer. Therefore, in the present application, by arranging two inhibition layers in the resistive layer, the ion diffusion in the resistive layer can be effectively inhibited by the two inhibition layers, thereby improving the off-state resistance of the resistive memory.

[0088] The third oxide layer, the fourth oxide layer and the fifth oxide layer can be prepared by physical vapor deposition.

[0089] In some embodiments, when preparing a resistive switching layer on the bottom electrode layer, the resistive switching layer can be prepared on the bottom electrode layer by physical vapor deposition (PVD), that is, materials such as unsaturated oxides or saturated oxides of metals are deposited on the bottom electrode layer to form a resistive switching layer, and the resistive switching layer prepared by physical vapor deposition has better quality.

[0090] Among them, physical vapor deposition technology refers to the use of physical methods under vacuum conditions to vaporize the surface of the material source (solid or liquid) into gaseous atoms or molecules, or partially ionize it into ions, and through a low-pressure gas (or plasma) process. Physical vapor deposition is one of the main surface treatment technologies.

[0091] In some embodiments, the inhibitory layer can be formed within the resistive switching layer by physical vapor deposition (PVD), where a material such as a saturated oxide of a first metal or a nitride of the first metal is deposited within the resistive switching layer to form the resistive switching layer. Alternatively, the inhibitory layer can be formed within the resistive switching layer by atomic layer deposition (ALD). ALD is a method of depositing a material onto a substrate surface layer by layer in the form of a single atomic film. A relatively high oxygen concentration is required when forming the inhibitory layer within the resistive switching layer via ALD.

[0092] In an embodiment, the resistive switching layer and the inhibiting layer may also be grown and formed in a multi-cathode chamber, or may be grown and formed in different chambers.

[0093] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0094] Although the embodiments of the present disclosure have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations may be made to the embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A resistive random access memory, characterized in that: include: a bottom electrode layer and a top electrode layer; A resistive switching layer, wherein the resistive switching layer is disposed between the bottom electrode layer and the top electrode layer; The inhibition layer is disposed in the resistive switching layer and is used to inhibit ion diffusion in the resistive switching layer.

2. The resistive random access memory according to claim 1, characterized in that: The inhibition layer includes a saturated oxide layer of the first metal or a nitride layer of the first metal.

3. The resistive random access memory according to claim 2, characterized in that: The first metal is Al, Mg, Ti, Ni or Si.

4. The resistive random access memory according to claim 2, characterized in that: The resistive layer includes a first oxide layer and a second oxide layer, and the inhibition layer is disposed between the first oxide layer and the second oxide layer.

5. The resistive random access memory according to claim 4, characterized in that: The first oxide layer includes an unsaturated oxide layer of a second metal.

6. The resistive random access memory according to claim 4, characterized in that: The second oxide layer includes a saturated oxide layer of a second metal.

7. The resistive random access memory according to claim 4, characterized in that: The first oxide layer is disposed on the bottom electrode layer, and the top electrode layer is disposed on a side of the second oxide layer away from the inhibition layer.

8. The resistive random access memory according to any one of claims 4 to 7, characterized in that: The thickness of the inhibition layer is less than 2 nm.

9. The resistive random access memory according to any one of claims 4 to 7, characterized in that: The thickness of the first oxide layer is in the range of 10 nm < h2 < 20 nm, the thickness of the second oxide layer is in the range of 1 nm < h1 < 5 nm, and the thickness of the inhibition layer is less than 2 nm.

10. The resistive random access memory according to claim 2, characterized in that: The resistive layer includes a third oxide layer, a fourth oxide layer and a fifth oxide layer, and the inhibition layer includes a first inhibition layer and a second inhibition layer; The first inhibition layer is disposed between the third oxide layer and the fourth oxide layer, and the second inhibition layer is disposed between the fourth oxide layer and the fifth oxide layer.

11. The resistive random access memory according to claim 10, characterized in that: The third oxide layer includes an unsaturated oxide layer of the second metal, and the fourth oxide layer includes an unsaturated oxide layer of the second metal.

12. The resistive random access memory according to claim 11, characterized in that: The molecular saturation of the fourth oxide layer is greater than the molecular saturation of the third oxide layer.

13. The resistive random access memory according to claim 10, characterized in that: The fifth oxide layer includes a saturated oxide layer of the second metal.

14. The resistive random access memory according to claim 10, characterized in that: The third oxide layer is disposed on the bottom electrode layer, and the top electrode layer is disposed on a side of the fifth oxide layer away from the second inhibition layer.

15. The resistive random access memory according to any one of claims 10 to 14, characterized in that: The thickness of the first inhibition layer is less than 2 nm, and the thickness of the second inhibition layer is less than 2 nm.

16. The resistive random access memory according to any one of claims 10 to 14, characterized in that: The first metal is Al, the thickness range of the third oxide layer is 5nm<h3<20nm, the thickness range of the fourth oxide layer is 5nm<h4<15nm, the thickness range of the fifth oxide layer is 1nm<h5<5nm, the thickness of the first inhibition layer is less than 2nm, and the thickness of the second inhibition layer is less than 2nm.

17. The resistive random access memory according to any one of claims 10 to 14, characterized in that: The first metal is Mg, the thickness range of the third oxide layer is 5nm<h3<20nm, the thickness range of the fourth oxide layer is 5nm<h4<15nm, the thickness range of the fifth oxide layer is 1nm<h5<5nm, the thickness of the first inhibition layer is less than 1nm, and the thickness of the second inhibition layer is less than 1nm.

18. The resistive random access memory according to claim 6 or 13, characterized in that: The insulation band gap of the suppression layer is greater than the insulation band gap of the saturated oxide layer.

19. The resistive random access memory according to claim 6 or 13, characterized in that: The metal activity of the inhibition layer is greater than the metal activity of the saturated oxide layer.

20. The resistive random access memory according to any one of claims 5, 6, 11-13, characterized in that: The second metal is Hf or Ta.

21. The resistive random access memory according to claim 5, 11 or 12, characterized in that: The second metal is Ta, and the molecular saturation range of the unsaturated oxide layer is 1<Ω<1.

7.

22. The resistive random access memory according to claim 6 or 13, characterized in that: The second metal is Ta, and the molecular saturation of the saturated oxide layer is 2.

5.

23. A method for preparing a resistive random access memory, characterized in that: include: preparing a bottom electrode layer; Preparing a resistive switching layer on the bottom electrode layer, and preparing an inhibition layer in the resistive switching layer, wherein the inhibition layer is used to inhibit ion diffusion in the resistive switching layer; A top electrode layer is prepared on the resistive switching layer.

24. The method for preparing a resistive random access memory according to claim 23, characterized in that: The resistive switching layer includes a first oxide layer and a second oxide layer, the resistive switching layer is prepared on the bottom electrode layer, and an inhibition layer is prepared in the resistive switching layer, including: preparing a first oxide layer on the bottom electrode layer; forming the inhibition layer on the first oxide layer; A second oxide layer is formed on the inhibition layer.

25. The method for preparing a resistive random access memory according to claim 23, characterized in that: The resistive switching layer includes a third oxide layer, a fourth oxide layer and a fifth oxide layer, the inhibiting layer includes a first inhibiting layer and a second inhibiting layer, the resistive switching layer is prepared on the bottom electrode layer, and the inhibiting layer is prepared in the resistive switching layer, including: preparing a third oxide layer on the bottom electrode layer; preparing the first inhibition layer on the third oxide layer; forming a fourth oxide layer on the first inhibition layer; preparing a second inhibition layer on the fourth oxide layer; A fifth oxide layer is formed on the second inhibition layer.

26. The method for preparing a resistive random access memory according to any one of claims 23 to 25, characterized in that: Preparing a resistive switching layer on the bottom electrode layer, comprising: The resistive switching layer is prepared on the bottom electrode layer by physical vapor deposition.

27. The method for preparing a resistive random access memory according to any one of claims 23 to 25, characterized in that: Preparing an inhibition layer in the resistive switching layer, comprising: Prepare an inhibition layer in the resistive layer by physical vapor deposition; Alternatively, the inhibition layer is prepared in the resistive layer by atomic layer deposition.

Images