Semiconductor device and wire bonding device

Abstract

The present invention is for reducing the manufacturing cost of a semiconductor component. This semiconductor device is formed of a semiconductor chip, a wiring board, and a first bonding wire. The semiconductor chip has a first electrode. The wiring board has a second electrode. The semiconductor chip is fixed to the wiring board. The first bonding wire has a portion in contact with the first electrode, a portion in contact with the second electrode, and a portion having an arch-like shape therebetween. The first bonding wire has carbon nanotubes.

Description

Semiconductor device and wire bonding device

[0001] FIELD OF THE INVENTION One embodiment of the present invention relates to a semiconductor device, a method for mounting a semiconductor device, and a connection wiring used in a semiconductor chip.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] Electronic components such as LSI (Large Scale Integration) chips include a semiconductor chip cut out from a semiconductor substrate such as a silicon wafer, and a lead frame that secures the semiconductor chip. The semiconductor chip and the lead frame are connected by bonding wires. Low-resistance metals such as gold or alloys containing gold (gold alloys) are used for the bonding wires. Patent Document 1 discloses a semiconductor device that uses gold or gold alloys for the bonding wires.

[0004] JP 2021-158320 A

[0005] Gold and other precious metals used in bonding wires are scarce and have limited reserves, which is one of the factors that increase the manufacturing costs of semiconductor components that use large amounts of such materials.

[0006] An object of one embodiment of the present invention is to reduce the manufacturing cost of semiconductor components.An object of one embodiment of the present invention is to provide a bonding wire that replaces gold and a manufacturing method of semiconductor components using the same.An object of one embodiment of the present invention is to provide a wire bonding apparatus and a wire bonding method having a novel structure.

[0007] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure and a manufacturing method thereof. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0009] One aspect of the present invention is a semiconductor device having a semiconductor chip, a wiring substrate, and a first bonding wire. The semiconductor chip has a first electrode. The wiring substrate has a second electrode. The semiconductor chip is fixed to the wiring substrate. The first bonding wire has a portion that contacts the first electrode, a portion that contacts the second electrode, and a portion that has an arched shape between them. The first bonding wire has a carbon nanotube.

[0010] In the above, the first bonding wire preferably has a carbon nanotube processed into a twisted yarn.

[0011] In any of the above, it is preferable that the first bonding wire has a Young's modulus of 1 GPa or more and 150 GPa or less.

[0012] In any of the above, the first bonding wire preferably has a diameter of 1 μm or more and 150 μm or less.

[0013] In any of the above, the first electrode and the first bonding wire are preferably fixed by a first adhesive, and the second electrode and the first bonding wire are preferably fixed by a second adhesive, and in this case, the first adhesive and the second adhesive preferably contain gold, silver, or tin.

[0014] In any of the above, it is preferable that the device further includes a second bonding wire, a third electrode, and a fourth electrode. The third electrode is provided on the semiconductor chip. The fourth electrode is provided on the semiconductor chip or the wiring substrate. The second bonding wire has a portion that contacts the third electrode, a portion that contacts the fourth electrode, and an arch-shaped portion between them. Furthermore, it is preferable that the second bonding wire has a different length from the first bonding wire, and that the second bonding wire contains gold or a gold alloy.

[0015] In the above, the second bonding wire is preferably shorter than the first bonding wire, or the second bonding wire is preferably longer than the first bonding wire.

[0016] Another aspect of the present invention is a wire bonding apparatus having a first nozzle. The first nozzle has a first hole through which a bonding wire is fed and a second hole through which an adhesive is dispensed. In a bonding process, the wire bonding apparatus dispenses the adhesive from the second hole so as to cover the bonding wire and the electrode while the tip of the bonding wire is in contact with the electrode.

[0017] In the above, it is preferable that a plurality of second holes are provided symmetrically with respect to the first hole.

[0018] Another aspect of the present invention is a wire bonding apparatus having a first nozzle and a second nozzle. The first nozzle has a first hole through which a bonding wire is fed. The second nozzle has a second hole through which an adhesive is dispensed. In a bonding process, the wire bonding apparatus dispenses the adhesive from the second nozzle onto an electrode, and then presses the first nozzle against the adhesive on the electrode so that the tip of the bonding wire contacts the electrode.

[0019] According to one aspect of the present invention, it is possible to reduce the manufacturing cost of semiconductor components. According to one aspect of the present invention, it is possible to provide a bonding wire that replaces gold and a manufacturing method of semiconductor components using the same. According to one aspect of the present invention, it is possible to provide a wire bonding apparatus and a wire bonding method having a novel configuration.

[0020] According to one aspect of the present invention, it is possible to provide a semiconductor device having a novel structure and a manufacturing method thereof. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0021] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0022] FIGS. 1A to 1E are configuration examples of bonding wires. FIGS. 2A to 2E are configuration examples of wire bonding apparatuses. FIGS. 3A to 3F are configuration examples of wire bonding apparatuses. FIGS. 4A to 4D are configuration examples of wire bonding apparatuses. FIGS. 5A and 5B are configuration examples of semiconductor devices. FIG. 6 is a configuration example of a semiconductor device. FIG. 7 is a configuration example of a memory device. FIGS. 8A and 8B are configuration examples of memory devices. FIGS. 9A and 9B are configuration examples of memory devices. FIGS. 10A to 10C are configuration examples of memory devices. FIG. 11 is a configuration example of a memory device. FIGS. 12A to 12D are configuration examples of semiconductor devices. FIGS. 13A and 13B are configuration examples of semiconductor devices. FIG. 14 is a configuration example of a memory device. FIG. 15 is a configuration example of a memory device. FIGS. 16A and 16B are configuration examples of semiconductor devices. FIGS. 17A and 17B are configuration examples of electronic components. 18A and 18B are configuration examples of electronic equipment, and Fig. 18C to Fig. 18E are configuration examples of mainframe computers. Fig. 19A is a configuration example of space equipment. Fig. 19B is a configuration example of a storage system.

[0023] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0025] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0026] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0027] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0028] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a supporting surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "lower" and the laminate side as "upper."

[0029] Embodiment 1 In this embodiment, a wiring material of one embodiment of the present invention, a structural example of a semiconductor device using the wiring material, a manufacturing method of the semiconductor device, and the like will be described.

[0030] In one aspect of the present invention, a material containing carbon nanotubes (hereinafter also referred to as CNTs) is used for bonding wires (hereinafter also referred to as wiring) that connect a semiconductor chip and a lead frame. CNTs have high conductivity and can be synthesized in large quantities at low cost, so using CNTs for bonding wires can reduce costs compared to using precious metals such as gold.

[0031] Although the case where a lead frame is used will be described here, the present invention is not limited thereto, and various substrates provided with electrodes (electrode pads) for connecting bonding wires can be used. For example, an interposer substrate, a ceramic package, a PCB (Printed Wiring Board) substrate, etc. can also be used. A substrate to which the bonding wire and wire bonding method of one embodiment of the present invention can be applied may be simply called a wiring substrate.

[0032] In addition, a bonding wire may be made of a material containing CNTs and a material containing a precious metal such as gold or a gold alloy. For example, two types of bonding wires can be used depending on the distance between the electrodes. By using a bonding wire made of a material containing CNTs and a material containing a precious metal in combination, the amount of precious metal used can be reduced compared to when all bonding wires are made of materials containing precious metals, thereby reducing costs.

[0033] For bonding wires using CNTs, it is preferable to use CNTs processed into a twisted yarn. Since the strength and rigidity of the twisted CNTs can be controlled by the number of twists and twist shape during processing, it is possible to easily achieve the optimal strength and rigidity for use in bonding wires. For example, the Young's modulus of the bonding wire can be set to 1 GPa or more and 150 GPa or less, preferably 10 GPa or more and 130 GPa or less, and more preferably 20 GPa or more and 120 GPa or less. The diameter of the bonding wire can be set to 1 μm or more and 150 μm or less, preferably 5 μm or more and 130 μm or less, and more preferably 10 μm or more and 100 μm or less. By setting the Young's modulus and diameter in this range, it becomes possible to handle the wire in the same way as gold or a gold alloy.

[0034] When applied to semiconductor devices requiring a large current, such as power devices, the diameter of the bonding wire may be larger than 150 μm. For example, it may be larger than 150 μm and smaller than 3 mm, preferably larger than 200 μm and smaller than 2.5 mm. Furthermore, the cross section of the bonding wire is not limited to a substantially circular shape, but may also be a polygonal shape, such as a square. By making the cross section of the bonding wire rectangular, a plate-shaped (ribbon-shaped) bonding wire may be obtained.

[0035] A more specific example will be described below with reference to the drawings.

[0036] [Configuration Example of Bonding Wire] FIG. 1A is a schematic diagram of a CNT 100 that can be used for a bonding wire according to one embodiment of the present invention.

[0037] CNT100 is a carbon compound in which graphene sheets having a network of six-membered rings composed of carbon atoms (C) are arranged in a ring shape (also called a cylindrical or tubular shape). The CNT100 has a length of 1 mm or more and 5 cm or less, preferably 5 mm or more and 5 cm or less, typically about 2 cm. Note that CNTs having a length of more than 5 cm (for example, 10 cm or more and 30 cm or less) may also be used. The longer the length of each CNT100, the higher the strength and conductivity when twisted into a yarn, which is preferable.

[0038] There are three known types of CNTs, each with a different geometric structure: armchair, zigzag, and chiral. From the viewpoint of electrical conductivity, it is preferable to use armchair CNTs. Fig. 1A shows a CNT 100 having an armchair structure. However, the CNT is not limited to the armchair type, and zigzag or chiral CNTs may also be used.

[0039] Although a single-walled CNT is shown here as an example of the CNT 100, a multi-walled CNT with two or more walls may also be used. By using a multi-walled CNT, it is possible to increase the rigidity compared to a single-walled CNT.

[0040] FIG. 1B shows a schematic diagram of a CNT 100a containing a metal Me. The metal Me is located inside the cylindrical CNT and has a cylindrical shape. Note that the metal Me is not limited to a cylindrical shape, and may be spherical, polygonal, or cylindrical. The inclusion of the metal Me is preferable because it further increases the conductivity. As the metal Me, various metals can be used, including noble metals such as gold, silver, and copper, as well as nickel, zinc, palladium, aluminum, indium, tin, hafnium, lead, and iron. In particular, it is preferable to use metals with low melting points and low resistance, such as gold, silver, copper, and nickel.

[0041] When heated, the metal contained in the CNT 100a may be eluted from its tip. Furthermore, the elution may occur at a temperature significantly lower (for example, several hundred degrees) than the melting point of the metal itself. Therefore, the eluted metal may be used in the bonding portion with the electrode during wire bonding. Therefore, by utilizing the molten metal, it is possible to directly bond a bonding wire using the CNT 100a to an electrode.

[0042] FIG. 1C is a schematic diagram showing how the CNTs 100 are processed into twisted yarn.

[0043] CNTs 100 are formed on the upper surface of the substrate 105, growing vertically aligned at high density. A collection of CNTs formed at high density is sometimes called a CNT forest. The CNT forest can be formed on the substrate 105 by, for example, a chemical vapor deposition (CVD) method.

[0044] When one CNT 100 is pulled out from the end of the CNT forest, other CNTs 100 bound by van der Waals forces are subsequently pulled out. By repeating this process, CNTs 100 are pulled out continuously without interruption, resulting in a thread-like CNT linked body 100C. By twisting multiple linked bodies 100C pulled out from the CNT forest in this way, a twisted CNT yarn 102 can be obtained.

[0045] 1C is a schematic diagram of twister 104. Twister 104 has a mechanism for rotating its tip and a mechanism for moving it in a direction away from substrate 105. With the ends of multiple CNT yarns 102 fixed to the tip of twister 104, twister 104 moves away from substrate 105 while rotating the tip, thereby spinning CNT yarn 102. The number of twists in CNT yarn 102 can be controlled by the number of rotations per unit time and the movement speed of twister 104.

[0046] 1D shows a schematic diagram of the CNT yarn 102 thus produced. The CNT yarn 102 has a configuration in which multiple CNTs 100 are twisted at high density.

[0047] Furthermore, a thicker, stronger twisted yarn can be produced by further twisting multiple CNT yarns 102. Fig. 1E shows a schematic diagram of a CNT yarn 103 produced by further twisting three CNT yarns 102. To facilitate understanding, the three CNT yarns 102 are shown with different hatching patterns.

[0048] The CNT yarns 102 and 103 illustrated here can be used for bonding wires. Note that, in addition to CNT 100 and CNT 100a, a CNT yarn obtained by twisting CNT 100 and a CNT yarn obtained by twisting CNT 100a can also be used.

[0049] [Example of Wire Bonding Apparatus] A wire bonding apparatus according to one embodiment of the present invention and a wire bonding method using the same will be described below.

[0050] 2A shows a configuration example of a wire bonding apparatus according to one embodiment of the present invention. The wire bonding apparatus has a nozzle 110.

[0051] The nozzle 110 is provided with a hole 115 for feeding out the bonding wire 111. The nozzle 110 can feed out the bonding wire 111 of a required length from the hole 115 at an appropriate speed. The tip of the bonding wire 111 is processed to have a spherical shape. For example, the spherical portion can be formed at the tip by heating and melting the tip of the wire-like bonding wire 111 by arc discharge.

[0052] The bonding wire 111 can be made of gold, silver, copper, aluminum, palladium, platinum, or an alloy containing one or more of these. Alternatively, the metal-encapsulated CNT 100a illustrated in FIG. 1B can be used. When the CNT 100a is used, the encapsulated metal is eluted by heating, forming a spherical portion containing the eluted metal. The spherical portion may be made of only the eluted metal, or may be a mixture of CNT and metal.

[0053] Next, a wire bonding method (also called a bonding process) using a wire bonding apparatus having the nozzle 110 will be described.

[0054] As shown in FIG. 2B , bonding is performed by pressing the spherical tip of the bonding wire 111 against the upper surface of an electrode 112a provided on a base material 113a. Examples of the base material 113a include a semiconductor chip and a lead frame. The nozzle 110 has an ultrasonic wave generating function, and presses the spherical tip against a heated electrode. Under load, ultrasonic waves are generated, bonding the bonding wire 111 and the electrode 112a. After bonding is completed, as shown in FIG. 2C , the bonding wire 111 is fed out from the nozzle 110 and moved to the next electrode 112b to be bonded. FIG. 2D shows the bonding to the electrode 112b on a different base material 113b. As shown in FIG. 2D , the nozzle 110 is pressed against the bonding wire 111 to bend it, thereby bonding the bonding wire 111 and the electrode 112b. After bonding, as shown in FIG. 2E , the nozzle 110 is raised, cutting the bonding wire 111 and completing the bonding. 2D and other figures, the tip of the nozzle 110 has a sharp shape, so that when the nozzle 110 is pressed against the electrode 112b, the bonding wire 111 can be cut at the same time as bonding. In this manner, two electrodes can be bonded by the bonding wire 111.

[0055] 3A shows an example of the configuration of a wire bonding apparatus different from that described above. The wire bonding apparatus shown in FIG.

[0056] The nozzle 120 is provided with a hole 125a for feeding out the bonding wire 121 and a hole 125b for discharging the adhesive 122. The nozzle 120 can discharge the adhesive 122 from the hole 125a at a required amount. The nozzle 120 preferably has a plurality of holes 125b. In this case, it is preferable that the plurality of holes 125b are provided symmetrically with the hole 125a at the center. For example, a configuration can be adopted in which two holes 125b are provided on either side of the hole 125a. Alternatively, the holes 125b may have an annular shape that is concentrically provided with the hole 125a at the center.

[0057] 3D, 3E, and 3F show schematic horizontal cross sections of the nozzle 120 to illustrate examples of the positional relationship between the holes 125a and 125b. In FIG. 3D, two holes 125b are provided symmetrically with respect to the hole 125a. In FIG. 3E, four holes 125b are provided equidistantly around the hole 125a. In FIG. 3F, an annular hole 125b is provided surrounding the hole 125a. It is preferable that the multiple holes 125b are arranged so that they are equally spaced from the hole 125a. This allows for high-yield bonding between electrodes arranged in different directions without rotating the nozzle 120. The multiple holes 125b may be arranged asymmetrically with respect to the hole 125a.

[0058] The bonding wire 121 can be made of a non-metallic material such as CNT yarn 102 or CNT yarn 103 using the above-mentioned CNT 100. Alternatively, a CNT yarn using CNT 100a containing a metal may be used. The wire bonding apparatus shown in FIG. 3A can bond a bonding wire made of a material that is difficult to melt by arc discharge or the like.

[0059] The adhesive 122 preferably contains a low-melting-point metal such as gold, silver, or tin. For example, gold, silver, tin, or an alloy containing one or more of these may be used. Alternatively, other low-melting-point metals may be used. The adhesive 122 may be a wire of the above metal or alloy, or a conductive paste in which the metal is dispersed in a resin.

[0060] The nozzle 120 preferably has a heating mechanism for melting or solidifying the adhesive 122. Alternatively, the electrode 112 may be heated.

[0061] Next, a bonding method using the wire bonding apparatus shown in FIG. 3A will be described. First, the bonding wire 121 is pressed against the upper surface of the electrode 112 provided on the base material 113. Next, as shown in FIG. 3B, with the bonding wire 121 and the electrode 112 in contact, adhesive 122 is ejected from the hole 125b. The adhesive 122 is ejected so as to cover the upper surfaces of the bonding wire 121 and the electrode 112. At this time, by maintaining the tip of the nozzle 120 in contact with the adhesive 122, the adhesive 122 melts, and surface tension allows the adhesive 122 to adhere to both the bonding wire 121 and the electrode 112. Next, by moving the nozzle 120 upward, the adhesive 122 solidifies, bonding the bonding wire 121 and the electrode 112. Thereafter, as shown in FIG. 3C, the bonding wire 121 is fed from the nozzle 120, and the nozzle 120 is moved to the next electrode to be bonded. By bonding the next electrode in the same manner as above, the two electrodes can be connected by a bonding wire 121 .

[0062] In this specification, the term "tip of a bonding wire" refers not only to the cut surface of the bonding wire but also to the side surface of the bonding wire near the tip. For example, the cut surface of the bonding wire and the surface within 2 mm of the cut surface in the longitudinal direction are referred to as the tip. Therefore, a case in which the bonding wire is bent and the cut surface does not contact the electrode, but only the side surface contacts the electrode, is also included in one aspect of the present invention. Furthermore, when the tip of the bonding wire is spherical, the spherical portion and the side surface in its vicinity (the surface within 2 mm of the spherical portion in the longitudinal direction) are referred to as the tip.

[0063] Fig. 4A shows a configuration example of a wire bonding apparatus different from that described above. The wire bonding apparatus shown in Fig. 4A is provided with a nozzle 130a that pays out bonding wire 121 and a nozzle 130b that dispenses adhesive 122, which are provided independently. Nozzle 130a has a hole 135a that pays out bonding wire 121. Nozzle 130b has a hole 135b that dispenses adhesive 122.

[0064] Next, a bonding method using the wire bonding apparatus shown in FIG. 4A will be described. First, as shown in FIG. 4B, adhesive 122 is ejected from nozzle 130b onto the upper surface of electrode 112. Next, after nozzle 130b is moved away from electrode 112, as shown in FIG. 4C, nozzle 130a is lowered and the tip of nozzle 130a is pressed against adhesive 122 on electrode 112 so that bonding wire 121 contacts the upper surface of electrode 112. At this time, as described above, adhesive 122 melts and adheres to bonding wire 121 and electrode 112 due to surface tension. Next, nozzle 130a is moved upward, causing adhesive 122 to solidify, thereby bonding bonding wire 121 and electrode 112. Thereafter, as shown in FIG. 4D, bonding wire 121 is paid out from nozzle 130a, and nozzle 130a is moved to the next electrode.

[0065] The above is a description of the wire bonding apparatus and the wire bonding method.

[0066] [Configuration Example of Semiconductor Device] Hereinafter, a configuration example of a semiconductor device to which a bonding wire according to one embodiment of the present invention is applied will be described.

[0067] 5A shows a perspective view of the semiconductor device 140. The semiconductor device 140 has a lead frame 141 and a semiconductor chip 142 fixed to the lead frame 141.

[0068] A plurality of electrodes 145 are provided on the lead frame 141. A plurality of electrodes 144 are provided on the top of the semiconductor chip 142. The electrodes 145 and 144 are connected by bonding wires 121. The semiconductor chip 142 is fixed to the lead frame 141 by an adhesive layer 143.

[0069] A paste-like adhesive or a tape-like (sheet-like) adhesive can be used as the adhesive layer 143. It is preferable to use a conductive material such as a resin material (silver paste) with silver particles dispersed therein for the adhesive layer 143, as this improves heat dissipation.

[0070] 5B shows an enlarged view of the bonding wire 121 and its vicinity. The bonding wire 121 is bonded to an electrode 144 of the semiconductor chip 142 using adhesive 122a. The bonding wire 121 is also bonded to an electrode 145 of the lead frame 141 using adhesive 122a. The bonding wire 121 has an arched shape so that the portion between the pair of bonding portions does not come into contact with components such as the semiconductor chip 142, adhesive layer 143, and lead frame 141.

[0071] In this specification, the term "arched" refers to a shape that includes an upwardly convex curve. Therefore, when referring to an arched shape, the shape may include either or both straight and curved portions.

[0072] By using a twisted yarn containing CNT for the bonding wire 121, the amount of precious metals such as gold used can be reduced, leading to cost reduction.

[0073] FIG. 6 shows an example in which a stacked body in which a plurality of semiconductor chips are stacked is used.

[0074] 6, four semiconductor chips (semiconductor chips 142a, 142b, 142c, and 142d) are stacked on a lead frame 141. An adhesive layer 143a is provided between the semiconductor chip 142a and the lead frame 141. Similarly, adhesive layers 143b, 143c, and 143d are provided between the semiconductor chip 142a and the semiconductor chip 142b, between the semiconductor chip 142b and the semiconductor chip 142c, and between the semiconductor chip 142c and the semiconductor chip 142d, respectively.

[0075] The semiconductor chips 142a, 142b, 142c, and 142d are provided with electrodes 144a, 144b, 144c, and 144d, respectively.

[0076] FIG. 6 shows a bonding wire 121L with a long bonding distance and a bonding wire 121S with an even shorter bonding distance.

[0077] The bonding wire 121L is a bonding wire that connects at least the electrode 145 of the lead frame 141 to an electrode of one of the semiconductor chips. Figure 6 shows an example of two types of bonding wires 121L. One of the bonding wires 121L connects the electrode 145 of the lead frame 141 to the electrode 144d of the semiconductor chip 142d. The other of the bonding wires 121L connects the electrodes 145, 144a, 144b, 144c, and 144d, respectively.

[0078] On the other hand, the bonding wire 121S is a bonding wire with a shorter connection distance than the bonding wire 121L, and is used to connect electrodes of semiconductor chips together, etc. In Fig. 6, two bonding wires 121S are shown, each connecting electrodes of two adjacent semiconductor chips.

[0079] Here, a material containing CNTs can be applied to one of the bonding wires 121L with a long connection distance and the bonding wire 121S with a short connection distance, and a material containing a precious metal such as gold can be applied to the other. This allows the amount of precious metal used to be reduced compared to when all bonding wires are made of a material containing precious metal, thereby reducing the manufacturing cost of the semiconductor device 140.

[0080] In particular, a material containing CNTs can be applied to the bonding wire 121L having a long connection distance, and a material containing a precious metal such as gold can be applied to the bonding wire 121S having a short connection distance, which allows for more effective reduction in the amount of precious metal such as gold used, thereby enhancing the effect of reducing the manufacturing cost of the semiconductor device 140.

[0081] On the other hand, a material containing a precious metal such as gold may be applied to the bonding wire 121L having a long connection distance, and a material containing CNT may be applied to the bonding wire 121S having a short connection distance. In some cases, the resistance of the bonding wire becomes a problem in the long connection distance portion. In such a case, it is preferable to apply a low-resistance metal material to the bonding wire 121L.

[0082] The above is a description of an example of the configuration of the semiconductor device.

[0083] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0084] In this embodiment, a memory device and a transistor that can be used in a semiconductor device of one embodiment of the present invention will be described. The memory device exemplified below is one mode of the semiconductor chip 142 or the semiconductor chips 142a to 142d described in Embodiment 1.

[0085] In this embodiment, a configuration example of a memory device in which a layer having a functional circuit that has a function of amplifying and outputting a data potential held in the memory cell is provided between layers having stacked memory cells will be described.

[0086] [Configuration Example of Storage Device] FIG. 7 illustrates a block diagram of a storage device of one embodiment of the present invention.

[0087] 7 includes a drive circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 including a plurality of functional circuits 51.

[0088] 7 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). Also, Fig. 7 shows an example in which a functional circuit 51 is provided for each wiring BL that functions as a bit line, and an example in which the functional layer 50 has a plurality of functional circuits 51 provided corresponding to the n wirings BL.

[0089] In FIG. 7 , the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. Furthermore, in the present embodiment and the like, an arbitrary row may be referred to as row i. Furthermore, an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. Furthermore, in the present embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. Furthermore, in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 and does not exceed m. Similarly, when "j+α" is used, "j+α" is not less than 1 and does not exceed n.

[0090] The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0091] The memory cells 10 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 10 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0092] The memory array 20 may be a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, with the access transistor being an OS transistor. The current flowing between the source and drain of an OS transistor in the off state, i.e., leakage current, is extremely small. By turning off (non-conducting) the access transistor, DOSRAM can retain charge corresponding to data stored in a capacitance element (capacitor) for a long period of time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAMs composed of transistors having silicon in their channel formation regions (Si transistors). As a result, power consumption can be reduced. Furthermore, the high frequency characteristics of OS transistors enable high-speed read and write operations. This allows for a memory device with high operating speed.

[0093] 7, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10.

[0094] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conduction state or non-conduction state) of an access transistor functioning as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring CL (not shown) can be separately provided as a wiring that has a function of transmitting a back-gate potential to the back-gate of an OS transistor that is an access transistor. The wiring PL may also have a function of transmitting the back-gate potential.

[0095] The memory cells 10 included in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL. The wiring BL can be arranged in a direction perpendicular to the substrate surface on which the driver circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. This shortens the signal propagation distance between two circuits connected to the bit line, significantly reducing the resistance and parasitic capacitance of the bit line, thereby realizing reduced power consumption and signal delay. Furthermore, the memory cells 10 can be operated even if the capacitance of the capacitive element included in the memory cell 10 is reduced.

[0096] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via a wiring GBL (not shown), which will be described later. This configuration allows a slight potential difference in the wiring BL to be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the driver circuit 21 is provided, similar to the wiring BL. By arranging the wirings BL and GBL extending from the memory cells 10 of the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL are significantly reduced, thereby realizing reduced power consumption and signal delay.

[0097] The wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a conductor provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source or the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0098] The memory array 20 can be provided overlapping the drive circuit 21. By providing the drive circuit 21 and the memory array 20 overlapping, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, thereby realizing reductions in power consumption and signal delay. In addition, the storage device 300 can be made smaller.

[0099] The functional circuit 51 is configured with OS transistors similar to the transistors included in the DOSRAM memory cells 10, and can be freely arranged on a circuit using Si transistors similar to the memory arrays 20[1] to 20[m], thereby facilitating integration. The signal amplification configuration in the functional circuit 51 allows for the miniaturization of subsequent circuits such as the sense amplifier 46, thereby enabling the miniaturization of the memory device 300.

[0100] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0101] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0102] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0103] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0104] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0105] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0106] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, the function of holding the read data, etc.

[0107] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0108] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW22 is controlled by the signal PON1, and the on / off of the PSW23 is controlled by the signal PON2. In FIG. 7, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0109] The memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on a drive circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased. Figure 8A shows a perspective view of a storage device 300 having a functional layer 50 and five layers (m = 5) of memory arrays 20[1] to 20[5] stacked on a drive circuit 21.

[0110] 8A, the memory array 20 provided in the first layer is shown as memory array 20[1], the memory array 20 provided in the second layer is shown as memory array 20[2], and the memory array 20 provided in the fifth layer is shown as memory array 20[5]. Also shown in FIG. 8A are wiring WL and wiring PL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that, to make the drawing easier to understand, the wiring WL and wiring PL of each memory array 20 are partially omitted.

[0111] 8B is a schematic diagram illustrating a configuration example of a functional circuit 51 connected to the wiring BL illustrated in FIG. 8A and memory cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL. Also, FIG. 8B illustrates a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0112] 8B illustrates an example of a circuit configuration of a memory cell 10 connected to a wiring BL. The memory cell 10 includes a transistor 11 and a capacitor 12. The transistor 11, the capacitor 12, and each wiring (such as a wiring BL and a wiring WL) may also be referred to as a wiring BL[1] and a wiring WL[1], for example.

[0113] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to a wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of a capacitor 12. The other electrode of the capacitor 12 is connected to a wiring PL. The gate of the transistor 11 is connected to a wiring WL. The back gate of the transistor 11 is connected to a wiring CL.

[0114] The wiring PL is a wiring that applies a constant potential to maintain the potential of the capacitor 12. The wiring CL is a wiring that applies a constant potential to control the threshold voltage of the transistor 11. The wiring PL and the wiring CL may have the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.

[0115] The wiring GBL shown in Fig. 8B is provided to electrically connect the driver circuit 21 and the functional layer 50. Fig. 9A is a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are repeated as a repeating unit 70. Note that although Fig. 9A shows one wiring GBL, the wiring GBL may be provided as needed depending on the number of functional circuits 51 provided in the functional layer 50.

[0116] The wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source or the drain of a transistor included in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.

[0117] The repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked. The memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 9B . The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be provided as appropriate depending on the number of functional circuits 51.

[0118] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged perpendicular to the surface of a substrate on which the driver circuit 21 is provided. By providing the wirings functioning as bit lines extending from the memory array 20 perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit lines can be significantly reduced.

[0119] In one embodiment of the present invention, a layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting a data potential held in the memory cell 10. With this structure, a slight potential difference of the wiring BL that functions as a bit line can be amplified when reading data, and the sense amplifier 46 included in the driver circuit 21 can be driven. Since circuits such as a sense amplifier can be miniaturized, the memory device 300 can be miniaturized. Furthermore, the memory device 300 can operate even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0120] Although the above description illustrates an example in which the memory cell 10 has a 1T (transistor) 1C (capacitor) configuration, the present invention is not limited to this. For example, as shown in FIG. 10A , a 2T1C memory cell may be used in a storage device. The memory cell shown in FIG. 10A includes transistors 11a, 11b, and 11c and a capacitor 12a. Here, the transistors 11a, 11b, and 11c may have the same configuration as the transistor 11, and the capacitor 12a may have the same configuration as the capacitor 12. A RAM with such a configuration may be called NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0121] 10A , one of the source and drain of transistor 11a is electrically connected to one electrode of capacitor 12a and the first gate of transistor 11b. One of the source and drain of transistor 11b is electrically connected to one of the source and drain of transistor 11c. Wiring may be provided as appropriate to the first gate, the other of the source and drain, and the second gate of transistor 11a, the other of the source and drain and the second gate of transistor 11b, the first gate, the other of the source and drain, and the second gate of transistor 11c, and the other electrode of capacitor 12a. The structure of the memory device can also be modified as appropriate in accordance with these wirings.

[0122] Also, as shown in FIG. 10B, the transistor 11c may not be provided, and the configuration may include only the transistors 11a and 11b and the capacitance element 12a.

[0123] 10C, if the parasitic capacitance of the transistors 11a and 11b is sufficiently large, the capacitance element 12a may not be provided, in which case the memory cell is formed only by the transistors 11a and 11b.

[0124] 11 will be used to describe a configuration example of the functional circuit 51 described with reference to FIGS. 7 to 9 and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21. FIG. 11 illustrates a driver circuit 21 connected to wirings GBL (wirings GBL_A and GBL_B) that are connected to functional circuits 51 (functional circuits 51_A and 51_B) that are connected to memory cells 10 (memory cells 10_A and 10_B) that are connected to different wirings BL (wirings BL_A and BL_B). As the driver circuit 21 illustrated in FIG. 11, in addition to the sense amplifier 46, precharge circuits 71_A, precharge circuits 71_B, switch circuits 72_A, switch circuits 72_B, and a write / read circuit 73 are illustrated.

[0125] 11 are OS transistors similar to the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked in the same manner as the memory arrays 20[1] to 20[m].

[0126] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the sources or drains of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the sources or drains of the transistors 53_b and 54_b. The wirings GBL_A and GBL_B are provided in the vertical direction like the wirings BL_A and BL_B, and are connected to the transistors included in the driver circuit 21. As shown in FIG. 11 , the selection signal MUX, the control signal WE, and the control signal RE are applied to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, respectively.

[0127] 11 are configured with Si transistors. Switches 83_A to 83_D that configure switch circuits 72_A and 72_B can also be configured with Si transistors. One of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches that configure precharge circuits 71_A, 71_B, sense amplifier 46, and switch circuit 72_A.

[0128] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal applied to a precharge line PCL1.

[0129] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal applied to a precharge line PCL2.

[0130] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to a wiring VHH or a wiring VLL. The wiring VHH or the wiring VLL has a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors that form an inverter loop. The potentials of the precharged wirings BL_A and BL_B change when the memory cells 10_A and 10_B are selected, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D and the write / read circuit 73. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs. The write / read circuit 73 controls the writing of data signals in response to the signal EN_data.

[0131] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wirings GBL_A and GBL_B. The switch circuit 72_A is switched on or off under the control of a switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write / read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B is switched on or off under the control of a switching signal CSEL2. The switches 83_C and 83_D may be configured in the same manner as the switches 83_A and 83_B.

[0132] 11 , the memory device 300 can be configured such that the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected via wirings BL and GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 50 including transistors that configure the functional circuit 51 increases, the load on the wirings BL is reduced, which shortens the write time and makes it easier to read data.

[0133] 11 , each transistor included in the functional circuits 51_A and 51_B is controlled in response to control signals WE and RE and a selection signal MUX. Each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL in response to the control signal and the selection signal. The functional circuits 51_A and 51_B can function as sense amplifiers including OS transistors. This configuration allows a slight potential difference in the wiring BL to be amplified during read operation, thereby driving the sense amplifier 46 using Si transistors.

[0134] [Configuration Example of Transistor] Next, a configuration example of a transistor that can be used in the memory device will be described.

[0135] 12A to 12D are top views and cross-sectional views of a semiconductor device (transistor 200). FIG. 12A is a top view of the semiconductor device. FIGS. 12B to 12D are cross-sectional views of the semiconductor device. FIG. 12B is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 12A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 12C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 12A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 12D is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 12A and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view of FIG. 12A for clarity. FIG. 13A is an enlarged view of FIG. 12B, and FIG. 13B is an enlarged view of FIG. 12C.

[0136] The transistor 200 includes an insulator 215 provided on a substrate (not shown), an insulator 216 on the insulator 215, a conductor 205 (conductors 205a and 205b) provided so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an insulator 226 on the insulator 224, and an oxide 230 (oxide 2 The oxide 230 includes a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. In addition, an insulator 255 is provided between the insulator 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280 and the insulator 250.

[0137] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulators 255, 250, and conductor 260 are embedded inside openings provided in the insulators 280 and 275. An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282.

[0138] The oxide 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulators 226, 224, and 222 each have a region that functions as a second gate insulator of the transistor 200.

[0139] The conductor 242a has a region which functions as one of the source electrode and the drain electrode of the transistor 200. The conductor 242b has a region which functions as the other of the source electrode and the drain electrode of the transistor 200.

[0140] The conductor 242a has a layered structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a layered structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 in contact with the oxide 230b are preferably conductors that are resistant to oxidation, such as metal nitrides. This prevents the conductors 242a and 242b from being excessively oxidized by the oxygen contained in the oxide 230b. Furthermore, the conductors 242a2 and 242b2 are preferably conductors such as metal layers that have higher conductivity than the conductors 242a1 and 242b1. This allows the conductors 242a and 242b to function as highly conductive wiring or electrodes. Furthermore, in this case, it is preferable that the thicknesses of the conductors 242a2 and 242b2 are thicker than the thicknesses of the conductors 242a1 and 242b1. This can further increase the conductivity of the conductors 242a and 242b. In this way, a semiconductor device can be provided in which the conductors 242a and 242b, which function as wirings or electrodes, are provided in contact with the upper surface of the oxide 230, which functions as an active layer.

[0141] Here, the conductors 242a and 242b can also be expressed as a pair of conductors. Similarly, the conductors 242a1 and 242b1, and the conductors 242a2 and 242b2 can also be expressed as a pair of conductors.

[0142] The portion of the oxide 230 that does not overlap with either the conductor 242a or the conductor 242b and overlaps with the conductor 260 with the insulator 250 interposed therebetween functions as a channel formation region.

[0143] The openings in the insulators 280 and 275 overlap the region between the conductors 242a2 and 242b2. Furthermore, portions of the conductors 242a1 and 242b1 are formed to protrude into the openings. Therefore, the insulator 255 contacts the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 within the openings. Furthermore, the insulator 250 contacts the top surface of the oxide 230 in the region between the conductors 242a1 and 242b1.

[0144] The insulator 255 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and has the function of protecting the conductors 242a2 and 242b2. As will be described in detail later, after the conductors 242a1 and 242b1 are separated, it is preferable to perform heat treatment in an oxygen-containing atmosphere before forming the insulator 250. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductors 242a2 and 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented.

[0145] The insulator 226 is provided between the oxide 230 and the insulator 224 and functions as a barrier insulator that prevents impurities such as hydrogen contained in the insulator 224 from diffusing into the oxide 230 .

[0146] In this specification and the like, a barrier insulator refers to an insulator having barrier properties. In this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0147] The insulator 226 preferably has a barrier property against at least hydrogen. For example, examples of barrier insulators against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 226 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulators against hydrogen. In particular, the insulator 226 more preferably contains silicon nitride.

[0148] The oxide 230 preferably includes an oxide 230a on the insulator 226 and an oxide 230b on the oxide 230a. By including the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0149] In this embodiment, the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b, but is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b, or a stacked structure of three or more layers.

[0150] In the oxide 230b, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged. Regions N and N in FIG. 13A ＋ The pair of regions N correspond to the source and drain regions, and the portion sandwiched between the pair of regions N corresponds to the channel forming region.

[0151] The oxide 230 (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0152] The band gap of a metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. A transistor having a metal oxide in a channel formation region like this is called an OS transistor. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0153] The oxide 230 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0154] The oxide 230 may be, for example, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum Examples of usable materials include zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable materials include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0155] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0156] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0157] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0158] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0159] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0160] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0161] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0162] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this structure, the transistor 200 can have large on-state current and high frequency characteristics.

[0163] Furthermore, since the oxide 230 a and the oxide 230 b contain a common element other than oxygen as a main component, the density of defect states at the interface between the oxide 230 a and the oxide 230 b can be reduced, which reduces the effect of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0164] Specifically, the oxide 230a can be a metal oxide having an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The oxide 230b can be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, when a single layer of oxide 230b is provided as oxide 230, the metal oxide that can be used for oxide 230a may be used for oxide 230b. Furthermore, the compositions of metal oxides that can be used for oxide 230a and oxide 230b are not limited to those described above. For example, the composition of a metal oxide that can be used for oxide 230a may be used for oxide 230b. Similarly, the composition of a metal oxide that can be used for oxide 230b may be used for oxide 230a.

[0165] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0166] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0167] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be suppressed, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0168] An example of fabricating a metal oxide film by using two types of film formation methods will be described below.

[0169] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. At this time, a sputtering method can be used as a deposition method, thereby forming a metal oxide having high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or another deposition method may be used.

[0170] When a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer (also referred to as "mixing") may be formed at the interface between the metal oxide and the surface to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By forming a first layer of metal oxide on the surface to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, or the like, which are described as the first film formation method, and then providing a second layer of metal oxide using the first film formation method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface to be formed can be suppressed. Furthermore, impurities contained in the surface to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0171] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed.The wet method is also one of the film formation methods that causes little damage to the surface on which the film is formed.An example of a wet method is a spray coating method.

[0172] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0173] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0174] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the second layer (i.e., CAAC) having high crystallinity can be used as a nucleus or seed to increase the crystallinity of an oxide semiconductor layer in contact with the second layer. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer can be used as a nucleus or seed to cause solid-phase growth of a metal oxide in the oxide semiconductor layer in contact with the second layer, thereby forming an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC). The AG CAAC structure refers to an oxide semiconductor layer having a two-layer structure of at least a first layer and a second layer, and may have a stacked structure of three or more layers.

[0175] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0176] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide 230b. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0177] The insulator 275 preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This configuration can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242a and the conductor 242b. Therefore, it is possible to prevent the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 280, thereby increasing their resistivity and reducing their on-state current. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0178] For example, the insulator 275 is preferably a single layer or a multilayer structure of a barrier insulator against hydrogen, such as oxides, such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides, such as silicon nitride.

[0179] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making it possible to make the source and drain regions n-type.

[0180] Furthermore, in this embodiment, an insulator 255 is provided between the insulator 250 and the conductor 242a, and between the insulator 250 and the conductor 242b. This allows the distance between the conductor 260 and the conductor 242a and the distance between the conductor 260 and the conductor 242b to be increased by the thickness of the insulator 255. Therefore, the film thickness of the insulator 250 can be made thinner to reduce the Loff region while reducing the parasitic capacitance between the conductor 260 and the conductor 242a and between the conductor 242b and the conductor 242b.

[0181] Furthermore, it is preferable that insulators (insulators 282 and 283) having a function of suppressing hydrogen diffusion be provided so as to cover one or both of the top and bottom of the transistor 200, etc. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0182] In the transistor 200, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Furthermore, the conductor 205 is preferably provided to extend in the channel width direction, as shown in FIGS. 12A and 12C . With this structure, when a plurality of transistors are provided, the conductor 205 functions as a wiring.

[0183] The conductor 205 may have a single-layer structure or a multilayer structure. In FIG. 12 and other figures, the conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to fill a recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 is approximately the same as the height of the upper surface of the insulator 216.

[0184] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0185] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0186] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0187] Insulator 222, insulator 224, and insulator 226 function as a second gate insulator.

[0188] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0189] Insulator 224 preferably comprises, for example, silicon oxide or silicon oxynitride.

[0190] The insulator 224 functions as a spacer for positioning the bottom surface of the oxide 230b higher than the bottom surface of the conductor 260. Therefore, it is preferable to form the insulator 224 relatively thick, and it is preferable to use an insulator whose deposition rate can be easily increased, such as silicon oxide or silicon oxynitride. However, impurities such as hydrogen easily diffuse into such insulators, so it is important to provide an insulator 226 having barrier properties against hydrogen between the insulator 224 and the oxide 230.

[0191] The insulator 224 is preferably processed into an island shape, similar to the insulator 226 and the oxide 230. This means that when multiple transistors 200 are provided, each transistor 200 has an insulator 224 of approximately the same size. However, this is not limiting, and similar to the insulator 222, the insulator 224 may also be configured not to be patterned.

[0192] Each of the insulators 222, 224, and 226 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials. Note that a configuration may be adopted in which either or both of the insulators 224 and 222 are not included.

[0193] The conductors 242a, 242b, and 260 are preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0194] In Figure 12B, conductors 242a and 242b are shown as a two-layer structure. Conductor 242a is a laminated film of conductor 242a1 and conductor 242a2 on conductor 242a1, and conductor 242b is a laminated film of conductor 242b1 and conductor 242b2 on conductor 242b1. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the layers in contact with oxide 230b (conductors 242a1 and 242b1). This can prevent the conductivity of conductors 242a and 242b from decreasing. It can also prevent oxygen from being extracted from oxide 230b, preventing excessive oxygen vacancies from being formed. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1), since this can reduce the hydrogen concentration in the oxide 230b.

[0195] 12B and 12C , the insulator 255 is disposed in an opening formed in the insulator 280 or the like, and contacts the side surfaces of the insulator 280, the side surfaces of the insulator 275, the side surfaces of the insulator 271a, the side surfaces of the insulator 271b, the side surfaces of the conductors 242a2, 242b2, 242a1, and 242b1, and the top surface of the insulator 222. In other words, the openings of the insulator 255 can be said to be formed so as to expose the island-shaped oxide 230 in the openings. Furthermore, in the region where the openings of the insulator 255 are formed, the insulator 250 contacts the oxide 230 and the insulator 222. Note that in FIG. 12C , the insulator 255 has openings only near the oxide 230, but the present invention is not limited to this. The insulator 255 only needs to have an opening in at least the region of the oxide 230b that is sandwiched between the conductors 242a1 and 242b1. Therefore, for example, the insulator 255 may have almost no region in contact with the insulator 222 and may be formed in a sidewall shape in the opening formed in the insulator 280.

[0196] The insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Because the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 is an inorganic insulator that is resistant to oxidation. Furthermore, because the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 255 is an inorganic insulator that is resistant to oxidation of the conductors 242a2 and 242b2. Therefore, it is preferable that the insulator 255 be made of an insulating material that has barrier properties against oxygen. For example, silicon nitride can be used as the insulator 255.

[0197] By using such an insulator 255, the conductors 242a2 and 242b2 are not excessively oxidized even if heat treatment is performed in an oxygen-containing atmosphere after separating the conductors 242a1 and 242b1 and before forming the insulator 250. For example, the thickness of the oxide film on the side surfaces of the conductors 242a2 and 242b2 near the conductor 260 can be set to 0.5 nm or more and 5 nm or less, preferably 0.5 nm or more and 3 nm or less, and more preferably 0.5 nm or more and 2 nm or less.

[0198] Alternatively, the insulator 255 may have a stacked structure of two or more layers using an inorganic insulator that is resistant to oxidation. For example, the insulator 255 may have a two-layer structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, a two-layer structure of a silicon nitride film and a silicon oxide film on the silicon nitride film, a two-layer structure of an aluminum oxide film and a silicon oxide film on the aluminum oxide film, a two-layer structure of a silicon oxide film and a silicon nitride film on the silicon oxide film, or a two-layer structure of a silicon oxide film and an aluminum oxide film on the silicon oxide film.

[0199] Furthermore, the insulator 255 functions as part of a mask when dividing the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 12B , in a cross-sectional view of the transistor 200, the side edges of the insulator 255 preferably roughly coincide with the side edges of the conductor 242a1 and the conductor 242b1.

[0200] Here, the portion of conductor 242a1 on whose upper surface insulator 255 is formed protrudes more toward conductor 260 than conductor 242a2. Similarly, the portion of conductor 242b1 on whose upper surface insulator 255 is formed protrudes more toward conductor 260 than conductor 242b2.

[0201] 12B and 12C , the conductor 260 is disposed in an opening formed in the insulator 280, the insulator 275, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 230, the insulator 226, and the insulator 224. The conductor 260 is disposed in the opening so as to cover, via the insulator 250, the side surface of the insulator 224, the side surface of the insulator 226, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b. A portion of the conductor 260 is disposed overlapping the conductors 242a1 and 242b1. The conductor 260 is disposed so that its top surface is approximately at the same height as the top of the insulator 250 and the top surface of the insulator 280.

[0202] In the opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be approximately perpendicular to the upper surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the insulators 255 and 250, etc., provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0203] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 12A and 12C. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0204] 12C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as a rounded shape).

[0205] In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin structure. In this specification, a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0206] By forming the transistor 200 in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor.

[0207] In this embodiment, the insulators 224 and 226 are provided in an island shape. Therefore, as shown in FIG. 12C , at least a portion of the lower surface of the conductor 260 can be provided below the lower surface of the oxide 230b. This allows the conductor 260 to be provided facing the upper surface and side surface of the oxide 230b, and therefore the electric field of the conductor 260 can be applied to the upper surface and side surface of the oxide 230b. By providing the insulators 224 and 226 in an island shape in this way, the transistor 200 can have an S-channel structure.

[0208] 12C illustrates an example of a transistor with an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0209] In Figure 12B and other figures, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0210] For example, it is preferable to use titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like for the conductor 260a.

[0211] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0212] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged to overlap the region between the conductor 242a1 and the conductor 242b1 without alignment.

[0213] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0214] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0215] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0216] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0217] [Constituent Materials of Semiconductor Device] Constituent materials that can be used for the semiconductor device will be described below. Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.

[0218] [Substrate] The substrate on which a transistor is formed can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides, substrates containing metal oxides, substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0219] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0220] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0221] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0222] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0223] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0224] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0225] [Conductor] The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. Examples of the conductor include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0226] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0227] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0228] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0229] [Configuration Example of Memory Cell] Next, a configuration example of the memory cell 10 that can be used in the above-described storage device will be described with reference to FIG.

[0230] In FIG. 14, the X direction is parallel to the channel length direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0231] As shown in FIG. 14 , the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided over the transistor 11, and an insulator 284 is provided over the insulator 285. The insulators 285 and 284 may be the same as those used for the insulator 216. The transistor 11 has a similar structure to the transistor 200, and the same components are denoted by the same reference numerals. For details of the transistor 200, the above description can be referred to. A conductor 240 is provided in contact with one of the source and drain (conductor 242a) of the transistor 11. The conductor 240 extends in the Z direction and functions as a wiring BL.

[0232] The capacitor 12 includes a conductor 153 on the conductor 242b, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.

[0233] At least a portion of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the openings formed in the insulators 271b, 275, 280, 282, 283, and 285. The ends of the conductors 153, 154, and 160 are located at least on the insulator 282, and preferably on the insulator 285. The insulator 154 is disposed so as to cover the end of the conductor 153. This allows the conductors 153 and 160 to be electrically insulated from each other.

[0234] The deeper the openings provided in the insulators 271b, 275, 280, 282, 283, and 285 are (that is, the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitor 12. Increasing the capacitance per unit area of ​​the capacitor 12 allows for miniaturization or high integration of the semiconductor device.

[0235] The conductor 153 has a region that functions as one electrode (lower electrode) of the capacitor 12. The insulator 154 has a region that functions as a dielectric of the capacitor 12. The conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitor 12. The capacitor 12 constitutes a metal-insulator-metal (MIM) capacitor.

[0236] In addition, the conductor 242 b provided so as to overlap the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitor 12 .

[0237] The conductor 153 and the conductor 160 included in the capacitor 12 can be formed using any of the conductors that can be used for the conductor 205 or the conductor 260. The conductor 153 and the conductor 160 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductor 153 can be formed using titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0238] The upper surface of the conductor 242b2 is in contact with the lower surface of the conductor 153. Here, by using a conductive material with good conductivity as the conductor 242b2, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0239] Alternatively, the conductor 160a may be made of titanium nitride formed by ALD or CVD, and the conductor 160b may be made of tungsten formed by CVD. Note that if the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single-layer structure of tungsten formed by CVD.

[0240] A high-dielectric (high-k) material (a material with a high relative dielectric constant) is preferably used for the insulator 154 of the capacitor 12. The insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0241] Examples of high-dielectric-constant (high-k) insulators include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.

[0242] For example, examples of insulators made of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-k materials, the insulator 154 can be made thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor 12.

[0243] Furthermore, it is preferable to use a laminated structure of insulators made of the above materials, and it is preferable to use a laminated structure of a high-dielectric constant (high-k) material and a material having a higher dielectric strength than the high-dielectric constant (high-k) material. For example, an insulator formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order can be used as the insulator 154. Alternatively, an insulator formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order can be used. Alternatively, an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order can be used. By using a laminated structure of an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element 12 can be suppressed.

[0244] The deeper the openings in the insulators 271b, 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitor 12 can be. Here, since the insulators 271b, 275, 282, and 283 function as barrier insulators, it is preferable to set their thicknesses according to the barrier properties required for the semiconductor device. Furthermore, since the thickness of the insulator 280 determines the thickness of the conductor 260 that functions as a gate electrode, it is preferable to set the thickness of the insulator 280 according to the thickness of the conductor 260 required for the semiconductor device.

[0245] Therefore, it is preferable to set the capacitance of the capacitor 12 by adjusting the film thickness of the insulator 285. For example, the film thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm. Forming the capacitor 12 in such a range allows the capacitor 12 to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that a configuration may be adopted in which the capacitance of the capacitor provided in each memory cell is different in each of the multiple memory cell layers. In such a configuration, for example, the film thickness of the insulator 285 provided in each memory cell layer may be different.

[0246] In the opening provided in the insulator 285 or the like in which the capacitor element 12 is disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening of the insulator 285 or the like can be improved, and defects such as voids can be reduced.

[0247] Furthermore, the conductor 242a provided so as to overlap the oxide 230 functions as wiring that is electrically connected to the conductor 240. For example, in Fig. 14, the upper surface and side end portions of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction. In particular, in Fig. 14, the upper surface and side end portions of the conductor 242a2 and the side end portions of the conductor 242a1 are in contact with the conductor 240.

[0248] By directly contacting the conductor 240 with at least one of the upper surface and side end of the conductor 242a, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, thereby increasing the memory capacity of the memory device. It is preferable that the conductor 240 contacts a portion of the upper surface and side end of the conductor 242a. By contacting multiple surfaces of the conductor 242a, the contact resistance between the conductor 240 and the conductor 242a can be reduced. In particular, as shown in FIG. 14 , by contacting a portion of the upper surface and side end of the highly conductive conductor 242a2, the contact resistance between the conductor 240 and the conductor 242a can be further reduced.

[0249] Conductor 240 is disposed within openings formed in insulators 216 , 222 , 275 , 280 , 282 , 283 , 285 and 284 .

[0250] The conductor 240 preferably has a layered structure of the conductor 240a and the conductor 240b. For example, as shown in FIG. 14 , the conductor 240 can be structured such that the conductor 240a is provided in contact with the inner wall of the opening, and the conductor 240b is provided further inside. That is, the conductor 240a is arranged closer to the insulators 216, 222, 275, 280, 282, 283, 285, and 284 than the conductor 240b. The conductor 240a also contacts the upper surface and side end of the conductor 242a.

[0251] The conductor 240a is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. The conductor 240a can have a single-layer structure or a multi-layer structure using one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, for example. This can suppress impurities such as water and hydrogen from entering the oxide 230 through the conductor 240.

[0252] Furthermore, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 240b can be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0253] For example, it is preferable to use titanium nitride as the conductor 240a and tungsten as the conductor 240b. In this case, the conductor 240a is a conductor containing titanium and nitrogen, and the conductor 240b is a conductor containing tungsten.

[0254] The conductor 240 may have a single layer structure or a laminated structure of three or more layers.

[0255] 14 , it is preferable that an insulator 241 be provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 216, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surfaces of the insulators 224, 226, oxide 230, and conductor 242a, which are formed to protrude into the openings. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the interior of the opening via the insulator 241.

[0256] 14, the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. This configuration allows the conductor 240 to contact at least a portion of the side end of the conductor 242a. The insulator 241 formed below the conductor 242a preferably has an area that contacts the side surface of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240.

[0257] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. This structure can prevent impurities such as water and hydrogen contained in the insulator 280, etc. from mixing into the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0258] 14 shows the structure in which the insulator 241 is a single layer, the present invention is not limited to this. The insulator 241 may have a stacked structure of two or more layers.

[0259] When the insulator 241 has a two-layer stacked structure, a first layer in contact with the inner wall of the opening of the insulator 280 or the like may be a barrier insulating film against oxygen, and a second layer inside the first layer may be a barrier insulating film against hydrogen. For example, the first layer may be made of aluminum oxide deposited by the ALD method, and the second layer may be made of silicon nitride deposited by the PEALD method. This structure can suppress oxidation of the conductor 240 and further reduce the intrusion of hydrogen from the conductor 240 into the oxide 230 or the like. This can improve the electrical characteristics and reliability of the transistor 11.

[0260] In the opening where the conductor 240 and the insulator 241 are disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, coverage of the insulator 241 and the like provided in the opening is improved.

[0261] [Configuration Example of Storage Device 300] A configuration example of the storage device 300 will be described with reference to FIG.

[0262] The memory device 300 includes a driver circuit 21, which is a layer including a transistor 310 and the like; a functional layer 50, which is a layer including transistors 52, 53, 54, 55, and the like, on the driver circuit 21; and memory arrays 20[1] to 20[m] (only memory arrays 20[1] and 20[2] are shown in FIG. 15 ) on the functional layer 50. Note that the transistor 52 corresponds to the transistors 52_a and 52_b, the transistor 53 corresponds to the transistors 53_a and 53_b, the transistor 54 corresponds to the transistors 54_a and 54_b, and the transistor 55 corresponds to the transistors 55_a and 55_b.

[0263] 15 illustrates a transistor 310 included in the driver circuit 21. The transistor 310 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0264] Here, in the transistor 310 shown in FIG. 15 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0265] Note that the transistor 310 illustrated in FIG. 15 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or the driving method.

[0266] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0267] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings. The bonding wires of one embodiment of the present invention (e.g., CNT100, CNT100a, etc.) illustrated in Embodiment 1 can be used independently for the conductors 207, 209, 240, 328, and 330 shown in FIG. 15 .

[0268] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0269] 15 also illustrates transistors 52, 53, and 55 included in the functional layer 50. The transistors 52, 53, and 55 have the same configuration as the transistor 11 included in the memory cell 10. The sources and drains of the transistors 52, 53, and 55 are connected in series.

[0270] An insulator 208 is provided over the transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided over the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided over the insulator 210, and an insulator 214 is provided over the insulator 212. Parts of a conductor 240 provided in the memory array 20[1] are buried in the openings formed in the insulators 212 and 214. Here, the insulators 208 and 210 can be made of an insulator that can be used for the insulator 216. The insulator 212 can be made of an insulator that can be used for the insulator 283. The insulator 214 can be made of an insulator that can be used for the insulator 282.

[0271] The bottom surface of the conductor 207 is in contact with the top surface of the conductor 260 of the transistor 52. The top surface of the conductor 207 is in contact with the bottom surface of the conductor 209. The top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 20[1]. With this structure, the conductor 240 corresponding to the wiring BL can be electrically connected to the gate of the transistor 52.

[0272] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240 of each memory cell 10 is electrically connected to the conductor 240 in the upper layer and the conductor 240 in the lower layer.

[0273] 15, the conductor 240 is shared by adjacent memory cells 10. In addition, in the adjacent memory cells 10, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240.

[0274] Here, the conductor 160 functioning as the upper electrode of the capacitor 12 in the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 261 functioning as the second gate electrode of the transistor 11 in the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer can be formed so as to be embedded in an opening formed in the same insulator 216. The conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer are formed by processing a single conductive film, resulting in the above-described configuration. In this case, the conductor 160 of the capacitor 12 in the lower layer has the same material as the conductor 261 of the transistor 11 in the upper layer.

[0275] As described above, by simultaneously forming the conductor 160 of the capacitor element 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer, the manufacturing process of the memory device according to this embodiment can be reduced, and the productivity of the memory device can be improved.

[0276] In the memory array 20 described above, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10. Furthermore, the memory array 20 can be fabricated using the same manufacturing process repeatedly in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20.

[0277] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0278] Embodiment 3 In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIGS.

[0279] 16A and 16B, multiple circuits (systems) are implemented on a chip 1200. The technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0280] As shown in FIG. 16A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0281] 16B, chip 1200 is provided with bumps (not shown), which are connected to a first surface of package substrate 1201. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of package substrate 1201, which are connected to motherboard 1203.

[0282] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have low power consumption, high speed, and large capacity.

[0283] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the OS transistor described in the above embodiment, it becomes possible to perform image processing or multiply-and-accumulate operations with low power consumption.

[0284] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0285] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0286] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0287] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0288] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0289] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0290] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be called a GPU module 1204.

[0291] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0292] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0293] Embodiment 4 This embodiment will describe electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiments. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0294] [Electronic Component] FIG. 17A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 17A has a semiconductor device 710 inside a mold 711. FIG. 17A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0295] The bonding wire of one embodiment of the present invention, which is exemplified in Embodiment 1, can be used as the wire 714 .

[0296] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0297] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0298] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0299] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0300] 17B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0301] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0302] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0303] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0304] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0305] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0306] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0307] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0308] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 17B shows an example in which electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0309] In addition, instead of or in addition to solder balls, the bonding wires exemplified in embodiment 1 may be used to connect electrodes provided on package substrate 732 to electrodes provided on other substrates.

[0310] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0311] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 18A . The electronic device 6500 shown in FIG. 18A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0312] 18B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0313] [Mainframe] Next, Fig. 18C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 18C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0314] The computer 5620 can have the configuration shown in the perspective view in Fig. 18D, for example. In Fig. 18D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0315] PC card 5621 shown in Figure 18E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that although Figure 18E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referenced for information on these semiconductor devices.

[0316] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0317] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0318] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0319] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0320] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0321] Note that the bonding wires exemplified in Embodiment Mode 1 can be used instead of solder to connect the semiconductor devices 5627 and 5628 to the board 5622 .

[0322] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0323] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0324] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0325] Fig. 19A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 19A, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0326] 19A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0327] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0328] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0329] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0330] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0331] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0332] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0333] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0334] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0335] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0336] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0337] Fig. 19B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 19B has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0338] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0339] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0340] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0341] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0342] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0343] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0344] 100: CNT, 100a: CNT, 100C: connector, 102: CNT yarn, 103: CNT yarn, 104: twister, 105: substrate, 110: nozzle, 111: bonding wire, 112: electrode, 112a: electrode, 112b: electrode, 113: base material, 113a: base material, 113b: base material, 115: hole, 120: nozzle, 121: bonding wire, 121L: bonding wire, 121S: bonding wire, 122: adhesive, 122a: adhesive, 125a: hole, 125b: hole, 130a: nozzle, 130b: nozzle, 135a: hole, 135b: hole, 140: semiconductor device, 141: lead frame, 142: semiconductor chip, 142a: semiconductor chip, 142b: semiconductor chip, 142c: semiconductor chip, 142d: semiconductor chip, 143: adhesive layer, 143a: adhesive layer, 143b: adhesive layer, 143c: adhesive layer, 143d: adhesive layer, 144: electrode, 144a: electrode, 144b: electrode, 144c: electrode, 144d: electrode, 145: electrode

Claims

A semiconductor chip, a wiring board, and a first bonding wire, The semiconductor chip has a first electrode, the wiring board has a second electrode; the semiconductor chip is fixed to the wiring substrate; the first bonding wire has a portion in contact with the first electrode, a portion in contact with the second electrode, and a portion having an arch shape therebetween; the first bonding wire comprises a carbon nanotube; Semiconductor device. 　 In claim 1, The first bonding wire has a carbon nanotube processed into a twisted yarn. Semiconductor device. 　 In claim 1 or 2, The first bonding wire has a Young's modulus of 1 GPa or more and 150 GPa or less. Semiconductor device. 　 In claim 1 or 2, The first bonding wire has a diameter of 1 μm or more and 150 μm or less. Semiconductor device. 　 In claim 1 or 2, the first electrode and the first bonding wire are fixed by a first adhesive; the second electrode and the first bonding wire are fixed by a second adhesive; the first adhesive and the second adhesive each comprise gold, silver, or tin; Semiconductor device. 　 In claim 1 or 2, a second bonding wire, a third electrode, and a fourth electrode; the third electrode is provided on the semiconductor chip, the fourth electrode is provided on the semiconductor chip or the wiring substrate, the second bonding wire has a portion in contact with the third electrode, a portion in contact with the fourth electrode, and a portion having an arch shape therebetween; the second bonding wire has a different length than the first bonding wire; the second bonding wire comprises gold or a gold alloy; Semiconductor device. 　 In claim 6, The second bonding wire is shorter than the first bonding wire. Semiconductor device. 　 In claim 6, The second bonding wire is longer than the first bonding wire. Semiconductor device. 　 A first nozzle is provided. the first nozzle has a first hole for feeding out a bonding wire and a second hole for discharging an adhesive; In a bonding step, the adhesive is discharged from the second hole so as to cover the bonding wire and the electrode while the tip of the bonding wire is in contact with the electrode. Wire bonding equipment. 　 In claim 9, The second hole is provided symmetrically with respect to the first hole. Wire bonding equipment. 　 A first nozzle and a second nozzle, the first nozzle has a first hole through which a bonding wire is fed, the second nozzle has a second hole for discharging an adhesive; In a bonding step, after the adhesive is discharged from the second nozzle onto the electrode, the first nozzle is pressed against the adhesive on the electrode so that a tip of the bonding wire comes into contact with the electrode. Wire bonding equipment.

Images