Semiconductor device and storage device

Abstract

Provided is a novel semiconductor device. This semiconductor device includes first to fourth transistors, a first capacitive element, and a second capacitive element. The first to fourth transistors each have a gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to a first electrode of the first capacitive element, the gate of the third transistor, and the gate of the fourth transistor. The first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the second terminal of the fourth transistor, and a first electrode of the second capacitive element. The gates of the first transistor and the second transistor are electrically connected to each other. Second electrodes of the first capacitive element and the second capacitive element are electrically connected to each other.

Description

Semiconductor device and storage device

[0001] One embodiment of the present invention relates to a semiconductor device and a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Therefore, examples of technical fields related to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, testing methods thereof, and methods of using thereof.

[0004] In recent years, development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories with various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include DRAM, SRAM, and flash memory.

[0005] Furthermore, a transistor using a metal oxide for a semiconductor layer in which a channel is formed (hereinafter also referred to as an "OS transistor") is known. Since an OS transistor has an extremely low off-state current, by using an OS transistor as a write transistor in a memory cell, a memory cell with excellent retention characteristics can be provided. For example, Non-Patent Document 1 discloses a NOSRAM (registered trademark) using an OS transistor.

[0006] T. Matsuzaki et al. , “A 128kb 4bit / Cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET Using Vt Cancel Write Method,”ISSCC Dig. Tech. Papers, 2015, pp. 306-307.

[0007] In a high-temperature environment, the off-state current of a transistor is likely to increase, making it difficult to retain data written in a semiconductor device functioning as a memory cell, which may result in a deterioration in the retention characteristics of the semiconductor device functioning as a memory cell.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device whose retention characteristics are not easily deteriorated even in a high-temperature environment, to provide a highly reliable semiconductor device, to provide a semiconductor device with low power consumption, or to provide a novel semiconductor device.

[0009] Note that the description of the above-mentioned problems does not preclude the existence of other problems. Those skilled in the art can naturally derive other problems from the description in the specification, drawings, claims, etc., and other problems can be extracted from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problems and other problems).

[0010] (1) One embodiment of the present invention is a semiconductor device including first to fourth transistors, a first capacitor, and a second capacitor, each of the first to fourth transistors having a gate, a first terminal, and a second terminal, each of the first capacitor and the second capacitor having a first electrode and a second electrode, the first terminal of the first transistor being electrically connected to the first electrode of the first capacitor, the gate of the third transistor, and the gate of the fourth transistor, the first terminal of the second transistor being electrically connected to the second terminal of the first transistor, the second terminal of the fourth transistor, and the first electrode of the second capacitor, the gates of the first transistor and the second transistor being electrically connected to each other, and the second electrodes of the first capacitor and the second capacitor being electrically connected to each other.

[0011] Also, in (1), for example, the gates of the first transistor and the second transistor are electrically connected to the first wiring, the second terminal of the second transistor is electrically connected to the second wiring, the first terminal of the third transistor is electrically connected to the third wiring, the second terminal of the third transistor is electrically connected to the fourth wiring, the first terminal of the fourth transistor is electrically connected to the fifth wiring, and the second electrodes of the first capacitance element and the second capacitance element are electrically connected to the sixth wiring.

[0012] In (1), each of the first, second, and fourth transistors preferably includes an oxide semiconductor in a semiconductor layer where a channel is formed, and the third transistor preferably includes silicon in a semiconductor layer where a channel is formed.

[0013] In (1), it is preferable to use vertical transistors as the first, second, and fourth transistors, and it is preferable to use a Fin-type transistor as the third transistor.

[0014] (2) Another aspect of the present invention is a semiconductor device including n (n is an integer of 3 or more) first transistors, second transistors, third transistors, and n capacitors, wherein each of the n first transistors, second transistors, and third transistors has a gate, a first terminal, and a second terminal, and each of the n capacitors has a first electrode and a second electrode, and the first terminal of a first first transistor is electrically connected to the first electrode of the first capacitor, the gate of the second transistor, and the gate of the third transistor, and the second terminal is electrically connected to the second terminal of the third transistor, the first terminal of the i-th (i is an integer greater than or equal to 2 and less than or equal to n-1) first transistor is electrically connected to the second terminal of the i-1th first transistor and the first electrode of the i-th capacitance element, the first terminal of the n-th first transistor is electrically connected to the second terminal of the n-1th first transistor and the first electrode of the n-th capacitance element, the gates of the n first transistors are electrically connected to each other, and the second electrodes of the n capacitance elements are electrically connected to each other.

[0015] Also, in (2), for example, the gate of each of the n first transistors is electrically connected to the first wiring, the second terminal of the nth first transistor is electrically connected to the second wiring, the first terminal of the second transistor is electrically connected to the third wiring, the second terminal of the second transistor is electrically connected to the fourth wiring, the first terminal of the third transistor is electrically connected to the fifth wiring, and the second electrode of each of the n capacitance elements is electrically connected to the sixth wiring.

[0016] In (2), each of the n first transistors and the n third transistors preferably includes an oxide semiconductor in a semiconductor layer where a channel is formed, and the second transistor preferably includes silicon in a semiconductor layer where a channel is formed.

[0017] In (2), it is preferable that the n first and third transistors are vertical transistors, and that the n second transistors are Fin-type transistors.

[0018] (3) Another embodiment of the present invention is a semiconductor device including first to third transistors and first to third capacitors, each of the first to third transistors having a gate, a first terminal, and a second terminal, each of the first to third capacitors having a first electrode and a second electrode, the first terminal of the first transistor being electrically connected to a first electrode of the first capacitor and a gate of the third transistor, the first terminal of the second transistor being electrically connected to a second terminal of the first transistor, a first electrode of the second capacitor, and a first electrode of the third capacitor, the gates of the first transistor and the second transistor being electrically connected to each other, and the second electrodes of the first capacitor and the second capacitor being electrically connected to each other.

[0019] Also, in (3), for example, the gates of the first transistor and the second transistor are electrically connected to the first wiring, the second terminal of the second transistor is electrically connected to the second wiring, the first terminal of the third transistor is electrically connected to the third wiring, the second terminal of the third transistor is electrically connected to the fourth wiring, the second electrodes of the first capacitance element and the second capacitance element are electrically connected to the sixth wiring, and the second electrode of the third capacitance element is electrically connected to the fifth wiring.

[0020] In (3), each of the first transistor and the second transistor preferably includes an oxide semiconductor in a semiconductor layer in which a channel is formed, and the third transistor preferably includes silicon in a semiconductor layer in which a channel is formed.

[0021] In (3), it is preferable to use vertical transistors as the first and second transistors, and it is preferable to use a Fin-type transistor as the third transistor.

[0022] Another embodiment of the present invention is a memory device including a memory cell array having a plurality of semiconductor devices according to (1), (2), or (3), and a peripheral circuit having a function of writing data to the memory cell array and a function of reading data from the memory cell array.

[0023] According to one embodiment of the present invention, a semiconductor device whose retention characteristics are less likely to deteriorate even in a high-temperature environment, a highly reliable semiconductor device, a low-power semiconductor device, or a novel semiconductor device can be provided.

[0024] Note that the description of the above effects does not preclude the existence of other effects. Those skilled in the art can naturally derive the other effects from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0025] 1A to 1D are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIG. 2 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 3 is a graph showing the relationship between the temperature of the operating environment of a transistor and the off-state current Ioff. FIGS. 4A and 4B are schematic perspective views illustrating an example of a configuration. FIGS. 5A and 5B are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIGS. 6A and 6B are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIGS. 7A and 7B are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIG. 8 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIGS. 9A and 9B are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIG. 10 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIGS. 11A and 11B are diagrams illustrating an example of a circuit configuration of a semiconductor device. FIG. 12 is a diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 13 is a timing chart illustrating an example of an operation of the semiconductor device. FIGS. 14A and 14B are circuit diagrams illustrating an example of an operation of the semiconductor device. FIG. 15 is a circuit diagram illustrating an example of an operation of the semiconductor device. FIGS. 16A and 16B are circuit diagrams illustrating an example of operation of a semiconductor device. FIGS. 17A and 17B are circuit diagrams illustrating an example of operation of a semiconductor device. FIG. 18 is a circuit diagram illustrating an example of operation of a semiconductor device. FIGS. 19A1 to 19A7 and 19B1 to 19B6 are diagrams illustrating electrical connections. FIGS. 20A to 20C are diagrams illustrating an example of a configuration of a transistor. FIGS. 21A to 21C are diagrams illustrating an example of a configuration of a transistor. FIGS. 22A and 22B are diagrams illustrating an example of a configuration of a transistor. FIGS. 23A and 23B are diagrams illustrating an example of a configuration of a transistor. FIGS. 24A to 24C are diagrams illustrating an example of a configuration of a transistor. FIGS. 25A to 25C are diagrams illustrating an example of a configuration of a transistor. FIGS. 26A to 26E are diagrams illustrating an example of a configuration of a transistor. FIGS. 27A and 27B are diagrams illustrating an example of a configuration of a transistor. FIGS. 28A to 28E are diagrams illustrating an example of a configuration of a transistor. FIG. 29 is a diagram illustrating an example of a configuration of a transistor. 30A to 30E are diagrams illustrating examples of the structure of a transistor, and FIGS. 31A to 31D are cross-sectional views illustrating a method for forming a metal oxide film.32A to 32D are cross-sectional views illustrating a method for forming a metal oxide film. FIGS. 33A and 33B are views illustrating an example configuration of a memory device. FIG. 34 is a view illustrating an example planar configuration of a semiconductor device. FIG. 35 is a view illustrating an example cross-sectional configuration of a semiconductor device. FIG. 36 is a view illustrating an example cross-sectional configuration of a semiconductor device. FIG. 37 is a block diagram illustrating a CPU. FIG. 38 is a block diagram illustrating a CPU. FIGS. 39A and 39B are perspective views of a semiconductor device. FIGS. 40A and 40B are perspective views of a semiconductor device. FIGS. 41A and 41B are views illustrating the hierarchy of a memory device. FIGS. 42A and 42B are views illustrating an example of electronic equipment, and FIGS. 42C to 42E are views illustrating an example of a mainframe computer. FIG. 43 is a view illustrating an example of space equipment. FIG. 44 is a view illustrating an example of a storage system applicable to a data center.

[0026] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0027] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0028] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0029] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, plan views, etc.

[0030] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0031] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0032] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0033] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0034] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may be interchanged with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0035] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0036] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0037] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions in a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region.

[0038] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region.

[0039] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a supplied voltage.

[0040] In this specification, one of the source or the drain of a transistor may be referred to as a "first terminal of the transistor", and the other of the source or the drain of the transistor may be referred to as a "second terminal of the transistor".

[0041] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0042] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchanged.

[0043] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0044] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in an electrically conductive state (a state in which electricity can be passed), and the "off state" of a transistor means that the source and drain of the transistor are in an electrically non-conductive state (a state that can be considered to be electrically disconnected).

[0045] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0046] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS. Unless otherwise specified, the transistors described in this specification are enhancement-type (normally-off) n-type transistors.

[0047] In addition, in drawings and the like, to clearly show the potential of wirings, electrodes, etc., "H" indicating a potential H or "L" indicating a potential L may be added adjacent to the wirings, electrodes, etc. Furthermore, "H" or "L" may be enclosed in a box next to wirings, electrodes, etc. where a potential change has occurred. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor. Furthermore, an arrow may be added to indicate the direction of current flow.

[0048] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, this includes an error of plus or minus 10%, unless otherwise specified.

[0049] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0050] Generally, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) interposed therebetween. In this specification, one of the two electrodes may be referred to as a first electrode, and the other of the two electrodes may be referred to as a second electrode. In this specification, the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, the term "capacitance element" includes a configuration in which two electrodes face each other with an insulator interposed therebetween, a configuration in which two wires face each other with an insulator interposed therebetween, or a configuration in which two wires are arranged with an insulator interposed therebetween.

[0051] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0052] In this specification, "connection" includes, as an example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, as examples, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0053] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0054] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 19A1 and 19A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where there is a time when a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 19A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0055] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 19A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 19A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0056] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 19A6 and 19A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 19A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 19A6 and 19A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0057] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0058] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 19B1, 19B2, and 19B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 19B4 and 19B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 19B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0059] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0060] 1A is a circuit diagram of a semiconductor device 10A according to one embodiment of the present invention. The semiconductor device 10A functions as, for example, a memory element (also referred to as a "memory cell").

[0061] 1A includes two transistors M1, two capacitance elements Cs, a transistor M2, and a transistor M3. In FIG. 1A and other figures, the first transistor M1 is indicated as transistor M1[1], and the second transistor M1 is indicated as transistor M1[2]. The first capacitance element Cs is indicated as capacitance element Cs[1], and the second capacitance element Cs is indicated as capacitance element Cs[2].

[0062] In the semiconductor device 10A shown in FIG. 1A, one of the source and drain of the transistor M1[1] is connected to one electrode of the capacitor Cs[1], the gate of the transistor M2, and the gate of the transistor M3. One of the source and drain of the transistor M1[2] is connected to one electrode of the capacitor Cs[2] and the other of the source and drain of the transistor M1[1]. The other of the source and drain of the transistor M1[2] is connected to a wiring WBL. The gates of the transistors M1[1] and M1[2] are connected to a wiring WWL.

[0063] One of the source and the drain of the transistor M3 is connected to a wiring PL, and the other of the source and the drain is connected to one of the source and the drain of the transistor M1[2], one electrode of the capacitor Cs[2], and the other of the source and the drain of the transistor M1[1]. A potential H is supplied to the wiring PL.

[0064] One of the source and drain of the transistor M2 is connected to the wiring RBL, and the other of the source and drain of the transistor M2 is connected to the wiring RWL. The other electrodes of the capacitors Cs[1] and Cs[2] are connected to the wiring COM. A fixed potential such as GND or a common potential (e.g., 0 V) ​​is supplied to the wiring COM.

[0065] A region where one of the source or drain of the transistor M1[1], one electrode of the capacitor Cs[1], the gate of the transistor M2, and the gate of the transistor M3 are connected and always at the same potential is called a node ND[1]. A region where one of the source or drain of the transistor M1[2], one electrode of the capacitor Cs[2], and the other of the source or drain of the transistor M3 are connected and always at the same potential is called a node ND[2].

[0066] 1B, the semiconductor device 10A may include n transistors M1 (n is an integer of 3 or greater), n capacitance elements Cs, a transistor M2, and a transistor M3. In FIG. 1B and other figures, the nth transistor M1 is indicated as transistor M1[n], and the nth capacitance element Cs is indicated as capacitance element Cs[n]. The ith transistor M1 (i is an integer of 2 to n-1) is indicated as transistor M1[i], and the ith capacitance element Cs is indicated as capacitance element Cs[i].

[0067] 1B, the gates of the n transistors M1 are connected to a wiring WWL, and the other electrodes of the n capacitance elements Cs are connected to a wiring COM.

[0068] In the semiconductor device 10A shown in FIG. 1B, one of the source and the drain of the transistor M1[i] is connected to one electrode of the capacitor Cs[i] and the other of the source and the drain of the transistor M1[i-1].

[0069] In the semiconductor device 10A shown in FIG. 1B, one of the source and the drain of the transistor M1[n] is connected to one electrode of the capacitor Cs[n] and the other of the source and the drain of the transistor M1[n-1].

[0070] 1B , a region where one of the source or drain of the transistor M1[i], one electrode of the capacitor Cs[i], and the other of the source or drain of the transistor M1[i-1] are connected and always at the same potential is called a node ND[i]. Similarly, a region where one of the source or drain of the transistor M1[n], one electrode of the capacitor Cs[n], and the other of the source or drain of the transistor M1[n-1] are connected and always at the same potential is called a node ND[n].

[0071] 1A and 1B, the transistors included in the semiconductor device 10A are n-type transistors, but one embodiment of the present invention is not limited thereto. P-type transistors can be used for some or all of the transistors included in the semiconductor device 10A. Normally-off transistors are easier to realize with p-type transistors than with n-type transistors, and circuit design is relatively easy. Meanwhile, n-type transistors have higher field-effect mobility than p-type transistors, and therefore the operating speed of the semiconductor device 10A can be increased. For example, n-type transistors can be used for the transistors M1 and M3, and a p-type transistor can be used for the transistor M2.

[0072] In addition, the transistor according to one embodiment of the present invention can have various structures. For example, a planar type, a Fin type, a top-gate type, a bottom-gate type, etc. In addition, a MOS transistor, a junction transistor, a bipolar transistor, etc. can be used as the transistor according to one embodiment of the present invention.

[0073] The semiconductor layer of the transistor of the semiconductor device 10A can be made of various semiconductor materials such as elemental semiconductors such as silicon and germanium, compound semiconductors such as silicon carbide and gallium arsenide, and oxide semiconductors, which are a type of compound semiconductor.

[0074] 1A and 1B, a transistor having a back gate can be used as the transistor included in the semiconductor device 10A. Fig. 1C shows an example of a circuit symbol for a transistor having a back gate.

[0075] The gate and back gate of the transistor are arranged to sandwich a channel formation region of the semiconductor layer. Both the gate and the back gate are formed of conductive layers. Note that a semiconductor layer with low resistivity can be used as the conductive layer. The back gate can function in the same way as the gate. When the gate is used to control the on and off states of the transistor, the potential of the back gate can be set to the same potential as the gate. Furthermore, the back gate can be set to GND or any other potential.

[0076] For example, when turning on a transistor, supplying a potential that turns the transistor on to both the gate and the back gate increases the on-state current compared to supplying only one to the gate. Connecting the gate and back gate, as shown in Figure 1D, makes it possible to maintain the gate and back gate at the same potential. Furthermore, controlling the back gate potential independently of the gate allows for adjustment of the transistor's threshold voltage.

[0077] Furthermore, a fixed potential such as GND can be supplied to the back gate. Since the gate and the back gate are formed of a conductive layer or the like, sandwiching the channel formation region of the semiconductor layer between the gate and the back gate makes it difficult for an electric field generated outside the transistor to act on the channel formation region (also referred to as an "electric field shielding effect"). Therefore, providing a back gate in a transistor stabilizes the operation of the transistor. Furthermore, providing a back gate in a transistor reduces variations in characteristics among multiple transistors. Providing a back gate in a transistor can improve the reliability of the transistor. Therefore, the reliability of a semiconductor device including the transistor can be improved. Note that the electric field shielding effect can be obtained even when one or both of the gate and the back gate are electrically floating (also referred to as a "floating state"), but the effect can be enhanced by supplying a potential to the gate and the back gate.

[0078] The semiconductor device 10A has a function of writing data supplied from the wiring WBL to the node ND[1] by turning on the transistor M1. The semiconductor device 10A also has a function of retaining the data written to the node ND[1] by turning off the transistor M1. Therefore, the transistor M1 may be referred to as a "write transistor" or a "retention transistor."

[0079] Furthermore, the semiconductor device 10A can switch the on and off states of the transistor M2 depending on the data held in the node ND[1]. Furthermore, the potential of the wiring RBL can be changed depending on the state of the transistor M2, thereby reading out the data held in the node ND. Therefore, the transistor M2 may be referred to as a "read transistor" or an "amplifying transistor."

[0080] As described above, the transistor M1 functions as a storage transistor that stores data written to the node ND[1] (here, charge corresponding to a specific potential). Therefore, an OS transistor is preferably used as the transistor M1. The oxide semiconductor used for the semiconductor layer in which the channel of the OS transistor is formed has a band gap of 2 eV or more. Therefore, the off-state current of the OS transistor is significantly smaller than that of a transistor using silicon for the semiconductor layer in which the channel is formed (also referred to as a "Si transistor"). Specifically, the off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 pA (1×10 −１２ A) Below, 1aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less or 1yA (1 x 10 −２４ A) It can be as follows:

[0081] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, their off-state current hardly increases even in environmental temperatures of 100° C. or higher and 200° C. or lower. Furthermore, their on-state current is unlikely to decrease even in environmental temperatures of 100° C. or higher and 200° C. or lower. A semiconductor device including an OS transistor operates stably even in high-temperature environments and exhibits high reliability.

[0082] Furthermore, the electrical characteristics of an OS transistor are less susceptible to change due to radiation such as cosmic rays, which means that soft errors caused by radiation are less likely to occur, and semiconductor devices including an OS transistor have high reliability.

[0083] In this manner, by using an OS transistor as the transistor M1, the charge held in the node ND[1] is less likely to be reduced, and fluctuations in the potential of the node ND[1] can be suppressed. Therefore, data written to the node ND[1] can be held for a long period of time.

[0084] Furthermore, when the potential difference between the source and drain of the transistor M1[1] increases, the off-state current of the transistor M1[1] tends to increase, particularly in a high-temperature environment.

[0085] The semiconductor device 10A according to one embodiment of the present invention has a configuration in which the node ND[2] and the wiring PL are connected through the source and drain of the transistor M3. The connection of the node ND[2] and the wiring PL through the source and drain of the transistor M3 prevents an increase in the potential difference between the nodes ND[1] and ND[2] and suppresses potential fluctuations of the node ND[1].

[0086] For example, when a potential H is held at node ND[1], the potential H can be supplied from wiring PL to node ND[2] via transistor M3, thereby preventing an increase in the potential difference between the source and drain of transistor M1[1].

[0087] Furthermore, when the potential L is held at the node ND[1], the transistor M3 is turned off, which stops the supply of the potential H from the wiring PL to the node ND[2] and suppresses the potential rise at the node ND[1]. This prevents the potential difference between the source and drain of the transistor M1[1] from increasing.

[0088] In this way, data written to the node ND[1] can be held for a longer period of time. The transistor M3 has a function of supplying a potential to the node ND[2] and a function of holding the potential of the node ND[2]. Similar to the transistor M1, an OS transistor is preferably used as the transistor M3.

[0089] 2, the semiconductor device 10A can have multiple transistors M3. In FIG. 2, the first transistor M3 is indicated as transistor M3[1], the second transistor M3 is indicated as transistor M3[2], and the i-th transistor M3 is indicated as transistor M3[i]. The semiconductor device 10A shown in FIG. 2 has n-1 transistors M3.

[0090] 1A and 1B, the gate, source, and drain of transistor M3[1] are connected in the same manner as transistor M3 shown in FIG. 1A and FIG. 1B, and therefore the description thereof is omitted. In the semiconductor device 10A shown in FIG. 2, the gate of transistor M3[i] is connected to one of the source and drain of transistor M1[i]. Therefore, the gate of transistor M3[i] is connected to node ND[i]. In addition, one of the source and drain of transistor M3[i] is connected to wiring PL, and the other is connected to one of the source and drain of transistor M1[i+1] (not shown).

[0091] 2, the potential difference between adjacent nodes ND can be prevented from increasing at all nodes ND, and therefore the semiconductor device 10A shown in FIG. 2 can retain data written to node ND[1] for a longer period of time than the semiconductor device 10A shown in FIG. 1B.

[0092] Furthermore, the semiconductor device 10A according to one embodiment of the present invention can retain data written to the node ND[1] for a long period of time, and therefore can significantly reduce the frequency of performing a refresh operation for the data written to the node ND. In other words, the semiconductor device 10A according to one embodiment of the present invention can substantially eliminate the need for a refresh operation. Therefore, the semiconductor device 10A according to one embodiment of the present invention can reduce the power required for the refresh operation.

[0093] Furthermore, in the semiconductor device 10A, data is rewritten by charging and discharging the node ND[1], and therefore, in principle, there is no limit to the number of times that data can be rewritten. Note that a memory cell formed using an OS transistor may be referred to as an "OS memory." Also, a memory device including a memory cell formed using an OS transistor may be referred to as an "OS memory."

[0094] 3 shows the relationship between the temperature of the operating environment (also referred to as "ambient temperature") of a Si transistor and an OS transistor and the off-state current Ioff. The horizontal axis of the graph in FIG. 3 represents the reciprocal of absolute temperature. Thus, the left side of the horizontal axis indicates a higher ambient temperature, and the right side indicates a lower ambient temperature. Note that "RT" in FIG. 3 indicates that the ambient temperature is room temperature (25° C. to 27° C.).

[0095] The vertical axis of the graph shown in Fig. 3 represents the value of the off-state current Ioff in logarithm. The off-state current Ioff in Fig. 3 is the current that flows between the source and drain of the transistor M1[1] when, for example, the potential of the node ND[1] of the semiconductor device 10A shown in Fig. 1A is VDD, the potential of the wiring WBL is VSS, and the transistor M1[1] is in an off state.

[0096] 3 corresponds to, for example, the current flowing between the node ND[1] and the wiring WBL when the transistor M1[1] is off. In the graph shown in FIG. 3, a profile 91 shows the temperature dependence of the off-current Ioff (here, the current flowing between the node ND[1] and the wiring WBL) when Si transistors are used for the transistors M1[1] and M1[2] of the semiconductor device 10A shown in FIG. 1A. A profile 92 shows the temperature dependence of the off-current Ioff when OS transistors are used for the transistors M1[1] and M1[2] of the semiconductor device 10A shown in FIG. 1A. A profile 93 shows the temperature dependence of the off-current Ioff when OS transistors are used for all of the n transistors M1 of the semiconductor device 10A shown in FIG. 1B.

[0097] 3, the off-state current Ioff is smaller when OS transistors are used for the transistors M1[1] and M1[2] (profile 92) than when Si transistors are used for the transistors M1[1] and M1[2] (profile 91) both at room temperature and at high temperatures. Furthermore, by using an OS transistor as the transistor M1 and connecting three or more transistors M1 in series, the off-state current Ioff can be further reduced (profile 93).

[0098] The transistor M2, which functions as a read transistor, can be a transistor having a higher mobility than the transistor M1. For example, a Si transistor can be used as the transistor M2. Since a Si transistor has a higher mobility than an OS transistor, the speed at which data stored in the semiconductor device 10A can be read can be increased.

[0099] For example, by using OS transistors as the transistors M1 and M3 and a Si transistor as the transistor M2, a highly reliable memory cell capable of high-speed operation can be realized.

[0100] Furthermore, in the semiconductor device 10A, it is preferable that the transistors M1 and M3 are stacked on the transistor M2. By stacking the transistors, the area occupied by the semiconductor device 10A can be reduced. Fig. 4A shows a schematic perspective view of the semiconductor device 10A. Fig. 4B shows a schematic perspective view for explaining the configuration of the semiconductor device 10A in more detail.

[0101] 4A and 4B includes an element layer 60 superimposed on an element layer 50. The element layer 50 includes a transistor M2, and the element layer 60 includes a transistor M1 and a transistor M3. For example, when a Si transistor is used as the transistor M2, it is preferable to use a single-crystal silicon substrate as the element layer 50 and form the transistor M1 on the silicon substrate. By forming the channel formation region of the Si transistor used as the transistor M2 on the silicon substrate, a Si transistor having a single-crystal semiconductor in the channel formation region and having a high operating speed can be formed.

[0102] Also, for example, an SOI (Silicon on Insulator) substrate or the like can be used as the element layer 50. Examples of SOI substrates that can be used include a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that occur in the surface layer, a Smart Cut method in which a semiconductor substrate is cleaved by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, and an ELTRAN method (registered trademark: Epitaxial Layer Transfer). Si transistors fabricated using an SOI substrate have reduced parasitic capacitance and can achieve high-speed operation.

[0103] Note that elements or circuits other than the transistor M2 can be provided in the element layer 50. For example, a driver circuit for supplying signals to the wirings WWL, WBL, and the like can be provided in the element layer 50.

[0104] Furthermore, when thin film transistors such as OS transistors are used as the transistors M1 and M3 included in the element layer 60, the element layer 60 can be easily provided overlapping the element layer 50. In addition, as described above, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in characteristics. Therefore, even if the transistors M1 and M3 including OS transistors are provided overlapping the transistor M2 including a Si transistor, they are less susceptible to the heat generated by the transistor M2, and high reliability can be achieved. Note that, like the element layer 50, elements or circuits other than the transistors M1 and M3 can be provided in the element layer 60.

[0105] Furthermore, the same semiconductor material can be used for the semiconductor layers of the transistors M1, M2, and M3. For example, when the transistors M1, M2, and M3 are OS transistors, the semiconductor device 10A can be provided only in the element layer 60. By using the same semiconductor material for the semiconductor layers of the transistors M1, M2, and M3, the transistors M1 and M2 can be formed simultaneously in the same process. This improves the productivity of the semiconductor device 10A.

[0106] <Variation 1> A semiconductor device 10B, which is a variation of the semiconductor device 10A, is shown in FIG. 5A. For example, as in the semiconductor device 10B shown in FIG. 5A, a transistor M4 may be added to the configuration of the semiconductor device 10A. In the semiconductor device 10B shown in FIG. 5A, the other of the source or the drain of the transistor M2 is connected to one of the source or the drain of the transistor M4. The other of the source or the drain of the transistor M4 is connected to a wiring SL, and the gate of the transistor M4 is connected to a wiring RWL.

[0107] When multiple semiconductor devices 10B functioning as memory cells are arranged in a matrix, the state of other memory cells may affect the read operation of data stored in one memory cell. By providing transistor M4, the effect on the memory cell being read can be suppressed. Furthermore, by providing transistor M4, a specific memory cell can be more accurately selected and the data stored in that memory cell can be read. Therefore, transistor M4 is sometimes referred to as a "selection transistor." By providing transistor M4, the operation of semiconductor device 10B can be stabilized, and the reliability of semiconductor device 10B can be improved.

[0108] <Variation 2> FIG. 5B shows a semiconductor device 10C, which is a variation of the semiconductor device 10B. The semiconductor device 10C shown in FIG. 5B differs from the semiconductor device 10B in that it does not include the transistor M4 and uses a transistor with a back gate as the transistor M2. In the semiconductor device 10C, the other of the source and drain of the transistor M2 is connected to the wiring SL, and the back gate is connected to the wiring RWL. By using a transistor with a back gate as the transistor M2, the transistor M2 can function as a selection transistor. Since the formation of the transistor M4 is not necessary, reliability can be improved without increasing the occupied area. Note that the semiconductor device 10C is also a variation of the semiconductor device 10A shown in FIG. 1A.

[0109] Furthermore, when a transistor having a back gate is used as the transistor M2, the back gate can be connected to one of the source or drain of the transistor M1[1], one electrode of the capacitor Cs[1], and the gate of the transistor M3, and the gate can be connected to the wiring RWL.

[0110] In particular, when the EOT (equivalent oxide thickness) of the insulating layer functioning as a gate insulating layer on the back-gate side is smaller than the EOT of the insulating layer functioning as a gate insulating layer on the gate side, connecting the gate of the transistor M2 to the wiring RWL makes it easy to switch the transistor M2 between on and off even when the amplitude of the potential supplied to the wiring RWL is reduced. Therefore, the power consumption of the semiconductor device 10C can be reduced. In this case, a region where one of the source and drain of the transistor M1[1], one electrode of the capacitor Cs[1], the gate of the transistor M3, and the back-gate of the transistor M2 are connected functions as the node ND[1].

[0111] 6A shows a semiconductor device 10D, which is a modification of the semiconductor device 10A shown in FIG. 1A. The semiconductor device 10D differs from the semiconductor device 10A shown in FIG. 1A in that the other of the source and the drain of the transistor M2 is connected to a wiring SL, and the other electrodes of the capacitors Cs[1] and Cs[2] are connected to a wiring RWL.

[0112] By configuring the semiconductor device 10D, data can be read without being affected by the states of other memory cells, even without providing the transistor M4, which stabilizes the operation of the semiconductor device 10D and improves the reliability of the semiconductor device 10D.

[0113] <Modification 4> FIG. 6B shows a semiconductor device 10E, which is a modification of the semiconductor device 10A shown in FIG. 1A. The semiconductor device 10E shown in FIG. 6B has a configuration in which the capacitance element Cs[2] is removed from the semiconductor device 10A shown in FIG. 1A. If the capacitance value of the capacitance element Cs[1] can be ensured to be sufficient for the function required of a memory cell, it is possible to omit the capacitance element Cs[2]. By not providing the capacitance element Cs[2], the area occupied by the semiconductor device 10E can be reduced. This allows for an increase in the degree of integration of the semiconductor device 10F. Furthermore, the memory density of a memory device using the semiconductor device 10E can be increased.

[0114] <Variation 5> Figure 7A shows a semiconductor device 10F, which is a variation of the semiconductor device 10A shown in Figure 1A. The semiconductor device 10F has a configuration in which the capacitance element Cs[1] is removed from the semiconductor device 10A shown in Figure 1A. If a parasitic capacitance of a capacitance sufficient for the function required of a memory cell occurs at the node ND[1], it is possible to omit the capacitance element Cs[1]. Furthermore, for example, the gate capacitance of the transistor M2 and the gate capacitance of the transistor M3 can be used as the capacitance element Cs[1].

[0115] By not providing the capacitive element Cs[1], the area occupied by the semiconductor device 10F can be reduced, thereby increasing the degree of integration of the semiconductor device 10F and increasing the memory density of a memory device using the semiconductor device 10F.

[0116] <Modification 6> Fig. 7B shows a semiconductor device 10G, which is a modification of the semiconductor device 10F. The semiconductor device 10G shown in Fig. 7B is also a modification of the semiconductor device 10E shown in Fig. 6B. Therefore, the semiconductor device 10G is also a modification of the semiconductor device 10A shown in Fig. 1A.

[0117] The semiconductor device 10G has a configuration in which the capacitor Cs[2] is removed from the semiconductor device 10F. If parasitic capacitance of a capacitance sufficient for the function required of a memory cell occurs at the node ND[1] and the node ND[2], the capacitor Cs[1] and the capacitor Cs[2] do not need to be provided. By not providing the capacitor Cs[1] and the capacitor Cs[2], the area occupied by the semiconductor device 10G can be reduced. Furthermore, the formation of the wiring COM is also unnecessary. Therefore, the integration degree of the semiconductor device 10G can be increased. Furthermore, the memory density of a memory device using the semiconductor device 10G can be increased.

[0118] 8 shows a semiconductor device 10H, which is a modification of the semiconductor device 10A shown in Fig. 1A. The semiconductor device 10H differs from the semiconductor device 10A shown in Fig. 1A in that a transistor M4 is provided between one of the source and the drain of the transistor M3 and a wiring PL.

[0119] In the semiconductor device 10H, one of the source and drain of the transistor M4 is connected to the wiring PL, and the other is connected to one of the source and drain of the transistor M3. The gate of the transistor M4 is connected to one of the source and drain of the transistor M4. Therefore, the transistor M4 functions as a diode. In the semiconductor device 10H, one of the source and drain of the transistor M4 corresponds to the anode, and the other corresponds to the cathode.

[0120] For example, consider a case where the potential H is held at each of the nodes ND[1] and ND[2], and the power supply to the semiconductor device 10H is stopped, causing the potential of the wiring PL to drop. By providing a diode between the transistor M3 and the wiring PL, with the wiring PL serving as the anode and the transistor M3 serving as the cathode, the potential drop of the node ND[2] can be suppressed. Therefore, the potential difference between the nodes ND[1] and ND[2] is suppressed from increasing, and data written to the node ND[1] can be retained for a long period of time even if the power supply to the semiconductor device 10H is stopped.

[0121] 9A shows a semiconductor device 10I that is a modification of the semiconductor device 10A shown in Fig. 1A. The semiconductor device 10I differs from the semiconductor device 10A shown in Fig. 1A in that it includes a capacitive element Cd[1] instead of the transistor M3.

[0122] One electrode of the capacitor Cd[1] is connected to the node ND[2] of the semiconductor device 10I. That is, one electrode of the capacitor Cd[1] is connected to the other of the source or the drain of the transistor M1[1], one of the source or the drain of the transistor M1[2], and one electrode of the capacitor Cs[2]. The other electrode of the capacitor Cd[1] is connected to the wiring PL.

[0123] A fixed potential such as GND or a common potential (e.g., 0 V) ​​is supplied to the wiring PL. As described above, in this embodiment, a potential H is supplied to the wiring PL. Note that the potential supplied to the other electrode of the capacitance element Cd[1] can also be GND or a common potential (e.g., 0 V). Therefore, the other electrode of the capacitance element Cd[1] can also be connected to the wiring COM.

[0124] By increasing the number of capacitors connected to the node ND[2], the potential of the node ND[2] can be held for a long period of time. In other words, by increasing the capacitance of the capacitors connected to the node ND[2], the potential of the node ND[2] can be held for a long period of time.

[0125] 9B , the semiconductor device 10I may include n transistors M1, n capacitors Cs, m capacitors Cd (where m is an integer greater than or equal to 2 and less than or equal to n−1), and a transistor M2. In FIG. 9B , similar to FIG. 1B , the nth transistor M1 is denoted as transistor M1[n], and the nth capacitor Cs is denoted as capacitor Cs[n]. The ith transistor M1 (where i is an integer greater than or equal to 2 and less than or equal to n−1) is denoted as transistor M1[i], and the ith capacitor Cs is denoted as capacitor Cs[i]. In FIG. 9B , the mth capacitor Cd is denoted as capacitor Cd[m], and the kth capacitor Cd (where k is an integer greater than or equal to 1 and less than or equal to m−1) is denoted as capacitor Cd[k].

[0126] 9B , the gates of the n transistors M1 are connected to a wiring WWL, the other electrodes of the n capacitance elements Cs are connected to a wiring COM, and the other electrodes of the m capacitance elements Cd are connected to a wiring PL.

[0127] In the semiconductor device 10I shown in Figure 9B, one of the source or drain of the transistor M1[i] is connected to one electrode of the capacitance element Cs[i], one electrode of the capacitance element Cd[k], and the other of the source or drain of the transistor M1[i-1].

[0128] For example, when i is 3, one of the source and drain of transistor M1[3] (not shown) is connected to one electrode of capacitor Cs[3] (not shown) and the other of the source and drain of transistor M1[2]. Also, since k is i-1, one of the source and drain of transistor M1[3] is connected to one electrode of capacitor Cd[2] (not shown). Note that the other of the source and drain of transistor M1[3] is connected to one electrode of capacitor Cd[3] (not shown).

[0129] In the semiconductor device 10I shown in Figure 9B, one of the source and drain of the transistor M1[n] is connected to one electrode of the capacitor Cs[n], one electrode of the capacitor Cd[m], and the other of the source and drain of the transistor M1[n-1].

[0130] 9B , a region where one of the source or drain of the transistor M1[i], one electrode of the capacitor Cs[i], one electrode of the capacitor Cd[k], and the other of the source or drain of the transistor M1[i-1] are connected and always at the same potential is called a node ND[i]. Similarly, a region where one of the source or drain of the transistor M1[n], one electrode of the capacitor Cs[n], one electrode of the capacitor Cd[m], and the other of the source or drain of the transistor M1[n-1] are connected and always at the same potential is called a node ND[n].

[0131] In addition, in order to maintain the potential of the node ND[1], it is preferable that the capacitor Cs[1] be a capacitor with a small leakage current. On the other hand, by using capacitors with a larger leakage current than the capacitor Cs[1] as the capacitors Cs and Cd other than the capacitor Cs[1], a decrease in the potential of the node ND[2] due to the off-current of the transistor M1[2] can be suppressed.

[0132] For example, when transistors M1[1] and M1[2] are off, a potential H (e.g., VDD) is supplied to the wiring PL, a potential L (e.g., VSS) is supplied to the wiring COM, the potential of the wiring WBL is potential L, and the potential of the node ND[2] is potential H, as shown in Figure 10, a current Ib flows from the node ND[2] to the wiring WBL via the source and drain of the transistor M1[2].

[0133] Furthermore, by using a capacitor with a large leakage current as the capacitor Cs[2], the current Ia is likely to flow from the node ND[2] to the wiring COM via the capacitor Cs[2]. Furthermore, by using a capacitor with a large leakage current as the capacitor Cd[1], the current Ic is likely to flow from the wiring PL to the node ND[2] via the capacitor Cd[1].

[0134] At this time, the potential of node ND[2] can be maintained by setting the leakage currents of capacitors Cs[2] and Cd[1] so that Ic = Ia + Ib holds. In other words, the potential difference between the source and drain of transistor M1[1] can be prevented from increasing. This suppresses fluctuations in the potential of node ND[1], enabling data written to node ND[1] to be retained for a longer period of time.

[0135] Furthermore, when the value of current Ib is 1 / 5 or less, preferably 1 / 10 or less, of the values ​​of current Ia and current Ic, for example, by making the values ​​of current Ia and current Ic equal, the potential of node ND[2] can be set to (potential H+potential L) / 2, which is an intermediate potential between potential H and potential L. In other words, the potential of node ND[2] can be controlled by adjusting the magnitude of the leakage current of current Ia and current Ic.

[0136] Furthermore, when data is written from the wiring WBL to the node ND[1], if the potential of the wiring WBL and the potential of the node ND[1] are different, a current Iw flows between the wiring WBL and the node ND[1]. For example, if the potential of the wiring WBL is higher than the potential of the node ND[1], a current Iw flows from the wiring WBL to the node ND[1]. If the potential of the wiring WBL is lower than the potential of the node ND[1], a current Iw flows from the node ND[1] to the wiring WBL.

[0137] To ensure reliable writing of data from wiring WBL to node ND[1], the values ​​of current Ia and current Ic are preferably 1 / 5 or less of the maximum value of current Iw, more preferably 1 / 10 or less, and even more preferably 1 / 50 or less.

[0138] 11A shows a semiconductor device 10J, which is a modification of the semiconductor device 10I shown in Fig. 9A. The semiconductor device 10J differs from the semiconductor device 10I shown in Fig. 9A in that it has a resistive element Rs[1] instead of the capacitive element Cs[2] and a resistive element Rd[1] instead of the capacitive element Cd[1].

[0139] Each of the resistor elements Rs and Rd has two terminals. One terminal of the resistor element Rs[1] and one terminal of the resistor element Rd[1] are connected to the node ND[2] of the semiconductor device 10J. That is, one terminal of the resistor element Rs[1] is connected to the other of the source or drain of the transistor M1[1], one of the source or drain of the transistor M1[2], and one terminal of the resistor element Rd[1]. The other terminal of the resistor element Rs[1] is connected to the wiring COM. The other terminal of the resistor element Rd[1] is connected to the wiring PL.

[0140] 11B, the semiconductor device 10J may include n transistors M1, m resistors Rs, m resistors Rd, a transistor M2, and a capacitor Cs[1]. In FIG. 11B, similar to FIG. 9B, the nth transistor M1 is indicated as transistor M1[n], the mth resistor Rs is indicated as resistor Rs[m], and the mth resistor Rd is indicated as resistor Rd[m]. Furthermore, the ith transistor M1 is indicated as transistor M1[i], the kth resistor Rs is indicated as resistor Rs[k], and the kth resistor Rd is indicated as resistor Rd[k].

[0141] 11B, the gates of the n transistors M1 are connected to a wiring WWL, the other terminals of the m resistor elements Rs are connected to a wiring COM, and the other terminals of the m resistor elements Rd are connected to a wiring PL.

[0142] In the semiconductor device 10J shown in Figure 11B, one of the source or drain of transistor M1[i] is connected to one terminal of resistor element Rs[k], one terminal of resistor element Rd[k], and the other of the source or drain of transistor M1[i-1].

[0143] For example, when i is 3, one of the source and drain of transistor M1[3] (not shown) is connected to one terminal of resistor Rs[2] (not shown), one terminal of resistor Rd[2] (not shown), and the other of the source and drain of transistor M1[2]. The other of the source and drain of transistor M1[3] is connected to one terminal of resistor Rs[3] (not shown), one terminal of resistor Rd[3] (not shown), and one of the source and drain of transistor M1[4].

[0144] In the semiconductor device 10J shown in Figure 11B, one of the source or drain of transistor M1[n] is connected to one terminal of resistor element Rs[m], one terminal of resistor element Rd[m], and the other of the source or drain of transistor M1[n-1].

[0145] 11B , a region where one of the source or drain of transistor M1[i], one terminal of resistor Rs[k], one terminal of resistor Rd[k], and the other of the source or drain of transistor M1[i-1] are connected and always at the same potential is called node ND[i]. Similarly, a region where one of the source or drain of transistor M1[n], one terminal of resistor Rs[m], one terminal of resistor Rd[m], and the other of the source or drain of transistor M1[n-1] are connected and always at the same potential is called node ND[n].

[0146] By connecting the resistor Rs[1] and the resistor Rd[1] to the node ND[2], a potential drop at the node ND[2] due to the off-state current of the transistor M1[2] can be suppressed. For example, when the transistors M1[1] and M1[2] are off, a potential H (e.g., VDD) is supplied to the wiring PL, a potential L (e.g., VSS) is supplied to the wiring COM, the potential of the wiring WBL is the potential L, and the potential of the node ND[2] is the potential H, as shown in FIG. 12, a current Ib flows from the node ND[2] to the wiring WBL via the source and drain of the transistor M1[2]. Also, a current Ia flows through the resistor Rs[1], and a current Ic flows through the resistor Rd[1].

[0147] At this time, the resistance values ​​of resistor elements Rs[1] and Rd[1] are set so that Ic = Ia + Ib holds, thereby maintaining the potential of node ND[2]. In other words, the potential difference between the source and drain of transistor M1[1] can be prevented from increasing. This suppresses fluctuations in the potential of node ND[1], enabling data written to node ND[1] to be retained for a longer period of time.

[0148] For example, by making the resistance values ​​of the resistor elements Rs[1] and Rd[1] equal, the potential of the node ND[2] can be set to (potential H+potential L) / 2, which is an intermediate potential between potential H and potential L. In other words, by adjusting the resistance values ​​of the resistor elements Rs[1] and Rd[1], the potential of the node ND[2] can be controlled.

[0149] As described above, when writing data from the wiring WBL to the node ND[1], if the potential of the wiring WBL and the potential of the node ND[1] are different, a current Iw flows between the wiring WBL and the node ND[1]. Therefore, in the semiconductor device 10J, in order to more reliably write data from the wiring WBL to the node ND[1], each of the current Ia and the current Ic is preferably 1 / 5 or less of the maximum value of the current Iw, more preferably 1 / 10 or less, and even more preferably 1 / 50 or less.

[0150] <Operation Example> Next, an example of a data write operation and an example of a data read operation of the semiconductor device 10A shown in FIG. 1A will be described. Here, an example of an operation to write data "1" to the semiconductor device 10A, an example of an operation to write data "0" to the semiconductor device 10A, and an example of an operation to read data "1" from the semiconductor device 10A will be described. Furthermore, it is assumed that normally-off n-type transistors are used as the transistors M1, M2, and M3 included in the semiconductor device 10A. FIG. 13 is a timing chart for explaining an example of an operation of the semiconductor device 10A. FIGS. 14A and 14B, 15, 16A and 16B, 17A and 17B, and 18 are circuit diagrams for explaining an example of an operation of the semiconductor device 10A.

[0151] [Data Write Operation] First, an example of an operation for writing data "1" to the semiconductor device 10A will be described. As a state immediately before the data "1" write operation, the potentials of the wiring WWL, the wiring WBL, the node ND[1], and the node ND[2] are set to potential L, and the potentials of the wiring RWL and the wiring RBL are set to potential H (see FIG. 13). Also, the potential L is supplied to the wiring COM, and the potential H is supplied to the wiring PL.

[0152] In the period T11, an H potential is supplied to the wiring RWL, the wiring WWL, and the wiring WBL (see FIGS. 13 and 14A). Then, the transistors M1[1] and M1[2] are turned on, and the potentials of the nodes ND[1] and ND[2] become H potentials. Therefore, the H potential is written to the node ND[1] as a potential corresponding to data "1." More precisely, an amount of charge is supplied to the node ND[1] such that the potential of the node ND[1] becomes H potential.

[0153] The gate, source, and drain of the transistor M2 are all at the same potential (potential H in this case), so the transistor M2 is in an off state. Similarly, the gate, source, and drain of the transistor M3 are all at the same potential, so the transistor M3 is also in an off state.

[0154] In the period T12, a potential L is supplied to the wiring WWL. Then, the transistors M1[1] and M1[2] are turned off, and the nodes ND[1] and ND[2] are brought into a floating state. Therefore, the data (charge) written to the node ND[1] is retained (see FIGS. 13 and 14B).

[0155] As described above, an OS transistor has an extremely low off-state current. By using an OS transistor as the transistor M1, data written to the node ND[1] can be held for a long period of time. Therefore, the node ND[1] does not need to be refreshed, and the power consumption of the semiconductor device 10A can be reduced.

[0156] In addition, an OS transistor has a higher drain breakdown voltage than a Si transistor. Therefore, by using an OS transistor as the transistor M1, the potential held at the node ND[1] can be increased. That is, the potential difference between the potential H and the potential L can be increased. Therefore, multi-level data or analog data can be held at the node ND[1].

[0157] Furthermore, by connecting multiple transistors M1 in series as the transistor M1 provided between the node ND[1] and the wiring WBL, the off-state current can be further reduced, thereby improving the data retention capability of the semiconductor device 10A. Furthermore, by providing multiple capacitors Cs in the semiconductor device 10A, the data retention capability of the semiconductor device 10A can be improved. The semiconductor device 10A includes multiple transistors M1 and multiple capacitors Cs, allowing data written to the node ND[1] to be retained for a longer period of time. In particular, data written to the node ND[1] can be retained for a longer period of time even in a high-temperature environment of 100° C. or higher, where the off-state current is likely to increase.

[0158] Furthermore, by using an OS transistor as the transistor M3, the potential of the node ND[2] can be held for a long period of time. By holding the potential of the node ND[2], the potential difference between the nodes ND[1] and ND[2] can be prevented from increasing, and fluctuations in the potential of the node ND[1] can be suppressed.

[0159] Next, the operation of the semiconductor device 10A will be described when a potential L is supplied to the wiring WBL and the potential of the node ND[2] is reduced while both the node ND[1] and the node ND[2] are held at the potential H. In the period T13, the potential L is supplied to the wiring WBL, the off-state current of the transistor M1[2] increases, and the potential of the node ND[2] is reduced (see FIGS. 13 and 15).

[0160] When the potential of the node ND[2] drops to a potential (potential H-Vth) that is lower than the potential H by the threshold voltage (Vth) of the transistor M3, the transistor M3 is turned on. When the transistor M3 is turned on, a potential is supplied to the node ND[2] from the wiring PL via the source and drain of the transistor M3. Because the potential H is supplied to the wiring PL, a potential that is lower than the potential H by the threshold voltage (Vth) of the transistor M3 is supplied to the node ND[2]. In other words, the potential H-Vth is supplied to the node ND[2].

[0161] Therefore, the potential difference between the source and drain of the transistor M1 does not exceed Vth. Furthermore, even if leakage occurs between the source and drain due to the supply of a potential H-Vth to the node ND[2], the potential of the node ND[1] does not fall below the potential H-Vth. Since the gate of the transistor M2 is connected to the node ND[1], if the potential H-Vth is a potential that can turn on the transistor M2 during data reading, the data can be read as "1." Therefore, the semiconductor device 10A according to one embodiment of the present invention can retain data written to the node ND[1] for a long period of time.

[0162] Next, an example of an operation of writing data "0" to the semiconductor device 10A will be described. In a state immediately before the operation of writing data "0", the potential of the wiring WWL is the potential L, and the potentials of the wiring WBL, the node ND[1], the node ND[2], the wiring RWL, and the wiring RBL are the potential H.

[0163] In the period T21, an H potential is supplied to the wiring WWL, and a potential L is supplied to the wiring WBL (see FIGS. 13 and 16A). Then, the transistors M1[1] and M1[2] are turned on, and the potentials of the nodes ND[1] and ND[2] become the potential L. Therefore, the potential L is written to the node ND[1] as a potential corresponding to data "0." More precisely, an amount of charge is supplied to the node ND[1] such that the potential of the node ND[1] becomes the potential L.

[0164] Furthermore, since the potential of the node ND[1] becomes the potential L, both the transistor M2 and the transistor M3 are turned off.

[0165] In the period T22, a potential L is supplied to the wiring WWL. Then, the transistors M1[1] and M1[2] are turned off, and the nodes ND[1] and ND[2] are brought into a floating state. Therefore, the data (charge) written to the node ND[1] is retained (see FIGS. 13 and 16B).

[0166] [Read Operation] Next, a description will be given of an example of a read operation of data held in the semiconductor device 10A. In this embodiment, a description will be given of an example of a read operation when a potential H corresponding to data "1" is held in the semiconductor device 10A.

[0167] In a period T31, the wiring RBL is precharged to a potential H. That is, the wiring RBL is kept in a floating state at the potential H (see FIGS. 13 and 17A).

[0168] Next, in a period T32, a potential L is supplied to the wiring RWL (see FIGS. 15 and 17B). When the potential of the node ND[1] is a potential H corresponding to data "1," the potential of the wiring RWL changes from the potential H to the potential L, turning on the transistor M2. When the transistor M2 is turned on, the wiring RBL and the wiring RWL are brought into electrical continuity, and the potential of the wiring RBL changes from the potential H to the potential L.

[0169] Note that when the node ND[1] holds a potential L corresponding to data "0," the transistor M2 does not turn on even when the potential L is supplied to the wiring RWL. In this case, the potential of the wiring RBL remains at a potential H. Therefore, by detecting a change in the potential of the wiring RBL when the potential L is supplied to the wiring RWL, the data held in the semiconductor device 10A can be read.

[0170] Next, in a period T33, a potential H is supplied to the wirings RWL and RBL (see FIGS. 15 and 18). When the potentials of the wirings RWL and RBL become the potential H, the transistor M2 is turned off.

[0171] The semiconductor device 10 according to one embodiment of the present invention (semiconductor device 10A, semiconductor device 10B, semiconductor device 10C, semiconductor device 10D, semiconductor device 10E, semiconductor device 10F, semiconductor device 10G, semiconductor device 10H, semiconductor device 10I, and semiconductor device 10J) functions as a memory cell that writes charge to node ND[1] via transistor M1. Therefore, a high voltage, which is required in, for example, a flash memory, is not required, and high-speed write operations can be realized. Furthermore, since charge is not injected into or extracted from a floating gate or a charge trap layer, the semiconductor device 10 has virtually no limit on the number of write and read operations. Unlike flash memories, the semiconductor device 10 does not experience instability due to an increase in electron trap centers even during repeated rewrite operations. The semiconductor device 10 according to one embodiment of the present invention exhibits less degradation and higher reliability than conventional flash memories. In particular, the use of an OS transistor as transistor M1 enables long-term data retention even in high-temperature environments, thereby achieving high reliability even in high-temperature environments.

[0172] Furthermore, the semiconductor device 10 according to one aspect of the present invention does not involve structural changes at the atomic level, unlike magnetic memories or resistance change memories, etc. Therefore, the semiconductor device 10 according to one aspect of the present invention has superior rewrite endurance to magnetic memories and resistance change memories.

[0173] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0174] Embodiment 2 In this embodiment, a transistor that can be used for a semiconductor device according to one embodiment of the present invention will be described.

[0175] 20A is a plan view of a transistor 200A that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200A is an example of a planar transistor. In this specification, a planar transistor refers to a transistor in which a source electrode and a drain electrode are located at the same height or approximately the same height and a current flowing through a semiconductor has a lateral component.

[0176] Fig. 20B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 20A. Fig. 20C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in Fig. 20A. Note that some elements are omitted from the plan view of Fig. 20A for clarity. Some elements may also be omitted from other plan views.

[0177] The transistor 200A has an insulating layer 202 over a substrate 201 and a semiconductor layer 203 over the insulating layer 202. The transistor 200A also has an insulating layer 204 over the insulating layer 202 and the semiconductor layer 203. The transistor 200A also has a conductive layer 205 over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions that overlap with each other with the insulating layer 204 interposed therebetween.

[0178] The semiconductor layer 203 has a region 203a, a channel formation region 203b, and a region 203c. The region 203a functions as either a source region or a drain region. The region 203c functions as the other of the source region and the drain region. In the semiconductor layer 203, a region overlapping with the conductive layer 205 functions as the channel formation region 203b. Therefore, the conductive layer 205 functions as the gate electrode of the transistor 200A. The insulating layer 204 functions as a gate insulating layer of the transistor 200A.

[0179] The length of the channel formation region 203b in the X direction is the channel length L of the transistor 200A (see FIG. 20B), and the length of the channel formation region 203b in the Y direction is the channel width W of the transistor 200A (see FIG. 20C).

[0180] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203a of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203c of the semiconductor layer 203.

[0181] Furthermore, a conductive layer 208a is provided over the insulating layer 206 and the opening 207a, and a conductive layer 208b is provided over the insulating layer 206 and the opening 207b. The conductive layer 208a is connected to the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is connected to the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as a drain electrode of the transistor 200A, and the conductive layer 208b functions as a source electrode of the transistor 200A.

[0182] In addition, an insulating layer 209 is provided over the insulating layer 206 and the conductive layer 208 (the conductive layer 208a and the conductive layer 208b).

[0183] 21A is a plan view of a transistor 200B that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200B is a variation of the transistor 200A. To avoid repetition of description, differences between the transistor 200B and the transistor 200A will be mainly described.

[0184] Fig. 21B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 21A. Fig. 21C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in Fig. 21A.

[0185] The transistor 200B differs from the transistor 200A in that a conductive layer 219 is provided between the substrate 201 and the insulating layer 202. The conductive layer 219 functions as a backgate electrode of the transistor 200B. Therefore, the conductive layer 219 overlaps with the channel formation region 203b. The conductive layer 219 preferably extends beyond the end of the channel formation region 203b. That is, the conductive layer 219 preferably covers the channel formation region 203b. Covering the channel formation region 203b with the conductive layer 219 can enhance the electric field shielding effect described in the above embodiment.

[0186] 22A is a plan view of a transistor 200C that can be used in a semiconductor device according to one embodiment of the present invention, and FIG. 22B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in FIG.

[0187] The transistor 200C includes an insulating layer 202 over a substrate 201 and a conductive layer 255 over the insulating layer 202. The transistor 200C also includes an insulating layer 257 over the conductive layer 255, an insulating layer 258 over the insulating layer 257, and an insulating layer 259 over the insulating layer 258. Note that in this specification, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as an insulating layer 256 or a spacer layer. The transistor 200C also includes a conductive layer 261 over the insulating layer 259.

[0188] An opening 262 penetrating the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region overlapping with part of the conductive layer 255. A semiconductor layer 263 is provided to cover the opening 262.

[0189] The semiconductor layer 263 has a region overlapping with the bottom of the opening 262 and a region overlapping with the side surface of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 inside the opening 262. The semiconductor layer 263 also has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 inside the opening 262.

[0190] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 with the insulating layer 264 interposed therebetween.

[0191] The insulating layer 264 and the conductive layer 265 each have a region overlapping with the opening 262. The insulating layer 264 and the conductive layer 265 each have a region overlapping with the inside of the opening 262. Inside the opening 262, the semiconductor layer 263 has a region overlapping with the conductive layer 265 with the insulating layer 264 interposed therebetween and a region overlapping with a side surface of the opening 262 (a side surface of the insulating layer 256).

[0192] Furthermore, an insulating layer 266 is provided on the insulating layer 264. Note that the upper surface of the insulating layer 266 is preferably flat. Alternatively, it is preferable that the heights (positions in the Z direction) of the upper surfaces of the insulating layer 266 and the conductive layer 265 are the same or approximately the same. For example, the flatness of the upper surface of the insulating layer 266 can be improved by performing chemical mechanical polishing (CMP) processing or the like. Furthermore, by performing CMP processing, the positions of the upper surfaces of the insulating layer 266 and the conductive layer 265 can be made to be the same or approximately the same. By performing CMP processing, unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0193] When an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0194] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable to use a material containing oxygen and in which hydrogen is reduced for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 in which hydrogen is reduced makes it difficult for the semiconductor layer 263 to become n-type. Furthermore, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 containing oxygen reduces oxygen vacancies in the semiconductor layer 263, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0195] In the case where an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen that is released by heating. A material that releases oxygen by heating is a material that releases oxygen in an amount of 1.0×10 converted into oxygen atoms as determined by thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 400°C.

[0196] Furthermore, when a material containing excess oxygen is used for the insulating layer 258, a material through which oxygen is not easily transmitted may be used for the insulating layers 257 and 259. Examples of the material through which oxygen is not easily transmitted include an oxide containing one or both of aluminum and hafnium, and a nitride of silicon. By using a material through which oxygen is not easily transmitted for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is not easily released into the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure in which an insulating layer containing silicon and oxygen (the insulating layer 258) is provided between two insulating layers containing silicon and nitrogen (the insulating layer 257 and the insulating layer 259) is preferable.

[0197] When an oxide semiconductor is used for the semiconductor layer 263, by using a material containing hydrogen for the insulating layers 257 and 259, hydrogen is supplied to a region of the semiconductor layer 263 in contact with the insulating layer 257 and a region of the semiconductor layer 263 in contact with the insulating layer 259, and each region of the semiconductor layer 263 becomes n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0198] The conductive layer 261 functions as one of the source electrode and the drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode and the drain electrode of the transistor 200C. The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source and the drain of the transistor 200C are arranged at different heights. In other words, the source and the drain of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0199] In the above configuration, in the transistor 200C, which is a VFET, the length of the side surface of the insulating layer 158 as viewed from the X direction or the Y direction is the channel length L (channel length L1) (see FIG. 22B). Therefore, the channel length L of the transistor 200C is determined depending on the thickness t1 of the insulating layer 258.

[0200] Furthermore, it is preferable to use a material that does not contain hydrogen or that contains very little hydrogen for the insulating layers 257 and 259. For example, silicon nitride or silicon nitride oxide containing very little hydrogen can be used. In this case, the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259 are not made n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 functions as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 functions as the other of the source region and the drain region. The region of the semiconductor layer 263 in contact with the insulating layer 258 functions as a channel formation region.

[0201] In this case, the sum of the lengths of the side surfaces of the insulating layers 257, 258, and 259 as viewed from the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 200C is determined according to the total thickness t2 of the insulating layers 257, 258, and 259. In this manner, the transistor 200C has a channel formation region that extends along the side surface of the insulating layer 256.

[0202] Furthermore, because the semiconductor layer 263 is provided in the opening 262, the perimeter of the opening 262 as viewed in the Z direction corresponds to the channel width W of the transistor 200C (see FIG. 22A ). The perimeter can be determined, for example, at a position halfway between the thickness t1 or the thickness t2 of the insulating layer 258. If necessary, the perimeter of any position on the opening 262 can be set to the channel width W. For example, the perimeter of the bottom of the opening 262 can be set to the channel width W, or the perimeter of the top of the opening 262 can be set to the channel width W. Although FIG. 22A shows the outline (planar shape) of the opening 262 as viewed in the Z direction as a circle, this is not limiting. For example, the outline of the opening 262 as viewed in the Z direction can be an ellipse, a rectangle, or the like.

[0203] In the memory device of one embodiment of the present invention, the channel length L is preferably smaller than at least the channel width W. In one embodiment of the present invention, the channel length L is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

[0204] In order to improve the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the side surface of the opening 262, i.e., the taper angle θ of each of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, is set to 45° or more and less than 90°, preferably 50° or more and 75° or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of the layer (see FIG. 22B ).

[0205] A vertical transistor can occupy a smaller area than a transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane (also called a "horizontal transistor"). Therefore, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0206] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 256 or 258. Therefore, the channel length of the transistor can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-state current of the transistor 200C, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0207] 23A is a plan view of a transistor 200D that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200D is a variation of the transistor 200C. To avoid repetition of description, differences between the transistor 200D and the transistor 200C will be mainly described.

[0208] FIG. 23B is a cross-sectional view taken along the dashed line A1-A2 in FIG. 23A.

[0209] The transistor 200D includes an insulating layer 258a and an insulating layer 258b between the insulating layer 257 and the insulating layer 259, and a conductive layer 267 between the insulating layer 258a and the insulating layer 258b. The insulating layer 258a and the insulating layer 258b can be formed using a material and a method similar to those of the insulating layer 258. The opening 262 of the transistor 200D is provided to penetrate the conductive layer 261, the insulating layer 259, the insulating layer 258b, the conductive layer 267, the insulating layer 258a, and the insulating layer 257 in a region overlapping with part of the conductive layer 255.

[0210] In the transistor 200D, an insulating layer 268 is provided along the side surface of the opening 262. Inside the opening 262, the insulating layer 268 has a region overlapping with a side surface of the conductive layer 261, a region overlapping with a side surface of the insulating layer 259, a region overlapping with a side surface of the insulating layer 258b, a region overlapping with a side surface of the conductive layer 267, a region overlapping with a side surface of the insulating layer 258a, and a region overlapping with a side surface of the insulating layer 257.

[0211] Furthermore, inside the opening 262, the semiconductor layer 263 in the transistor 200D has a region that overlaps with a side surface of the conductive layer 261 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 259 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 258b via the insulating layer 268, a region that overlaps with a side surface of the conductive layer 267 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 258a via the insulating layer 268, and a region that overlaps with a side surface of the insulating layer 257 via the insulating layer 268.

[0212] When the conductive layer 265 is used as a gate electrode, the conductive layer 267 functions as a back gate electrode. When the conductive layer 267 is used as a gate electrode, the conductive layer 265 functions as a back gate electrode. One of the insulating layer 264 and the insulating layer 268 functions as a gate insulating layer, and the other functions as a back gate insulating layer. The insulating layer 268 can be formed using a material and a method similar to those of the insulating layer 264.

[0213] <Transistor Structure Example 5> Fig. 24A is a plan view of a transistor 200E that can be used for a semiconductor device of one embodiment of the present invention. Fig. 24B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Fig. 24A . Fig. 24C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in Fig. 24A . Note that Fig. 24B is a cross-sectional view of the transistor 200E in the channel length direction, and Fig. 24C is a cross-sectional view of the transistor 200E in the channel width direction.

[0214] 24A to 24C , the transistor 200E includes a semiconductor layer 520a disposed on the substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, the insulating layer 580, and the insulating layer 550. 24B and 24C , the top surface of the conductive layer 560 is substantially aligned with the top surfaces of the insulating layer 550, the insulating layer 554, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layers 520a, 520b, and 520c may be collectively referred to as the semiconductor layer 520. The conductive layers 542a and 542b may be collectively referred to as the conductive layer 542.

[0215] 24A to 24C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the semiconductor layer 520c and the insulating layer 580. The insulating layer 554 is in contact with the side surface of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0216] Although the transistor 200E has a three-layer structure including the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be used. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may have a stacked structure of two or more layers.

[0217] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the semiconductor layer 520b, and the second metal oxide has a composition similar to that of the semiconductor layer 520a.

[0218] Here, the conductive layer 560 functions as the gate electrode of the transistor, and the conductive layers 542a and 542b function as source and drain electrodes, respectively. As described above, the conductive layer 560 is formed so as to fill the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200E, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200E. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0219] 24A to 24C , the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 in the transistor 200E has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0220] The transistor 200E includes an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520a is disposed on the insulating layer 524.

[0221] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200E. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the insulating layer 554, the semiconductor layer 520c, and the insulating layer 580.

[0222] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layers 522, 554, and 574 preferably have a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like). For example, the insulating layers 522, 554, and 574 preferably have a lower hydrogen permeability than the insulating layers 524, 550, and 580. The insulating layers 522 and 554 preferably have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulating layers 522 and 554 preferably have a lower oxygen permeability than the insulating layers 524, 550, and 580.

[0223] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from being mixed into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0224] 24B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) connected to the transistor 200E and functioning as a plug is provided. Note that an example is shown in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 functioning as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 24B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0225] Here, the height of the top surface of the conductive layer 545 and the height of the top surface of the insulating layer 581 can be approximately the same. Note that although the transistor 200E shows a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 can also be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0226] Furthermore, the thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this way, removing the low-resistance region located between the conductive layers 542a and 542b on the top surface of the semiconductor layer 520b can prevent a channel from being formed in the region.

[0227] Next, the detailed structure of the transistor 200E that can be used in the semiconductor device of one embodiment of the present invention will be described.

[0228] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0229] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom and sidewalls of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The top surface of the conductive layer 505b is lower than the top surfaces of the conductive layer 505a and the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is approximately the same as the height of the top surface of the conductive layer 505a and the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0230] In the case where an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c can be formed of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ A conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is used.

[0231] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layers 505a and 505c, it is possible to prevent impurities such as hydrogen contained in the conductive layer 505b from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0232] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode.

[0233] The conductive layer 505 is preferably provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 24C, the conductive layer 505 preferably extends to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0234] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0235] The conductive layer 505 can be used as wiring by extending it beyond the end of the semiconductor layer 520. However, the present invention is not limited to this, and a structure in which a conductive layer functioning as wiring is provided under the conductive layer 505 can also be used.

[0236] The insulating layer 514 is preferably formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side. Therefore, the insulating layer 514 is preferably formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side. ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., copper atoms are difficult to penetrate), or an insulating material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is difficult to penetrate).

[0237] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200E side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing toward the substrate side of the insulating layer 514.

[0238] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0239] When the conductive layer 560 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0240] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200E is improved.

[0241] 24C , the insulating layer 524 may have a thinner film thickness in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b than in other regions. The insulating layer 524 preferably has a film thickness in the region that does not overlap with the insulating layer 554 and the semiconductor layer 520b that allows sufficient diffusion of the oxygen.

[0242] As the insulating layer 522, like the insulating layer 514, a material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side is used. For example, the insulating layer 522 is made of a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be prevented from entering the transistor 200E from the outside.

[0243] Furthermore, the insulating layer 522 is preferably made of a material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the oxygen is less likely to permeate). For example, the insulating layer 522 is made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, so that oxygen diffusing from the semiconductor layer 520 toward the substrate can be reduced. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0244] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used as the insulating layer 522. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200E.

[0245] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to these insulating layers. Alternatively, these insulating layers can be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can be stacked on the above insulating layers. For example, the insulating layer 522 can have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0246] The insulating layer 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ It is preferable to use an insulating layer containing a so-called high-k material such as (BST) in a single layer or a laminated layer. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0247] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0248] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0249] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. For example, when the semiconductor layer 520 includes at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a is made higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In is made higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c can use the metal oxide used for the semiconductor layer 520a or the semiconductor layer 520b.

[0250] The energy of the conduction band minimum of the semiconductor layer 520a and the semiconductor layer 520c is preferably higher than the energy of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c is preferably lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c is preferably higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In is preferably higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0251] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, it is preferable that the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c is low.

[0252] Specifically, the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low defect level density. For example, when the semiconductor layer 520b is an In—Ga—Zn oxide, the semiconductor layers 520a and 520c can be made of In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide, or the like. The semiconductor layer 520c can also have a stacked structure. For example, a stacked structure of In—Ga—Zn oxide and Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of In—Ga—Zn oxide and gallium oxide on the In—Ga—Zn oxide can be used. In other words, a stacked structure of In—Ga—Zn oxide and an oxide not containing In can be used as the semiconductor layer 520c.

[0253] Specifically, the semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. The semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. The semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:1 [atomic ratio] or the vicinity thereof, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:5 [atomic ratio] or the vicinity thereof, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and gallium oxide.

[0254] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect state density at the interface between the semiconductor layers 520a and 520b and the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200E to achieve high on-state current and high frequency characteristics. Note that if the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the semiconductor layers 520b and 520c, it is expected that the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, since the semiconductor layer 520c has a stacked structure and an oxide not containing In is located above the stacked structure, it is possible to suppress In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating layer, and diffusion of In can cause poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, a highly reliable semiconductor device can be provided.

[0255] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or that maintains its conductivity even when it absorbs oxygen.

[0256] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200E. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0257] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0258] The insulating layer 550 is formed using an insulating material in which the concentration of impurities such as water or hydrogen is reduced, similarly to the insulating layer 524. The thickness of the insulating layer 550 is 1 nm to 20 nm.

[0259] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0260] Although the conductive layer 560 is shown as a two-layer structure in FIGS. 24A to 24C, a single-layer structure or a stacked structure of three or more layers can also be used.

[0261] The conductive layer 560a is formed of the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive layer having a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0262] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0263] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0264] 24B and 24C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200E, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200E, and improves its frequency characteristics.

[0265] Like the insulating layer 514, the insulating layer 554 is made of an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200E from the insulating layer 580 side. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 24B and 24C , the insulating layer 554 is provided in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. This structure can prevent hydrogen contained in the insulating layer 580 from entering the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520a, the semiconductor layer 520b, and the insulating layer 524.

[0266] Furthermore, an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., oxygen is less likely to permeate) is used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0267] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, thereby preventing the transistor from becoming normally on.

[0268] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0269] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0270] The insulating layer 574, like the insulating layer 514, is formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulating layer 580 from above. The insulating layer 574 is formed using an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like, for example.

[0271] 24A to 24C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524 and the like.

[0272] The conductive layers 545a and 545b are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layers 545a and 545b are provided opposite to each other with the conductive layer 560 interposed therebetween. Note that the height of the top surfaces of the conductive layers 545a and 545b is preferably flush with the top surface of the insulating layer 581.

[0273] Note that an insulating layer 541a is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the opening, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the opening, and the conductive layer 545b is in contact with the conductive layer 542b.

[0274] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b can have a stacked structure of two or more layers.

[0275] When the conductive layer 545 has a stacked structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used for the conductive layers in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be prevented from entering the semiconductor layer 520 through the conductive layers 545a and 545b.

[0276] The insulating layers 541a and 541b may be, for example, insulating layers that can be used for the insulating layer 554. The insulating layers 541a and 541b are provided in contact with the insulating layer 554, and therefore can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0277] <Transistor Configuration Example 6> A modification of the transistor 200E shown in FIGS. 24A to 24C is shown in FIG. 25. FIG. 25A is a plan view of a transistor F which is a modification of the transistor 200E. FIG. 25B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 25A. FIG. 25C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in FIG. 25A. Since the transistor F is a modification of the transistor 200E, differences between the transistor F and the transistor 200E will be mainly described.

[0278] The transistor F has a structure in which the semiconductor layer 520c and the conductive layer 505c are removed from the structure of the transistor 200E. Reducing the number of components of the transistor reduces production costs. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, improving manufacturing yield.

[0279] Furthermore, the transistor F has a region where the insulating layer 554 and the insulating layer 522 are in contact with each other outside the semiconductor layer 520, and the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used for the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing to the outside through the insulating layer 524 but also prevents excessive oxygen from being supplied to the semiconductor layer 520 from the insulating layer 524 side.

[0280] Note that an insulating layer is preferably provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Aluminum oxide, hafnium oxide, or the like is preferably used for the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the semiconductor layer 520 to the insulating layer 550, excessive supply of oxygen from the insulating layer 550 to the semiconductor layer 520, oxidation of the conductive layer 542, and the like.

[0281] <Transistor Configuration Example 7> FIG. 26A is a plan view of a transistor 200G that can be used in a semiconductor device of one embodiment of the present invention. FIG. 26B is a schematic perspective view of the transistor 200G. FIGS. 26C to 26E are cross-sectional views of the transistor 200G. FIG. 26C is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 26A and is also a cross-sectional view of the transistor 200G in the channel width direction (Y direction). FIG. 26D is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 26A and is also a cross-sectional view of the transistor 200G in the channel width direction. FIG. 26E is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 26A and is also a cross-sectional view of the transistor 200G in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that some components are omitted from the plan view of FIG. 26A and the schematic perspective view of FIG. 26B. Also, FIG. 27A shows an enlarged view of the vicinity of the conductive layer 260 in FIG. 26E. Also, FIG. 27B shows an enlarged view of the vicinity of the semiconductor layer 230 in FIG. 26C.

[0282] The transistor 200G according to this embodiment includes an insulating layer 215 on a substrate (not shown), an insulating layer 216 on the insulating layer 215, an insulating layer 221 on the insulating layer 216, an insulating layer 222 on the insulating layer 221, a semiconductor layer 230 on the insulating layer 222, conductive layers 242a and 242b on the semiconductor layer 230 and the insulating layer 222, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 (conductive layer 260a and conductive layer 260b) on the insulating layer 250. Note that in this specification, the conductive layer 242a and the conductive layer 242b may be collectively referred to as the conductive layer 242.

[0283] An insulating layer 275 is provided on the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 275. The insulating layer 250 and the conductive layer 260 are provided inside a first opening that penetrates the insulating layer 280 and the insulating layer 275 and reaches the semiconductor layer 230. In a plan view, the first opening has a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. Therefore, in a plan view, the insulating layer 250 and the conductive layer 260 provided inside the first opening also have a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. The conductive layer 260 also functions as wiring. The insulating layer 250 has a region in contact with the semiconductor layer 230 within the first opening. Furthermore, an insulating layer 282 is provided on the insulating layer 280 and the conductive layer 260. Furthermore, an insulating layer 283 is provided on the insulating layer 282.

[0284] Furthermore, insulating layer 241a is provided in contact with the inner wall of the second opening, which penetrates insulating layers 283, 282, 280, and 275 to reach conductive layer 242a, and conductive layer 245a is provided in contact with insulating layer 241a. Conductive layer 245a has a region in contact with conductive layer 242a at the bottom of the first opening.

[0285] Furthermore, insulating layer 241b is provided in contact with the inner wall of the third opening, which penetrates insulating layers 283, 282, 280, and 275 to reach conductive layer 242b, and conductive layer 245b is provided in contact with insulating layer 241b. Conductive layer 245b has a region in contact with conductive layer 242b at the bottom of the second opening.

[0286] In this specification, the conductive layers 245a and 245b may be collectively referred to as conductive layers 245. The insulating layers 241a and 241b may be collectively referred to as insulating layers 241.

[0287] The semiconductor layer 230 includes a channel formation region of the transistor 200G. The conductive layer 260 has a region that functions as a gate electrode of the transistor 200G. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 200G. In the transistor 200G, a region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel formation region. A region of the conductive layer 260 that overlaps with the semiconductor layer 230 functions as a gate electrode. A region of the insulating layer 250 where the insulating layer 250 and the semiconductor layer 230 overlap and where the insulating layer 250 and the conductive layer 260 overlap functions as a gate insulating layer.

[0288] The conductive layer 242a has a region functioning as one of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245a functions as a plug connected to the conductive layer 242a. The conductive layer 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245b functions as a plug connected to the conductive layer 242b.

[0289] The semiconductor layer 230 is formed on the insulating layer 222. As shown in FIG. 27B , the semiconductor layer 230 has a shape with a high aspect ratio when viewed cross-sectionally in the channel width direction. Therefore, the semiconductor layer 230 can also be said to have a fin-like shape. A transistor whose semiconductor layer is fin-shaped is also called a "fin transistor," "fin transistor," or "fin transistor."

[0290] Specifically, a Fin-type transistor is a transistor in which, in a cross-sectional view in the channel width direction (Y direction), the channel formation region of the semiconductor layer has two regions (two surfaces) extending in the Z direction, and has a shape in which a length H (described later) is greater than a length Lx (described later). In a cross-sectional view in the channel width direction, a shape in which the length H is greater than the length Lx is preferable because it allows the channel width per unit area to be increased.

[0291] In this specification, the maximum length of the semiconductor layer 230 in the Y direction in the channel formation region is defined as length Lx, and the maximum length of the semiconductor layer 230 in the channel formation region in a direction perpendicular to the surface on which it is formed (e.g., the top surface of the insulating layer 222) is defined as length H.

[0292] The length Lx can also be considered to be the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, "length Lx" can be read as "width Lx." The length H can also be considered to be the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, "length H" can be read as "height H."

[0293] The ratio of the length H to the length Lx is referred to as the aspect ratio of the semiconductor layer 230. The aspect ratio of the semiconductor layer 230 is preferably as large as possible without causing the semiconductor layer 230 to collapse during the manufacturing process of the transistor 200G. The aspect ratio of the semiconductor layer 230 is preferably greater than 1 and less than 400, more preferably greater than 2 and less than 100, more preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 is preferably greater than 1 and less than 400 times the length Lx of the semiconductor layer 230, more preferably greater than 2 and less than 100 times, more preferably greater than 5 and less than 40 times, and even more preferably greater than 10 and less than 20 times. Alternatively, for example, the height H may be greater than 2 and less than 10 times the length Lx. For example, the length Lx is preferably 5 nm to 100 nm, more preferably 5 nm to 50 nm, and even more preferably 10 nm to 30 nm. Furthermore, for example, the height H is preferably 50 nm to 2000 nm, and more preferably 100 nm to 1000 nm. For example, the height H can be 50 nm to 100 nm.

[0294] 27B , in a cross-sectional view in the channel width direction, the angle θ formed between the formation surface of the semiconductor layer 230 on the insulating layer 222 and the side surface of the semiconductor layer 230 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0295] An insulating layer 250, a conductive layer 260, and a conductive layer 242 are provided to cover the semiconductor layer 230 having such an aspect ratio. In the transistor 200G, as shown in FIG. 27B , portions of the insulating layer 250 and the conductive layer 260 are provided so as to sandwich the semiconductor layer 230 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 230 and the conductive layer 260 are provided facing each other with the insulating layer 250 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230 each function as a channel formation region. Therefore, compared to when the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 200G is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 230.

[0296] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 200G can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the area occupied by the transistor 200G. This allows for miniaturization or high integration of the semiconductor device.

[0297] Furthermore, as shown in FIG. 27B and other figures, it is preferable that the upper portion of the semiconductor layer 230 has a curved shape. Such a curved shape can prevent defects such as voids from forming in the insulating layer 250 and the conductive layer 242 near the upper portion of the semiconductor layer 230. Note that in FIG. 27B and other figures, a symmetrical structure is shown in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 230, but the present invention is not limited to this. For example, an asymmetrical structure may also be used in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 230.

[0298] When an oxide semiconductor is used as the semiconductor layer 230, as shown in FIGS. 27A and 27B, a configuration including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c disclosed in the third embodiment can be applied.

[0299] 27A and 27B , when an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250c on the insulating layer 250b, and an insulating layer 250d on the insulating layer 250c. In this case, the insulating layer 250a and the insulating layer 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0300] Examples of insulating layers having the function of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulating layer 250a and the insulating layer 250c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0301] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 250a and the insulating layer 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250a and the insulating layer 250c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.

[0302] For the insulating layer 250a and the insulating layer 250c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0303] In this embodiment, an aluminum oxide film is used as the insulating layer 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulating layer 250a in contact with the semiconductor layer 230, hydrogen contained in the semiconductor layer 230 and the like can be more effectively captured and fixed to the insulating layer 250a.

[0304] In this embodiment, hafnium oxide is used as the insulating layer 250 c. By providing the insulating layer 250 c between the insulating layer 250 b and the insulating layer 250 d, hydrogen contained in the insulating layer 250 b and the like can be more effectively captured and fixed.

[0305] Next, the insulating layer 250b is preferably an insulating layer that is stable to heat, such as silicon oxide or silicon oxynitride. The silicon oxide film used as the insulating layer 250b is preferably formed by a PEALD method.

[0306] In order to suppress oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260, it is preferable to provide a barrier insulating layer against oxygen near each of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 250a, the insulating layer 250d, the insulating layer 250c, and the insulating layer 275.

[0307] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulating layer having barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulating layer. Furthermore, for example, an insulating layer having barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulating layer.

[0308] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulating layer 250a, the insulating layer 250c, the insulating layer 250d, and the insulating layer 275 each preferably have a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulating layer against oxygen.

[0309] The insulating layer 250a preferably has a barrier property against oxygen. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has a region in contact with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200G.

[0310] The insulating layer 250a is provided in contact with the top surface and side surfaces of the semiconductor layer 230 and the top surface of the insulating layer 222. The insulating layer 250a has a barrier property against oxygen, which can suppress oxygen from being released from the channel formation region of the semiconductor layer 230 when heat treatment or the like is performed. Therefore, oxygen vacancies can be reduced in the semiconductor layer 230.

[0311] Furthermore, by providing the insulating layer 250a, it is possible to suppress the supply of an excessive amount of oxygen from the insulating layer 280 to the semiconductor layer 230, and to supply an appropriate amount of oxygen to the semiconductor layer 230. Therefore, it is possible to suppress the source region and the drain region from being excessively oxidized, which would result in a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200G.

[0312] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and is therefore suitable for the insulating layer 250a.

[0313] The insulating layer 250d also preferably has a barrier property against oxygen. The insulating layer 250d is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260 and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250d. In this case, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0314] Furthermore, the insulating layer 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0315] The insulating layer 275 also preferably has a barrier property against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. The insulating layer 275 is provided in contact with the side surface of the conductive layer 242, the side surface of the semiconductor layer 230, and the top surface of the insulating layer 222. This structure can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242. Therefore, it is possible to prevent the conductive layer 242 from being oxidized by the oxygen contained in the insulating layer 280 and its resistivity from increasing. The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. For example, it is preferable to use silicon nitride as the insulating layer 275. In this case, the insulating layer 275 is an insulating layer containing at least nitrogen and silicon.

[0316] In order to suppress a decrease in the hydrogen concentrations in the source and drain regions in the semiconductor layer 230, it is preferable to provide a barrier insulating layer against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulating layer against hydrogen is, for example, the insulating layer 275.

[0317] Examples of the barrier insulating layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulating layer 275 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulating layers against hydrogen.

[0318] By providing the insulating layer 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making the source and drain regions n-type.

[0319] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200G can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0320] The insulating layers 250a to 250d function as part of a gate insulating layer. The insulating layers 250a to 250d, together with the conductive layer 260, are provided in an opening formed in the insulating layer 280. To miniaturize the transistor 200G, the insulating layers 250a to 250d are preferably thin. The thicknesses of the insulating layers 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250a to 250d may have a region with the above-described thickness at least in part.

[0321] The thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0322] In order to thin the insulating layers 250a to 250d as described above, it is preferable to form the insulating layers 250a to 250d by using the ALD method. Furthermore, it is preferable to form the insulating layers 250a to 250d by using the ALD method in order to provide the insulating layers 250a to 250d in openings in the insulating layer 280, etc. By forming the insulating layers 250 by using the ALD method, it is possible to form the insulating layer 250 with good coverage on the side surfaces of the first openings formed in the insulating layer 280, the side edges of the conductive layers 242a and 242b, and the like.

[0323] Although the insulating layer 250 has been described above as having a four-layer structure of the insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250a to 250d. By forming the insulating layer 250 using one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the transistor 200G can be simplified and the productivity of a semiconductor device including the transistor 200G can be improved.

[0324] As shown in FIG. 26A , the shape of the semiconductor layer 230 in a planar view is preferably a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) with both ends coinciding. That is, it is preferable that the semiconductor layer 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction). This can prevent the semiconductor layer 230 from collapsing during the transistor fabrication process when the aspect ratio of the semiconductor layer 230 is increased. Note that the semiconductor layer 230 shown in FIG. 26A can also be described as having a shape with an opening in the center. In FIG. 26A , the shape of the semiconductor layer 230 in a planar view is line-symmetrical about the A1-A2 axis, but the present invention is not limited to this. For example, the shape of the semiconductor layer 230 in a planar view may be asymmetrical.

[0325] The structure shown in Fig. 26A is a structure in which two peripheral semiconductor layers 230 are formed in the Y direction. As shown in Fig. 26A, the semiconductor layer 230 preferably overlaps with the conductive layer 260 at two or more locations in a plan view. Therefore, the conductive layer 260 preferably has two or more regions that overlap with the semiconductor layer 230. In other words, it is preferable that the semiconductor layer 230 and the conductive layer 260 have two or more regions where they overlap with each other.

[0326] With this structure, as shown in FIG. 26B , multiple fin-shaped semiconductor layers 230 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped semiconductor layers 230 includes a channel formation region. That is, the transistor 200G functions as a multi-channel transistor. Therefore, the channel width of the transistor 200G can be further increased, thereby increasing the on-state current. Therefore, the operating speed of a semiconductor device including the transistor 200G can be increased.

[0327] Although the above description has been given of a configuration in which two circumferential semiconductor layers 230 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 230 are provided is possible. Furthermore, the circumferential semiconductor layers 230 can be joined to form a semiconductor layer 230 having a shape with a plurality of openings. Furthermore, it is also possible to use a semiconductor layer 230 in a lattice shape in plan view.

[0328] <Transistor Configuration Example 8> Next, a transistor 200H, which is a variation of the transistor 200G, will be described. FIG. 28A is a plan view of the transistor 200H that can be used in a semiconductor device of one embodiment of the present invention. FIG. 28B is a schematic perspective view of the transistor 200H. FIGS. 28C to 28E are cross-sectional views of the transistor 200H. FIG. 28C is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 28A and is also a cross-sectional view of the transistor 200H in the channel width direction (Y direction). FIG. 28D is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 28A and is also a cross-sectional view of the transistor 200H in the channel width direction. FIG. 28E is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 28A and is also a cross-sectional view of the transistor 200H in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of Figure 28A and the schematic perspective view of Figure 28B, some components are omitted. Also, Figure 29 shows an enlarged view of the semiconductor layer 230 of Figure 28C.

[0329] As shown in FIGS. 28B to 28E , a configuration in which an insulating layer 224 is provided below the semiconductor layer 230 is also possible. The planar shape of the insulating layer 224 (the shape when viewed from the Z direction) is the same as that of the semiconductor layer 230. Therefore, in a planar view, the insulating layer 224 overlaps with the semiconductor layer 230. The lower surface of the insulating layer 224 contacts the insulating layer 222, the side surface of the insulating layer 224 contacts the insulating layer 250 and the conductive layer 242a, and the upper surface of the insulating layer 224 contacts the lower surface of the semiconductor layer 230. Furthermore, the insulating layer 224 can be made of an insulating material that can be used for the insulating layer 250b. For example, the insulating layer 224 can be made of silicon oxide.

[0330] 28A to 28E correspond to Fig. 26A to 26E. Also, Fig. 29 corresponds to Fig. 27B. Therefore, matters not explained below regarding the configurations according to Fig. 28A to 28E and Fig. 29 can be understood by referring to the explanations given above regarding Fig. 26A to 26E and Fig. 27B.

[0331] 29 , it is preferable that the thickness t2 of the insulating layer 250 at the bottom of the first opening be thinner than the thickness t1 (the length of the insulating layer 224 in the direction perpendicular to the surface on which it is formed) of the insulating layer 224. With this configuration, the lower surface of the conductive layer 260 (conductive layer 260 a) located in the first opening can be positioned lower than the lower surface of the semiconductor layer 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0332] By positioning the lower surface of the conductive layer 260 below the lower surface of the semiconductor layer 230, a sufficient gate electric field can be applied from the upper end to the lower end of the semiconductor layer 230. In other words, within the opening of the insulating layer 280 or the like, the entire semiconductor layer 230 is electrically surrounded by the electric field of the conductive layer 260, allowing it to function as a channel formation region. This configuration prevents the lower end of the semiconductor layer 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistors, that are caused by the parasitic channel. In other words, the electrical characteristics of the transistor 200H can be improved.

[0333] Furthermore, as described above, the channel width can be increased by making the semiconductor layer 230 function as a channel formation region from the top end to the bottom end, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200H.

[0334] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0335] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 200H in the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230 and the insulating layer 250, which functions as a gate insulating layer, can be the entire bulk of the semiconductor layer 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the semiconductor layer 230 has a CAAC structure and a fin-like structure. With this structure, the current paths flowing to the source and drain of the transistor can be parallel to the ab plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material, and by using such an oxide semiconductor, a device having two-dimensional conduction can be fabricated.

[0336] <Transistor Configuration Example 9> A transistor 200I, which is a variation of the transistor 200G, is shown in Figures 30A to 30E. The transistor 200I differs from the transistor 200G in that a conductive layer 205 is provided under an insulating layer 221. Figures 30A to 30E correspond to Figures 26A to 26E. Matters not described below regarding the configurations in Figures 30A to 30E can be understood with reference to the description of Figures 26A to 26E.

[0337] The conductive layer 205 has a region overlapping with the channel formation region of the semiconductor layer 230. Thus, the conductive layer 205 has a region that functions as a gate electrode, similar to the conductive layer 260. The conductive layer 260 may be referred to as a first gate electrode (upper gate electrode) of the transistor 200I, and the conductive layer 205 may be referred to as a second gate electrode (lower gate electrode) of the transistor 200I. When the conductive layer 260 is referred to as a gate electrode of the transistor 200I, the conductive layer 205 may be referred to as a backgate electrode of the transistor 200I.

[0338] When the conductive layer 205 is provided under the insulating layer 221 as in the transistor 200I, each of the insulating layers 222 and 221 has a region that functions as a gate insulating layer, similar to the insulating layer 250. Specifically, a region of each of the insulating layers 222 and 221 that overlaps with the conductive layer 205 functions as a gate insulating layer. The insulating layer 250 may be referred to as a first gate insulating layer (upper gate insulating layer), and the insulating layer 222 and the insulating layer 221 may be referred to as a second gate insulating layer (lower gate insulating layer).

[0339] In the transistor 200I, the conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. In Figures 30C and 30E, the conductive layer 205 is provided inside a fourth opening that penetrates the insulating layer 216 and reaches the insulating layer 215. In addition, the fourth opening has, in a plan view, a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the end of the semiconductor layer 230. Therefore, in a plan view, the conductive layer 205 provided inside the fourth opening also has a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the end of the semiconductor layer 230. The conductive layer 205 also functions as wiring.

[0340] 30C and 30E , the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is provided in contact with the bottom and sidewalls of the fourth opening. The conductive layer 205b is provided so as to fill a recess in the conductive layer 205a formed along the bottom and sidewalls of the fourth opening. Here, the height of the upper surface of the conductive layer 205 is the same as or approximately the same as the height of the upper surface of the insulating layer 216.

[0341] Here, the conductive layer 205a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0342] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 216 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 205a, it is possible to suppress oxidation of the conductive layer 205b and a decrease in conductivity. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0343] The conductive layer 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0344] As described above, the conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200I can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200I and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential of the conductive layer 260 is 0 V compared to not applying a negative potential to the conductive layer 205.

[0345] The electrical resistivity of the conductive layer 205 is designed taking into consideration the potential applied to the conductive layer 205, and the film thickness of the conductive layer 205 is set to match the electrical resistivity. The film thickness of the insulating layer 216 is approximately the same as that of the conductive layer 205. Here, it is preferable to make the film thicknesses of the conductive layer 205 and the insulating layer 216 thin within the range permitted by the design of the conductive layer 205. By making the film thickness of the insulating layer 216 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 216 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 230 can be suppressed.

[0346] Although the above describes a stacked structure of the conductive layer 205a and the conductive layer 205b, the present invention is not limited to this, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, a structure can be adopted in which a conductive layer made of the same material as the conductive layer 205a is further provided on the conductive layer 205b in the stacked structure of the conductive layer 205a and the conductive layer 205b. In this case, the conductive layer can be formed so that the top surface of the conductive layer 205b is lower than the top of the conductive layer 205a, and so as to fill the recess formed by the conductive layer 205a and the conductive layer 205b.

[0347] In addition to the materials disclosed in this embodiment, the materials for conductive layers shown in other embodiments can be used as materials for conductive layer 205, conductive layer 242, conductive layer 245, and conductive layer 260. In addition to the materials disclosed in this embodiment, the materials for insulating layer shown in other embodiments can be used as materials for insulating layer 215, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 241, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 282, and insulating layer 283.

[0348] The transistor 200I described in this embodiment can be used as a transistor included in the semiconductor device 10. The transistor 200I can have a large on-state current without increasing the occupation area.

[0349] <Constituent Materials of Transistor> Next, constituent materials that can be used for the transistor 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, transistor 200E, transistor 200F, transistor 200G, transistor 200H, and transistor 200I) will be described.

[0350] [Substrate] When a transistor is provided on a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light transparency and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

[0351] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0352] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Also, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0353] Examples of materials that can be used for flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0354] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, it is also possible to use a substrate on which elements are provided. Elements that can be provided on the substrate include capacitance elements, resistance elements, switching elements, light-emitting elements, memory elements, and the like.

[0355] [Insulating Layer] An inorganic insulating film is used for each of the insulating layers (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 215, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 241, insulating layer 257, insulating layer 250, insulating layer 258, insulating layer 258a, insulating layer 258b, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 268, insulating layer 516, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. Furthermore, organic insulating films can also be used for insulating layers included in semiconductor devices.

[0356] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0357] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for insulating layers that function as gate insulating layers, such as insulating layer 204 and insulating layer 264, enables lower voltages during transistor operation while maintaining the physical film thickness. It also enables thinner equivalent oxide thickness (EOT) for the gate insulating layer. On the other hand, using a material with a low dielectric constant for an insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0358] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0359] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0360] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 242, conductive layer 245, conductive layer 255, conductive layer 260, conductive layer 267, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in the transistor 200, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy can be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. It is also possible to use semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0361] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0362] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0363] In addition, it is possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, a stacked structure can be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. In addition, a stacked structure can be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. In addition, a stacked structure can be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0364] For example, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203 of the transistor 200A or 200B, a conductive layer functioning as a gate electrode, such as the conductive layer 205 or the conductive layer 219, may have a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, oxygen desorbed from the conductive material is easily supplied to a channel formation region of the semiconductor layer 203.

[0365] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, the conductive layers 208a, 208b, 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b are conductive layers in contact with the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, respectively. Therefore, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion may be used for each of the conductive layers. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b.

[0366] By using a conductive material containing oxygen for the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity can be maintained even if the conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity of the conductive layers 208a, 208b, 255, 261, 542a, and 542b can be maintained, which is preferable. For each of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b, for example, ITO, ITSO, IZO (registered trademark), or the like can be used.

[0367] [Semiconductor Layer] As the semiconductor layer (semiconductor layer 203, semiconductor layer 230, semiconductor layer 263, semiconductor layer 520, etc.), a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of the semiconductor material that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Examples of the compound semiconductor that can be used include organic materials having semiconductor properties, metal oxides having semiconductor properties (also referred to as "oxide semiconductors"), and nitrides having semiconductor properties (also referred to as "nitride semiconductors"). Note that these semiconductor materials may contain impurities as dopants.

[0368] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0369] For example, by using silicon for the semiconductor layer 203 of the transistor 200A or 200B and adding phosphorus or arsenic as an n-type dopant to the regions 203a and 203c of the semiconductor layer 203, the transistor can function as an n-type transistor. Also, by adding boron as a p-type dopant to the regions 203a and 203c of the semiconductor layer 203, the transistor can function as a p-type transistor. When the regions 203a and 203c of the semiconductor layer 203 contain both an n-type dopant and a p-type dopant, the conductivity type with a higher dopant concentration is more likely to be realized.

[0370] Two-dimensional materials that function as semiconductors can also be used as the semiconductor layer of a transistor. Two-dimensional materials, also known as layered materials, are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0371] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0372] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer, the off-state current of the transistor can be significantly reduced. Since an OS transistor has a small off-state current, the power consumption of the semiconductor device can be reduced. Note that the oxide semiconductor will be described in detail in Embodiment 3.

[0373] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0374] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0375] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a memory device including the transistor can be improved.

[0376] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0377] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0378] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0379] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0380] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO). Examples of the usable oxide include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of the usable oxide include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0381] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0382] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0383] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0384] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0385] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0386] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0387] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0388] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0389] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by a first deposition method and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, thereby increasing the crystallinity of the oxide semiconductor layer.

[0390] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. The ALD and CVD methods are suitable as the first film formation method because they can reduce damage to the surface to be formed compared to the sputtering method described below.

[0391] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0392] The ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs one or both of a high substrate temperature condition during film formation and an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0393] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0394] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0395] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0396] Note that the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0397] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0398] For example, the oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and forming a metal oxide as a third layer by the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0399] [Method for Manufacturing Oxide Semiconductor Layer] The semiconductor layer 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming a semiconductor layer 230a on the layer 229, which is a surface to be formed, by an ALD method, forming a semiconductor layer 230b, which is an oxide semiconductor layer, on the semiconductor layer 230a, which is an oxide semiconductor layer, by a sputtering method, and forming a semiconductor layer 230c, which is an oxide semiconductor layer, on the semiconductor layer 230b, by an ALD method. Furthermore, after forming the semiconductor layer 230, which is an oxide semiconductor layer, it is preferable to perform heat treatment. The heat treatment can improve the crystallinity of the semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, it may be heat applied during the manufacturing process.

[0400] The layer 229 corresponds to the insulating layer 202, the insulating layer 256, the insulating layer 258, or the like described in the above embodiments. The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide contained in the semiconductor layer 230.

[0401] An example of a method for manufacturing the semiconductor layer 230 will be described with reference to FIGS. 31A to 31D and 32A to 32D.

[0402] When a metal oxide film is formed by a sputtering method, alloying may occur between components contained in the metal oxide film and components contained in the layer on which the film is formed due to damage caused by sputtering particles on the surface on which the film is formed or by energy imparted to the substrate by the sputtering particles, etc. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is formed.

[0403] Therefore, first, a semiconductor layer 230a is formed on the layer 229 by ALD (FIG. 31A), and then a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering (FIG. 31B).

[0404] In the method for forming an oxide semiconductor layer of one embodiment of the present invention, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 by a deposition method that causes little damage to a surface on which the semiconductor layer 230a is formed. This suppresses alloying of components contained in the semiconductor layer 230 and components contained in the layer 229, thereby enabling the semiconductor layer 230 to have higher crystallinity.

[0405] By using the above configuration, the thickness of the alloyed region can be reduced, or made so thin that it is difficult to observe. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 31A and 31B show an example in which no alloyed region is formed between layer 229 and semiconductor layer 230a.

[0406] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0407] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the semiconductor layer 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (In, if the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-value is defined as the depth (position) of the interface between the region and the semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the semiconductor layer 230a becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0408] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0409] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0410] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0411] By reducing the alloyed region, it becomes possible to form the CAAC structure near the surface to be formed. Here, "near the surface to be formed" refers to, for example, a region from more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, approximately perpendicularly from the surface to be formed of the semiconductor layer 230.

[0412] The CAAC structure near the formation surface can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0413] When the semiconductor layer 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 31A , the semiconductor layer 230a may have a region having lower crystallinity than the semiconductor layer 230b.

[0414] The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure.

[0415] When the semiconductor layer 230b is formed by sputtering, a mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. Furthermore, when the semiconductor layer 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, and at least a portion of the semiconductor layer 230a may be crystallized.

[0416] In forming the semiconductor layer 230b by a sputtering method, it is preferable to heat the substrate. In forming the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, it is possible to form a metal oxide with high crystallinity in some cases.

[0417] Next, a semiconductor layer 230c is formed on the semiconductor layer 230b by ALD (FIG. 31C). For the formation of the semiconductor layer 230c by ALD, the method for forming the semiconductor layer 230a can be referred to.

[0418] When the semiconductor layer 230c is formed on the semiconductor layer 230b having the CAAC structure by the ALD method, the semiconductor layer 230c may grow epitaxially using the semiconductor layer 230b as a nucleus. Therefore, when the semiconductor layer 230c is formed, the semiconductor layer 230c may have a region having the CAAC structure. Furthermore, it is preferable that the region having the CAAC structure is formed over the entire semiconductor layer 230c.

[0419] Next, a heat treatment step may be performed. This heat treatment step may increase the crystallinity of the region having the CAAC structure in the semiconductor layer 230c. Furthermore, if the region is formed only below the semiconductor layer 230c after film formation by the ALD method, this heat treatment step may cause the region to expand upward (FIG. 31D). That is, this heat treatment may cause the region having the CAAC structure to be formed throughout the entire semiconductor layer 230c.

[0420] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is converted into CAAC by this heat treatment process ( FIG. 31D ). It is expected that the CAAC conversion is facilitated by the mixed layer 231 formed in the semiconductor layer 230a during the deposition of the semiconductor layer 230b, which acts as a nucleus or seed. It is preferable that the region in the semiconductor layer 230a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 229.

[0421] Furthermore, because the CAAC is formed from the top to the bottom of the semiconductor layer 230a, the CAAC can be formed up to the vicinity of the layer 229 without being limited by the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the semiconductor layer 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0422] 31A to 31D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 31A to 31D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide according to one embodiment of the present invention. As shown in FIGS. 31A to 31D , the semiconductor layer 230a and the semiconductor layer 230c each have high crystallinity using the highly crystalline semiconductor layer 230b as a nucleus or seed. Specifically, the crystallinity of the semiconductor layer 230a may be increased by heat treatment during the formation of the semiconductor layer 230b or after the formation of the semiconductor layer 230c. The crystallinity of the semiconductor layer 230c may be increased by heat treatment during the formation of the semiconductor layer 230c or after the formation of the semiconductor layer 230c. The heat treatment has an assisting effect of increasing the crystallinity.

[0423] As described above, in the metal oxide film formation method of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the semiconductor layer 230a and the semiconductor layer 230c here) can be increased by using the semiconductor layer 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the semiconductor layer 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although FIGS. 32A to 32D illustrate a structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c, the present invention is not limited thereto. For example, the structure including the semiconductor layer 230a and the semiconductor layer 230b can also be an AG CAAC.

[0424] In the semiconductor layer 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. Figure 32A shows the state in which the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are each crystallized. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Also, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. The semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observed. The semiconductor layer 230 may be expressed as a single layer.

[0425] Furthermore, there are cases where a portion of the semiconductor layer 230a or the semiconductor layer 230c is not crystallized. The example shown in Fig. 32B shows a state in which the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. Fig. 32C shows a state in which the vicinity of the surface in the semiconductor layer 230c is not crystallized. Fig. 32D shows a state in which the vicinity of the interface with the layer 229 in the semiconductor layer 230a and the vicinity of the surface of the semiconductor layer 230c are not crystallized.

[0426] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0427] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the semiconductor layer 230, the boundaries between the stacked semiconductor layers 230a, 230b, and 230c may not be visible. In particular, after heat treatment, it may be difficult to identify the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, a TEM or the like.

[0428] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, crystals that reflect the crystal orientation of the semiconductor layer 230b are formed, and polycrystallization can be suppressed.

[0429] Furthermore, it is preferable that the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small. This allows the semiconductor layer 230a or the semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the semiconductor layer 230b. In this case, for example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0430] As long as the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or 230c is small, the crystal structure of the semiconductor layer 230a or 230c is not particularly limited. The crystal structure of the semiconductor layer 230a or 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0431] [Composition of Oxide Semiconductor Layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The semiconductor layer 230b can be formed by, for example, a sputtering method. The semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the semiconductor layer 230b becomes a metal oxide with high crystallinity. Furthermore, the semiconductor layer 230b preferably contains an element M in addition to zinc. By containing the element M in the semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor using an oxide semiconductor layer can be improved. Specifically, the semiconductor layer 230b may be made of a metal oxide having an In:M:Zn = 1:1:1 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:1.2 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:0.5 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:2 atomic ratio or a composition thereabout, an In:M:Zn = 4:2:3 atomic ratio or a composition thereabout, an In:M:Zn = 1:3:2 atomic ratio or a composition thereabout, or an In:M:Zn = 1:3:4 atomic ratio or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0432] The semiconductor layer 230b can be configured without containing the element M. For example, an In—Zn oxide can be used as the semiconductor layer 230b. Specifically, the semiconductor layer 230b can have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, an indium oxide can be used. The semiconductor layer 230b can also be configured with a trace amount of the element M. For example, the semiconductor layer 230b can have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, the semiconductor layer 230b can have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0433] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a high proportion of In. The semiconductor layer 230a and the semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0434] The semiconductor layer 230a and the semiconductor layer 230c may be configured to not contain the element M. For example, an In-Zn oxide may be used. Specifically, the composition may be an In:Zn=1:1 (atomic ratio) or a composition close to that, an In:Zn=2:1 (atomic ratio) or a composition close to that, or an In:Zn=4:1 (atomic ratio) or a composition close to that. Alternatively, an indium oxide may be used as the semiconductor layer 230a and the semiconductor layer 230c. The semiconductor layer 230a and the semiconductor layer 230c may be configured to contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0435] Increasing the zinc content of the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by an ALD method and the semiconductor layer 230b is formed by a sputtering method, zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby facilitating the formation of CAAC.

[0436] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a higher proportion of In than the semiconductor layer 230b.

[0437] Alternatively, for example, a metal oxide having a higher Ga content than the semiconductor layer 230b can be used for the semiconductor layer 230a and the semiconductor layer 230c. For example, it is preferable to use a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout for the semiconductor layer 230a and the semiconductor layer 230c, respectively. Increasing the Ga content may result in the band gaps of the semiconductor layer 230a and the semiconductor layer 230c being larger than those of the semiconductor layer 230b. As a result, the semiconductor layer 230b is sandwiched between the semiconductor layer 230a and the semiconductor layer 230c, which have larger band gaps, and the semiconductor layer 230b functions primarily as a current path (channel). By sandwiching the semiconductor layer 230b between the semiconductor layers 230a and 230c, it is possible to reduce trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof, thereby realizing a buried channel transistor in which the channel is kept away from the insulating layer interface, and thus increasing the field-effect mobility.

[0438] In the oxide semiconductor layer of one embodiment of the present invention, even when the semiconductor layers 230a and 230c are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the semiconductor layers 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the semiconductor layer 230a and the semiconductor layer 230c and the semiconductor layer 230b.

[0439] In particular, even when the semiconductor layers 230 a and 230 c have a high In content, the semiconductor layers can have suitable crystallinity for use as semiconductor layers of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0440] The semiconductor layer 230a and the semiconductor layer 230c may have different compositions.

[0441] Furthermore, the semiconductor layers 230a and 230c can be made of a metal oxide having the same composition as the semiconductor layer 230b.

[0442] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0443] The composition of the metal oxide used in the semiconductor layer 230 can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed using a combination of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0444] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0445] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0446] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0447] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0448] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0449] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0450] The c-axis orientation rates of the region formed as semiconductor layer 230a, the region formed as semiconductor layer 230b, and the region formed as semiconductor layer 230c are defined as Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0451] After the semiconductor layer 230 is fabricated, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0452] The semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, namely, a first region, a second region, and a third region, starting from the top of the layer 229. Each region is a layer-like region.

[0453] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0454] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the semiconductor layer 230 .

[0455] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0456] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0457] Embodiment 4 In this embodiment, a configuration example of a memory device 300 including a semiconductor device 10 according to one embodiment of the present invention will be described. As described above, the semiconductor device 10 functions as a memory cell.

[0458] 33A is a block diagram illustrating a configuration example of a memory device 300 including the semiconductor device 10 of one embodiment of the present invention. The memory device 300 illustrated in FIG. 33A includes a driver circuit 21 and a memory cell array 310.

[0459] The memory cell array 310 has a plurality of semiconductor devices 10 arranged in a matrix of p rows and q columns (each of p and q is an integer greater than or equal to 1). By arranging a plurality of semiconductor devices 10 in a matrix, a memory device with a large storage capacity can be realized.

[0460] In Figure 33A, the semiconductor device 10 in the first row and first column is shown as semiconductor device 10[1,1], the semiconductor device 10 in the pth row and qth column is shown as semiconductor device 10[p,q], the semiconductor device 10 in the pth row and first column is shown as semiconductor device 10[p,1], the semiconductor device 10 in the first row and qth column is shown as semiconductor device 10[1,q], and the semiconductor device 10 in the rth row and sth column (r is an integer of 1 to p inclusive indicating an arbitrary row, and s is an integer of 1 to q inclusive indicating an arbitrary column) is shown as semiconductor device 10[r,s].

[0461] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction (direction along the X axis) is referred to as a "row" and the Y direction (direction along the Y axis) is referred to as a "column," but it is also possible to refer to the X direction as a "column" and the Y direction as a "row."

[0462] The drive circuit 21 includes a power switch 22, a power switch 23, and a peripheral circuit group 31. The peripheral circuit group 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0463] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals not described in this embodiment can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0464] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 32.

[0465] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0466] The voltage generating circuit 33 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when a signal of potential H is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a voltage.

[0467] The peripheral circuit 41 has a function of writing data to the memory cell array 310 and a function of reading data from the memory cell array 310. In other words, it has a function of selecting a specific semiconductor device 10 from the multiple semiconductor devices 10 included in the memory cell array 310 and writing data thereto, and a function of reading data stored in the specific semiconductor device 10. The peripheral circuit 41 has a row decoder circuit 42, a column decoder circuit 44, a row driver circuit 43, a column driver circuit 45, an input circuit 47, a sense amplifier circuit 46, and an output circuit 48.

[0468] The row decoder circuit 42 and the column decoder circuit 44 have the function of decoding the signal ADDR. The row decoder circuit 42 is a circuit for specifying a row to be accessed, and the column decoder circuit 44 is a circuit for specifying a column to be accessed. The row driver circuit 43 has the function of selecting a wiring (such as a wiring WWL or a wiring RWL) specified by the row decoder circuit 42. The column driver circuit 45 has the function of supplying data to be stored in the semiconductor device 10 to a wiring WBL specified by the column decoder circuit 44. The column driver circuit 45 also has the function of supplying a potential H to a wiring RBL specified by the column decoder circuit 44. The sense amplifier circuit 46 has the function of detecting a change in the potential of the wiring RBL specified by the column decoder circuit 44 and reading out data stored in the semiconductor device 10.

[0469] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver circuit 45. The output data of the input circuit 47 is data (Din) to be written to the semiconductor device 10. The data (Dout) read from the semiconductor device 10 by the sense amplifier circuit 46 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0470] The power switch 22 has a function of controlling the supply of VDD to the peripheral circuit group 31. The power switch 23 has a function of controlling the supply of a potential VHM to the row driver circuit 43. Here, the high power supply potential of the memory device 300 is VDD, and the low power supply potential is GND. The potential VHM is a power supply potential used to set a word line (e.g., wiring WWL) to a potential H, and is a potential higher than VDD. The on / off of the power switch 22 is controlled by a signal PON1, and the on / off of the power switch 23 is controlled by a signal PON2. In FIG. 33A, the number of power domains to which VDD is supplied in the peripheral circuit group 31 is one, but multiple power domains may also be used. In this case, a power switch may be provided for each power domain.

[0471] As described in Embodiment 1, the driver circuit 21 and the transistor M2 of the semiconductor device 10 can be provided in the element layer 50. Alternatively, the driver circuit 21 and the transistor M2 and the transistor M3 of the semiconductor device 10 can be provided in the element layer 50. As described in Embodiment 1, the element layer 50 can be formed using a single crystal semiconductor substrate, an SOI substrate, or the like.

[0472] Furthermore, an element layer 60 including the transistor M1 of the semiconductor device 10 can be provided overlapping the element layer 50. Thus, part of the memory cell array 310 is formed in the element layer 50, and another part of the memory cell array 310 is formed in the element layer 60. The memory device 300 described in this embodiment has a configuration in which the driver circuit 21 and the transistor M2 of the semiconductor device 10 are provided in the element layer 50, and the transistor M1 is provided in the element layer 60 (see FIG. 33B ). As described above, the transistor M3 can also be provided in the element layer 50.

[0473] By separately forming the element layer 50 including the driver circuit 21 and the element layer 60 including the transistor M1 of the semiconductor device 10, it is possible to check the operation of the driver circuit 21 included in the element layer 50 before forming the element layer 60 on the element layer 50. Therefore, only non-defective element layers 50 can be used, which improves the manufacturing yield of the memory device 300. Therefore, the productivity of the memory device 300 can be increased.

[0474] Furthermore, by stacking the element layer 50 including the driver circuit 21 and the transistor M2 of the semiconductor device 10 and the element layer 60 including the transistor M1 of the semiconductor device 10, the signal propagation distance within the memory cell array 310 can be shortened. The signal propagation distance between the driver circuit 21 and the memory cell array 310 can also be shortened. Therefore, not only the parasitic resistance and parasitic capacitance within the memory cell array 310 but also the parasitic resistance and parasitic capacitance between the driver circuit 21 and the memory cell array 310 are reduced, thereby reducing power consumption and signal delay. Furthermore, the memory device 300 can be miniaturized. Furthermore, the memory capacity per unit area can be increased.

[0475] <Example of Planar Configuration and Stacked Configuration of Memory Cell> An example of a planar configuration and stacked configuration of a memory cell included in the memory device 300 will be described. As an example of a semiconductor device 10 functioning as a memory cell, an example of a planar configuration of the semiconductor device 10A shown in FIG. 1A is shown in FIG. 34. Also, FIG. 35 shows an example of a cross-sectional configuration between X1-X2 indicated by a dashed line in FIG. 34. Also, FIG. 36 shows an example of a cross-sectional configuration between X3-X4 indicated by a dashed line in FIG. 34.

[0476] 34, some elements are omitted for clarity. For example, the element layer 50 including the transistor M2 is not shown. To avoid repetition, the description of the semiconductor device 10A will be omitted here.

[0477] 35 illustrates a transistor 400 as the transistor M2 included in the element layer 50. In addition, in FIGS. 35 and 36, a transistor 200C is illustrated as the transistor M1 and the transistor M3 included in the element layer 60. Note that, in order to reduce repetition of explanation, explanations related to the transistor 200C will be omitted here.

[0478] The transistor 400 functioning as the transistor M2 is provided over a substrate 371 and includes a conductive layer 376 functioning as a gate electrode, an insulating layer 375 functioning as a gate insulating layer, a semiconductor region 373 formed of part of the substrate 371, and low-resistance regions 374a and 374b functioning as source and drain regions. The transistor 400 functioning as the transistor M2 can be either a p-channel transistor or an n-channel transistor. The substrate 371 can be, for example, a single crystal silicon substrate.

[0479] Here, in the transistor 400 shown in FIG. 35 , a semiconductor region 373 (a part of a substrate 371) where a channel is formed has a convex shape. A conductive layer 376 is provided to cover the side and top surfaces of the semiconductor region 373 with an insulating layer 375 interposed therebetween. Note that the conductive layer 376 can be formed using a material that adjusts the work function. Such a transistor is also called a Fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that functions as a mask for forming the convex portion may remain in contact with the top of the convex portion. Here, a case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but it is also possible to form a semiconductor film having a convex shape by processing an SOI (silicon-on-insulator) substrate.

[0480] The structure of the transistor 400 functioning as the transistor M2 can also be used as a transistor included in the driver circuit 21. Note that the transistor 400 illustrated in FIG. 35 is just an example, and the structure is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration or the driving method.

[0481] The element layer 50 may be provided with a wiring layer provided with an interlayer film, wiring, plugs, and the like. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug may be integrated. That is, there may be cases where a part of the conductive layer functions as the wiring, and there may be cases where a part of the conductive layer functions as the plug.

[0482] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 392 and the like are embedded in the insulating layer 390 and the insulating layer 391. A conductive layer 395, a conductive layer 397, a conductive layer 398, and the like are embedded in the insulating layer 393 and the insulating layer 394. The conductive layer 392 and the conductive layer 395 function as contact plugs or wirings.

[0483] The insulating layer serving as an interlayer film preferably also serves as a planarizing film that covers the uneven shape below it. For example, the top surface of the insulating layer 391 may be subjected to CMP treatment or the like to improve the planarity.

[0484] 35 and 36, an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 394 and the conductive layer 395. A conductive layer 385, a conductive layer 386, and a conductive layer 387 are formed in the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 385, the conductive layer 386, and the conductive layer 387 function as contact plugs or wirings.

[0485] Moreover, conductive layers 255a, 255b, 255c, and 255d are provided over the insulating layer 384. The conductive layers 255a, 255b, 255c, and 255d can be provided simultaneously using the same material as the conductive layer 255 described in the above embodiment mode. The conductive layer 255a is connected to the conductive layer 376 through a conductive layer 386. The conductive layer 255c is connected to a conductive layer 397 through a conductive layer 385. The conductive layer 397 functions as a wiring WBL. The conductive layer 255d is connected to a conductive layer 398 through the conductive layer 387. The conductive layer 398 functions as a wiring PL.

[0486] Further, an insulating layer 257, an insulating layer 258, and an insulating layer 259 are provided over the conductive layer 255a, the conductive layer 255b, the conductive layer 255c, and the conductive layer 255d. Further, a conductive layer 261a and a conductive layer 261b are provided over the insulating layer 259. The conductive layer 261a and the conductive layer 261b can be provided at the same time using the same material as the conductive layer 261 described in the above embodiment mode.

[0487] 35, the opening 262 of the transistor M1[1] is shown as opening 262[1], and the opening 262 of the transistor M1[2] is shown as opening 262[2]. In FIG. 36, the opening of the transistor M3, which corresponds to the opening 262 of the transistor M1, is shown as opening 272.

[0488] Furthermore, part of the conductive layer 261b functions as the conductive layer 261 of the transistor M1[1], another part functions as the conductive layer 261 of the transistor M1[2], and still another part functions as the conductive layer 261 of the transistor M3.

[0489] An opening 269[1] that penetrates the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region that overlaps with a portion of the conductive layer 255a. The conductive layer 261a has, inside the opening 269[1], a region that overlaps with the bottom of the opening 269[1] and a region that overlaps with the side surface of the opening 269[1]. The conductive layer 261a is connected to the conductive layer 255a at the bottom of the opening 269[1].

[0490] An opening 269[2] that penetrates the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region that overlaps with part of the conductive layer 255b. The conductive layer 261b has, inside the opening 269[2], a region that overlaps with the bottom of the opening 269[2] and a region that overlaps with the side surface of the opening 269[2]. The conductive layer 261b is connected to the conductive layer 255b at the bottom of the opening 269[2].

[0491] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261a, the conductive layer 261b, the semiconductor layer 263[1], the semiconductor layer 263[2], and the semiconductor layer 263[3]. The insulating layer 264 overlaps with the opening 269[1] and has a region inside the opening 269[1] that overlaps with the conductive layer 261a. The insulating layer 264 overlaps with the opening 269[2] and has a region inside the opening 269[2] that overlaps with the conductive layer 261b.

[0492] Further, a conductive layer 265a, a conductive layer 265b, a conductive layer 265c, a conductive layer 265d, and a conductive layer 265e are provided over the insulating layer 264. The conductive layer 265b functions as the conductive layer 265 of the transistor M1[1]. The conductive layer 265d functions as the conductive layer 265 of the transistor M1[2]. The conductive layer 265e functions as the conductive layer 265 of the transistor M3. Thus, the conductive layer 265b functions as the gate electrode of the transistor M1[1], the conductive layer 265d functions as the gate electrode of the transistor M1[2], and the conductive layer 265e functions as the gate electrode of the transistor M3.

[0493] The conductive layer 265a has a region inside the opening 269[1] that overlaps with the conductive layer 261a with the insulating layer 264 interposed therebetween. In the opening 269[1] and its vicinity, a region where the conductive layer 261a and the conductive layer 265a overlap with each other with the insulating layer 264 interposed therebetween functions as a capacitor Cs[1]. The conductive layer 261a functions as one electrode of the capacitor Cs[1], and the conductive layer 265a functions as the other electrode of the capacitor Cs[1].

[0494] The conductive layer 265c has a region inside the opening 269[2] that overlaps with the conductive layer 261b with the insulating layer 264 interposed therebetween. In the opening 269[2] and its vicinity, a region where the conductive layers 261b and 265c overlap with each other with the insulating layer 264 interposed therebetween functions as a capacitor Cs[2]. The conductive layer 261b functions as one electrode of the capacitor Cs[2], and the conductive layer 265c functions as the other electrode of the capacitor Cs[2].

[0495] An opening 273 that penetrates the insulating layer 264, the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region overlapping with part of the conductive layer 255a. Inside the opening 273, the conductive layer 265e has a region that overlaps with the bottom of the opening 273 and a region that overlaps with the side surface of the opening 273. The conductive layer 265e is connected to the conductive layer 255a at the bottom of the opening 273.

[0496] The conductive layer 265a and the conductive layer 265c are connected to the wiring COM. Note that Figure 34 shows an example in which part of the wiring COM functions as the conductive layer 265a, and the other part functions as the conductive layer 265c. The conductive layer 265a, the conductive layer 265b, the conductive layer 265c, the conductive layer 265d, the conductive layer 265e, and the wiring COM can be formed using a material and a method similar to those of the conductive layer 265.

[0497] Moreover, an insulating layer 266 is provided over the insulating layer 264. Note that the top surface of the insulating layer 266 is preferably flat. Figure 35 shows a case where the positions of the top surfaces of the insulating layer 266, the conductive layer 265a, the conductive layer 265b, the conductive layer 265c, the conductive layer 265d, and the conductive layer 265e are aligned or approximately aligned. Figure 36 shows a case where part of the top surface of the conductive layer 265e is aligned or approximately aligned with the top surface of the insulating layer 266.

[0498] Further, an insulating layer 276 is provided over the insulating layer 266, the conductive layer 265a, the conductive layer 265b, the conductive layer 265c, and the conductive layer 265c, and a conductive layer 271[1] and a conductive layer 271[2] are provided so as to be embedded in the insulating layer 276. The conductive layer 271[1] is provided in a region overlapping with the conductive layer 265b, and the conductive layer 271[2] is provided in a region overlapping with the conductive layer 265d.

[0499] A conductive layer 278 is provided over the insulating layer 276, the conductive layer 271[1], and the conductive layer 271[2]. The conductive layer 265b is connected to the conductive layer 278 through the conductive layer 271[1]. The conductive layer 265d is connected to the conductive layer 278 through the conductive layer 271[2]. Thus, the conductive layer 265b and the conductive layer 265d are connected to each other through the conductive layer 271[1], the conductive layer 271[2], and the conductive layer 278. The conductive layer 278 functions as a wiring WWL.

[0500] In addition, an insulating layer 277 is provided over the insulating layer 276. Note that the top surface of the insulating layer 277 is preferably flat, similar to the insulating layer 266. Fig. 35 shows the case where the positions of the top surfaces of the conductive layer 278 and the insulating layer 277 are aligned or approximately aligned.

[0501] In addition, an insulating layer 279 is provided over the insulating layer 277 and the conductive layer 278. The insulating layer 276, the insulating layer 277, and the insulating layer 279 can be formed using the same material and method as the insulating layer described in the above embodiment mode. The conductive layer 271[1], the conductive layer 271[2], and the conductive layer 278 can be formed using the same material and method as the conductive layer described in the above embodiment mode.

[0502] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0503] Fifth Embodiment In this embodiment, an example of a processing device that can include the semiconductor device 10 or the memory device 300 will be described.

[0504] 37 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 37 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0505] The arithmetic device 960 shown in FIG. 37 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The arithmetic device 960 may have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0506] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via a bus interface 998.

[0507] As will be described later, a memory cell array 310 can be provided by stacking it on the arithmetic device 960. The memory cell array 310 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory cell array 310 to the cache 999. In this case, it is preferable that a part of the cache interface 989 has a drive circuit 21 that drives the memory cell array 310. The drive circuit 21 that drives the memory cell array 310 can be provided in the arithmetic device 960.

[0508] It is also possible to use only the memory cell array 310 as a cache without providing the cache 999 .

[0509] The arithmetic device 960 shown in FIG. 37 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 37 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0510] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0511] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates an address for a register 996 and reads or writes data from or to the register 996 depending on the state of the arithmetic unit 960.

[0512] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0513] In the arithmetic unit 960 shown in FIG. 37 , a register controller 997 selects a holding operation in a register 996 in accordance with an instruction from the ALU 991. That is, it selects whether data is to be held by a flip-flop or by a capacitor in the memory cells of the register 996. If holding data by a flip-flop is selected, power is supplied to the memory cells in the register 996. If holding data by a capacitor is selected, the data is rewritten to the capacitor, and the power supply to the memory cells in the register 996 can be stopped.

[0514] FIG. 38 shows an example in which a substrate 990 is provided with not only the arithmetic unit 960 but also a storage device 962, an interface circuit 964, an input / output unit 966, and the like.

[0515] The memory device 962 can be used as a lower-level cache than the cache 999, or as a main memory. The memory device 962 is connected to a cache interface 989 in the arithmetic device 960 via an interface circuit 964. The memory device 962 is also connected to a main memory provided on a separate chip via the interface circuit 964 and an input / output unit 966.

[0516] The memory device 300 having the memory cell array 310 can be applied to the memory device 962 .

[0517] Various interface circuits and bus lines are provided in the interface circuit 964. The interface circuit 964 may also include a power supply circuit, a clock generation circuit, and the like.

[0518] The interface circuit 964 may include, for example, an I2C (Inter Integrated Circuit), an SPI (Serial Peripheral Interface), a GPIO (General Purpose Input / Output), or the like.

[0519] The input / output portion 966 has an input portion to which a signal, a potential, etc. is input from the outside, and an output portion to which a signal is output to the outside. The input / output portion 966 is provided with a plurality of connection terminals, which are connected to a substrate different from the substrate 990 by connection wiring. The input / output portion 966 can also be provided with a buffer circuit, a protection circuit, etc.

[0520] Methods for connecting the substrate 990 to another substrate include wire bonding using gold or copper wiring, flip-chip bonding using bumps, or direct bonding (hybrid bonding) using a direct bonding technique such as Cu-Cu bonding. Alternatively, a bonding method without using a substrate can be used in which two or more layers are bonded together with insulating films and then through electrodes are formed to connect the electrodes provided on each layer. In particular, using direct bonding or a method using through electrodes allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at a high density, which is preferable because it increases the amount of data transmitted between layers.

[0521] The memory cell array 310 and the arithmetic device 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in FIGS. 39A and 39B. The semiconductor device 970A has a layer 930 on which memory cell arrays are provided, on the arithmetic device 960. The layer 930 is provided with memory cell arrays 310L1, 310L2, and 310L3. The arithmetic device 960 and each memory cell array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the layer 930 are shown separately in FIG. 39B.

[0522] By overlapping the layer 930 having the memory cell array and the arithmetic device 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, the short connection distance can reduce power consumption.

[0523] As a method for stacking the layer 930 having the memory cell array and the computing device 960, a method (also referred to as monolithic stacking) can be used in which the layer 930 having the memory cell array is stacked directly on the computing device 960. Alternatively, a method can be used in which the computing device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or a bonding technique of a conductive film (such as Cu-Cu bonding). The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce the manufacturing cost.

[0524] Here, the arithmetic device 960 does not have a cache 999, and the memory cell arrays 310L1, 310L2, and 310L3 provided in the layer 930 can each be used as caches. In this case, for example, the memory cell array 310L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory cell array 310L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory cell array 310L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory cell arrays, the memory cell array 310L3 has the largest capacity and is accessed least frequently. Furthermore, the memory cell array 310L1 has the smallest capacity and is accessed most frequently.

[0525] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory cell array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0526] 39B, drive circuits 21L1, 21L2, and 21L3 are also provided. Drive circuit 21L1 is connected to memory cell array 310L1 via connection electrode 940L1. Similarly, drive circuit 21L2 is connected to memory cell array 310L2 via connection electrode 940L2, and drive circuit 21L3 is connected to memory cell array 310L3 via connection electrode 940L3.

[0527] Although the case where three memory cell arrays function as caches is shown here, it is also possible to have one or two memory cell arrays function as caches, or even four or more.

[0528] When the memory cell array 310L1 is used as a cache, the drive circuit 21L1 can function as part of the cache interface 989. It is also possible to configure the drive circuit 21L1 to be connected to the cache interface 989. Similarly, the drive circuits 21L2 and 21L3 can also function as part of the cache interface 989 or be configured to be connected thereto.

[0529] Whether the memory cell array 310 is made to function as a cache or as a main memory is determined by the control circuit 32 of each drive circuit 21. The control circuit 32 can make a part of the memory cell array 310 of the storage device 300 function as a RAM based on a signal supplied from the arithmetic device 960.

[0530] The memory device 300 can cause a part of the memory cell array 310 to function as a cache and another part to function as a main memory. That is, the memory device 300 can function as both a cache and a main memory. The memory device 300 according to one aspect of the present invention can function as, for example, a universal memory.

[0531] It is also possible to provide a layer 930 having one memory cell array 310 overlapping the arithmetic device 960. Fig. 40A shows a perspective view of a semiconductor device 970B.

[0532] In the semiconductor device 970B, one memory cell array 310 is divided into multiple areas, each of which can be used for a different function. Figure 40A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0533] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0534] It is also possible to stack a plurality of memory cell arrays 310. Figure 40B shows a perspective view of a semiconductor device 970C.

[0535] The semiconductor device 970C includes a layer 930L1 having a memory cell array 310L1, a layer 930L2 having a memory cell array 310L2 on top of that, and a layer 930L3 having a memory cell array 310L3 on top of that. The memory cell array 310L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory cell array 310L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory cell array to be increased, thereby further improving processing power.

[0536] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0537] Embodiment 6 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0538] First, the hierarchy of a storage device will be described. Figure 41A shows the hierarchy of a conventional storage device.

[0539] In Figure 41A, the closer to the processor (CPU / GPU), the higher the access frequency, and the longer the base length of each area, the larger the data capacity. The closer the storage device to the processor, the faster the operating speed required, and the farther away the storage device, the larger the storage capacity and recording density required. Figure 41A shows a register as memory integrated into a processor such as a CPU or GPU, and shows an example in which SRAM is used as cache memory, DRAM is used as main memory, and NAND memory and HDD (Hard Disk Drive) are used as storage.

[0540] The memory embedded in processors such as CPUs and GPUs is used for temporary storage of calculation results, and is therefore frequently accessed by the arithmetic processing unit. Therefore, faster operating speed is required rather than storage capacity. Registers also have the function of storing setting information for the arithmetic processing unit.

[0541] A cache has the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0542] The main memory has a function of holding programs, data, etc. read from storage.

[0543] Storage has the function of storing data that requires long-term storage, various programs used by processing units, etc. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. For example, NAND memory such as 3D NAND, high-capacity non-volatile storage devices such as HDDs can be used.

[0544] In one embodiment of the present invention, among various memory devices shown in FIG. 41A , at least the DRAM used as the main memory is replaced with a memory device using an oxide semiconductor (OS memory). In particular, the DRAM requires a refresh operation and is a destructive readout memory device, and therefore consumes significantly more power than other memory devices. Therefore, power consumption can be significantly reduced by not using the DRAM. Note that in FIG. 41A , the range of various memory devices that is targeted for replacement with the OS memory is indicated by a dashed line. That is, not only the DRAM used as the main memory, but also at least a part of the SRAM used as the cache and the NAND memory used as storage can be replaced with the OS memory.

[0545] 41B illustrates an example of a semiconductor device according to one embodiment of the present invention, and is a schematic diagram illustrating various memory devices used in the semiconductor device, layer by layer.

[0546] In FIG. 41B, a plurality of caches (L1 cache, L2 cache) and a Last Level cache (LLC) are shown as caches.

[0547] Multiple caches are provided in the order of L1 cache and L2 cache from the highest to lowest. The higher the cache, the more frequently it is accessed by the processor, so high-speed operation is required. Since the operating speed can also be increased by reducing the data capacity, it is preferable to reduce the data capacity of the higher-level cache. The higher-level cache is preferably physically close to the processor and has a short wiring length, so it is preferable to provide it in a form integrated with the layer where the processor is provided. The lower-level cache can also be provided in a layer different from the processor.

[0548] The lowest level of cache can be called LLC. While LLCs are not required to operate faster than higher-level caches, they desirably have a large storage capacity. The OS memory of one embodiment of the present invention, which will be described below, is suitable for LLCs because it operates quickly and can retain data for a long period of time. Note that the OS memory of one embodiment of the present invention can also be applied to a final level cache (FLC).

[0549] SRAM can be used for various caches. OS memory is suitable for LLC and main memory. OS memory has high operating speed and can retain data for a long period of time.

[0550] The configuration exemplified here does not use DRAM, which has been conventionally used as a main memory, etc. Instead, the DRAM is replaced with an OS memory according to one embodiment of the present invention. This configuration allows for a dramatic reduction in power consumption (for example, to one hundredth or one thousandth or less). Therefore, it is expected that the worldwide deployment of information processing devices, including computers, servers, etc., to which this configuration is applied, will contribute significantly to the prevention of global warming.

[0551] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0552] Embodiment 7 This embodiment will describe electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiments. The electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0553] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 42A . The electronic device 6500 shown in FIG. 42A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the control device 6509 and the like.

[0554] 42B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the control device 6616 can reduce power consumption.

[0555] [Mainframe] Next, Fig. 42C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 42C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0556] The computer 5620 can have the configuration shown in the perspective view in Fig. 42D, for example. In Fig. 42D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0557] PC card 5621 shown in Figure 42E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 42E illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but these semiconductor devices can be understood by referring to the descriptions of semiconductor devices 5626, 5627, and 5628 below.

[0558] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0559] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for the respective terminals include HDMI (registered trademark).

[0560] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 c...

Claims

The transistor includes first to fourth transistors, a first capacitance element, and a second capacitance element, Each of the first to fourth transistors has a gate, a first terminal, and a second terminal; each of the first capacitance element and the second capacitance element has a first electrode and a second electrode; a first terminal of the first transistor is electrically connected to a first electrode of the first capacitance element, a gate of the third transistor, and a gate of the fourth transistor; a first terminal of the second transistor is electrically connected to a second terminal of the first transistor, a second terminal of the fourth transistor, and a first electrode of the second capacitive element; the gates of the first transistor and the second transistor are electrically connected to each other; A semiconductor device in which second electrodes of the first capacitance element and the second capacitance element are electrically connected to each other. 　 In claim 1, a gate of each of the first transistor and the second transistor is electrically connected to a first wiring; a second terminal of the second transistor is electrically connected to a second wiring; a first terminal of the third transistor is electrically connected to a third wiring; a second terminal of the third transistor is electrically connected to a fourth wiring; a first terminal of the fourth transistor is electrically connected to a fifth wiring; The semiconductor device, wherein the second electrodes of the first capacitance element and the second capacitance element are electrically connected to a sixth wiring. 　 In claim 1 or 2, Each of the first to third transistors is a semiconductor device including an oxide semiconductor in a semiconductor layer in which a channel is formed. 　 In claim 1 or 2, The semiconductor device, wherein each of the first to third transistors is a vertical transistor. 　 In claim 1 or 2, The third transistor is a semiconductor device including silicon in a semiconductor layer in which a channel is formed. 　 In claim 1 or 2, The third transistor is a Fin type transistor. 　 A memory cell array including a plurality of semiconductor devices according to claim 1 or 2; a peripheral circuit having a function of writing data to the memory cell array and a function of reading data from the memory cell array; A storage device comprising: 　 The semiconductor memory device includes n first transistors (n is an integer of 3 or more), a second transistor, a third transistor, and n capacitance elements, Each of the n first transistors, the n second transistor, and the n third transistor has a gate, a first terminal, and a second terminal; Each of the n capacitance elements has a first electrode and a second electrode, a first terminal of a first transistor is electrically connected to a first electrode of a first capacitance element, a gate of the second transistor, and a gate of the third transistor; a second terminal of a first first transistor is electrically connected to a second terminal of the third transistor; The first terminal of the i-th (i is an integer equal to or greater than 2 and equal to or less than n-1) first transistor is a second terminal of the (i-1)th first transistor and a first electrode of the i-th capacitance element are electrically connected to each other; The first terminal of the n-th first transistor is a second terminal of the n-1th first transistor and a first electrode of the nth capacitance element; the gates of the n first transistors are electrically connected to each other; The second electrodes of the n capacitance elements are electrically connected to each other. 　 In claim 8, the gate of each of the n first transistors is electrically connected to a first wiring; a second terminal of the n-th first transistor is electrically connected to a second wiring; a first terminal of the second transistor is electrically connected to a third wiring; a second terminal of the second transistor is electrically connected to a fourth wiring; the first terminal of the third transistor is electrically connected to a fifth wiring; A semiconductor device in which the second electrodes of the n capacitance elements are electrically connected to a sixth wiring. 　 In claim 8 or claim 9, The first transistor and the third transistor each include an oxide semiconductor in a semiconductor layer in which a channel is formed. 　 In claim 8 or claim 9, The first transistor is a vertical transistor. 　 In claim 8 or claim 9, The second transistor is a semiconductor device including silicon in a semiconductor layer in which a channel is formed. 　 In claim 8 or claim 9, The second transistor is a Fin type transistor. 　 A memory cell array including a plurality of semiconductor devices according to claim 8 or 9; a peripheral circuit having a function of writing data to the memory cell array and a function of reading data from the memory cell array; A storage device comprising: 　 The semiconductor device includes first to third transistors and first to third capacitance elements, Each of the first to third transistors has a gate, a first terminal, and a second terminal; Each of the first to third capacitive elements has a first electrode and a second electrode, a first terminal of the first transistor is electrically connected to a first electrode of the first capacitance element and a gate of the third transistor; a first terminal of the second transistor is electrically connected to a second terminal of the first transistor, a first electrode of the second capacitance element, and a first electrode of the third capacitance element; the gates of the first transistor and the second transistor are electrically connected to each other; A semiconductor device in which second electrodes of the first capacitance element and the second capacitance element are electrically connected to each other. 　 In claim 15, a gate of each of the first transistor and the second transistor is electrically connected to a first wiring; a second terminal of the second transistor is electrically connected to a second wiring; a first terminal of the third transistor is electrically connected to a third wiring; a second terminal of the third transistor is electrically connected to a fourth wiring; a second electrode of each of the first capacitance element and the second capacitance element is electrically connected to a sixth wiring; The second electrode of the third capacitance element is electrically connected to a fifth wiring. 　 In claim 15 or 16, Each of the first and second transistors is a semiconductor device including an oxide semiconductor in a semiconductor layer in which a channel is formed. 　 In claim 15 or 16, The semiconductor device, wherein each of the first and second transistors is a vertical transistor. 　 In claim 15 or 16, The third transistor is a semiconductor device including silicon in a semiconductor layer in which a channel is formed. 　 In claim 15 or 16, The third transistor is a Fin type transistor. A memory cell array including a plurality of semiconductor devices according to claim 15 or 16; a peripheral circuit having a function of writing data to the memory cell array and a function of reading data from the memory cell array; A storage device comprising:

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