Semiconductor device and production method for same

Abstract

This semiconductor device 100 comprises a source pad part (13p) that is provided on a front surface (11e) of a nitride semiconductor substrate (11) and has a recess (13pa) formed on the nitride semiconductor substrate side, a VIA (15) that passes through the nitride semiconductor substrate (11) at a position that corresponds to the recess (13pa) in the source pad part (13p), a back surface electrode (16c) that is provided on a back surface (11a) of the nitride semiconductor substrate (11), a VIA side wall electrode (16a) that is formed at a side wall of the recess (13pa) and a side wall (15a) of the VIA (15) and connects to the source pad part (13p), and a VIA upper layer electrode (16b) that is formed on the surface of the VIA side wall electrode (16a) and connects the back surface electrode (16c) and the VIA side wall electrode (16a).

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Conventionally, field-effect transistors made of nitride semiconductors have been used as semiconductor devices that operate at high power and high frequencies. In such semiconductor devices, parasitic inductance increases due to high-frequency operation. To address this issue, connecting the front and back electrodes via vias (VIAs) has been used to reduce the parasitic inductance and improve performance. However, this still presents a problem of poor performance and reliability due to poor electrical continuity between the front and back electrodes.

[0003] In order to stabilize the connection via this through hole and improve reliability, for example, Patent Document 1 discloses a configuration in which a diffusion suppression layer is provided in the source pad portion located directly above the through hole that penetrates the semiconductor substrate, thereby suppressing corrosion of the pad layer.

[0004] JP 2016-46306 A (paragraph 0044, FIG. 4)

[0005] However, the configuration of Patent Document 1 has problems such as poor conduction and film peeling of the back electrode when connecting the front electrode and the back electrode via the through-holes, which also leads to problems such as deterioration and instability of transistor characteristics and reduced reliability.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a manufacturing method thereof that suppresses poor conductivity and film peeling of the back electrode when connecting the front electrode and the back electrode via a through hole, and has improved, stabilized, and reliable transistor characteristics.

[0007] The semiconductor device according to the present disclosure is characterized by comprising: a surface electrode provided on a surface of a semiconductor substrate and having a recess formed on the semiconductor substrate side; a through hole provided at a position corresponding to the recess of the surface electrode and penetrating the semiconductor substrate; a first back electrode provided on a back surface of the semiconductor substrate; a second back electrode formed on a side wall of the recess and a side wall of the through hole and connected to the surface electrode; and a third back electrode formed on the surface of the second back electrode and connecting the first back electrode and the second back electrode.

[0008] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure is characterized by including the steps of: forming a surface electrode on a surface of a semiconductor substrate; forming a through hole at the position of the semiconductor substrate where the surface electrode is formed; dry etching the back surface of the surface electrode through the through hole to form a recess on the back surface of the surface electrode; and simultaneously forming a second back surface electrode on the side wall of the through hole, the second back surface electrode connecting to the side wall of the recess; and forming a third back surface electrode on the surface of the second back surface electrode, the third back surface electrode connecting to the second back surface electrode, and a first back surface electrode on the back surface of the semiconductor substrate, the third back surface electrode connecting to the third back surface electrode.

[0009] According to the present disclosure, it is possible to obtain a semiconductor device with excellent reliability, in which the connection between the front electrode and the back electrode via the through-hole has good conductivity, and the transistor characteristics are improved and stabilized.

[0010] 1 is a top view showing a configuration of a semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; FIG. 3 is a cross-sectional view showing a configuration of a pad portion of the semiconductor device according to the first embodiment; FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment; FIG. 7 is a top view showing a configuration of a semiconductor device according to a second embodiment; FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment; FIG. 9 is a cross-sectional view showing another configuration of the semiconductor device according to the second embodiment; FIG. 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment;

[0011] First Embodiment Fig. 1 is a top view showing a configuration of a semiconductor device 100 according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along the line AA in Fig. 1. Fig. 3 is a cross-sectional view taken along the line BB in Fig. 1.

[0012] In the semiconductor device 100 shown in FIG. 1, a drain electrode 12, a source electrode 13, and a gate electrode 14 are provided as surface electrodes 22 on a semiconductor substrate 11 as semiconductor elements, thereby constituting a high electron mobility transistor (HEMT).

[0013] These various electrodes (drain electrode 12, source electrode 13, gate electrode 14) each have a pad portion (drain pad portion 12p, source pad portion 13p, gate pad portion 14p) and a finger portion (drain finger portion 12f, source finger portion 13f, gate finger portion 14f), and the gate finger portion 14f is arranged between the drain finger portion 12f and the source finger portion 13f.

[0014] 2, the semiconductor substrate 11 has a back surface 11a and a front surface 11e of the semiconductor substrate, and the substrate 11b is, for example, a Si substrate, a SiC substrate, or a GaN substrate. The following describes the case where a GaN substrate is used.

[0015] On the surface of the GaN substrate 11b, a GaN 11c serving as an electron transit layer and an AlGaN 11d serving as an electron supply layer are provided in this order. The GaN substrate 11b is a layered structure having a thickness of approximately 10 μm to 100 μm, and the GaN 11c and AlGaN 11d each having a thickness of approximately 10 nm to 10 μm. The GaN 11c and AlGaN 11d are epitaxial layers formed by epitaxial growth.

[0016] By using a layered structure of nitride semiconductors such as GaN 11c and AlGaN 11d, a high-mobility two-dimensional electron layer can be formed, enabling the fabrication of a semiconductor device capable of high-frequency and high-power operation. Since a layered structure of nitrides of GaN 11c and AlGaN 11d is formed on the GaN substrate 11b, the layered structure of the GaN substrate 11b, GaN 11c, and AlGaN 11d is referred to as the nitride semiconductor substrate 11. A transistor with higher efficiency may be fabricated by further inserting an AlN layer into this layered structure or by forming a GaN layer on the top layer.

[0017] Various finger portions (drain finger portion 12 f, source finger portion 13 f, gate finger portion 14 f) are provided on the surface 11 e of the nitride semiconductor substrate 11. The gate finger portion 14 f forms a Schottky junction with the nitride semiconductor substrate 11 and is configured by laminating, for example, Pt, Ti, Pt, and Au in this order. The lower layer is Pt to form the Schottky junction, and Au or the like is laminated to reduce resistance.

[0018] The drain finger portion 12f and the source finger portion 13f are in ohmic contact with the nitride semiconductor substrate 11 and are made of, for example, Ti, Nb, Pt, and Au, and are laminated to a thickness of approximately 10 nm to 10 μm. From the viewpoint of adhesion, Ti is formed as the bottom layer. From the viewpoint of low resistance, Au is formed as the thickest layer.

[0019] Another metal film may be further formed to serve as an etching stop layer when forming the VIA before, during, or after forming the surface electrode 22. For example, Ni or a compound thereof having a high selectivity with respect to GaN 11c and AlGaN 11d is used when etching the VIA.

[0020] The above-mentioned metals are materials in which defect levels are unlikely to be formed in the substrate, and therefore the stability of transistor characteristics is improved.

[0021] A backside electrode 16c is provided on the backside 11a of the nitride semiconductor substrate 11. Connecting the backside electrode 16c to the source electrode 13 provided on the frontside 11e via a via 15 is effective in reducing parasitic inductance that increases during high frequency operation, thereby improving transistor characteristics. Note that, since the source electrode 13 is generally connected to ground, the backside electrode 16c is generally connected to the source electrode 13 and grounded.

[0022] 3, the source pad portion 13p has a recess 13pa on the back surface. Directly below the source pad portion 13p, a via 15 is provided that penetrates the nitride semiconductor substrate 11 in a tapered shape. The via 15 is tapered so as to be inclined (tapered) toward the recess 13pa of the source pad portion 13p.

[0023] The source pad portion 13p is electrically connected to a back surface electrode 16c provided on the back surface 11a of the nitride semiconductor substrate 11 via the recess 13pa of the source pad portion 13p and the via 15. The back surface electrode 16 includes: a back surface electrode 16c which is a first back surface electrode; a via sidewall electrode 16a which is a second back surface electrode provided on the sidewall 15a of the via 15 and on the sidewall of the recess 13pa of the source pad portion 13p and electrically connected to the source pad portion 13p; and a via upper layer electrode 16b which is a third back surface electrode provided on the sidewall 15a of the via 15, on the surface of the via sidewall electrode 16a, and in the center of the recess 13pa of the source pad portion 13p and electrically connected to the via sidewall electrode 16a and the back surface electrode 16c.

[0024] The VIA sidewall electrode 16a contains at least one element from the constituent material of the surface electrode 22. This reduces the difference in thermal expansion coefficient between the surface electrode 22 and the VIA sidewall electrode 16a, preventing peeling between them. The VIA sidewall electrode 16a may also be mainly composed of Au. The use of Au, which has high electrical conductivity, improves electrical conduction between the surface electrode 22 and the back electrode 16.

[0025] The via upper layer electrode 16b has a laminated structure of, for example, Ti, Pt, Au, etc. The via upper layer electrode 16b preferably has a structure in which the bottom layer is Ti and the thickest layer is Au. This is because, from the viewpoint of preventing peeling, it is effective to have a laminated structure with Ti as the bottom layer. Also, from the viewpoint of electrical conductivity, it is effective to have Au as the thickest layer.

[0026] In the first embodiment, the recess 13pa of the source pad portion 13p has a flat bottom surface (see FIG. 4A), but this is not limited thereto. As shown in FIG. 4B, the bottom surface of the recess 13pb may be recessed. Also, as shown in FIG. 4C, the bottom surface of the recess 13pc may have multiple recesses. This increases the contact area between the front surface electrode 22 and the back surface electrode 16, improving electrical connection.

[0027] In the first embodiment, the source pad portion 13p is connected to the back surface electrode 16, but this is not limitative. The source finger portion 13f may be connected, or any electrode may be connected as long as it is the front surface electrode 22.

[0028] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment of the present disclosure will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a flowchart showing the method for manufacturing the semiconductor device 100 according to the first embodiment. Fig. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0029] First, a GaN layer 11c and an AlGaN layer 11d are epitaxially grown on the surface of a GaN substrate 11b to form a nitride semiconductor substrate 11 (step S501 in FIG. 5).

[0030] 6A, a source electrode 13 including a source pad portion 13p is formed in a desired region of the surface 11e of the nitride semiconductor substrate 11 by vapor deposition and lift-off, and an ohmic contact is formed on the surface 11e of the nitride semiconductor substrate 11 through an annealing process (step S502 in FIG. 5). At this time, a drain electrode 12 is also formed.

[0031] The source electrode 13 and the drain electrode 12 are made of Ti, Nb, Pt, and Au, and are laminated to a thickness of about 10 nm to 10 μm. Ti is deposited first from the viewpoint of adhesion to the substrate, and Au is deposited to the thickest thickness from the viewpoint of reducing resistance.

[0032] Next, a gate electrode is formed by sputtering or vapor deposition and lift-off (step S503 in FIG. 5). A Schottky contact is formed on the surface 11e of the nitride semiconductor substrate 11.

[0033] Next, a protective film 24 is formed on these electrodes by the CVD method (see FIG. 6B), and then openings are made in the protective film 24 above the source electrode 13 and the drain electrode 12. Subsequently, a metal is formed by the sputtering method or the vapor deposition method and the lift-off method to thicken the source electrode 13 and the drain electrode 12 (step S504 in FIG. 5).

[0034] After this, a protective film may be formed on these electrodes, and then openings may be formed in the protective film above the electrodes, and metal may be formed on top of the openings like piers to establish electrical connection between the electrodes (step S505 in FIG. 5).

[0035] Next, the back surface of the substrate is processed. A protective film may be formed on the front surface of the substrate, and the substrate may be attached to a support substrate with the back surface facing up. This is to prevent adverse effects on the transistors on the front surface due to contact, etc.

[0036] Next, the nitride semiconductor substrate 11 is thinned by grinding and polishing (step S506 in FIG. 5 ) in order to facilitate connection by shortening the distance between the front surface electrode 22 and the back surface electrode 16 when connecting them by the VIA 15, and to reduce parasitic impedance.

[0037] Next, as shown in FIG. 6C, a Ni mask 25 is formed on the rear surface 11a of the nitride semiconductor substrate 11, and using this as a mask, VIAs 15 are formed in the substrate below the source pad portions 13p by dry etching (step S507 in FIG. 5).

[0038] Next, the source pad portion 13p is excavated by dry etching to form a recess 13pa in the source pad portion 13p, and at the same time, a VIA sidewall electrode 16a connected to the source pad portion 13p is formed on the sidewall of the recess 13pa of the source pad portion 13p and the sidewall 15a of the VIA 15 by a sputtering effect using the excavated source pad portion 13p (step S508 in FIG. 5). With this method, the VIA sidewall electrode 16a can be formed to be thicker the closer it is to the source pad portion 13p (see FIG. 6D).

[0039] The dry etching conditions were as follows: Cl-based gas was used, and the bias power to the substrate was 1 W / cm ２ The power is set to high. The substrate temperature is set to about 0°C to 150°C. This allows Au, the material for the source pad, to be efficiently sputtered and deposited on the inner wall of the VIA. The upper temperature limit is set so as not to affect the transistor characteristics. Lowering the substrate temperature can promote the deposition of Au on the inner wall of the VIA. The lower temperature limit is set so that by-products produced during etching do not cause poor electrical connections.

[0040] The VIA sidewall electrode 16a is formed from the metal elements of the surface electrode 22, with Au being the main component. This reflects the fact that Au is formed in the thickest thickness in the surface electrode 22. The VIA sidewall electrode 16a may also contain other metals used in the surface electrode 22, or may be a mixture containing Cl-based gas used in VIA etching, Ni from the Ni mask, Ga and N from the substrate, etc.

[0041] Finally, after removing the Ni mask 25, the via upper layer electrode 16b and the backside electrode 16c are formed (step S509 in FIG. 5), completing the manufacturing method for the semiconductor device 100 shown in FIG. 3. The via upper layer electrode 16b has a metal layered structure, for example, in which Ti, Pt, and Au are formed in that order. The via upper layer electrode 16b has a layered structure in which Ti is the bottom layer, for example, from the viewpoint of adhesion. The via upper layer electrode 16b has the thickest Au layer in the top layer, from the viewpoint of improving electrical conductivity. This allows both adhesion and electrical conductivity to be achieved.

[0042] The via upper layer electrode 16b is formed by sputtering or vapor deposition. Due to its film formation characteristics, the via upper layer electrode 16b is formed thinner as it approaches the source pad portion 13p in the depth direction of the via, but the via sidewall electrode 16a is formed thicker as it approaches the source pad portion 13p, so the thickness of the electrode in the depth direction within the via can be secured.

[0043] The VIA upper electrode 16b may be formed thick on the bottom surface of the recess 13pa of the source pad portion 13p by increasing the linearity of the reaction gas during film formation under high vacuum (see FIG. 7). This increases the conductivity of the back electrode 16 in contact with the front electrode 22.

[0044] The back electrode 16c has a metal laminate structure, for example, with Ti, Pt, and Au formed in that order. The back electrode 16c may be formed simultaneously with the VIA upper electrode 16b by the same film formation method. Alternatively, the back electrode 16c may be formed separately from the VIA upper electrode 16b in order to reduce the stress on the substrate caused by the back electrode 16c and to improve the coverage of the VIA upper electrode 16b within the VIA.

[0045] As described above, the semiconductor device 100 according to the first embodiment includes the source pad portion 13p provided on the front surface 11e of the nitride semiconductor substrate 11 and having the recess 13pa formed on the nitride semiconductor substrate side, the via 15 provided at a position corresponding to the recess 13pa of the source pad portion 13p and penetrating the nitride semiconductor substrate 11, the backside electrode 16c provided on the back surface 11a of the nitride semiconductor substrate 11, the via sidewall electrode 16a formed on the sidewall of the recess 13pa and the sidewall 15a of the via 15 and connecting to the source pad portion 13p, and the via upper layer electrode 16b formed on the surface of the via sidewall electrode 16a and connecting the backside electrode 16c and the via sidewall electrode 16a.

[0046] The manufacturing method of the semiconductor device 100 according to the first embodiment includes the steps of: forming a source pad portion 13p on the front surface 11e of the nitride semiconductor substrate 11; forming a via 15 at the position of the nitride semiconductor substrate 11 where the source pad portion 13p is formed; dry-etching the rear surface of the source pad portion 13p through the via 15 to form a recess 13pa on the rear surface of the source pad portion 13p, and simultaneously forming a via sidewall electrode 16a on the sidewall 15a of the via 15, the via sidewall electrode 16a connecting to the sidewall of the recess 13pa; and forming a via upper-layer electrode 16b connecting to the via sidewall electrode 16a on the front surface of the via sidewall electrode 16a, and a backside electrode 16c connecting to the via upper-layer electrode 16b on the rear surface 11a of the nitride semiconductor substrate 11.

[0047] As a result, in the connection between the front surface electrode and the back surface electrode via a VIA, the back surface electrode includes a VIA sidewall electrode and a VIA upper layer electrode, thereby ensuring the electrode thickness in the depth direction within the VIA. Furthermore, the front surface electrode has a recess in the VIA region, which increases the connection area between the front surface electrode and the back surface electrode and improves the electrical connection. As a result, in the connection between the front surface electrode and the back surface electrode via the through-hole, good conductivity is achieved, improving and stabilizing transistor characteristics, and a highly reliable semiconductor device can be obtained. Furthermore, since the VIA sidewall electrode can be formed on the sidewall of the VIA at the same time as forming the recess in the front surface electrode, semiconductor devices can be manufactured efficiently and at low cost.

[0048] Second Embodiment In the first embodiment, the case where the vias 15 are arranged in the source pad portion 13p has been described, but in the second embodiment, the case where the vias 15 are arranged in the source finger portion 13f will be described.

[0049] 8 is a top view showing the configuration of a semiconductor device 101 according to a second embodiment of the present disclosure. As shown in Fig. 8, the semiconductor device 101 does not require the source pad portion 13p provided in the semiconductor device 100 according to the first embodiment, and the vias 15 are disposed directly in the source finger portions 13f. This reduces inductance and improves transistor characteristics.

[0050] In the configuration of the semiconductor device 101, the vias 15 are arranged in the source finger portions 13f, and therefore the size of the vias 15 is smaller than the size of the vias 15 of the semiconductor device 100 due to restrictions imposed by the line width of the source finger portions 13f.

[0051] 9 is a cross-sectional view showing the configuration of a semiconductor device 101 according to a second embodiment of the present disclosure. As shown in FIG. 9 , the semiconductor device 101 has a structure in which the maximum thickness position 16aw of the via sidewall electrode 16a is moved away from the bottom of the recess 13pa. That is, the thickness of the via sidewall electrode 16a is greatest at a position far from the bottom of the recess 13pa. This results in a gentler taper angle of the via sidewall electrode 16a inside the via 15, which ensures the thickness of the via upper-layer electrode 16b in the region in contact with the via upper-layer electrode 16b, thereby improving electrical conductivity inside the via 15.

[0052] In order to move the maximum thickness position 16aw of the VIA sidewall electrode 16a to a position away from the bottom of the recess 13pa, there is a method of reducing the bias power during VIA etching. For example, when the bias power is set to 1 W / cm ２ to 0.1 W / cm ２ As the bias power is reduced to , the maximum thickness position 16aw of the VIA sidewall electrode 16a moves away from the bottom of the recess 13pa. This is because the reduction in bias power reduces the etching anisotropy, promoting the formation of an overhang shape in the VIA sidewall electrode 16a.

[0053] Other configurations and manufacturing methods of the semiconductor device 101 according to the second embodiment are similar to those of the semiconductor device 100 according to the first embodiment, and corresponding parts are designated by the same reference numerals and description thereof will be omitted.

[0054] In the second embodiment, the maximum thickness position 16aw of the VIA sidewall electrode 16a is moved to a position away from the bottom of the recess 13pa in order to ensure electrical continuity, but the present invention is not limited to this.

[0055] 10 is a top view showing another configuration of a semiconductor device 101 according to a second embodiment of the present disclosure. The semiconductor device 101 shown in Fig. 10 has a structure in which the positions of the source electrode 13 and the drain electrode 12 are interchanged with respect to the semiconductor device 101 shown in Fig. 8, with the source electrode 13 being disposed on the outer periphery. This increases the number of VIAs 15, improving the electrical connection between the front surface electrode 22 and the back surface electrode 16.

[0056] As described above, in the semiconductor device 101 according to the second embodiment, the vias 15 are disposed at the positions of the source finger portions 13f of the nitride semiconductor substrate 11, and the maximum thickness position 16aw of the via sidewall electrodes 16a is moved away from the bottom of the recesses 13pa, so that the source pad portion is unnecessary, the inductance is reduced, and the transistor characteristics are improved. Furthermore, the thickness of the via upper layer electrode can be secured in the region in contact with the via upper layer electrode, and the electrical conductivity inside the via can be improved.

[0057] Third Embodiment In a third embodiment, a case will be described in which dry etching is performed in a plurality of steps to form the vias 15.

[0058] In the third embodiment, in the manufacturing method of the semiconductor device of the first embodiment, dry etching is performed in multiple steps in the process of forming vias 15 at the positions of source pad portions 13p of nitride semiconductor substrate 11. After each dry etching, cleaning is performed to remove residues in the vias. A Cl-based gas is used in the dry etching, and wet etching using diluted hydrochloric acid or the like is used in the cleaning to remove residues in the vias.

[0059] 11 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a third embodiment of the present disclosure. According to the manufacturing method of a semiconductor device according to the third embodiment, after each dry etching, residues in the vias are removed by wet etching, and the substrate on the sidewalls of the vias is etched by reacting with a Cl-based gas, forming minute holes in the sidewalls 15a of the vias 15, as shown in FIG. 11 . The opening diameter of the holes is, for example, about 0.1 μm to 3 μm. By raising the substrate temperature during dry etching (for example, to 150° C.), reactivity with the nitride semiconductor substrate 11 is promoted, allowing the diameter of the minute holes to be increased.

[0060] Other configurations and manufacturing methods of the semiconductor device according to the third embodiment are similar to those of the semiconductor device 100 according to the first embodiment, and corresponding parts are designated by the same reference numerals and description thereof will be omitted.

[0061] By forming minute holes in the sidewalls 15a of the vias 15, the adhesion between the via sidewall electrodes 16a and upper via electrodes 16b, which are back electrodes, and the sidewalls 15a of the vias 15 is improved, thereby improving reliability.

[0062] As described above, according to the manufacturing method of the semiconductor device of the third embodiment, the process of forming the VIA 15 involves alternately performing dry etching and wet etching multiple times. Therefore, by forming a minute hole in the side wall of the VIA, the adhesion between the back electrode and the side wall of the VIA is improved, thereby improving reliability.

[0063] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are contemplated within the scope of the technology disclosed in this disclosure specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0064] REFERENCE SIGNS LIST 11 nitride semiconductor substrate (semiconductor substrate), 11a back surface, 11e front surface, 12 drain electrode, 12f drain finger portion, 12p drain pad portion, 13 source electrode, 13f source finger portion, 13p source pad portion, 13pa, 13pb, 13pc recess, 14 gate electrode, 14f gate finger portion, 14p gate pad portion, 15 VIA (through hole), 15a side wall, 16 back surface electrode, 16a VIA sidewall electrode (second back surface electrode), 16b VIA upper layer electrode (third back surface electrode), 16c back surface electrode (first back surface electrode), 22 front surface electrode, 100, 101 semiconductor device.

Claims

1. A semiconductor device, comprising: a surface electrode provided on a surface of a semiconductor substrate, with a recess formed on the semiconductor substrate side; a through hole provided at a position corresponding to the recess of the surface electrode and penetrating the semiconductor substrate; a first back surface electrode provided on a back surface of the semiconductor substrate; a second back surface electrode formed on side walls of the recess and the through hole and connected to the surface electrode; and a third back surface electrode formed on a surface of the second back surface electrode and connecting the first back surface electrode and the second back surface electrode.

2. The semiconductor device according to claim 1, wherein the second back surface electrode is formed thicker as it approaches the surface electrode.

3. The semiconductor device according to claim 1, wherein a position of a maximum thickness of the second back surface electrode is provided at a position away from a bottom position of the recess.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second back surface electrode is composed of one or more elements among elements included in the surface electrode.

5. The semiconductor device according to any one of claims 1 to 4, wherein the second back surface electrode has Au as a main component.

6. The semiconductor device according to any one of claims 1 to 5, wherein the third back surface electrode has a laminated structure of a plurality of metals.

7. The semiconductor device according to any one of claims 1 to 6, wherein the third back surface electrode is formed thicker as it approaches the first back surface electrode.

8. The semiconductor device according to any one of claims 1 to 7, wherein the through hole has a hole shape provided on its side wall.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate has a laminated structure including a GaN layer and an AlGaN layer.

10. A step of forming a surface electrode on the surface of a semiconductor substrate; a step of forming a through hole at a position where the surface electrode of the semiconductor substrate is formed; a step of dry etching the back surface of the surface electrode through the through hole to form a concave portion on the back surface of the surface electrode, and at the same time, forming a second back surface electrode connected to the side wall of the concave portion on the side wall of the through hole; and a step of forming a third back surface electrode connected to the second back surface electrode on the surface of the second back surface electrode and a first back surface electrode connected to the third back surface electrode on the back surface of the semiconductor substrate. A method for manufacturing a semiconductor device, characterized by including these steps.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the step of forming the through hole is characterized by performing dry etching and wet etching alternately a plurality of times.

Images