Semiconductor device, semiconductor module, and electronic apparatus

Abstract

This semiconductor device includes a Schottky gate type transistor. The Schottky gate type transistor comprises: a semiconductor that has a first crystal orientation on a surface thereof; and a control electrode that is in contact with said surface, is formed from a metal having a face-centered cubic lattice structure having a second crystal orientation, and is configured such that, in at least a portion thereof perpendicular to or parallel to the surface, the second crystal orientation conforms to the first crystal orientation.

Description

Semiconductor device, semiconductor module and electronic device

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and an electronic device.

[0002] For power amplifiers for communications, higher output and higher efficiency at high frequencies are desired. For this reason, high electron mobility transistors (HEMTs) are used as transistors for constructing power amplifiers. Metal-insulator semiconductor (MIS) HEMTs experience fluctuations in threshold voltage (Vth) due to voltage stress during transistor operation. For this reason, MIS HEMTs have not yet been put to practical use. Therefore, research and development of Schottky-gate HEMTs is underway. A Schottky-gate HEMT is disclosed, for example, in Patent Document 1.

[0003] JP 2013-77620 A

[0004] There is a concern that Schottky gate HEMTs may generate off-state leakage current, and therefore there is a need to develop semiconductor devices, semiconductor modules, and electronic devices that include Schottky gate HEMTs that can reduce leakage current.

[0005] A semiconductor device according to a first embodiment of the present disclosure includes a Schottky gate transistor, the Schottky gate transistor including a semiconductor having a first crystal orientation on a surface thereof, and a control electrode in contact with the surface, the control electrode being formed of a metal having a face-centered cubic lattice structure and a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction perpendicular or parallel to the surface.

[0006] In a semiconductor device according to a second embodiment of the present disclosure, the semiconductor is a barrier layer or a composite layer formed by laminating a cap layer on a barrier layer. The barrier layer or the cap layer is GaN having a first crystal orientation in the <1-210> direction. The control electrode has a second crystal orientation in the <11-2> direction.

[0007] A semiconductor module according to a third embodiment of the present disclosure includes a semiconductor device. The semiconductor device includes a Schottky gate transistor. The Schottky gate transistor includes a semiconductor having a first crystal orientation on a surface thereof, and a control electrode in contact with the surface, the control electrode being formed of a metal having a face-centered cubic lattice structure and having a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction perpendicular or parallel to the surface.

[0008] An electronic device according to a fourth embodiment of the present disclosure includes a semiconductor device. The semiconductor device includes a Schottky gate transistor. The Schottky gate transistor includes a semiconductor having a first crystal orientation on a surface thereof, and a control electrode in contact with the surface, the control electrode being formed of a metal having a face-centered cubic lattice structure and a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction perpendicular or parallel to the surface.

[0009] FIG. 1 is a vertical cross-sectional view of a semiconductor device including a Schottky gate transistor according to a first embodiment of the present disclosure. FIG. 2A is an enlarged vertical cross-sectional view of a main portion of the Schottky gate transistor shown in FIG. 1. FIG. 2B is a schematic diagram illustrating the crystalline structure and crystal orientation of a semiconductor constituting the Schottky gate transistor shown in FIG. 2A. FIG. 2C is a schematic diagram illustrating the crystalline structure and crystal orientation of a control electrode constituting the Schottky gate transistor shown in FIG. 2A. FIG. 2D is a schematic diagram illustrating the symmetrical crystalline structure and crystal orientation of the control electrode shown in FIG. 2C. FIG. 3A is a diagram illustrating the analysis results of the control electrode shown in FIG. 2A by out-of-plane X-ray diffraction (XRD) measurement. FIG. 3B is a diagram illustrating the analysis results of the control electrode shown in FIG. 2A by in-plane XRD measurement. FIG. 4A is a diagram illustrating the analysis results of the control electrode of a Schottky gate transistor according to a comparative example by out-of-plane XRD measurement. FIG. 4B is a diagram showing analysis results of the control electrode of the Schottky gate transistor according to the comparative example by in-plane XRD measurement. FIG. 5 is a graph showing measurement results of peak half-widths by asymmetric reflection measurement of the control electrode according to the first embodiment and the control electrode according to the comparative example in out-of-plane X-ray diffraction measurement. FIG. 6 is a graph showing transfer characteristics of the Schottky gate transistor according to the first embodiment and the Schottky gate transistor according to the comparative example. FIG. 7A is a graph showing on-stress test results of the Schottky gate transistor according to the first embodiment. FIG. 7B is a graph showing off-stress test results of the Schottky gate transistor according to the first embodiment. FIG. 8A is a graph showing on-stress test results of the Schottky gate transistor according to the comparative example. FIG. 8B is a graph showing off-stress test results of the Schottky gate transistor according to the comparative example. FIG. 9 is a vertical cross-sectional configuration diagram at a first step for explaining a manufacturing method of a semiconductor device incorporating the Schottky gate transistor according to the first embodiment. FIG. 10 is a vertical cross-sectional configuration diagram at a second step.Fig. 11 is a vertical cross-sectional configuration diagram of a third process. Fig. 12 is a vertical cross-sectional configuration diagram of a fourth process. Fig. 13 is a vertical cross-sectional configuration diagram of a fifth process. Fig. 14 is a vertical cross-sectional configuration diagram of a sixth process. Fig. 15 is a vertical cross-sectional configuration diagram of a seventh process. Fig. 16 is a vertical cross-sectional configuration diagram of an eighth process. Fig. 17 is a perspective view of a semiconductor module according to a second embodiment of the present disclosure. Fig. 18 is a block configuration diagram of an electronic device according to a third embodiment of the present disclosure.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment is a first example in which the present technology is applied to a semiconductor device equipped with a Schottky gate transistor. The first embodiment describes the longitudinal cross-sectional configuration and manufacturing method of the Schottky gate transistor. Furthermore, the first embodiment describes in detail the physical characteristics and electrical characteristics of the Schottky gate transistor in comparison with a Schottky gate transistor according to a comparative example. 2. Second Embodiment The second embodiment is a second example that describes a semiconductor module in which the semiconductor device according to the first embodiment is mounted. 3. Third Embodiment The third embodiment is a third example that describes an electronic device in which the semiconductor device according to the first embodiment is mounted. 4. Other Embodiments

[0011] 1 to 16 , a semiconductor device 1 according to a first embodiment of the present disclosure will be described. Here, the arrow X direction shown as appropriate in the drawings conveniently represents one planar direction of the semiconductor device 1 placed on a flat surface. The arrow Y direction represents another planar direction perpendicular to the arrow X direction. Furthermore, the arrow Z direction represents an upward direction perpendicular to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are illustrated to facilitate understanding of the description and do not limit the directions of the present technology.

[0012] [Configuration of Semiconductor Device 1] (1) Schematic Configuration of Schottky Gate Transistor Tr FIG. 1 shows an example of a vertical cross-sectional configuration of a semiconductor device 1 according to a first embodiment.

[0013] In the first embodiment, the semiconductor device 1 includes, as a main component, a Schottky gate transistor Tr for constructing, for example, a power device, a high-frequency device, etc. As the Schottky gate transistor Tr, for example, a Schottky barrier junction type HEMT is used. Here, the Schottky gate transistor Tr is formed as an n-channel conductivity type in which electrons are the majority carriers.

[0014] The Schottky gate transistor Tr includes, as its main components, a semiconductor 12 disposed on a substrate 10 with a buffer layer 11 interposed therebetween, a control electrode 20, and a pair of main electrodes 21.

[0015] (2) Structure of the Substrate 10 The semiconductor device 1 is configured based on the substrate 10. In the first embodiment, the substrate 10 is made of silicon carbide (SiC). The substrate 10 may be made of silicon (Si) or sapphire (Al ２ O ３ ) may be formed.

[0016] (3) Configuration of Buffer Layer 11 The buffer layer 11 is stacked on the surface of the substrate 10 in the direction of the arrow Z. The buffer layer 11 is used to ensure lattice matching between the substrate 10 and the semiconductor 12. In the first embodiment, the buffer layer 11 is made of aluminum gallium nitride (AlGaN). Alternatively, the buffer layer 11 may be made of aluminum nitride (AlN) or gallium nitride (GaN).

[0017] (4) Structure of the Semiconductor 12 The semiconductor 12 is stacked on the surface of the buffer layer 11 in the direction of the arrow Z. The semiconductor 12 is formed by sequentially stacking a channel layer 121, a spacer layer 122, a barrier layer 123, and a cap layer 124. The semiconductor 12 is basically formed of a III-V group compound semiconductor material as a compound semiconductor. This will be described in detail.

[0018] (4-1) Configuration of Channel Layer 121 The channel layer 121 is stacked on the surface of the buffer layer 11. The channel layer 121 is made of, for example, GaN. In the channel layer 121, carriers are accumulated near the spacer layer 122, and a two-dimensional electron gas (2DEG) that functions as a channel region for the carriers is generated.

[0019] (4-2) Configuration of Spacer Layer 122 The spacer layer 122 is stacked on the surface of the channel layer 121. The spacer layer 122 is made of, for example, AlN.

[0020] (4-3) Structure of Barrier Layer 123 The barrier layer 123 is laminated on the surface of the spacer layer 122. The barrier layer 123 is made of a compound semiconductor material that accumulates carriers in the channel layer 121 due to polarization with the channel layer 121. The barrier layer 123 is made of, for example, Al １－ｘ－ｙ Ga ｘ In ｙ The barrier layer 123 is made of AlInN (0≦x<1, 0≦y<1). Specifically, the barrier layer 123 is made of, for example, AlInN or AlGaN.

[0021] (4-4) Configuration of Cap Layer 124 The cap layer 124 is laminated on the surface of the barrier layer 123. In the first embodiment, the cap layer 124 is made of GaN. The crystal structure of GaN is a hexagonal wurtzite structure. The crystal structure of the cap layer 124 will be described in detail later. The cap layer 124 may also be made of silicon nitride (SiN).

[0022] Furthermore, in the first embodiment, the uppermost layer of the semiconductor 12 may be the barrier layer 123 , excluding the cap layer 124 .

[0023] (5) Configuration of Control Electrode 20 The control electrode 20 is stacked on the surface of the cap layer 124 of the semiconductor 12 and is formed as a gate electrode that contacts the cap layer 124 and forms a Schottky junction. In the first embodiment, the control electrode 20 is formed of a composite film in which nickel (Ni) 201 and gold (Au) 202 are sequentially stacked in the direction of the arrow Z. That is, the control electrode 20 contacts at least the surface of the cap layer 124 and is formed of a metal with a face-centered cubic lattice structure in at least a portion of the vertical direction (direction of the arrow Z) or horizontal direction (direction of the arrow X or arrow Y) relative to this surface. Here, the entire control electrode 20 is formed of a metal with a face-centered cubic lattice structure.

[0024] The control electrode 20 may be formed to contain the Ni 201 and Au 202, and may also contain one or more selected from copper (Cu), Al, platinum (Pt), and palladium (Pd).

[0025] (6) Configuration of the Main Electrode 21 A pair of main electrodes 21 are disposed on the surface of the cap layer 124 of the semiconductor 12, spaced apart from each other at both ends of the control electrode 20 in the gate length direction. One of the main electrodes 21 is used, for example, as a source electrode (S), and the other main electrode 21 is used, for example, as a drain electrode (D).

[0026] The pair of main electrodes 21 are formed of an electrode material that is in ohmic contact or near-ohmic contact with the cap layer 124. The pair of main electrodes 21 are formed of a composite film in which titanium (Ti), molybdenum (Mo), Al, Ni, and Au are sequentially laminated, for example.

[0027] Although not shown in the first embodiment, an n-type semiconductor region with a high impurity concentration may be disposed in the semiconductor 12 in the overlapping region of the pair of main electrodes 21. The n-type semiconductor region is used as a source region or a drain region, and is electrically connected to the pair of main electrodes 21 by ohmic contact. The n-type semiconductor region is formed to reach at least the channel layer 121 of the semiconductor 12 in order to be electrically connected to the two-dimensional electron gas 2DEG.

[0028] (7) Crystal Structure and Crystal Orientation of the Semiconductor 12 and the Control Electrode 20 Fig. 2A shows an example of an enlarged vertical cross-sectional configuration of a main part of a Schottky gate transistor Tr, including the semiconductor 12 and the control electrode 20. As shown in Fig. 2A, in the Schottky gate transistor Tr, the control electrode 20 is disposed on the surface of the cap layer 124 of the semiconductor 12.

[0029] 2B schematically shows an example of the crystal structure and crystal orientation of the compound semiconductor forming the cap layer 124 when the surface of the cap layer 124 is viewed from the direction of the arrow Z (hereinafter simply referred to as "in a plan view"). FIG. 2C schematically shows an example of the crystal structure and crystal orientation of the metal forming the control electrode 20 in a plan view. FIG. 2D also schematically shows an example of the symmetrical crystal structure and crystal orientation of the metal forming the control electrode 20 shown in FIG. 2C in a plan view.

[0030] In the first embodiment, the cap layer 124 of the semiconductor 12 is formed of GaN. As described above, the crystal structure of GaN is a hexagonal wurtzite structure. When the cap layer 124 is grown by epitaxial growth using an epitaxial growth method, a (0001) crystal plane of GaN is formed on the surface of the cap layer 124, as shown in FIG. 2B . When the (0001) crystal plane coincides with the plane defined by the arrow X direction and the arrow Y direction, the crystal orientation coincides with the arrow Y direction is the <1-210> direction. This direction is equivalent to the a-axis. The crystal orientation in the <1-210> direction corresponds to the "first crystal orientation" according to the present technology.

[0031] On the other hand, in the first embodiment, the control electrode 20 is formed by sequentially stacking Ni 201 and Au 202. The crystal structures of Ni 201 and Au 202 are identical cubic crystals in single crystal, and are face-centered cubic (fcc) structures. The crystal plane of the control electrode 20 contacts the surface of the cap layer 124. For example, when the control electrode 20 is formed of Au 202, as shown in FIG. 2C , the (111) plane of Au 202 contacts the (0001) crystal plane of GaN. When the (111) crystal plane coincides with the plane defined by the arrow X direction and the arrow Y direction, the crystal orientation coincides with the arrow Y direction is the <11-2> direction. The crystal orientation in the <11-2> direction corresponds to the "second crystal orientation" according to the present technology.

[0032] In the Schottky gate transistor Tr according to the first embodiment, the <1-210> direction, which is the crystal orientation of the cap layer 124, and the <11-2> direction, which is the crystal orientation of the control electrode 20, are aligned in at least a portion of the direction perpendicular or horizontal to the surface of the cap layer 124.

[0033] As shown in Figure 2C, the crystal orientation of Au202 has equivalent directions at 120 degrees and 240 degrees clockwise, respectively, based on the <11-2> direction, which coincides with the direction of the arrow Y from the center of the (111) crystal plane. In other words, in an asymmetric reflection measurement of out-of-plane XRD, the crystal orientation of Au202 has three-fold symmetry. Furthermore, as shown in Figure 2D, when the crystal is rotated 180 degrees around the center of the (111) crystal plane of Au202, three-fold symmetry exists in the crystal orientation of Au202, in addition to the crystal orientation of Au202 shown in Figure 2C. In other words, in an asymmetric reflection measurement, the crystal orientation of Au202 has a total of six-fold symmetry.

[0034] (8) XRD Analysis Results of Control Electrode 20 Fig. 3A shows an example of the analysis results of the control electrode 20 shown in Fig. 2A by out-of-plane XRD measurement. Fig. 3B shows an example of the analysis results of the control electrode 20 shown in Fig. 2A by in-plane XRD measurement. Fig. 4A shows an example of the analysis results of the control electrode of a Schottky gate transistor according to a comparative example by out-of-plane XRD measurement. Fig. 4B shows an example of the analysis results of the control electrode of a Schottky gate transistor according to a comparative example by in-plane XRD measurement.

[0035] As described above, the control electrode 20 according to the first embodiment is formed by laminating Au 202 on Ni 201. The control electrode according to the comparative example is formed by laminating Au on Ni, similar to the control electrode 20 according to the first embodiment.

[0036] As shown in Fig. 4A, in the control electrode according to the comparative example, the analysis result of out-of-plane XRD measurement shows that the diffracted X-ray signal is broadened. Also, as shown in Fig. 4B, in the control electrode according to the comparative example, the analysis result of in-plane XRD measurement shows that the diffracted X-ray signal is broadened. In other words, the control electrode according to the comparative example has random crystal orientation and low crystallinity.

[0037] In contrast to the control electrode according to the comparative example, as shown in FIG. 3A, the control electrode 20 according to the first embodiment does not show broadening of the diffracted X-ray signal according to the analysis results of out-of-plane XRD measurement. In other words, the control electrode 20 does not show Debye rings in the reciprocal lattice map. Furthermore, as shown in FIG. 3B, the control electrode 20 according to the first embodiment does not show broadening of the diffracted X-ray signal according to the analysis results of in-plane XRD measurement. In other words, the control electrode 20 according to the first embodiment has a uniform crystal orientation and high crystallinity.

[0038] FIG. 5 shows an example of the measurement results of the peak half-widths obtained by asymmetric reflection measurement of the control electrode 20 in out-of-plane XRD measurement. The vertical axis represents the peak half-width [sec]. As shown in FIG. 5, in the control electrode according to the comparative example, the peak half-widths of Ni and Au are approximately 7000 seconds. Compared to the control electrode according to the comparative example, the peak half-widths of Ni 201 and Au 202 in the control electrode 20 according to the first embodiment are approximately 1000 seconds and approximately 2000 seconds, respectively. That is, the peak half-widths of Ni 201 and Au 202 in the control electrode 20 are 5000 seconds or less.

[0039] (9) Electrical Characteristics of Schottky Gate Transistor Tr FIG. 6 shows an example of the transfer characteristics of the Schottky gate transistor Tr according to the first embodiment and the Schottky gate transistor according to the comparative example. The horizontal axis represents voltage (gate voltage) [V]. The vertical axis represents current (drain current) [au]. Data A represents the transfer characteristics of the Schottky gate transistor Tr according to the first embodiment. Data B represents the transfer characteristics of the Schottky gate transistor according to the comparative example.

[0040] 6, in the Schottky gate transistor according to the comparative example, a current (drain current) flows when the voltage (gate voltage) increases and reaches the threshold voltage Vth. The current that flows before the threshold voltage Vth is reached corresponds to the off-leak current. In contrast, as shown in data A, in the Schottky gate transistor Tr according to the first embodiment, a current similarly flows when the voltage increases and reaches the threshold voltage Vth, but the off-leak current is significantly reduced.

[0041] 7A shows an example of an on-stress test result of the Schottky gate transistor Tr according to the first embodiment. FIG. 8A shows an example of an on-stress test result of the Schottky gate transistor according to the comparative example. In each of FIGS. 7A and 8A, the horizontal axis represents temperature [°C], and the vertical axis represents threshold voltage Vth [V].

[0042] Data a represents the variation of threshold voltage Vth with respect to temperature after applying stress such that the amount of current flowing per unit length becomes 10 μA / mm. Data b represents the variation of threshold voltage Vth with respect to temperature after applying stress such that the amount of current flowing per unit length becomes 500 μA / mm. Data c represents the variation of threshold voltage Vth with respect to temperature after applying stress such that the amount of current flowing per unit length becomes 50 mA / mm.

[0043] 8A, in the Schottky gate transistor according to the comparative example, the threshold voltage Vth fluctuates with temperature changes in the on-stress test results. In contrast, as shown in FIG. 7A, in the Schottky gate transistor Tr according to the first embodiment, the threshold voltage Vth fluctuates little with temperature changes in the on-stress test results.

[0044] 7B shows an example of an off-stress test result of the Schottky gate transistor Tr according to the first embodiment. FIG. 8B shows an example of an off-stress test result of the Schottky gate transistor according to the comparative example. In each of FIGS. 7B and 8B, the horizontal axis represents temperature [°C], and the vertical axis represents threshold voltage Vth [V].

[0045] 8B, in the Schottky gate transistor according to the comparative example, the threshold voltage Vth fluctuates with temperature changes in the off-stress test results. In contrast, as shown in FIG. 7B, in the Schottky gate transistor Tr according to the first embodiment, the fluctuation in threshold voltage Vth with temperature changes is small in the off-stress test results.

[0046] [Manufacturing Method of Semiconductor Device 1] Next, a description will be given of a manufacturing method of the semiconductor device 1. Figures 9 to 16 show an example of cross sections of steps that explain each step of the manufacturing method of the semiconductor device 1 including the Schottky gate transistor Tr.

[0047] First, a substrate 10 is prepared, and as shown in FIG. 9, a buffer layer 11 and a semiconductor 12 are sequentially formed on the substrate 10. The buffer layer 11 and the semiconductor 12 are formed by epitaxial growth. As described above, in the first embodiment, the semiconductor 12 is formed by sequentially stacking, for example, a channel layer 121, a spacer layer 122, a barrier layer 123, and a cap layer 124. The cap layer 124, which is the uppermost layer of the semiconductor 12, is formed of GaN. The surface of the GaN has a first crystal orientation, specifically, a crystal orientation in the <1-210> direction.

[0048] 10, a passivation film 3 is formed on the surface of the semiconductor 12. In this example, the passivation film 3 is made of, for example, SiN. The SiN is formed by, for example, chemical vapor deposition (CVD).

[0049] 11, a mask 4 is formed on the surface of the passivation film 3. In the mask 4, an opening 4H1 is formed in a region where the control electrode 20 is to be formed, and openings 4H2 are formed in regions where the pair of main electrodes 21 are to be formed. The mask 4 is made of a photoresist film formed by photolithography.

[0050] Here, the photoresist film is formed on the surface of the cap layer 124 with the passivation film 3 interposed therebetween, so that no disturbance occurs in the crystal orientation on the surface of the cap layer 124. Furthermore, when the photoresist film touches the surface of the cap layer 124, a cleaning process is performed on the surface of the cap layer 124.

[0051] The passivation film 3 is patterned using the mask 4, and openings 3H1 and 3H2 are formed in the passivation film 3 (see FIG. 12). The openings 3H1 and 3H2 are formed by, for example, dry etching. Subsequently, the mask 4 is removed as shown in FIG. 12.

[0052] 13, an electrode material 20A for forming the control electrode 20 is formed on the surface of the passivation film 3. In the first embodiment, the electrode material 20A is formed of a composite film in which Ni 201 and Au 202 are sequentially laminated. The Ni 201 and Au 202 are formed by, for example, a vapor deposition method.

[0053] Here, a portion of the electrode material 20A contacts the surface of the cap layer 124 through the opening 3H1 in the passivation film 3. The surface of the GaN cap layer 124 is exposed in the opening 3H1. In the first embodiment, the electrode material 20A contacting the surface of the GaN is Ni201. The second crystal orientation of the Ni201, specifically the crystal orientation in the <11-2> direction, is aligned with the first crystal orientation of the GaN in at least a portion of the direction perpendicular or horizontal to the surface of the GaN.

[0054] 14, a mask 5 is formed on the surface of the electrode material 20A. The mask 5 is formed in the region where the control electrode 20 is to be formed. The mask 5 is made of a photoresist film formed by photolithography.

[0055] The electrode material 20A is patterned using the mask 5, and the control electrode 20 is formed from the electrode material 20A (see FIG. 15). For the patterning, for example, a dry etching method or a wet etching method is used. Subsequently, as shown in FIG. 15, the mask 5 is removed.

[0056] As shown in FIG. 16, a pair of main electrodes 21 are formed through the openings 3H2 in the passivation film 3 to make ohmic contact with the surface of the semiconductor 12.

[0057] When this series of manufacturing steps is completed, the Schottky gate transistor Tr according to the first embodiment is completed, and further the semiconductor device 1 is completed.

[0058] 1 and 2A to 2D, the semiconductor device 1 according to the first embodiment includes a Schottky gate transistor Tr. The Schottky gate transistor Tr includes a semiconductor 12 and a control electrode 20. The semiconductor 12 has a first crystal orientation on its surface. The control electrode 20 is in contact with the surface of the semiconductor 12 and is formed of a metal with a face-centered cubic lattice structure having a second crystal orientation. In addition, the control electrode 20 has the second crystal orientation aligned with the first crystal orientation in at least a portion of a direction perpendicular to or parallel to the surface of the semiconductor 12.

[0059] A detailed description will be given. In the first embodiment, as shown in FIG. 1, the Schottky gate transistor Tr is a Schottky gate HEMT. The semiconductor 12 is a barrier layer 123 or a composite layer in which a cap layer 124 is stacked on the barrier layer 123. The barrier layer 123 is formed to contain one or more elements selected from Al, Ga, In, and N. The cap layer 124 is formed to contain one or more elements selected from Al, Ga, In, N, and Si. The control electrode 20 is formed to contain one or more elements selected from Ni, Cu, Al, Au, Pt, and Pd.

[0060] For example, when the cap layer 124 is made of GaN, the (0001) crystal plane of GaN has a <1-210> direction as a first crystal orientation, as shown in Fig. 2B. When the metal in contact with the surface of the cap layer 124 of the control electrode 20 is, for example, Au 202, the surface of Au 202 in contact with the surface of the cap layer 124 has a <11-2> direction as a second crystal orientation, as shown in Figs. 2C and 2D.

[0061] 6, the Schottky gate transistor Tr configured in this manner can reduce the off-leak current compared to the Schottky gate transistor according to the comparative example. Therefore, the semiconductor device 1 equipped with the Schottky gate transistor Tr can reduce the leak current.

[0062] 2. Second Embodiment A semiconductor module 100 according to a second embodiment of the present disclosure will be described with reference to Fig. 17. Fig. 17 shows an example of a schematic structure of the semiconductor module 100 according to the second embodiment.

[0063] [Configuration of Semiconductor Module 100] The semiconductor module 100 according to the second embodiment is an antenna-integrated module in which, for example, edge antennas 101 arranged in an array and front-end components are mounted as a single module on a substrate 110. The front-end components include a switch 102, a low-noise amplifier 103, a band-pass filter 104, and a power amplifier 105. The semiconductor module 100 can be used, for example, as a transceiver for communications.

[0064] The semiconductor module 100 includes the semiconductor device 1 according to the first embodiment as transistors that constitute, for example, a switch 102, a low-noise amplifier 103, or a power amplifier 105.

[0065] [Operation and Effect] The semiconductor module 100 according to the second embodiment includes the semiconductor device 1, and therefore can achieve low power consumption in wireless communication.

[0066] 3. Third Embodiment A wireless communication device 300 according to a third embodiment of the present disclosure will be described with reference to Fig. 18. Fig. 18 shows an example of a schematic block configuration of the wireless communication device 300 according to the third embodiment.

[0067] [Configuration of Wireless Communication Device 300] The wireless communication device 300 according to the third embodiment includes an antenna ANT, an antenna switch circuit 301, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F. The interface unit I / F includes, for example, a wireless local area network (W-LAN) and Bluetooth (registered trademark). The wireless communication device 300 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection.

[0068] The wireless communication device 300 includes the semiconductor device 1 according to the first embodiment as transistors constituting an antenna switch circuit 301, a high power amplifier HPA, a radio frequency integrated circuit RFIC, or a baseband unit BB.

[0069] [Effects] The wireless communication device 300 according to the third embodiment can achieve low power consumption in wireless communication because it includes the semiconductor device 1. Therefore, when the wireless communication device 300 is a mobile communication terminal, the usage time of the wireless communication device 300 can be further extended, thereby further improving portability.

[0070] 4. Other Embodiments The present technology is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit and scope of the present technology.

[0071] As described above, the semiconductor device according to the first embodiment of the present disclosure includes a Schottky gate transistor. The Schottky gate transistor includes a semiconductor and a control electrode. The semiconductor has a first crystal orientation on its surface. The control electrode is in contact with the surface of the semiconductor and is formed of a metal with a face-centered cubic lattice structure having a second crystal orientation. In addition, the control electrode has the second crystal orientation aligned with the first crystal orientation in at least a portion of a direction perpendicular or horizontal to the surface of the semiconductor. A semiconductor device configured in this manner can reduce the off-leakage current of the Schottky gate transistor Tr. Therefore, a semiconductor device equipped with a Schottky gate transistor Tr can reduce leakage current.

[0072] In a semiconductor device according to a second embodiment of the present disclosure, the semiconductor in the semiconductor device according to the first embodiment is a barrier layer or a composite layer in which a cap layer is laminated on a barrier layer. The barrier layer or the cap layer is GaN having a first crystal orientation in the <1-210> direction. The control electrode has a second crystal orientation in the <11-2> direction. A semiconductor device configured in this manner can reduce leakage current, similar to the semiconductor device according to the first embodiment.

[0073] A semiconductor module according to a third embodiment of the present disclosure includes the semiconductor device according to the first embodiment. With the semiconductor module configured in this manner, it is possible to reduce leakage current in the semiconductor device, thereby achieving low power consumption.

[0074] An electronic device according to a fourth embodiment of the present disclosure includes the semiconductor device according to the first embodiment. With such a configuration, it is possible to reduce leakage current in the semiconductor device, thereby realizing low power consumption.

[0075] <Configuration of the Present Technology> The present technology has the following configuration. According to the present technology having the following configuration, it is possible to reduce leakage current in a semiconductor device. It is possible to achieve low power consumption in a semiconductor module and an electronic device.

[0076] (1) A semiconductor device comprising a Schottky gate transistor, the Schottky gate transistor comprising: a semiconductor having a first crystal orientation on a surface; and a control electrode in contact with the surface, the control electrode being formed of a metal with a face-centered cubic lattice structure having a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction perpendicular to or parallel to the surface. (2) The semiconductor device according to (1), in which the control electrode has no Debye rings in a reciprocal lattice map in out-of-plane X-ray diffraction measurement. (3) The semiconductor device according to (1) or (2), in which the control electrode has six-fold symmetry in asymmetric reflection measurement in out-of-plane X-ray diffraction measurement. (4) The semiconductor device according to any one of (1) to (3), in which the control electrode has a peak half-width of 5000 seconds or less in asymmetric reflection measurement in out-of-plane X-ray diffraction measurement. (5) The semiconductor device according to (1), wherein the semiconductor is a barrier layer or a composite layer formed by stacking a cap layer on a barrier layer. (6) The semiconductor device according to (5), wherein the barrier layer is formed containing one or more selected from Al, Ga, In, and N. (7) The semiconductor device according to (5) or (6), wherein the cap layer is formed containing one or more selected from Al, Ga, In, N, and Si. (8) The semiconductor device according to any one of (1) to (7), wherein the control electrode is formed containing one or more selected from Ni, Cu, Al, Au, Pt, and Pd. (9) The semiconductor device according to any one of (1) to (8), wherein the Schottky gate transistor is a Schottky gate high electron mobility transistor. (10) The semiconductor device according to (5), wherein the barrier layer or the cap layer is GaN having a <1-210> direction as the first crystal orientation, and the control electrode is the metal having a <11-2> direction as the second crystal orientation.(11) A semiconductor module comprising: a semiconductor device, the semiconductor device comprising a Schottky gate transistor, the Schottky gate transistor comprising: a semiconductor having a first crystal orientation on a surface; and a control electrode in contact with the surface, the control electrode being formed of a metal with a face-centered cubic lattice structure having a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction vertical or horizontal to the surface. (12) An electronic device comprising: a semiconductor device, the semiconductor device comprising a Schottky gate transistor, the Schottky gate transistor comprising: a semiconductor having a first crystal orientation on a surface; and a control electrode in contact with the surface, the control electrode being formed of a metal with a face-centered cubic lattice structure having a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction vertical or horizontal to the surface.

[0077] This application claims priority based on Japanese Patent Application No. 2023-197945, filed on November 22, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0078] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a Schottky gate transistor, the Schottky gate transistor comprising: a semiconductor having a first crystal orientation on a surface thereof; and a control electrode in contact with the surface, the control electrode being formed from a metal with a face-centered cubic lattice structure having a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction perpendicular or horizontal to the surface.

2. The semiconductor device according to claim 1, wherein the control electrode has no Debye rings in a reciprocal lattice map in out-of-plane X-ray diffraction measurement.

3. The semiconductor device according to claim 1, wherein in out-of-plane X-ray diffraction measurement, in asymmetric reflection measurement, the control electrode has six-fold symmetry.

4. The semiconductor device according to claim 1, wherein in out-of-plane X-ray diffraction measurement, the control electrode has a half-width at peak of 5000 seconds or less in asymmetric reflection measurement.

5. The semiconductor device according to claim 1, wherein the semiconductor is a barrier layer or a composite layer in which a cap layer is laminated on a barrier layer.

6. The semiconductor device according to claim 5, wherein the barrier layer is formed containing one or more elements selected from the group consisting of Al, Ga, In and N.

7. The semiconductor device according to claim 5, wherein the cap layer is formed containing one or more elements selected from the group consisting of Al, Ga, In, N and Si.

8. The semiconductor device according to claim 1, wherein the control electrode is formed containing one or more selected from the group consisting of Ni, Cu, Al, Au, Pt and Pd.

9. The semiconductor device according to claim 1, wherein the Schottky gate transistor is a Schottky gate high electron mobility transistor.

10. The semiconductor device according to claim 5, wherein the barrier layer or the cap layer is GaN having a <1-210> direction as the first crystal orientation, and the control electrode is the metal having a <11-2> direction as the second crystal orientation.

11. A semiconductor module comprising a semiconductor device, the semiconductor device comprising a Schottky gate type transistor, the Schottky gate type transistor comprising: a semiconductor having a first crystal orientation on a surface thereof; and a control electrode in contact with the surface, the control electrode being formed from a metal having a face-centered cubic lattice structure and having a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction vertical or horizontal to the surface.

12. An electronic device comprising a semiconductor device, the semiconductor device comprising a Schottky gate type transistor, the Schottky gate type transistor comprising: a semiconductor having a first crystal orientation on a surface; and a control electrode in contact with the surface, the control electrode being formed from a metal with a face-centered cubic lattice structure having a second crystal orientation, the second crystal orientation being aligned with the first crystal orientation in at least a portion of a direction vertical or horizontal to the surface.

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