Semiconductor device and power conversion device

Abstract

A semiconductor device (202) comprises: a lead frame (2) that includes a die pad (2a), a power lead (2c), and a control lead (2b); a semiconductor element (3p) that is mounted on a surface (2s) of the die pad (2a); a control semiconductor element (3i) that is mounted on one surface on one end side of the control lead (2b) and that controls the semiconductor element (3p); an insulating layer (9) that is disposed so as to span from a surface (2r) of the die pad (2a) to a lateral surface; and a sealing material (11) that seals the semiconductor element (3p), the control semiconductor element (3i), and the lead frame (2) in a state in which a portion of the insulating layer (9) that is disposed on the surface (2r) of the die pad (2a) is exposed. The thickness of an insulating layer (9e), which is a portion of the insulating layer (9) that is disposed at an edge portion of the surface (2r) of the die pad (2a), is greater than the thickness of the other portions, and the insulating layer (9e) protrudes from the surface of the sealing material (11).

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

[0002] Molded semiconductor devices, in which a semiconductor element and a wiring circuit are integrally sealed with resin using a mold, have been known for some time. Molded semiconductor devices are more manufacturable and can be made smaller than cased semiconductor devices, in which a low-elasticity resin is filled in a case to protect the semiconductor element.

[0003] Semiconductor elements generate heat due to losses during switching and conduction. This heat significantly increases the temperature of the semiconductor element, and if it is not properly dissipated, the lifespan of the semiconductor element will be shortened and even the semiconductor element may be destroyed. For this reason, semiconductor devices are equipped with heat dissipation fins, for example, by screwing or soldering. The heat generated by the semiconductor element is transferred to the heat dissipation fins via the bonding material, die pad, mold resin, and grease or insulating sheet, and is then dissipated into the atmosphere.

[0004] In this heat dissipation path, the mold resin has a lower thermal conductivity than other materials, and therefore is likely to affect the thermal resistance from the semiconductor element to the heat dissipation fins. For example, Patent Document 1 discloses a semiconductor device that can enhance heat dissipation while suppressing deformation of the substrate by exposing the backside of the die pad from the mold resin.

[0005] JP 2010-50323 A

[0006] However, the technology described in Patent Document 1 had a problem in that stress caused by heat generated by electronic components placed on the die pad caused peeling of the molding resin at the portion where the back surface of the die pad was exposed from the molding resin, thereby reducing the reliability of the semiconductor device.

[0007] Therefore, an object of the present disclosure is to provide a technique that can improve the reliability of a semiconductor device while enhancing heat dissipation.

[0008] The semiconductor device according to the present disclosure comprises a lead frame including a die pad, a first lead having one end connected to the die pad, and a second lead arranged on the opposite side of the die pad from the first lead, a semiconductor element mounted on one side of the die pad, a control semiconductor element mounted on one side of one end of the second lead and controlling the semiconductor element, an insulating layer arranged from the other side of the die pad opposite the one side to a side connecting the one side and the other side, and a sealing material that seals the semiconductor element, the control semiconductor element, and the lead frame while exposing the portion of the insulating layer arranged on the other side of the die pad, wherein the thickness of the portion of the insulating layer arranged on the edge portion of the other side of the die pad is thicker than the thickness of the remaining portion, and the portion of the insulating layer arranged on the edge portion protrudes from the surface of the sealing material.

[0009] According to the present disclosure, when connecting the semiconductor device and the heat dissipation fins, grease is placed on the other side of the die pad, but the thick portion of the insulating layer placed on the edge portion of the other side of the die pad surrounds the other side of the die pad, thereby preventing the grease from spreading outside the edge portion of the other side of the die pad. As a result, it is possible to ensure the necessary thickness of grease on the other side of the die pad, which is directly below the die pad on which the semiconductor element that serves as a heat source is mounted, thereby improving the heat dissipation performance of the semiconductor device.

[0010] Furthermore, the portion of the insulating layer disposed on the edge of the other side of the die pad adheres more firmly to the encapsulant than the metal material of the die pad, thereby preventing peeling of the encapsulant, thereby improving the reliability of the semiconductor device.

[0011] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0012] 1 is a top view of a semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1; FIG. 3 is a cross-sectional view showing a state in which the semiconductor device according to the first embodiment and a heat dissipation fin are connected; FIG. 4 is a side view showing a state in which the semiconductor device according to the first embodiment and a heat dissipation fin are connected and arranged vertically; FIG. 5 is a bottom view showing an example of a bottom structure of a sealing material included in the semiconductor device according to the first embodiment; FIG. 6 is a bottom view showing another example of a bottom structure of a sealing material included in the semiconductor device according to the first embodiment; FIG. 7 is a bottom view showing yet another example of a bottom structure of a sealing material included in the semiconductor device according to the first embodiment; FIG. 8 is a cross-sectional view showing an example of a peripheral structure of a die pad and a heat sink included in a semiconductor device according to a second embodiment; FIG. 9 is a cross-sectional view showing another example of a peripheral structure of a die pad and a heat sink included in a semiconductor device according to the second embodiment; FIG. 10 is a cross-sectional view showing a state in which the semiconductor device according to the second embodiment and a heat dissipation fin are connected; FIG. 11 is a cross-sectional view showing an example of a die pad and a peripheral structure included in a semiconductor device according to a third embodiment; FIG. 12 is a cross-sectional view showing another example of a die pad and a peripheral structure included in a semiconductor device according to the third embodiment;

[0013] First Preferred Embodiment Structure of Semiconductor Device A first preferred embodiment will be described below with reference to the drawings. Fig. 1 is a top view of a semiconductor device 202 according to the first preferred embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1.

[0014] In FIG. 1, the X direction, Y direction, and Z direction are perpendicular to one another. The X direction, Y direction, and Z direction shown in the following figures are also perpendicular to one another. Hereinafter, the direction including the X direction and the −X direction, which is the opposite direction of the X direction, will also be referred to as the “X-axis direction.” Hereinafter, the direction including the Y direction and the −Y direction, which is the opposite direction of the Y direction, will also be referred to as the “Y-axis direction.” Hereinafter, the direction including the Z direction and the −Z direction, which is the opposite direction of the Z direction, will also be referred to as the “Z-axis direction.”

[0015] First, a description will be given of the structure of a semiconductor device 202 according to embodiment 1. As shown in Figures 1 and 2, the semiconductor device 202 includes a lead frame 2, a semiconductor element 3p, a control semiconductor element 3i, an insulating layer 9, and a sealing material 11.

[0016] As shown in FIG. 2, the lead frame 2 includes a die pad 2a, a power lead 2c (first lead), a control lead 2b (second lead), and a suspension lead 2n.

[0017] The die pad 2a is formed in a plate shape. When viewed from the Z direction, the die pad 2a is formed in a rectangular shape. The die pad 2a has one surface 2s and the other surface 2r. The surface 2r is the surface of the die pad 2a opposite to the surface 2s. The surfaces 2s and 2r are flat surfaces. The die pad 2a is connected to one end of a power lead 2c via a suspension lead 2n.

[0018] The control lead 2b is arranged on the opposite side of the die pad 2a to the power lead 2c. Specifically, the power lead 2c is arranged in the X direction with respect to the die pad 2a, and the control lead 2b is arranged in the −X direction with respect to the die pad 2a.

[0019] The semiconductor element 3p is, for example, a power semiconductor element that operates at a high voltage. Note that the semiconductor element 3p is not limited to a power semiconductor element, and may be, for example, a semiconductor element that operates at a low voltage.

[0020] A semiconductor element 3p is mounted on a surface 2s of the die pad 2a. Specifically, the semiconductor element 3p is bonded to the surface 2s of the die pad 2a by a bonding material 4. The bonding material 4 is, for example, solder. Furthermore, a control semiconductor element 3i is bonded to the surface in the Z direction at one end of the control lead 2b by a bonding material 8. The bonding material 8 is, for example, solder.

[0021] Two wires 7s are connected to the control semiconductor element 3i. The wires 7s are signal transmission wires.

[0022] The semiconductor element 3p and the control semiconductor element 3i are electrically connected by wires 7s. The control semiconductor element 3i and the control lead 2b are also electrically connected by wires 7s. The semiconductor element 3p is also electrically connected to the power lead 2c by wires 7p.

[0023] An insulating layer 9 having a very thin thickness is provided on the surface 2r of the die pad 2a. The insulating layer 9 is formed by coating the surface 2r of the die pad 2a with an insulating resin very thinly, at a thickness of about 1 μm. In other words, the insulating layer 9 is disposed on the surface 2r of the die pad 2a. The insulating layer 9e is formed by thickly coating only the edge portion of the surface 2r of the die pad 2a with the insulating resin. In other words, the insulating layer 9e is a portion of the insulating layer 9 formed on the edge portion of the surface 2r of the die pad 2a. The thickness of the insulating layer 9e is thicker than the thickness of the other portions of the insulating layer 9. The insulating layer 9e may also be formed on the side surface of the die pad 2a. That is, as shown in FIG. 2 , the insulating layer 9 may be formed from the surface 2r of the die pad 2a to the side surface, and the insulating layer 9e may be formed from the edge portion of the surface 2r of the die pad 2a to the side surface. The side surfaces of the die pad 2a are surfaces that connect the surface 2s and the surface 2r of the die pad 2a, in other words, the surfaces in the X-axis direction and the Y-axis direction of the die pad 2a.

[0024] The sealing material 11 is, for example, a mold resin, and seals the semiconductor element 3p, the control semiconductor element 3i, the wires 7p and 7s, the die pad 2a, the suspension lead 2n, the power lead 2c, the control lead 2b, and the insulating layer 9 in a state where the tip end (other end) of the control lead 2b and the tip end (other end) of the power lead 2c and the portion of the insulating layer 9 formed on the surface 2r of the die pad 2a are exposed.

[0025] The sealing material 11 is formed in a rectangular shape when viewed from the surface 2r side of the die pad 2a. The sealing material 11 has a surface 11s and a surface 11r. The surface 11s is the surface of the sealing material 11 facing the Z direction. The surface 11r is the surface of the sealing material 11 opposite to the surface 11s and facing the -Z direction.

[0026] The control lead 2b protrudes in the -X direction from the -X side of the sealing material 11. The control lead 2b is bent so that the tip of the control lead 2b that is outside the sealing material 11 is parallel to the Z direction. The control lead 2b may be further bent so that it is parallel to the X direction.

[0027] The power lead 2c protrudes in the X direction from the side of the sealing material 11 in the X direction. The control lead 2b is bent so that the tip of the control lead 2b that is outside the sealing material 11 is parallel to the Z direction. Furthermore, the control lead 2b may be bent again so that it is parallel to the X direction.

[0028] Next, the configuration of each part will be specifically described. For example, copper (Cu) or aluminum (Al) is used as the material of the lead frame 2. Alternatively, an alloy composed of copper (Cu) and aluminum (Al) may be used as the material of the lead frame 2.

[0029] The surface of the lead frame 2 may be plated with nickel (Ni), silver (Ag), or gold (Au) to prevent oxidation. That is, a nickel plating film, a silver plating film, or a gold plating film may be formed on the surface of the lead frame 2. The plating film may be formed only on a part of the lead frame 2.

[0030] Hereinafter, the area to be plated is also referred to as the "plating area." The plating area is an area that is susceptible to surface oxidation. The plating area is, for example, the periphery of an area on the surface 2s of the die pad 2a where the semiconductor element 3p is bonded by the bonding material 4. The plating area is, for example, the periphery of an area on the Z-direction surface of the control lead 2b where the control semiconductor element 3i is bonded by the bonding material 8.

[0031] The plating target area is, for example, the periphery of the area of ​​the Z-direction surface of the control lead 2b where the wire 7s is connected, and the plating target area is, for example, the periphery of the area of ​​the Z-direction surface of the power lead 2c where the wire 7p is connected.

[0032] The semiconductor element 3p is an element that functions as, for example, a switching element or a rectifying element. The switching element is, for example, an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The rectifying element is a diode element.

[0033] The material constituting the semiconductor element 3p is, for example, silicon (Si). Note that the material constituting the semiconductor element 3p is not limited to silicon, and may be, for example, a wide bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C). A wide bandgap semiconductor material is a material having a bandgap wider than that of silicon. A semiconductor element 3p made of a wide bandgap semiconductor material can operate using a large current and in a high-temperature environment. Therefore, it is preferable that the material constituting the semiconductor element 3p be a wide bandgap semiconductor material.

[0034] Furthermore, an electronic component such as a resistor or capacitor may be mounted on the Z-direction surface of the control lead 2b instead of the control semiconductor element 3i. A semiconductor device 202 including such an electronic component is known as an IPM (Intelligent Power Module).

[0035] The material forming the wires 7p and 7s may be aluminum (Al), copper (Cu), gold (Au), silver (Ag), or the like. The material forming the wires 7p and 7s may also be an alloy. The alloy is composed of two or more metals selected from aluminum (Al), copper (Cu), gold (Au), and silver (Ag). The material forming the wires 7p and 7s may also be an alloy to which a metal element such as nickel (Ni) or iron (Fe) is added.

[0036] The wires 7p and 7s may have a thin wire shape or a cylindrical shape, for example. The cross section of the wires 7p and 7s may have a circular shape, for example. The diameter of the circle may be, for example, 10 μm or more and 500 μm or less.

[0037] The wires 7p and 7s are bonded in a wire bonding process by an existing method such as ball bonding or wedge bonding. If the material constituting the wire 7p is the same as the material constituting the wire 7s, the wires 7p and 7s can be bonded in the same wire bonding process.

[0038] Of the wires 7p and 7s, the wire 7p is the main wiring. Therefore, the wire 7p is thicker than the wire 7s. The wire 7p may have the same thickness as the wire 7i. Alternatively, the wire 7p may have a thinner thickness than the wire 7s.

[0039] For example, when the semiconductor device 202 is a discrete semiconductor device, the wire 7 p has the same thickness as the wire 7 s. When a semiconductor element having a complex configuration, such as an integrated circuit (IC) or a large scale integration (LSI), is mounted in the semiconductor device 202, the wire 7 p may have the same thickness as the wire 7 s.

[0040] The encapsulant 11 may also be a composite material. The composite material is a material containing, for example, a filler or other filler material and a resin as main components. The filler material is used to adjust the thermal expansion coefficient or mechanical properties of the encapsulant 11. The resin contained in the composite material is, for example, a thermosetting resin with high electrical resistivity, such as an epoxy resin. It is preferable that the encapsulant 11 have high insulation properties, good moldability, and reliability.

[0041] The encapsulant 11 is formed by, for example, transfer molding. The encapsulant 11 encapsulates a portion of the lead frame 2 so that the tip (other end) of the power lead 2c and the tip (other end) of the control lead 2b are exposed from the encapsulant 11. As described above, the encapsulant 11 also encapsulates the semiconductor element 3p, the control semiconductor element 3i, the wires 7p, 7s, the die pad 2a, the suspension lead 2n, the power lead 2c, the control lead 2b, and the insulating layer 9. In the semiconductor device 202, the tip (other end) of the power lead 2c and the tip (other end) of the control lead 2b exposed from the encapsulant 11 are electrically connected to a circuit board, other devices, etc. (not shown).

[0042] The material constituting the insulating layer 9 is a highly insulating material, such as an epoxy resin, a fluorine-based resin, or a silicone-based resin. The thickness of the insulating layer 9 is approximately 1 μm or more, and is set taking into account the insulating properties required for the semiconductor device 202. However, if the insulating layer 9 is thicker than a certain thickness, the heat dissipation performance may be equivalent to or less than that of a so-called ceramic substrate, in which ceramic is sandwiched between copper (Cu) plates. Therefore, the insulating layer 9 is preferably approximately 30 μm or less in thickness. Generally, ceramic substrates are made of materials such as alumina, aluminum nitride, or silicon nitride, and the thickness of ceramic substrates is 250 μm or more. Therefore, if the thickness of the insulating layer 9 is less than this, heat dissipation performance better than that of a ceramic substrate can be expected while maintaining insulation properties.

[0043] <Connection between semiconductor device and heat dissipation fins> Next, a description will be given of the connection between the semiconductor device 202 and the heat dissipation fins 22. Fig. 3 is a cross-sectional view showing the semiconductor device 202 according to the first embodiment connected to the heat dissipation fins 22. Fig. 4 is a side view showing the semiconductor device 202 according to the first embodiment connected to the heat dissipation fins 22 and arranged vertically.

[0044] As shown in FIG. 3 , the sealing material 11 of the semiconductor device 202 is connected to the heat dissipation fins 22 via grease 23. In this case, the insulating layer 9e disposed at the edge portion of the surface 2r of the die pad 2a protrudes in the −Z direction relative to the portion of the insulating layer 9 surrounded by the insulating layer 9e. In other words, on the surface 2r of the die pad 2a, the portion of the insulating layer 9 surrounded by the insulating layer 9e is recessed in the Z direction relative to the insulating layer 9e. Because the grease 23 can be held in the recessed portion formed on the surface 2r side of the die pad 2a, the thickness of the grease 23 located directly below the die pad 2a can be kept thin and constant. In this case, the insulating layer 9e disposed at the edge portion protrudes from the surface of the sealing material 11. The grease 23 may be present between the protruding insulating layer 9e and the heat dissipation fins 22, or the insulating layer 9e and the heat dissipation fins 22 may be in direct contact with each other.

[0045] Generally, when connecting the semiconductor device 202 and the heat dissipation fins 22 via grease 23, the grease 23 is applied thicker than necessary to absorb variations in warpage of the semiconductor device 202 or the heat dissipation fins 22. Alternatively, a thicker thermally conductive sheet may be used instead of the grease 23. In either case, the presence of an excessively thick grease 23 or thermally conductive sheet directly below the die pad 2a contributes to the deterioration of thermal resistance. On the other hand, if there is insufficient grease 23, it will be unable to follow the warpage of the semiconductor device 202 or the heat dissipation fins 22, resulting in a gap between the semiconductor device 202 and the heat dissipation fins 22, which will also contribute to the deterioration of thermal resistance as in the above case.

[0046] The semiconductor device 202 may be used in a machine or device that generates vibration. Furthermore, as shown in FIG. 4 , the semiconductor device 202 and the heat dissipation fins 22 may be installed vertically. In such a case, if the grease 23 spreads to the outside due to vibration, a gap may form between the sealing material 11 and the heat dissipation fins 22. This gap may prevent the heat generated from the semiconductor element 3p from being efficiently transferred to the heat dissipation fins 22, potentially reducing the heat dissipation performance of the semiconductor device 202.

[0047] To address these problems, in the first embodiment, the insulating layer 9e surrounds the surface 2r of the die pad 2a, thereby preventing the grease 23 from leaking and spreading outside the edge of the surface 2r of the die pad 2a. This allows the grease 23 to be held directly below the die pad 2a on which the semiconductor element 3p, which is a heat source, is mounted, making it possible to maintain constant heat dissipation in the semiconductor device 202. Here, "directly below the die pad 2a" refers to the -Z direction of the die pad 2a in FIG. 3 and the X direction of the die pad (not shown) in FIG. 4.

[0048] In the first embodiment, the semiconductor element 3p is connected to the heat dissipation fins 22 via the shortest possible distance without the presence of the thick sealing material 11 with low thermal conductivity in the heat dissipation path from the semiconductor element 3p, and therefore high heat dissipation is achieved in the semiconductor device 202. Normally, if the die pad 2a is exposed from the sealing material 11, when the semiconductor element 3p is energized, the sealing material 11 that played the role of insulating between the semiconductor element 3p and the heat dissipation fins 22 is no longer present, which can cause a short circuit.

[0049] In the first embodiment, insulating resin is coated very thinly on the surface 2r of the die pad 2a to a thickness of about 1 μm to form an insulating layer 9, which can achieve both insulating properties and high heat dissipation properties.

[0050] Furthermore, a screw fastening method is used to connect the sealing material 11 and the heat dissipation fins 22. Although not shown, the sealing material 11 and the heat dissipation fins 22 are fastened to each other by inserting screws (not shown) through screw holes 12 (see FIG. 1 ) that extend in the vertical direction and are provided on the side of the sealing material 11.

[0051] Next, the shape and width of the insulating layer 9e will be described with reference to Fig. 2 and Figs. 5 to 7. Fig. 5 is a bottom view showing an example of the bottom structure of the sealing material 11 included in the semiconductor device 202 according to the first embodiment. Fig. 6 is a bottom view showing another example of the bottom structure of the sealing material 11 included in the semiconductor device 202 according to the first embodiment. Fig. 7 is a bottom view showing yet another example of the bottom structure of the sealing material 11 included in the semiconductor device 202 according to the first embodiment.

[0052] 2 and 5, the lead frame 2 includes a plurality of die pads 2a, which are arranged at intervals along the longitudinal direction (Y-axis direction) of the encapsulant 11. By coating the edge portion of the surface 2r of the die pad 2a multiple times, an insulating layer 9e having a thickness greater than that of the insulating layer 9 is formed so as to surround the surface 2r of the die pad 2a. The width of the insulating layer 9e is uniform.

[0053] The thickness of the grease 23 applied when attaching the heat dissipation fin 22 can be adjusted depending on the difference in thickness between the insulating layer 9e and other parts of the insulating layer 9, so the thickness of the insulating layer 9e can be determined depending on the warping and surface unevenness of the semiconductor device 202 or the heat dissipation fin 22.

[0054] Furthermore, since the adhesion between resin and metal is generally weaker than that between other resins, the edge of the surface 2r of the die pad 2a, where the greatest stress occurs when the semiconductor device 202 is in operation, i.e., when the semiconductor element 3p is generating heat, often becomes the starting point for peeling between the sealing material 11 and the die pad 2a.

[0055] In the first embodiment, the insulating layer 9 including the insulating layer 9e is formed from the surface 2r of the die pad 2a to the side surface, so that the sealing material 11 and the insulating layer 9e are closely attached even at the edge portion of the surface 2r of the die pad 2a where the most stress is generated. The insulating layer 9e adheres more firmly to the sealing material 11 than the metal material of the die pad 2a, and therefore peeling of the sealing material 11 can be suppressed. As a result, high reliability can be ensured in the semiconductor device 202.

[0056] Next, as shown in Figures 6 and 7, in order to further improve the reliability of the semiconductor device 202, the width of the insulating layer 9e formed on a specified side at the edge portion of the surface 2r of the die pad 2a may be made wider than the width of the insulating layer 9e formed on the other sides.

[0057] Smile warpage or cry warpage occurs in the semiconductor device 202 mainly due to the difference in thermal expansion coefficient between the encapsulant 11 and the lead frame 2, as well as the difference in thermal expansion coefficient between other components. When the semiconductor device 202 and the heat dissipation fins 22 are screwed together, the above-mentioned warpage is corrected, and the greatest stress is applied to the side of the die pad 2a closest to the screw holes 12. Therefore, as shown in FIG. 6 , the width of the insulating layer 9e is increased by applying multiple coatings to the side of the die pad 2a closest to the screw holes 12, which are subjected to the greatest stress during screw fastening. More specifically, the width of the portion of the insulating layer 9e adjacent to the short side (the side extending in the X-axis direction) of the rectangular shape of the encapsulant 11 is wider than the width of the remaining portion of the insulating layer 9e. This makes it possible to counteract the stress during screw fastening.

[0058] Furthermore, as described above, when the semiconductor device 202 is operating, i.e., when the semiconductor element 3p is generating heat, the edge portion of the surface 2r of the die pad 2a, where the most stress is generated, often becomes the starting point for peeling between the sealing material 11 and the die pad 2a. As shown in Figure 2, stress is particularly likely to concentrate most at the bent portion, which is the connection portion between the die pad 2a and the suspension lead 2n, and peeling is likely to occur from there.

[0059] 7, the width of the insulating layer 9e is increased by applying multiple coatings to the side surfaces of the die pad 2a, which are subjected to the most stress when heat is generated. More specifically, the width of the portion of the insulating layer 9e adjacent to the long side (the side extending in the Y-axis direction) of the rectangular shape of the sealing material 11 is made wider than the width of the other portions of the insulating layer 9e. This makes it possible to deal with stress when heat is generated.

[0060] Next, a specific description will be given of the configuration of the heat dissipation fins 22. The material constituting the heat dissipation fins 22 is, for example, an alloy. The alloy is, for example, aluminum (Al) to which at least one of magnesium (Mg) and manganese (Mn) is added.

[0061] The material of the heat dissipation fins 22 is not limited to an alloy, but may be a metal other than an alloy. The material of the heat dissipation fins 22 may be, for example, copper (Cu). The heat dissipation fins 22 may also be a plate made of aluminum (Al).

[0062] Furthermore, the material forming the heat dissipation fins 22 may be a material other than metal, such as an inorganic or organic material with high thermal conductivity.

[0063] <Effects> As described above, the semiconductor device 202 according to the first embodiment includes the lead frame 2 including the die pad 2 a, the power lead 2 c having one end connected to the die pad 2 a, and the control lead 2 b arranged on the opposite side of the die pad 2 a from the power lead 2 c, the semiconductor element 3 p mounted on the surface 2 s of the die pad 2 a, the control semiconductor element 3 i mounted on one surface of one end of the control lead 2 b and controlling the semiconductor element 3 p, the insulating layer 9 arranged from the surface 2 r of the die pad 2 a opposite to the surface 2 s to the side surface connecting the surfaces 2 r and 2 s, and the sealing material 11 that seals the semiconductor element 3 p, the control semiconductor element 3 i, and the lead frame 2 while exposing the portion of the insulating layer 9 arranged on the surface 2 r of the die pad 2 a. The thickness of the insulating layer 9 e, which is a portion of the insulating layer 9 arranged on the edge portion of the surface 2 r of the die pad 2 a, is thicker than the thickness of the remaining portion, and the insulating layer 9 e protrudes from the surface of the sealing material 11.

[0064] In addition, the lead frame 2 includes a plurality of die pads 2a, and the sealing material 11 is formed in a rectangular shape when viewed from the surface 2r side of the plurality of die pads 2a, and the plurality of die pads 2a are arranged at intervals from each other along the longitudinal direction (Y-axis direction) of the sealing material 11, and the width of the insulating layer 9e is uniform.

[0065] Therefore, when connecting the semiconductor device 202 and the heat dissipation fins 22, the grease 23 is placed on the surface 2r of the die pad 2a, but the thick insulating layer 9e placed on the edge portion of the surface 2r of the die pad 2a surrounds the surface 2r of the die pad 2a, thereby preventing the grease 23 from spreading outside the edge portion of the surface 2r of the die pad 2a. As a result, it is possible to ensure a necessary thickness of grease 23 on the surface 2r side of the die pad 2a directly below the die pad 2a on which the semiconductor element 3p, which serves as a heat source, is mounted, thereby improving the heat dissipation performance of the semiconductor device 202.

[0066] Furthermore, the insulating layer 9e disposed on the edge portion of the surface 2r of the die pad 2a adheres more firmly to the sealing material 11 than the metal material of the die pad 2a, thereby preventing peeling of the sealing material 11. As a result, the reliability of the semiconductor device 202 can be improved.

[0067] Furthermore, since the thickness of the insulating layer 9 is 1 μm or more and 30 μm or less, it does not significantly hinder heat dissipation in the semiconductor device 202 .

[0068] Furthermore, the width of the portion of the insulating layer 9e adjacent to the short side (the side extending in the X-axis direction) of the rectangular shape of the sealing material 11 is formed wider than the width of the other portion of the insulating layer 9e, thereby making it possible to take measures against stress when the screws are fastened.

[0069] Furthermore, the width of the portion of the insulating layer 9e adjacent to the long side (the side extending in the Y-axis direction) of the rectangular shape of the sealing material 11 is formed wider than the width of the other portion of the insulating layer 9e, thereby making it possible to take measures against stress when heat is generated.

[0070] <Second Embodiment> Next, a semiconductor device 202 according to a second embodiment will be described. Fig. 8 is a cross-sectional view showing an example of the structure around the die pad 2a and heat sink 10 provided in the semiconductor device 202 according to the second embodiment. Fig. 9 is a cross-sectional view showing another example of the structure around the die pad 2a and heat sink 10 provided in the semiconductor device 202 according to the second embodiment. Fig. 10 is a cross-sectional view showing a state in which the semiconductor device 202 according to the second embodiment and the heat dissipation fins 22 are connected. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0071] 8, in the second embodiment, the semiconductor device 202 further includes a heat sink 10, and the location where the insulating layer 9 is disposed is different from that in the first embodiment. Note that the sealing material 11 is not shown in FIG.

[0072] The heat sink 10 is disposed on the surface 2r of the die pad 2a. The heat sink 10 has a surface 10s (one surface) facing the surface 2r of the die pad 2a, a surface 10r (the other surface) opposite the surface 10s, and a side surface connecting the surface 10s and the surface 10r. The side surfaces of the heat sink 10 are the surfaces of the heat sink 10 in the X-axis direction and the Y-axis direction.

[0073] The insulating layer 9 is disposed from the surface 10s of the heat sink 10 to the side surface. An insulating layer 9e is also formed on the edge portion of the surface 10s of the heat sink 10. In other words, the insulating layer 9e is a portion of the insulating layer 9 formed on the edge portion of the surface 10s of the heat sink 10. The insulating layer 9e may also be formed on the side surface of the heat sink 10. That is, as shown in FIG. 8 , the insulating layer 9 may be formed from the surface 10s of the heat sink 10 to the side surface, and the insulating layer 9e may be formed from the edge portion of the surface 10s of the heat sink 10 to the side surface.

[0074] The heat sink 10, on which the insulating layer 9 including the insulating layer 9e is disposed, and the die pad 2a are tightly attached by thermocompression bonding of the sealing material 11 (see FIG. 2) during transfer molding, and are mold-sealed together with other components. Although not shown, the sealing material 11 (see FIG. 2) seals the semiconductor element 3p, the control semiconductor element 3i (see FIG. 2), the lead frame 2, and the heat sink 10, with the surface 10r of the heat sink 10 exposed.

[0075] In the semiconductor device 202 according to the second embodiment, similarly to the first embodiment, the semiconductor device 202 can improve reliability while enhancing heat dissipation.

[0076] Since it is possible to coat a large number of heat sinks 10 by lining them up and spraying the insulating material onto them using a spray or the like, it is easier to form the insulating layer 9 than to selectively coat the die pad 2a of the lead frame 2 using a jig or the like.

[0077] Furthermore, by providing the heat sink 10 on which the insulating layer 9 including the insulating layer 9e is disposed inside the semiconductor device 202, the heat concentrated directly below the semiconductor element 3p can be spread by the heat sink 10. As a result, the heat can be efficiently transferred to the heat dissipation fins 22 (see FIG. 3), which are the heat dissipation path thereafter, and dissipated. Furthermore, since the insulating layer 9e has the same thickness as in the first embodiment, it does not significantly impede heat dissipation in the semiconductor device 202. Specifically, the thickness of the insulating layer 9 including the insulating layer 9e is approximately 1 μm or more and approximately 30 μm or less.

[0078] In addition, by using a material such as copper (Cu) for the heat sink 10, the rigidity of the lead frame 2, which has a smaller thermal expansion coefficient than the sealing material 11, can be improved, which also helps to suppress warping of the semiconductor device 202.

[0079] 9, the insulating layer 9 may be formed from the surface 10r of the heat sink 10 to the side surface, and the insulating layer 9e may be formed from the edge portion of the surface 10r of the heat sink 10 to the side surface. The sealing material 11 is not shown in FIG. 9. Although not shown, the sealing material 11 (see FIG. 2) seals the semiconductor element 3p, the control semiconductor element 3i (see FIG. 2), the lead frame 2, and the heat sink 10, leaving the portion of the insulating layer 9 located on the surface 10r of the heat sink 10 exposed. In the structure of FIG. 9, the die pad 2a and the heat sink 10 are in close contact without the insulating layer 9, and heat from the semiconductor element 3p can be spread to the heat sink 10 more efficiently than in the structure of FIG. 8.

[0080] 10, the sealing material 11 is connected to the heat dissipation fins 22 via the grease 23. At this time, the thickness of the grease 23 directly below the die pad 2a can be kept thin and constant at the bottom of the recess formed by the insulating layer 9 arranged on the surface 2r of the die pad 2a and the insulating layer 9e arranged on the edge portion.

[0081] Third Embodiment Next, a semiconductor device 202 according to a third embodiment will be described. Fig. 11 is a cross-sectional view showing an example of the structure of a die pad 2a and its periphery provided in the semiconductor device 202 according to the third embodiment. Fig. 12 is a cross-sectional view showing another example of the structure of a die pad 2a and its periphery provided in the semiconductor device 202 according to the third embodiment. Note that in the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0082] 11, forming a roughened insulating layer 9s on the side surface of the die pad 2a not only ensures close contact between the sealing material 11 and the insulating layer 9e located at the edge where stress is greatest, but also improves adhesion due to the anchor effect caused by the roughening treatment. As a result, even higher reliability can be ensured for the semiconductor device 202. Since the adhesion improves as the surface becomes finer and rougher, it is desirable that the arithmetic mean roughness Ra of the surface of the insulating layer 9e, which is the portion of the insulating layer 9 located at the edge, be 0.05 μm or more and 0.1 mm or less.

[0083] 12, by roughening the side surface of the die pad 2a and then forming an insulating layer 9s by a conventional method, it is possible to obtain the same anchor effect as in Fig. 11. Because coating by a conventional method is possible, it becomes easier to form an insulating layer 9s with a roughened surface, and the reliability of the semiconductor device 202 can be improved at low cost.

[0084] As shown in FIGS. 6 and 7, in order to further improve reliability, the roughened insulating layer 9s may be formed thicker on a predetermined side.

[0085] Fourth Embodiment In this embodiment, the semiconductor device 202 according to the above-described first to third embodiments is applied to a power conversion device 200. The application of the semiconductor device 202 according to the first to third embodiments is not limited to a specific power conversion device, but hereinafter, as the fourth embodiment, a case where the semiconductor device 202 according to the first to third embodiments is applied to a three-phase inverter will be described.

[0086] FIG. 13 is a block diagram showing the configuration of a power conversion system to which a power conversion device 200 according to the fourth embodiment is applied.

[0087] The power conversion system shown in Fig. 13 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0088] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 13 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0089] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0090] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown) and freewheeling diodes (not shown), and converts DC power supplied from the power supply 100 into AC power by switching the switching elements, and supplies the AC power to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit, and can be configured from six switching elements and six freewheeling diodes connected in anti-parallel to each switching element.

[0091] At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is configured using a semiconductor device 202 corresponding to any one of the above-described embodiments 1 to 3. In embodiment 4, as an example, the main conversion circuit 201 includes the semiconductor device 202 according to embodiment 1. Six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0092] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the semiconductor device 202, or may be provided separately from the semiconductor device 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. To maintain a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and to maintain a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0093] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0094] In the power conversion device 200 according to this embodiment, the semiconductor device 202 is used as a switching element and a free wheel diode of the main conversion circuit 201, and therefore, it is possible to achieve improved reliability.

[0095] In the present embodiment, an example has been described in which the semiconductor device 202 according to the first to third embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device 202 according to the first to third embodiments is not limited to this, and the semiconductor device 202 can be applied to various power conversion devices. In the present embodiment, the two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device 202 according to the first to third embodiments may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device 202 according to the first to third embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0096] Furthermore, the power conversion device 200 to which the semiconductor device 202 according to any one of the first to third embodiments is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0097] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0098] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0099] Various aspects of the present disclosure are summarized below as appendices.

[0100] (Supplementary Note 1) A semiconductor device comprising: a lead frame including a die pad, a first lead having one end connected to the die pad, and a second lead arranged on the opposite side of the die pad from the first lead; a semiconductor element mounted on one side of the die pad; a controlling semiconductor element mounted on one side of one end of the second lead and controlling the semiconductor element; an insulating layer arranged from the other side of the die pad opposite the one side to a side connecting the one side and the other side; and a sealing material that seals the semiconductor element, the controlling semiconductor element, and the lead frame while leaving exposed a portion of the insulating layer arranged on the other side of the die pad, wherein a thickness of a portion of the insulating layer arranged on an edge portion of the other side of the die pad is thicker than a thickness of the remaining portion, and the portion of the insulating layer arranged on the edge portion protrudes from a surface of the sealing material.

[0101] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the insulating layer has a thickness of 1 μm or more and 30 μm or less.

[0102] (Appendix 3) A semiconductor device as described in Appendix 1 or Appendix 2, wherein the lead frame includes a plurality of the die pads, the sealing material is formed in a rectangular shape when viewed from the other side of the plurality of die pads, the plurality of die pads are arranged at intervals from each other along the longitudinal direction of the sealing material, and the width of the portion of the insulating layer arranged at the edge portion is uniform.

[0103] (Appendix 4) A semiconductor device as described in Appendix 1 or Appendix 2, wherein the lead frame includes a plurality of the die pads, the sealing material is formed in a rectangular shape when viewed from the other side of the plurality of die pads, the plurality of die pads are arranged at intervals from each other along the longitudinal direction of the sealing material, and the width of the portion of the insulating layer adjacent to the rectangular short side of the sealing material at the edge portion is wider than the width of the remaining portion at the edge portion.

[0104] (Appendix 5) A semiconductor device as described in Appendix 1 or Appendix 2, wherein the lead frame includes a plurality of the die pads, the sealing material is formed in a rectangular shape when viewed from the other side of the plurality of die pads, the plurality of die pads are arranged at intervals from each other along the longitudinal direction of the sealing material, and the width of the portion of the insulating layer adjacent to the rectangular long side of the sealing material at the edge portion is wider than the width of the remaining portion at the edge portion.

[0105] a heat sink disposed on the other side opposite to the one side of the die pad, the heat sink having one side facing the other side of the die pad, the other side opposite to the one side, and a side connecting the one side and the other side; an insulating layer disposed from the other side of the heat sink to the side; and a sealing material that seals the semiconductor element, the controlling semiconductor element, the lead frame, and the heat sink while exposing a portion of the insulating layer disposed on the other side of the heat sink, wherein a thickness of the portion of the insulating layer disposed on an edge portion of the other side of the heat sink is greater than a thickness of other portions.

[0106] (Supplementary Note 7) The semiconductor device according to Supplementary Note 6, wherein the insulating layer has a thickness of 1 μm or more and 30 μm or less.

[0107] (Appendix 8) A semiconductor device according to appendix 6 or appendix 7, wherein the arithmetic mean roughness Ra of the surface of the portion of the insulating layer arranged on the edge portion of the other surface of the heat sink is 0.05 μm or more and 0.1 mm or less.

[0108] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 8, wherein the sealing material is connected to a heat dissipation fin via grease.

[0109] (Supplementary Note 10) A power conversion device comprising: a main conversion circuit having the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, which converts input power and outputs the converted power; and a control circuit which outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

[0110] 2 Lead frame, 2a Die pad, 2b Control lead, 2c Power lead, 3i Control semiconductor element, 3p Semiconductor element, 9, 9e Insulating layer, 10 Heat sink, 11 Sealing material, 22 Heat dissipation fin, 23 Grease, 200 Power conversion device, 201 Main conversion circuit, 202 Semiconductor device, 203 Control circuit.

Claims

1. A semiconductor device comprising: a lead frame including a die pad, a first lead having one end connected to the die pad, and a second lead arranged on the opposite side of the die pad to the first lead; a semiconductor element mounted on one side of the die pad; a controlling semiconductor element mounted on one side of one end of the second lead and controlling the semiconductor element; an insulating layer arranged from the other side of the die pad opposite to the one side to a side connecting the one side and the other side; and a sealing material that seals the semiconductor element, the controlling semiconductor element, and the lead frame while leaving a portion of the insulating layer arranged on the other side of the die pad exposed, wherein a thickness of a portion of the insulating layer arranged on an edge portion of the other side of the die pad is thicker than a thickness of any other portion, and the portion of the insulating layer arranged on the edge portion protrudes from a surface of the sealing material.

2. The semiconductor device according to claim 1, wherein the thickness of said insulating layer is not less than 1 μm and not more than 30 μm.

3. A semiconductor device as described in claim 1 or claim 2, wherein the lead frame includes a plurality of the die pads, the sealing material is formed in a rectangular shape when viewed from the other side of the plurality of die pads, the plurality of die pads are arranged at intervals from each other along the longitudinal direction of the sealing material, and the width of the portion of the insulating layer arranged at the edge portion is uniform.

4. A semiconductor device as described in claim 1 or claim 2, wherein the lead frame includes a plurality of the die pads, the sealing material is formed in a rectangular shape when viewed from the other side of the plurality of die pads, the plurality of die pads are arranged at intervals from one another along the longitudinal direction of the sealing material, and the width of a portion of the insulating layer adjacent to the rectangular short side of the sealing material at the edge portion is wider than the width of the remaining portion at the edge portion.

5. A semiconductor device as described in claim 1 or claim 2, wherein the lead frame includes a plurality of the die pads, the sealing material is formed in a rectangular shape when viewed from the other side of the plurality of die pads, the plurality of die pads are arranged at intervals from one another along the longitudinal direction of the sealing material, and the width of a portion of the insulating layer adjacent to the long side of the rectangular shape of the sealing material at the edge portion is wider than the width of the remaining portion at the edge portion.

6. A semiconductor device comprising: a lead frame including a die pad, a first lead having one end connected to the die pad, and a second lead arranged on the opposite side of the die pad to the first lead; a semiconductor element mounted on one side of the die pad; a controlling semiconductor element mounted on one side of one end of the second lead and controlling the semiconductor element; a heat sink arranged on the other side opposite to the one side of the die pad and having one side facing the other side of the die pad, the other side opposite to the one side, and a side connecting the one side and the other side; an insulating layer arranged from the other side of the heat sink to the side; and a sealing material that seals the semiconductor element, the controlling semiconductor element, the lead frame, and the heat sink while leaving a portion of the insulating layer arranged on the other side of the heat sink exposed, wherein a thickness of a portion of the insulating layer arranged on an edge portion of the other side of the heat sink is thicker than a thickness of other portions.

7. The semiconductor device according to claim 6, wherein the thickness of said insulating layer is not less than 1 μm and not more than 30 μm.

8. The semiconductor device according to claim 6 or 7, wherein the arithmetic mean roughness Ra of the surface of the portion of the insulating layer disposed on the edge portion of the other side of the heat sink is not less than 0.05 μm and not more than 0.1 mm.

9. The semiconductor device according to any one of claims 1 to 8, wherein the sealing material is connected to a heat dissipation fin via grease.

10. A power conversion device comprising: a main conversion circuit having a semiconductor device according to any one of claims 1 to 9, which converts and outputs input power; and a control circuit which outputs a control signal for controlling said main conversion circuit to said main conversion circuit.

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