Bonded semiconductor substrate and method for manufacturing bonded semiconductor substrate

Abstract

The present invention provides a bonded semiconductor substrate and a method for manufacturing a bonded semiconductor substrate, which make it possible to sufficiently ensure the bonding strength between a first semiconductor substrate and a second semiconductor substrate and which can prevent the occurrence of a bonding failure caused by a pit on a surface to be bonded.　Provided is a method for manufacturing a bonded semiconductor substrate which includes a first semiconductor substrate and a second semiconductor substrate that is in contact with the first semiconductor substrate, said method being characterized by comprising: an amorphous layer stacking step for stacking an amorphous layer, which has the same composition as the first semiconductor substrate, on a first surface to be bonded which is a bonding surface of the first semiconductor substrate to the second semiconductor substrate and / or a second surface to be bonded which is a bonding surface of the second semiconductor substrate to the first semiconductor substrate; a bonding step for, after the amorphous layer stacking step, forming a bonded substrate having a bonding interface by bonding the first surface to be bonded and the second surface to be bonded; and a heat treatment step for heat-treating the bonded substrate, wherein the amorphous layer stacking step and the bonding step are carried out in one apparatus.

Description

Bonded semiconductor substrate and method for manufacturing the same

[0001] The present invention relates to a bonded semiconductor substrate and a method for manufacturing the same.

[0002] Silicon carbide (hereinafter sometimes referred to as "SiC") is an example of a substrate material for power devices, but the manufacturing cost of the SiC single crystal substrate itself is high, which has hindered the practical use of the SiC single crystal substrate alone. In response to this, bonded semiconductor substrates have been developed in which a high-quality SiC single crystal substrate is used only for the layer where the device is formed, and a low-cost support substrate such as a SiC polycrystalline substrate is used for the other portions to reinforce the SiC single crystal substrate. For example, technology related to bonded semiconductor substrates is disclosed in Patent Document 1.

[0003] When a SiC polycrystalline substrate is used as a support substrate in a bonded semiconductor substrate, the SiC polycrystalline substrate has various plane orientations on its surface, and therefore, when attempting to planarize the surface by CMP, the etching rate varies depending on the plane orientation, which is significantly affected by the crystal grains, resulting in a decrease in surface flatness. In this state, when the surface of the SiC polycrystalline substrate is bonded to the highly flat surface of a SiC single crystal substrate, gaps are generated at the bonding interface, resulting in poor bonding.

[0004] For this reason, in Patent Document 1, a FAB gun (Fast Atom Beam Gun) is used to irradiate the surfaces of a SiC single crystal substrate and a SiC polycrystalline substrate with a neutral atomic beam of argon to form a bonding surface with high bonding strength even on a SiC polycrystalline substrate, which is difficult to flatten to the same degree as the surface of a SiC single crystal substrate. This irradiation amorphizes the surfaces of the SiC single crystal substrate and the SiC polycrystalline substrate, and after bonding the SiC single crystal substrate and the SiC polycrystalline substrate, heat treatment is performed to crystallize the amorphized layer to obtain a bonded semiconductor substrate.

[0005] Japanese Patent No. 6061251 Japanese Patent Application Laid-Open No. 2009-117533

[0006] In the method of Patent Document 1, the SiC single crystal substrate and the SiC polycrystalline substrate are directly bonded together, which improves the bonding strength of the bonding interface and reduces the number of defective bonding portions.

[0007] However, in Patent Document 1, the surface of the SiC polycrystalline substrate used as the support substrate is polished to reduce the surface roughness before bonding to the SiC single crystal substrate. However, even so, a plurality of pits remain on the polished surface of the SiC polycrystalline substrate, which may cause portions of the bonded interface to become poorly bonded after bonding.

[0008] Therefore, in order to solve the above-mentioned problems, an object of the present invention is to provide a bonded semiconductor substrate obtained by bonding a first semiconductor substrate and a second semiconductor substrate, which can ensure sufficient bonding strength between the first semiconductor substrate and the second semiconductor substrate and can suppress the occurrence of bonding defects due to pits on the surfaces to be bonded, and a method for manufacturing such a bonded semiconductor substrate.

[0009] In order to solve the above-mentioned problems, the method for manufacturing a bonded semiconductor substrate of the present invention is a method for manufacturing a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, and comprises: an amorphous layer laminating step of laminating an amorphous layer composed of the same composition as the first semiconductor substrate on at least one of a first bonding target surface, which is the surface of the first semiconductor substrate where the first semiconductor substrate is bonded to the second semiconductor substrate, or a second bonding target surface, which is the surface of the second semiconductor substrate where the second semiconductor substrate is bonded to the first semiconductor substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface together after the amorphous layer laminating step to form a bonded substrate having a bonding interface; and a heat treatment step of heat treating the bonded substrate, wherein the amorphous layer laminating step and the bonding step are performed in the same apparatus.

[0010] The first semiconductor substrate and the second semiconductor substrate may be made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), and diamond, wherein the first semiconductor substrate is polycrystalline and the second semiconductor substrate is single crystal.

[0011] The amorphous layer laminating step may be a step of laminating the amorphous layer on at least one of the first surface to be joined or the second surface to be joined by sputtering film formation using a sputtering method.

[0012] The method for manufacturing a bonded semiconductor substrate may further include, before the amorphous layer stacking step, an oxide removal step of removing at least one of an oxide on the first bonding target surface and an oxide on the second bonding target surface.

[0013] The oxide removal step may be a step of using at least one of the first surface to be joined or the second surface to be joined as a target and removing at least one of the oxides on the first surface to be joined or the oxides on the second surface to be joined by a sputtering method.

[0014] The heat treatment step may be a step of maintaining the temperature of the bonded substrate at 1500°C to 2200°C.

[0015] The method may further include an ion implantation step, before the amorphous layer laminating step, of implanting hydrogen ions or helium ions into the second bonding target surface to form an ion-implanted layer inside the second semiconductor substrate.

[0016] The method may further include a peeling step after the bonding step and before the heat treatment step, in which a microbubble layer formed by heating the ion-implanted layer is used as a peeling surface to peel off a portion of the second semiconductor substrate.

[0017] The amorphous layer deposition step may be a step of depositing an amorphous layer having a thickness of 10 nm to 30 nm.

[0018] In order to solve the above-mentioned problems, the present invention provides a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, the bonded semiconductor substrate being disk-shaped with a diameter of 100 to 210 mm, and the number of bonding defects at the bonding interface being 0.05 pcs / cm. ２ The following is the result.

[0019] The present invention can provide a bonded semiconductor substrate obtained by bonding a first semiconductor substrate and a second semiconductor substrate, in which the bonding strength between the first semiconductor substrate and the second semiconductor substrate is sufficiently ensured and the occurrence of bonding defects due to pits on the surfaces to be bonded can be suppressed, and a method for manufacturing the bonded semiconductor substrate can be provided.

[0020] Fig. 1 is a flow diagram showing an example of a method for manufacturing a bonded semiconductor substrate of the present invention. Fig. 2 is a schematic perspective view showing an example of a bonded semiconductor substrate of the present invention. Fig. 3 is a schematic side view of a single crystal substrate after formation of a hydrogen implanted layer in the present invention. Fig. 4 is a schematic side view of a single crystal substrate after lamination of an amorphous layer in the present invention. Fig. 5 is an explanatory diagram showing an example of an oxide removing step, an amorphous layer lamination step, and a bonding step in the present invention. Fig. 6 is a schematic side view of an example of a bonded substrate after the bonding step and before the delamination step. Fig. 7 is a schematic side view of an example of a bonded substrate after the delamination step and before the heat treatment step.

[0021] This specification discloses a bonded semiconductor substrate and a method for manufacturing the same, characterized in that the bonded semiconductor substrate is obtained by laminating an amorphous layer on at least one of the surfaces of a first semiconductor substrate and a second semiconductor substrate, bonding these semiconductor substrates together to form a bonded substrate having a bonded interface, and then performing a heat treatment to recrystallize the amorphous layer.

[0022] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

[0023] [Bonded Semiconductor Substrate] The bonded semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate, which are bonded together via a bonding interface.

[0024] <Configuration of Bonded Semiconductor Substrate> Figure 2 is a perspective view showing an example of a bonded semiconductor substrate of the present invention. Bonded semiconductor substrate 10 of the present invention is formed in the shape of a disk with, for example, an orientation flat. Bonded semiconductor substrate 10 includes support substrate 11, which is an example of a first semiconductor substrate, and single-crystal substrate 13, which is an example of a second semiconductor substrate, and single-crystal substrate 13 is bonded to support substrate 11 to form bonded interface 14.

[0025] The single crystal substrate 13 is made of, for example, a compound semiconductor (e.g., silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ The carbon (C) may be any of a single element semiconductor (e.g., silicon (Si), carbon (C)), and diamond. These elements are semiconductor materials that can be used to fabricate semiconductor devices. The carbon (C) may be other than diamond, such as graphite.

[0026] Various materials can be used for the support substrate 11. It is preferable that the support substrate 11 has resistance to various thermal processes applied to the single crystal substrate 13. For example, the support substrate 11 can be made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), diamond, sapphire (Al ２ O ３ ), and quartz (SiO ２ ) and the like. The carbon (C) is other than diamond, and is, for example, graphite.

[0027] Furthermore, support substrate 11 is preferably made of a material that has a small difference in thermal expansion coefficient from single crystal substrate 13. For this reason, support substrate 11 is preferably a polycrystalline substrate made of the same material as single crystal substrate 13. For example, single crystal substrate 13, which is an example of the second semiconductor substrate, may be a single crystal silicon carbide substrate (SiC single crystal substrate), and support substrate 11, which is an example of the first semiconductor substrate, may be a polycrystalline silicon carbide substrate (SiC polycrystalline substrate).

[0028] The SiC single crystal substrate may be a 4H—SiC single crystal substrate produced by, for example, sublimation deposition. The SiC single crystal substrate may be, for example, substantially disk-shaped with an orientation flat and a diameter of 4 to 8 inches (100 to 210 mm).

[0029] Furthermore, the SiC polycrystalline substrate may contain a mixture of SiC crystals of various polytypes and plane orientations. A SiC polycrystalline substrate containing a mixture of various polytypes and plane orientations can be manufactured without strict temperature control, thereby reducing the cost of manufacturing the support substrate 11. For example, a 3C-SiC polycrystalline substrate obtained by depositing a SiC polycrystalline film by chemical vapor deposition can be used. The shape of the SiC polycrystalline substrate may be substantially the same as that of a SiC single crystal substrate; for example, a substantially disk-shaped substrate with an orientation flat and a diameter of 4 to 8 inches (100 to 210 mm) can be used.

[0030] The thickness TT1 of the support substrate 11 may be determined so as to provide a mechanical strength sufficient to withstand subsequent processes, such as forming an epitaxial layer and then forming a semiconductor element or device thereon. For example, when the diameter of the support substrate 11 is 6 inches (approximately 150 mm), the thickness TT1 may be approximately 350 μm, and a substrate having a thickness TT1 of 300 to 500 μm can be used.

[0031] The bonded semiconductor substrate 10 is a disk-shaped substrate having a diameter of 4 to 8 inches (100 to 210 mm), and the number of bonded defects at the bonded interface 14 is 0.05 pcs / cm ２ For example, the number of defective bonding portions in a bonded semiconductor substrate having a diameter of 4 inches is 4 pcs or less, the number of defective bonding portions in a bonded semiconductor substrate having a diameter of 6 inches is 7 pcs or less, and the number of defective bonding portions in a bonded semiconductor substrate having a diameter of 8 inches is 12 pcs or less.

[0032] Poor bonding at the bonding interface 14 refers to a state in which a gap occurs at the bonding interface and the first semiconductor substrate and the second semiconductor substrate are not bonded together. For example, due to multiple pits present on the polished surface of a SiC polycrystalline substrate, there may be portions at the bonding interface after bonding that result in poor bonding.

[0033] Here, the defective bonding portion can be measured using a wafer surface defect inspection device, and is the area of ​​the effective region on the single crystal substrate where a device can be fabricated (for example, 161 cm in the case of a 6-inch substrate). ２The defect density (pcs / cm) can be calculated by dividing the number of voids (<8 pcs) formed at the interface between the single crystal substrate and the polycrystalline substrate detected within the effective area by the area of ​​the effective area. ２ The bonding failures are those in the region with a diameter of 10 μm or more.

[0034] [Method for Manufacturing Bonded Semiconductor Substrate] Next, as an example of a method for manufacturing a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate of the present invention, a method for manufacturing bonded semiconductor substrate 10 in which support substrate 11, which is the first semiconductor substrate, is a SiC polycrystalline substrate and single crystal substrate 13, which is the second semiconductor substrate, is a 4H—SiC single crystal substrate will be described. Here, with reference to the flow diagram showing an example of a method for manufacturing a bonded semiconductor substrate shown in FIG. 1 , a case in which bonded semiconductor substrate 10 is manufactured using a technique for delaminating single crystal substrate 13 by ablation of hydrogen atoms will be described.

[0035] The first and second semiconductor substrates may be made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ The carbon (C) may be any of diamond and graphite, for example.

[0036] The first semiconductor substrate may be polycrystalline, and the second semiconductor substrate may be single crystal. When a SiC single crystal substrate is used for single crystal substrate 13, it is not limited to a 4H-SiC single crystal substrate, and SiC single crystal substrates of various polytypes, such as 3C-SiC and 6H-SiC, can be used as single crystal substrate 13. When a SiC polycrystalline substrate is used for support substrate 11, it is not limited to a 3C-SiC polycrystalline substrate, and SiC polycrystalline substrates of various polytypes can be used.

[0037] First, the support substrate 11 and the single crystal substrate 13 are prepared. The support substrate 11 and the single crystal substrate 13 can be obtained with the surfaces to be bonded already planarized. The planarization may be performed by grinding or cutting, or by a CMP method. Alternatively, the surfaces to be bonded may be planarized by the user.

[0038] <Hydrogen Ion Implantation Step (Step S0)> In step S0 of Fig. 1, a hydrogen ion implantation step is performed in which hydrogen ions are implanted from the bonding target surface 13a of the single crystal substrate 13. When hydrogen ions are implanted into the single crystal substrate 13, the hydrogen ions reach a depth corresponding to the incident energy and are distributed at a high concentration. As a result, a hydrogen-implanted layer 15, indicated by a dotted line, is formed at a predetermined depth from the bonding target surface 13a, as shown in the side schematic diagram of Fig. 3. For example, the hydrogen-implanted layer 15 is formed at a depth of about 0.6 µm from the bonding target surface 13a.

[0039] A helium implantation layer may be formed by ion implanting helium instead of hydrogen, or by alternately implanting hydrogen and helium ions to form an implantation layer, and the same peeling effect can be expected in the peeling step described below.

[0040] The hydrogen ion implantation step is not an essential step in the present invention, and the present invention may be carried out by purchasing a single crystal substrate 13 after hydrogen ion implantation, or by using the same.

[0041] Furthermore, the hydrogen ion implantation process is a process that can be adopted, for example, even when the first semiconductor substrate is a SiC polycrystalline substrate and the second semiconductor substrate is a SiC single crystal substrate, or when the first semiconductor substrate is a Si substrate and the second semiconductor substrate is a Si substrate, and is a process that can be performed before or after the amorphous layer stacking process described below.

[0042] <Oxide Removal Step (Step S1)> This step is a step of removing at least one of the oxide on the first surface to be bonded 11 a and the oxide on the second surface to be bonded 13 a before the amorphous layer stacking step. By removing the oxide, bonds of Si, C, etc. can be exposed on the first surface to be bonded 11 a and the second surface to be bonded 13 a, thereby enabling the first semiconductor substrate and the second semiconductor substrate to be bonded more firmly.

[0043] The specific technique for the oxide removal step is not particularly limited as long as it is a technique that can remove the oxide on the first surface to be bonded 11 a or the second surface to be bonded 13 a. For example, a method that causes atoms or molecules to collide with the first surface to be bonded or the second surface to be bonded to remove the oxide or adsorption layer on these surfaces by a sputtering phenomenon, or a method that chemically reacts a reactive gas with the oxide on the first surface to be bonded or the second surface to be bonded to remove it by etching, can be used.

[0044] In the present invention, when a sputtering method is used in the subsequent amorphous layer stacking step, it is preferable to also remove oxides by sputtering in the oxide removal step. That is, at least one of the first surface to be joined 11 a or the second surface to be joined 13 a may be used as a target, and at least one of the oxides on the first surface to be joined or the oxides on the second surface to be joined may be removed by sputtering. Specifically, the oxides may be removed by irradiating the surface to be joined 11 a or the surface to be joined 13 a with argon ions used in the sputtering method, rather than the target material, (FIG. 5).

[0045] The oxide removal step is performed in step S1 of Fig. 1. For example, as shown in Fig. 5, the single crystal substrate 13 and the support substrate 11 are placed in a chamber 101 of a sputtering device, and are processed by facing sputtering targets 102 and 103, respectively. For example, the output of argon ions is set to 0.5 kW to 2.0 kW, which is lower than that of a normal sputtering method, and the argon ions are irradiated onto at least one of the surfaces 11a and 13a to be joined, thereby removing oxides adhering to these surfaces. The degree of vacuum in the chamber 101 is set to, for example, 10 to 1 x 10 －２ It may be about Pa.

[0046] Furthermore, by performing the oxide removal process and the subsequent amorphous layer lamination process using a sputtering method and by performing these processes consecutively in the same apparatus, these processes are performed in a vacuum, so that the bonding target surfaces 11a and 13a are not oxidized, etc., and the amorphous layers can be laminated while maintaining their active state, making it possible to suppress bonding defects caused by oxides, thereby shortening the manufacturing time and enabling the first semiconductor substrate and the second semiconductor substrate to be more firmly bonded.

[0047] The oxide removal step is not an essential step, and can be omitted if the two substrates can be bonded together in the bonding step described below to form the bonded semiconductor substrate 10 without any problems. When performing the oxide removal step, if oxide exists on only one of the first surface to be bonded 11 a and the second surface to be bonded 13 a, it is sufficient to remove the oxide from only that surface, and it is not necessary to perform the oxide removal step on both surfaces.

[0048] <Amorphous Layer Lamination Step (Step S2)> This step is a step of laminating an amorphous layer 12 having the same composition as that of the first semiconductor substrate on the first surface to be bonded of the first semiconductor substrate or the second surface to be bonded of the second semiconductor substrate, or on both surfaces thereof. That is, this is a step of depositing and laminating the amorphous layer 12 on at least one of the surface to be bonded 11 a or the surface to be bonded 13 a, and the amorphous layer 12 may be laminated on both the surface to be bonded 11 a and the surface to be bonded 13 a.

[0049] 1, in step S2, an amorphous layer 12 is laminated on the bonding target surface 13a of the single crystal substrate 13. The amorphous layer 12 may be any layer in which the elements constituting it have no regularity in their arrangement, that is, it is not crystalline, but has elements arranged irregularly.

[0050] The amorphous layer 12 is preferably deposited by a physical vapor deposition method, such as evaporation or sputtering.

[0051] In the present invention, atomic diffusion bonding is performed in a subsequent bonding process. Patent Document 1 discloses a method of amorphizing the surfaces of a single crystal substrate and a polycrystalline substrate by irradiating them with a neutral argon atomic beam using a FAB gun, followed by heat treatment to crystallize the amorphized layer and then bonding them. However, the method described in Patent Document 1 amorphizes the surfaces of these substrates themselves, and this method also has limitations on the thickness of the amorphous layer that can be formed. In Patent Document 1, for example, the thickness of the amorphous layer is 2 nm. Therefore, if pits or the like occur on the surface of the polycrystalline substrate, the pits may remain as they are even after bonding the single crystal substrate and the polycrystalline substrate, resulting in poor bonding.

[0052] The bonding process of the present invention is atomic diffusion bonding, which is a direct bonding at room temperature, as in Patent Document 1, but the amorphous layer is formed by depositing it using a physical vapor deposition method to achieve direct bonding. Because room-temperature bonding can be used as the bonding process, a heating step is not required, and warping of the substrate due to thermal stress does not occur, making high-precision bonding easy. Furthermore, covalent bonding at the atomic level provides strong bonding strength, resulting in excellent reliability and durability as a bonded semiconductor substrate. Furthermore, because the amorphous film is deposited using a physical vapor deposition method, the amorphous layer can be deposited to any thickness, reducing the occurrence of bonding defects caused by surface roughness on the bonding surface compared to the method of Patent Document 1. Details will be described later.

[0053] As a physical vapor deposition method, a sputtering method is particularly preferred because it allows the amorphous layer to be deposited with a uniform thickness over the entire surface to be laminated. A commercially available sputtering device can be used for the sputtering method.

[0054] The amorphous layer 12 is preferably composed of the same composition as the support substrate 11. By using the same composition, it is possible to maintain strong bonding strength, reduce distortion at the bonding interface during bonding, and suppress warping of the substrate caused by differences in linear expansion coefficients during heat treatment in the semiconductor device manufacturing process. Furthermore, since the optical properties of the amorphous layer 12 can be matched to those of the support substrate 11, noise from the bonding interface during optical defect inspection of the finally manufactured bonded semiconductor substrate 10 can be reduced, ensuring defect detection accuracy. When the support substrate 11 is SiC polycrystalline, the amorphous layer 12 is preferably composed of SiC with the same composition as the support substrate 11.

[0055] As an example of an embodiment of the present invention, a method for depositing the amorphous layer 12 by sputtering film formation using a sputtering method will be described in detail.

[0056] First, as shown in FIG. 5 , single crystal substrate 13 and support substrate 11 are placed in chamber 101, and sputtering is performed with each substrate facing sputtering targets 102 and 103. Taking into consideration the sputtering yield, a SiC target can be used that provides an amorphous layer of SiC with a Si:C ratio of approximately 1:1. The Si:C ratio of the SiC target may be adjusted as appropriate. For example, a SiC target with a Si-rich composition may be used. It is more preferable to use a SiC target with a Si-rich composition because an amorphous layer formed using a SiC target with a Si-rich composition can be heated at a temperature lower than the softening point of the polycrystalline substrate during the heat treatment process for diffusing and polycrystallizing the amorphous layer.

[0057] The atmosphere in the chamber 101 during the lamination process of the amorphous layer is a vacuum, and the degree of vacuum is, for example, 10 to 1×10－２ The pressure may be about Pa. The output is 0.5 to 5.0 kW, and can be set to, for example, 1 kW.

[0058] Furthermore, in order to control the conductivity, at least one of nitrogen (N), phosphorus (P), and boron (B) can be added to the amorphous layer. For example, nitrogen (N) can be added to the amorphous layer by introducing 0.1 to 50 volume % of nitrogen (N) into the atmosphere in the chamber 101 in addition to the inert gas argon (Ar) before sputtering deposition.

[0059] The thickness of the laminated amorphous layer is preferably 10 nm or more. For example, an amorphous layer of 5 nm may be formed on each of the bonding target surfaces 11 a and 13 a to make the total thickness 10 nm, or a 10 nm amorphous layer may be formed on only one of the surfaces. There is no upper limit to the thickness of the amorphous layer, but considering the productivity of the sputtering process, a thickness of 30 nm or less is preferred.

[0060] By stacking such an amorphous layer 12, the elements in the amorphous layer 12 become more likely to move in the subsequent heat treatment process, making it easier for the elements to move into pits in the SiC polycrystalline substrate of the support substrate 11 and fill the pits, thereby making it possible to suppress the occurrence of poor bonding.

[0061] For example, when the amorphous layer 12 is formed on the single crystal substrate 13, a structure in which the amorphous layer 12 is laminated on the surface of the single crystal substrate 13 is formed, as shown in the schematic side view of FIG.

[0062] <Bonding Step (Step S3)> This step is a step of bonding the first surface to be bonded and the second surface to be bonded together after the amorphous layer stacking step, to form a bonded substrate having a bonding interface.

[0063] 1, a bonding process is performed. In the bonding process, for example, the bonding target surface 11a of the support substrate 11, on which the amorphous layer 12 is stacked, and the bonding target surface 13a of the single crystal substrate 13 are aligned in the chamber 101 and then brought into contact in a vacuum. As a result, bonds present on the bonding target surface 11a and the bonding target surface 13a in an active state bond with each other, and the support substrate 11 and the single crystal substrate 13 are bonded. As a result, a structure in which the support substrate 11 and the single crystal substrate 13 are bonded is formed, as shown in the schematic diagram of FIG. 6.

[0064] The bonding temperature may be room temperature, and the pressure during bonding may be such that warping of the substrates is suppressed and a flat surface is ensured. For example, it may be 100N to 500N.

[0065] The bonding step is preferably performed as a continuous step in the same apparatus as the amorphous layer lamination step, since the amorphous layer lamination step and the bonding step can be performed continuously under the same vacuum conditions, and therefore the surfaces of the amorphous layers 12 on the bonding target surfaces 11 a and 13 a can be prevented from being oxidized, etc., and can be kept in an active state, ensuring stable bonding.

[0066] Furthermore, the oxide removal step, amorphous layer stacking step, and bonding step may be performed as consecutive steps in the same apparatus. This allows consecutive processing to be performed in a vacuum, so that the bonding target surfaces 11 a and 13 a can be stacked and bonded to the amorphous layer 12 while maintaining their active state without being oxidized, etc., and bonding defects caused by oxides can be suppressed, thereby shortening the manufacturing time and enabling stronger bonding between the first semiconductor substrate and the second semiconductor substrate.

[0067] <Delamination Step (Step S4)> This step can be performed after the bonding step and before the heat treatment step, in which a microbubble layer is formed in the hydrogen implantation layer 15 by applying heat during the delamination step, and a part of the second semiconductor substrate is delaminate using the microbubble layer as a delamination surface. In other words, the single crystal substrate 13 is delaminate using the hydrogen implantation layer 15 on which the microbubble layer has been formed in the single crystal substrate 13 as a delamination surface.

[0068] 1, a separation step is performed. Specifically, the support substrate 11 and the single crystal substrate 13 bonded together are heated to about 800°C or higher. The atmosphere during separation may be at least one of an inert gas atmosphere such as argon (Ar) or nitrogen (N), or a vacuum atmosphere. The degree of vacuum is, for example, 1×10 －４ ~1 x 10 －６ The pressure may be about 100 Pa. The separation may be performed by rapid thermal annealing (RTA) or using a furnace. This allows the single crystal substrate 13 to be separated at the hydrogen-implanted layer 15. As a result, as shown in the schematic diagram of FIG. 7 , a bonded substrate 30 can be formed in which a thin single crystal substrate 13, for example, 0.6 μm thick, is bonded to a support substrate 11.

[0069] <Heat Treatment Step (Step S5)> This step is a step of heat treating the bonded substrate, and the bonded semiconductor substrate 10 is completed by the heat treatment step.

[0070] In step S5 of FIG. 1 , a heat treatment process is performed. In this heat treatment process, the bonded substrate 30, which includes the support substrate 11, the amorphous layer 12, and the single-crystal substrate 13, is heat-treated. The heat treatment temperature may be set so that the temperature of the bonded substrate 30 is 1500°C to 2200°C, preferably about 1700°C. By setting the heat treatment temperature (i.e., the temperature of the bonded substrate 30) to 1500°C to 2200°C, the bonded substrate 30 can be heat-treated without any problems to form the bonded semiconductor substrate 10. If the heat treatment temperature is less than 1500°C, the amorphous layer 12 may remain, potentially reducing the bonding strength of the bonded interface 14. Furthermore, if the heat treatment temperature exceeds 2200°C, the substrate material may sublimate, potentially causing roughness on the surface of the bonded substrate 30.

[0071] The atmosphere for the heat treatment may be at least one of an inert gas atmosphere such as argon (Ar) or nitrogen (N) and a vacuum atmosphere. The degree of vacuum is, for example, 1×10 －４ ~1 x 10 －６The heat treatment process may be performed in the furnace in which the delamination process was performed. Furthermore, if the heat treatment temperature is maintained for 1 minute or more, the amorphous layer 12 can be completely crystallized and eliminated. There is no particular upper limit to the time for which the heat treatment temperature is maintained, but in consideration of manufacturing efficiency, the upper limit may be set to, for example, 100 hours. For example, the time for which the heat treatment temperature is maintained can be set between 1 minute and 10 hours.

[0072] In the heat treatment process of step S5, when elements in amorphous layer 12 are recrystallized, the elements move, and the phenomenon of the elements moving into pits in the SiC polycrystalline substrate of support substrate 11 and filling the pits becomes more likely to occur, and as a result, it becomes possible to suppress bonding defects at bonding interface 14.

[0073] The above manufacturing method is used to produce a bonded semiconductor substrate 10 comprising a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, the bonded semiconductor substrate 10 being disk-shaped with a diameter of 101.6 to 203.2 mm, and the number of bonding defects at the bonding interface being 0.05 pcs / cm ２ The bonded semiconductor substrate 10 can be manufactured as follows.

[0074] Furthermore, in the method for manufacturing junction semiconductor substrate 10 of the present invention, after the heat treatment step (step S5), a single crystal layer of a required thickness may be epitaxially grown on single crystal substrate 13. The epitaxial layer thus obtained becomes the formation region for various elements of the semiconductor device. The thickness of the epitaxial layer required for forming the various elements is not particularly limited, but is generally 5 μm or more in the case of a SiC junction semiconductor substrate, for example.

[0075] <Analysis of Bonding Strength> A bonded semiconductor substrate 10 was produced by bonding a SiC single crystal substrate and a SiC polycrystalline substrate based on the above-described method for manufacturing a bonded semiconductor substrate, and a tensile test was performed on the bonded semiconductor substrate 10. Even when a pressure of 20 MPa, the upper limit of the apparatus, was applied, the bonded surfaces did not peel off. This shows that even when the surfaces to be bonded have such high surface roughness that they cannot be bonded using conventional direct bonding methods (e.g., Patent Document 2), by using the method for manufacturing a bonded semiconductor substrate according to the present invention, it is possible to bond a SiC single crystal substrate and a SiC polycrystalline substrate with sufficient bonding strength to withstand semiconductor processes, etc.

[0076] <Analysis of Bonding Defects> Five 6-inch bonded semiconductor substrates were fabricated by bonding a SiC single crystal substrate and a SiC polycrystalline substrate based on the above-described method for manufacturing a bonded semiconductor substrate of the present invention, and the number of bonding defects was confirmed for each of these substrates using a wafer surface defect inspection device (SICA88 manufactured by Lasertec Corporation). As a comparative example, five 6-inch bonded semiconductor substrates were fabricated by bonding a SiC single crystal substrate and a SiC polycrystalline substrate based on the semiconductor substrate manufacturing method described in Patent Document 1, and the number of bonding defects was similarly confirmed for each of these substrates.

[0077] The number of defective bonding portions in a bonded semiconductor substrate manufactured based on the semiconductor substrate manufacturing method described in Patent Document 1 is 0.1 to 0.5 pcs / cm ２ On the other hand, the number of bonded transferred portions of bonded semiconductor substrate 10 produced by the method for producing a bonded semiconductor substrate of the present invention using a SiC polycrystalline substrate having a surface to be bonded with the same surface roughness as the surface roughness of the surface to be bonded of the SiC polycrystalline substrate used in the production method described in Patent Document 1 was <0.05 pcs / cm for all five substrates. ２ This is what happened.

[0078] Furthermore, it was found that the number of bonded poor portions in a bonded semiconductor substrate produced based on the semiconductor substrate manufacturing method described in Patent Document 1 has a large positive correlation with the surface roughness of the bonding surface of the SiC polycrystalline substrate used as the support substrate, and the number of bonded poor portions tends to increase as the surface roughness increases. On the other hand, the number of bonded poor portions in a bonded semiconductor substrate 10 produced by the bonded semiconductor substrate manufacturing method of the present invention has a small positive correlation with the surface roughness of the bonding surface of the SiC polycrystalline substrate used as the support substrate, and no tendency for the number of bonded poor portions to increase as the surface roughness increases. It was confirmed that the number of bonded poor portions can be reduced by adjusting the thickness of the deposited amorphous layer.

[0079] From the above, it can be seen that the method for manufacturing a bonded semiconductor substrate of the present invention can suppress the occurrence of bond defects in the manufactured bonded semiconductor substrate 10.

[0080] <Effects> In the method for manufacturing a bonded semiconductor substrate of the present invention, by stacking an amorphous layer on at least one of the first surface to be bonded 11 a of the first semiconductor substrate or the second surface to be bonded 13 a of the second semiconductor substrate, the atoms constituting the semiconductor are made more mobile, and for example, a phenomenon in which elements move into pits on the surface to be bonded 11 a of the SiC polycrystalline substrate used as support substrate 11 and fill the pits is more likely to occur, making it possible to suppress the occurrence of poor bonding portions.

[0081] (Summary) As described above, the present invention can provide a bonded semiconductor substrate and a method for manufacturing a bonded semiconductor substrate that can suppress the occurrence of bonding defects caused by pits and prevent peeling of the substrates at the bonding interface, and is therefore industrially useful.

[0082] 10: semiconductor substrate, 11: support substrate, 11a: surface to be bonded, 12: amorphous layer, 13: single crystal substrate, 13a: surface to be bonded, 14: bonding interface, 15: hydrogen implanted layer, 30: bonded substrate, 101: chamber, 102: sputtering target, 103: sputtering target

Claims

1. A method for manufacturing a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, comprising: an amorphous layer laminating step of laminating an amorphous layer composed of the same composition as the first semiconductor substrate on at least one of a first bonding target surface, which is the surface of the first semiconductor substrate where the first semiconductor substrate is bonded to the second semiconductor substrate, or a second bonding target surface, which is the surface of the second semiconductor substrate where the second semiconductor substrate is bonded to the first semiconductor substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface after the amorphous layer laminating step to form a bonded substrate having a bonding interface; and a heat treatment step of heat treating the bonded substrate, wherein the amorphous layer laminating step and the bonding step are performed in the same apparatus.

2. The first semiconductor substrate and the second semiconductor substrate are made of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ 2. The method of claim 1, wherein the first semiconductor substrate is polycrystalline and the second semiconductor substrate is single crystal, and the first semiconductor substrate is either one of silicon, nickel, tantalum, or diamond.

3. The method for manufacturing a bonded semiconductor substrate as described in claim 1, wherein the amorphous layer lamination step is a step of laminating the amorphous layer on at least one of the first bonding target surface or the second bonding target surface by sputtering deposition using a sputtering method.

4. A method for manufacturing a bonded semiconductor substrate as set forth in claim 1, further comprising, before said amorphous layer laminating step, an oxide removal step of removing at least one of an oxide on said first bonding target surface and an oxide on said second bonding target surface.

5. A method for manufacturing a bonded semiconductor substrate as described in claim 4, wherein the oxide removal step is a step of using at least one of the first bonding target surface or the second bonding target surface as a target and removing at least one of the oxide on the first bonding target surface or the oxide on the second bonding target surface by a sputtering method.

6. The method for producing a bonded semiconductor substrate according to claim 1, wherein the heat treatment step is a step of maintaining the temperature of the bonded substrate at 1500°C to 2200°C.

7. The method for manufacturing a bonded semiconductor substrate as set forth in claim 1, further comprising, prior to said amorphous layer lamination step, an ion implantation step of implanting hydrogen ions or helium ions into said second bonding target surface to form an ion implanted layer inside said second semiconductor substrate.

8. The method for manufacturing a bonded semiconductor substrate according to claim 7, further comprising a peeling step after the bonding step and before the heat treatment step, the peeling step being a step of peeling off a part of the second semiconductor substrate using a microbubble layer formed by heating the ion implantation layer as a peeling surface.

9. The method for producing a junction semiconductor substrate according to claim 1, wherein the amorphous layer laminating step is a step of laminating an amorphous layer having a thickness of 10 nm to 30 nm.

10. A bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, the bonded semiconductor substrate being disk-shaped with a diameter of 100 to 210 mm, and the number of bonding defects at the bonding interface being 0.05 pcs / cm ２ A bonded semiconductor substrate,

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