Information processing device, information processing method, and program

Abstract

The present invention provides an information processing device, an information processing method, and a program with which computational accuracy, computational speed, and circuit scale can all be achieved.　An information processing device 1 includes a reservoir provided between an input layer having one or more nodes and an output layer, and having a storage means storing an input / output relationship enabling unique determination of an output value to be output to the output layer on the basis of information input from the nodes of the input layer. It is desirable that the storage means be implemented by one or more LUTs on an FPGA, and it is more desirable that one node of the reservoir be implemented by a single LUT.

Description

Information processing device, information processing method, and program

[0001] The present invention relates to an information processing device, particularly a reservoir computing device, and also to an information processing method, particularly an information processing method using a reservoir computing device.The present invention also relates to a program for causing a computer to operate as an information processing device.

[0002] Neural networks (NNs) that mimic the function and structure of neurons in the human brain are known, as are recurrent neural networks (RNNs) that have a structure in which signals are passed back within the network (the output of a certain layer is passed back to the input).

[0003] Furthermore, reservoir computing (RC) is known as a type of RNN. RC is one of the AI ​​technologies that has attracted attention in recent years and is applied to real-time data processing. Implementing RC in an FPGA (Field Programmable Gate Array) makes it possible to realize a high-speed, low-power system. Here, non-patent documents 1 to 6 are available as literature on RC.

[0004] Kawashima, Y. Katori, T. Morie, and H. Tamukoh, “An areaefficient multiply-accumulation architecture and implementations for time-domain neural processing,” in 2021 International Conference on Field-Programmable Technology (ICFPT). IEEE, pp. 1-4, 2021.K. Yoshida, Y. Abe, M. Akai-Kasaya, and T. Asai, “FPGA Architecture for Reservoir Computing with time-division input interfaces and online learning systems,” IEICE Technical Report; IEICE Tech. Rep., 2021.Herbert Jaeger, “Tutorial on training recurrent neural networks, covering BPPT, RTRL, EKF and the" echo state network" approach”, GMD-Forschungszentrum Informationstechnik, 2002.Miquel L. Alomar, Vincent Canals, Nicolas Perez-Mora, Victor Martinez-Moll, Josep L. Rossello, “FPGA-Based Stochastic Echo State Networks for Time-Series Forecasting”, Computational Intelligence and Neuroscience, 2016.Ichiro Kawashima, Yuichi Katori, Takashi Morie, Hakaru Tamukoh, “An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing”, 2021 International Conference on Field-Programmable Technology (ICFPT), pp. 1-4, Online, December 6-10 (9), 2021.Victor M. Gan, Yibin Liang, Lianjun Li, Lingjia Liu, Yang Yi, “A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection”, ACM Journal on Emerging Technologies in Computing Systems, Volume 17, Issue 4, Article No.47, pp. 1-15, 2021.

[0005] As can be seen from Non-Patent Documents 1 to 6, in RC, the computational complexity and circuit size of the reservoir are dominant (see Non-Patent Document 1). Therefore, time-sharing of reservoir calculations has been proposed as an FPGA implementation method for RC (see Non-Patent Document 2). This method implements only a small number of calculation circuits in the FPGA and reuses them while changing the data to realize reservoir calculations. In other words, the circuit size is reduced by reducing the number of calculation circuits implemented in the FPGA. However, this method has the problem of causing a significant increase in calculation time.

[0006] On the other hand, a method for quantizing reservoir operations has also been proposed (see Non-Patent Document 4). This method reduces the circuit size required per operation circuit by quantizing the weights and activation values ​​of each reservoir neuron. Therefore, although it is possible to reduce the circuit size, it still has the problem of causing a decrease in operation accuracy.

[0007] Although FPGA implementation methods that simultaneously incorporate these two techniques have been proposed (see Non-Patent Documents 5 and 6), due to the problems mentioned above, it can be said that it is difficult to achieve all three of the requirements of computational accuracy, computational speed, and circuit size with conventional FPGA implementation methods for reservoir computing.

[0008] Therefore, an object of the present invention is to provide an information processing device, an information processing method, and a program that can achieve three things: calculation accuracy, calculation speed, and circuit scale.

[0009] The information processing device of the present invention includes a reservoir provided between an input layer having one or more nodes and an output layer, the reservoir having a storage means for storing an input-output relationship that can uniquely determine an output value to be output to the output layer based on information input from the nodes of the input layer. As a result, the operation of the reservoir is completed simply by determining the output for an input according to the input-output relationship stored in the storage means.

[0010] It is preferable that the storage means is realized by one or more LUTs on the FPGA, and it is more preferable that one node constituting the reservoir is realized by one LUT. Also, when the number of connections of one node constituting the reservoir is k, the number of combinations of the number of connections k is j (=2 k ) output value is stored in memory Z of the LUT. i It is more desirable that the values ​​are stored in (i=0 to j-1) respectively.

[0011] Furthermore, it is desirable that the output layer uses a differential calculation method as its calculation method, which calculates only the output values ​​from the nodes that make up the reservoir and whose states have changed. It is even more desirable that, when detecting the nodes that make up the reservoir and whose states have changed, this differential calculation method compares the state at a certain time with the states at multiple times before that time, and starts calculation from the state with the smallest difference.

[0012] On the other hand, the information processing method of the present invention includes the steps of providing a reservoir between an input layer having one or more nodes and an output layer, storing in a storage means an input / output relationship that can uniquely determine an output value to be output to the output layer based on information input from the nodes of the input layer, and outputting to the output layer the output value that has been uniquely determined by the reservoir referring to the storage means based on input data from the input layer.

[0013] The program of the present invention is a program for causing a computer to operate as an information processing device having a reservoir provided between an input layer having one or more nodes and an output layer, the reservoir having a memory means for storing an input / output relationship that can uniquely determine an output value to be output to the output layer based on information input from a node in the input layer.

[0014] According to the information processing device of the present invention, the reservoir calculation is completed simply by determining the output in response to the input according to the input / output relationship stored in the memory means, so it is possible to provide an information processing device that can achieve both calculation accuracy, calculation speed, and circuit size.

[0015] Furthermore, the information processing method and program of the present invention can achieve the same effects as the information processing device of the present invention.

[0016] 1 is a diagram showing an example of a typical reservoir computing model. 2 is a diagram showing an example of the calculation of a 3-input 1-output LUT. 3 is a diagram showing an example of a microcomputer development board (microcomputer board, target board). 4 is a schematic diagram showing one node of a general LUT-Network. 5 (A) is a diagram showing the configuration between the input layer and reservoir layer in FIG. 1, a schematic diagram of a node in the reservoir layer to which information is input from the input layer, and 6 (B) is a configuration diagram of the node in question, which is composed of an LUT. 7 (A) is a diagram showing the configuration within the reservoir layer in FIG. 1, a schematic diagram of a node in the reservoir layer to which information (signal) is input traced back from the reservoir, and 8 (B) is a configuration diagram of the node in question, which is composed of an LUT. 9 (A) is a diagram showing the configuration between the reservoir layer and output layer in FIG. 1, a schematic diagram of a node in the output layer, and 10 (B) is a configuration diagram of a general node in question. 10 is a diagram showing an example of the input / output relationship of reservoir neurons to be stored in an LUT. 1A and 1B are diagrams for explaining the configuration of an output layer arithmetic circuit, where (A) is a diagram for explaining a general time-sharing method, and (B) is a diagram for explaining a calculation method for calculating only output values ​​from neurons that make up a reservoir whose state has changed.

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[0017] The following describes in detail an embodiment of the present invention, but the following description of the components is merely an example (representative example) of an embodiment of the present invention, and the present invention is not limited to the following content unless the gist of the present invention is changed. In addition, in this description, neurons and nodes are synonymous, and reservoirs and reservoir layers are synonymous.

[0018] [Reservoir Computing] Reservoirs are suitable for classification and prediction using time series data, and require nonlinearity to perform nonlinear transformations on input data (time series data). In addition, reservoirs need to store past input data (short-term memory) in order to classify and regress the input data (time series data).

[0019] As reservoir computing models such as those shown in Figure 1, Echo State Network (ESN), Liquid State Machine (LSM), and Chaotic Boltzmann Machine-RC (CBM-RC) are known. i is the number of nodes in the input layer, N r is the number of nodes in the reservoir (reservoir layer), N о is the number of nodes in the output layer. ir is the weight between the input layer and the reservoir, and W rr is the load (weight) between reservoirs, and W ro is the weight between the reservoir and the output layer. In reservoir computing, W ir and W rr is fixed by a random number. ro is optimized using ridge regression etc.

[0020] [BNN] Binarized neural networks (BNNs) are a general term for neural networks that do not use floating-point numbers (binarized). Compared to other neural network methods, BNNs have the advantage of not requiring multiplication and requiring significantly less memory. For this reason, BNNs are suitable for FPGA implementation.

[0021] [LUT-Network] The LUT-Network is known as a type of BNN. The LUT-Network is a neural network that is further developed from the BNN and focuses on FPGA implementation (a neural network realized using FPGA LUTs (LUT elements)). The LUT (Lookup Table) is a logic block mounted on the FPGA and is a rewritable part.

[0022] Figure 2 (A) shows a 3-input, 1-output LUT (LUT-3), which can be represented as a truth table as shown in Figure 2 (B). The table information (truth table) of such an LUT is stored in SRAM, so any calculation can be realized by rewriting the table information in the SRAM. In a reservoir implemented in a conventional FPGA, neurons are created using adders and multipliers created using the LUT, and a collection of such neurons constitutes the reservoir.

[0023] There are various types of LUTs, including four-input, one-output (LUT-4), six-input, one-output (LUT-6), and others. For example, the microcomputer development board shown in Figure 3 is manufactured by AMD (Advanced Micro Devices) (manufacturer number: SK-KR260-G), and is equipped with approximately 100,000 LUT-6s.

[0024] Figure 4 is a schematic diagram showing one node of a typical LUT-Network, where one node is one LUT. In the example shown in Figure 4, LUT-6 is used, so the number of inputs to one node is 6 (X0 to X5) to match the LUT.

[0025] [Information Processing Device of the Present Invention] (1. Input Layer, Reservoir) The information processing device of the present invention is a reservoir computing device that includes a reservoir provided between an input layer having one or more nodes and an output layer. The reservoir has a number of nodes (N shown in FIG. 1) r ) the higher the performance. ir and W rr is fixed and does not need to be rewritten. Therefore, the inventors of the present application came up with the idea of ​​storing the input / output relationship of the neurons in the reservoir as is in the storage means.

[0026] The storage means may be, for example, the LUT employed in this embodiment, BRAM (Block RAM), URAM (Ultra RAM), DRAM (Dynamic RAM), SRAM (Static RAM), eDRAM (Embedded DRAM), MRAM (Magnetoresistive RAM), or Flash Memory, but is not limited to these as long as it can store the input / output relationship of the neurons in the reservoir.

[0027] It is known that an arbitrary circuit can be created by combining an LUT and an SRAM, but this has the disadvantage that the written data cannot be changed after the circuit is implemented. ir and W rr Since the LUT-Network is fixed, there is no need to change the written data after the circuit is implemented. Furthermore, the connections between nodes in a neural network implemented in an FPGA are limited by the number of inputs to the LUT because the circuit scale increases exponentially. However, the reservoir layer can also operate with sparse connections. Based on this, the inventors of the present application focused on constructing a reservoir using an LUT-Network and came up with the idea of ​​directly copying (storing) the input / output relationships of the reservoir's neurons into the LUT.

[0028] Furthermore, when constructing a reservoir using an LUT-Network, the inventors of the present application considered a reservoir computing model based on the following conditions: [Condition 1] Input and output can be realized as two values ​​(1 bit). [Condition 2] It works even if the connections are sparse. [Condition 3] It does not retain values, and the output is determined only by the input and weight. Of the above conditions 1 to 3, LSM and CBM-RC do not satisfy condition 3, and it is difficult to resolve this. For this reason, in this invention, an ESN (binary ESN) with two values ​​for input and output is adopted.

[0029] More specifically, in this invention, the binary ESN, which is the most common model and is suitable for implementing the LUT-Network as described above, is adopted as the basic model and is improved upon. Note that instead of the ESN, LSM (Liquid State Machine), ChNN-RC (Chaotic Neural Network Reservoir Computing), CA-RC (Cellular Automata Reservoir Computing), etc. can also be adopted.

[0030] To provide an overview of the reservoir computing device of the present invention (hereinafter, the reservoir computing device implemented in an FPGA will be referred to as "LUTNet-RC"), the LUTNet-RC comprises an input layer having one or more nodes, a reservoir constructed by an LUT-Network, and an output layer, similar to the typical reservoir computing model shown in Figure 1. In this embodiment, a 6-input, 1-output (LUT-6) LUT is used for the reservoir.

[0031] The input layer does not perform any calculations, but rather stores input data.

[0032] On the other hand, in the reservoir, the output state S i [t+1] is determined by the network state x[t] one time before and the input u(t+1) (see equations (1) to (3)). Here, k is the number of connections of the reservoir node. In this embodiment, the LUT has six inputs, so the number of connections k is set to 6 accordingly.

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[0036] In addition, the output value of the output layer is determined by equation (4) based on the output from the reservoir.

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[0038] To explain the reservoir in more detail, conventionally, reservoir nodes that receive information input from the input layer are created by adders and multipliers created using an LUT. In other words, conventional reservoir nodes output values ​​that are product-sum calculated based on information input from the input layer to the output layer. In contrast, the reservoir of LUTNet-RC stores an input-output relationship in an LUT that can uniquely determine the output value to be output to the output layer based on information input from the input layer node.

[0039] For example, as shown in FIG. 5B, the reservoir node that receives information from the input layer is b i The input / output relationship is stored in a +k input, 1 output LUT. On the other hand, as shown in Figure 6(B), the input / output relationship of a reservoir node that has input of information (signal) going back from the reservoir is stored in a k input, 1 output LUT.

[0040] FIG. 8 shows an example of the input / output relationship of reservoir neurons stored in the LUT. When the number of connections k of the reservoir nodes is 6, the number of combinations of inputs (0 / 1) of X0 to X5 is 64 (2 to the sixth power). Therefore, based on the information (X0 to X5) input from the nodes of the input layer, the output value (Z) output to the output layer is uniquely determined by referring to the input / output relationship shown in FIG. 8. For example, when the information input from the nodes of the input layer is X0:1, X1:0, X2:1, X3:0, X4:0, X5:0, the output value (Z) is determined by the Z in the storage means (hereinafter referred to as "memory"). 40 It can be seen that the value (1) stored in the LUT is the value (1) stored in the LUT. Of course, the input / output relationship stored in the LUT can also be referenced in calculations within the reservoir layer.

[0041] In this way, the output value for each combination of inputs X0 to X5 is stored in a specific area of ​​memory (Z0 to Z5). 63 ), one neuron in the reservoir can be configured with one LUT. r By using the LUT, a reservoir with any number of nodes can be constructed.

[0042] Then, the output values ​​from the nodes of the reservoir configured by the LUT are r The result is transmitted to the output layer and the product-sum operation is output (see FIG. 7).

[0043] (2. Output Layer) Here, as the circuit configuration of the output layer, it is possible to adopt a general time-sharing method as shown in Figure 9(A). This method calculates the output values ​​from all neurons in the reservoir at time t, but since the output values ​​of all neurons are calculated, the calculation time increases in proportion to the number of neurons. In other words, with this method, there is a risk that a sufficient calculation speed cannot be obtained when the number of neurons in the reservoir is large.

[0044] Therefore, as shown in Figure 9(B), it is conceivable to adopt a calculation method (called a "difference calculation method") for calculating only the output values ​​from the neurons that make up the reservoir and whose states have changed, in the circuit configuration of the output layer. For example, in the example shown in Figure 9(B), only the output values ​​from the j1th and j2th neurons whose states have changed are calculated, and the previous input value z' i The difference between is calculated.

[0045] The differential calculation method can achieve a sufficient calculation speed compared to the general time-division method, even when the number of neurons in the reservoir is large. However, the differential calculation method only compares the state at a certain time (t) with the state one time before (t-1). Therefore, while it is effective when there are few neurons whose states have changed, when there are many neurons whose states have changed, the calculation time increases and there is a risk that a sufficient calculation speed cannot be achieved.

[0046] Therefore, the inventors of the present invention have come up with a method for detecting changes in the state of neurons constituting a reservoir by comparing the state at a certain time with the states at multiple times before the time and starting calculation from the state with the smallest difference. This method (hereinafter referred to as the "multiple difference method"), as illustrated in Figure 10, compares the state at a certain time (t) with the states at multiple times before the time (t-1 to t-3), and starts calculation from the state with the smallest difference (the j1th neuron).

[0047] The multi-difference calculation method can suppress an increase in calculation time even when there are many neurons whose states have changed, as well as when there are only a few neurons whose states have changed, thereby achieving sufficient calculation speed.

[0048] Furthermore, as shown in FIG. 11, by implementing LUTNet-RC in a PL (Programmable Logic) FPGA, an information processing device (reservoir computing device) 1 of the present invention can be constructed.

[0049] [Example] As an example, the results of an experiment using the reservoir computing device 1 of this embodiment are shown below. Note that the LUTNet-RC of the reservoir computing device 1 in the example has a number of nodes in the reservoir layer, N r The total circuit scale is as shown in Tables 1 to 3.

[0050] Table 1 shows the circuit scale of the input layer and reservoir layer, indicating the number of LUTs and FFs for each bit precision of the input. Table 2 shows the circuit scale of the output layer, indicating the number of LUTs, FFs, and BRAMs for each of the circuit configurations of the output layer (time division, differential operation, and multi-differential operation).

[0051] The speedup rate shown in Table 2 is an index showing how much faster it is compared to the time-division method, and shows the results of a simulation on software using the state at the time of NARMA10 input. For example, it can be seen that by using the differential operation method for the output layer, it is possible to achieve an 18-fold speedup compared to the time-division method. On the other hand, it can be seen that by using the multi-differential operation method for the output layer (see the four states t, t-1, t-2, t-3), it is possible to achieve a 25-fold speedup compared to the time-division method.

[0052] Table 3 shows the circuit scale including the input layer, reservoir layer, and output layer, and the number of LUTs and FFs is the sum of the values ​​shown in Tables 1 and 2. The input bit precision in Table 3 is 10.

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[0056] [Calculation Accuracy] Table 4 shows the results of a comparison of calculation accuracy between LUTNet-RC and each conventional method. Conventional methods 1 to 10 are techniques described in the following reference documents.

[0057] (Conventional Method 1) V. M. Gan, Y. Liang, L. Li, L. Liu, and Y. Yi, “A cost-efficient digital esn architecture on fpga for ofdm symbol detection,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 17, no. 4, pp. 1-15, 2021. (Conventional Method 2) C. Lin, Y. Liang, and Y. Yi, “Fpga-based reservoir computing with optimized reservoir node architecture,” in 2022 23rd International Symposium on Quality Electronic Design (ISQED). IEEE, 2022, pp. 1-6. (Conventional Method 3) K. Honda and H. Tamukoh, “A hardware-oriented echo state network and its fpga implementation,” Journal of Robotics, Networking and Artificial Life, vol. 7, no. 1, pp. 58-62, 2020. (Conventional Method 4) D. Kleyko, E. P. Frady, M. Kheffache, and E. Osipov, “Integer echo state networks: Efficient reservoir computing for digital hardware,” IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 4, pp. 1688-1701, 2020. (Conventional Method 5) M. L. Alomar, V. Canals, N. Perez-Mora, V. Martinez-Moll, and J. L.Rossello, “Fpga-based stochastic echo state networks for time-series forecasting,” Computational intelligence and neuroscience, vol. 2016, pp. 15-15, 2016. (Conventional method 6) K. Yoshida, Y. Abe, M. Akai-Kasaya, and T. Asai, “Fpga architecture for reservoir computing with time-division input interfaces and online learning systems,” IEICE Technical Report; IEICE Tech. Rep., 2021. (Conventional method 7) B. Penkovsky, L. Larger, and D. Brunner, “Efficient design of hardwareenabled reservoir computing in fpgas,” Journal of Applied Physics, vol. 124, no. 16, 2018. (Conventional method 8) B. Schrauwen, M. D’Haene, D. Verstraeten, and J. Van Campenhout, “Compact hardware liquid state machines on fpga for real-time speech recognition,” Neural networks, vol. 21, no. 2-3, pp. 511-523, 2008. (Conventional method 9) I. Kawashima, Y. Katori, T. Morie, and H. Tamukoh, “An areaefficient multiply-accumulation architecture and implementations for time-domain neural processing,” in 2021 International Conference on Field-Programmable Technology (ICFPT).IEEE, 2021, pp. 1-4. (Conventional method 10) D. Pramanta and H. Tamukoh, “Fpga implementation of pulse-coupled phase oscillators working as a reservoir at the edge of chaos,” in 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021, pp. 1-5.

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[0059] From the comparison results, it can be seen that LUTNet-RC has the highest accuracy in the benchmark task (NARAMA10), with smaller MSE (mean square error) and other values ​​than conventional methods.

[0060] [Calculation Speed] Furthermore, the results of a comparison of the calculation speed between LUTNet-RC and each conventional method are shown in Table 5. Conventional methods 1 to 10 are as described above.

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[0062] Referring to Table 5, there are conventional methods with higher throughput than LUTNet-RC (for example, Conventional Method 1 and Conventional Method 5), but this is because the number of nodes in the reservoir layer is small, at 32 and 50, respectively. Therefore, when the number of nodes in Conventional Methods 1 and 5 is matched to that of LUTNet-RC (1,500) or to the experimental condition of 100 nodes in the benchmark task (NARAMA10), the increase in calculation time in the reservoir layer significantly reduces the throughput of Conventional Methods 1 and 5.

[0063] In response to this fact, the reservoir layer of LUTNet-RC stores input / output relationships in the LUT that can uniquely determine the output values ​​to be output to the output layer based on the information input from the nodes in the input layer, and the calculation is completed simply by reading the LUT (i.e., in one clock). This means that the calculation speed of the reservoir layer of LUTNet-RC can be said to be extremely fast, and depending on the circuit configuration of the output layer, it can be said that even faster calculation speeds can be achieved. This is evident from the fact that the throughput when a differential calculation method or a multi-differential calculation method is adopted in the circuit configuration of the output layer is significantly improved compared to the throughput when these methods are not adopted.

[0064] Note that Figure 12 shows the node waveform of the reservoir of LUTNet-RC, and from this waveform, it can be seen that the neuron output is frequently inverted regularly. In other words, it can be seen that there are many neurons whose states are changing. For this reason, it is considered preferable to adopt a multi-difference calculation method rather than a difference calculation method in the output layer of LUTNet-RC. In short, with LUTNet-RC, calculations are completed in one clock in the reservoir layer, and the frequent regular inversion of the neuron output in the reservoir layer (there are many neurons whose states are changing) can be improved by ingenuity in the output layer, thereby achieving sufficient calculation speed.

[0065] As shown in Figure 12, the reason why the neuron output in the LUTNet-RC reservoir is frequently inverted regularly is thought to be due to the binarization of the neuron output. In other words, it seems that subtle changes in the calculated value in the reservoir are rounded to either 0 or 1 by the binary activation function.

[0066] As another application example, by using a multi-difference calculation method in the output layer, it is possible to achieve speedup at least 25 times faster than the time-division method, making inference on the order of Mfps possible.

[0067] [Circuit Size] Table 6 also shows the results of a comparison of the circuit size between LUTNet-RC and each conventional method. Conventional methods 1 to 10 are as described above. Note that the circuit size (LUT, FF, DSP, BRAM) of LUTNet-RC in Table 6 is partially larger than that shown in Table 3 because Table 6 shows the circuit size of the entire system on the PL shown in FIG. 11, which also includes the communication circuit with the PS (for example, approximately 5,000 LUTs are used for DMA pub and DMA sub).

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[0069] From these comparison results, it can be seen that the circuit scale of LUTNet-RC is approximately 1 / 10 to 1 / 100 of that of conventional methods in terms of the number of nodes (when comparing the number of nodes of each conventional method at 1,500). In other words, as mentioned above, LUTNet-RC can be said to achieve a significant reduction in circuit scale while maintaining sufficient performance (computation accuracy, computation speed). Therefore, it can be said that LUTNet-RC can be implemented in edge devices that require high performance (computation accuracy, computation speed).

[0070] From the above embodiments, it can be said that the information processing device (LUTNet-RC) of the present invention is able to achieve three things at the same time: calculation accuracy, calculation speed, and circuit size.

[0071] The information processing device (LUTNet-RC) described so far is merely an example of one embodiment, and its design can be modified as appropriate as long as the gist of the device is not altered. For example, any method can be adopted to construct the LUTNet-RC. Specifically, for the input layer and reservoir layer, Python can be used to generate a circuit configuration (program) to be stored in an FPGA. For the output layer, Verilog can be used to generate a circuit incorporating a hardware-oriented algorithm. Furthermore, in this description, the values ​​stored in memory are binary data (0 or 1), but the information input from the input layer nodes and the output values ​​are not limited to this.

[0072] The present invention provides an information processing device, information processing method and program that can achieve a balance between calculation accuracy, calculation speed and circuit scale, and is particularly useful in industry because it can be implemented in small devices.

[0073] 1. Information processing device (reservoir computing device)

Claims

1. An information processing device comprising: a reservoir provided between an input layer having one or more nodes and an output layer, the reservoir having a memory means for storing an input / output relationship that can uniquely determine an output value to be output to the output layer based on information input from a node in the input layer.

2. The information processing device according to claim 1, wherein the storage means is realized by one or more LUTs on an FPGA.

3. The information processing device according to claim 2, wherein one node constituting the reservoir is realized by one LUT.

4. If the number of connections of one node constituting the reservoir is k, the number of combinations of the number of connections k (=2 k ) of the output value is stored in the memory Z i The information processing device according to claim 3 , wherein the first and second inputs are stored in the first and second memory locations (i=0 to j−1), respectively.

5. An information processing device according to any one of claims 1 to 4, wherein the output layer uses a differential calculation method for calculating only the output values ​​from nodes that make up the reservoir and whose states have changed.

6. The information processing device according to claim 5, wherein the difference calculation method, when detecting a node that constitutes the reservoir whose state has changed, compares the state at a certain time with the states at multiple times prior to that time, and starts calculation from the state with the smallest difference.

7. An information processing method comprising the steps of: providing a reservoir between an input layer having one or more nodes and an output layer; storing in a storage means an input / output relationship that can uniquely determine an output value to be output to the output layer based on information input from a node of the input layer; and outputting to the output layer an output value that is uniquely determined by the reservoir referring to the storage means based on input data from the input layer.

8. A program for operating a computer as an information processing device having a reservoir provided between an input layer having one or more nodes and an output layer, the reservoir having a memory means for storing an input / output relationship capable of uniquely determining an output value to be output to the output layer based on information input from a node of the input layer.

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