Semiconductor device

Abstract

This semiconductor device includes: a semiconductor substrate; a transistor; a temperature-sensitive diode; a fourth insulating layer formed above the temperature-sensitive diode; a diode pad provided at a position separated from the temperature-sensitive diode when viewed from the thickness direction of the semiconductor substrate; an embedded wiring; and a first transistor pad. The semiconductor substrate includes a substrate upper surface and a substrate lower surface facing opposite the substrate upper surface. The transistor is formed above the substrate upper surface of the semiconductor substrate. The temperature-sensitive diode is formed above the substrate upper surface of the semiconductor substrate. The embedded wiring is embedded in the fourth insulating layer and is used to connect the temperature-sensitive diode and the diode pad. The first transistor pad: includes a section formed above the temperature-sensitive diode with the fourth insulating layer disposed therebetween; and is electrically connected to the transistor.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Switching elements such as insulated gate bipolar transistors (IGBTs) used in automotive inverter devices tend to generate heat because they rapidly switch between supplying and blocking current. Therefore, to prevent the temperature of the switching elements from exceeding a guaranteed operating range, some switching elements are equipped with a temperature-sensing diode configured to detect the temperature of the switching elements. For example, Patent Document 1 discloses a switching element equipped with a temperature-sensing diode.

[0003] JP 2017-103272 A

[0004] [Summary] In semiconductor devices, a technique is known in which electrode pads are formed over a wide area on the top surface of the semiconductor device and then electrically connected to the electrode pads by metal clips. By adopting such electrical connections, it is possible to improve the heat dissipation and reduce the resistance of the semiconductor device compared to conventional wire bonding.

[0005] Here, when the electrical connection using an electrode pad and a metal clip is adopted for the upper surface of the switching element, the presence of a temperature-sensitive diode limits the shape of the electrode pad and the placement of the metal clip. Specifically, a switching element equipped with a temperature-sensitive diode includes diode wiring for extending the anode and cathode of the temperature-sensitive diode to the outside of the temperature-sensitive diode. The diode wiring is provided on the temperature-sensitive diode and covered with an organic protective film. The diode wiring must be electrically isolated from the portion through which the current for the switching element flows. Therefore, the electrode pad must be formed in a shape that avoids the diode wiring and the organic protective film, and the metal clip must be positioned in a position that avoids the diode wiring and the organic protective film.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate having a substrate upper surface and a substrate lower surface facing opposite to the substrate upper surface, a transistor formed on the substrate upper surface of the semiconductor substrate, a temperature-sensitive diode formed on the substrate upper surface of the semiconductor substrate, an insulating layer formed on the temperature-sensitive diode, a diode pad provided at a position spaced apart from the temperature-sensitive diode when viewed in the thickness direction of the semiconductor substrate, buried wiring embedded in the insulating layer and used to connect the temperature-sensitive diode and the diode pad, and a first transistor pad including a portion formed above the temperature-sensitive diode across the insulating layer and electrically connected to the transistor.

[0007] FIG. 1 is a plan view of a semiconductor device according to an embodiment. FIG. 2 is a plan view of the semiconductor device of FIG. 1 with a protective insulating film removed. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 1. FIG. 4 is a cross-sectional view taken along line 4-4 in FIG. 1. FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. 2. FIG. 6 is an enlarged view of a cathode pad and its vicinity in the semiconductor device of FIG. 1. FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. 6. FIG. 8 is a plan view of the semiconductor device of FIG. 1 with a conductive member bonded thereto. FIG. 9 is a plan view of the semiconductor device of FIG. 1 with a conductive member bonded thereto. FIG. 10 is a cross-sectional view of a semiconductor device according to a modified example.

[0008] DETAILED DESCRIPTION Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. For simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Furthermore, cross-sectional views may omit hatching lines for ease of understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be construed as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] [Plane Layout of Semiconductor Device] FIG. 1 is a schematic plan view of an exemplary semiconductor device 10 according to one embodiment. The semiconductor device 10 includes a transistor 20 and a temperature-sensitive diode 40 that detects the temperature of the semiconductor device 10. The transistor 20 and the temperature-sensitive diode 40 are mounted on the same chip. The transistor 20 is an insulated gate bipolar transistor (IGBT). The semiconductor device 10 is used, for example, as a switching element in an on-board inverter device. In this case, a current of, for example, 5 A or more and 1000 A or less flows through the semiconductor device 10. Details of the transistor 20 and the temperature-sensitive diode 40 will be described later.

[0011] As shown in FIG. 1, the semiconductor device 10 is, for example, a rectangular flat plate. The semiconductor device 10 has a top surface 10s, a back surface 10r (see FIGS. 3 and 4) facing the opposite side to the top surface 10s, and four side surfaces 10a to 10d formed between the top surface 10s and the back surface 10r. The side surfaces 10a to 10d are, for example, surfaces connecting the top surface 10s and the back surface 10r, and are perpendicular to both the top surface 10s and the back surface 10r. The top surface 10s is, for example, rectangular.

[0012] In the following description, the direction in which the device top surface 10s and device back surface 10r face is referred to as the "z direction." The z direction can also be said to be the height direction of the semiconductor device 10. Two mutually orthogonal directions perpendicular to the z direction are referred to as the "x direction" and "y direction." In this embodiment, the device side surfaces 10a and 10b constitute both end surfaces of the semiconductor device 10 in the x direction, and the device side surfaces 10c and 10d constitute both end surfaces of the semiconductor device 10 in the y direction. As used herein, the term "plan view" refers to viewing the semiconductor device 10 from above along the z direction, unless explicitly stated otherwise. Furthermore, plan view refers to viewing in the thickness direction of the semiconductor substrate 30, which will be described later.

[0013] In a plan view, the semiconductor device 10 includes an active region A located in the central portion of the semiconductor device 10 and a peripheral region B located on the outer periphery of the semiconductor device 10. The active region A is a region in which the transistor 20 or the temperature-sensitive diode 40 is formed. The peripheral region B is a region in which neither the transistor 20 nor the temperature-sensitive diode 40 is formed. The peripheral region B is a region that surrounds the active region A in a plan view and extends in a band shape along the periphery of the active region A. The peripheral region B is annular in shape surrounding the active region A in a plan view. The term "annular" as used in this disclosure may refer to any structure that forms a loop, i.e., a continuous shape without ends. "Annular" shapes include, but are not limited to, circles, ellipses, and polygons with pointed or rounded corners.

[0014] The active region A includes a diode region A1 in which the temperature sensing diode 40 is formed and a transistor region A2 in which the transistor 20 is formed. The diode region A1 is located in the center of the active region A in a planar view. The transistor region A2 is a region that surrounds the diode region A1 in a planar view. The transistor region A2 is annular in shape that surrounds the diode region A1 in a planar view. The diode region A1 and the transistor 20 are arranged so as to be spaced apart from each other without overlapping each other in a planar view.

[0015] 2 shows the arrangement of electrode pads in the semiconductor device 10. FIG. 2 is a plan view of the semiconductor device 10 of FIG. 1 with a protective insulating film 14, which will be described later, removed. As shown in FIG. 2, a first transistor pad 11 and a second transistor pad 12, which are electrically connected to the transistor 20, and a diode pad 13, which is electrically connected to the temperature-sensitive diode 40, are arranged on the top surface 10s of the semiconductor device 10. Each of the first transistor pad 11, the second transistor pad 12, and the diode pad 13 may be made of any conductive material including at least one of copper (Cu), aluminum (Al), an AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN).

[0016] The first transistor pad 11 is an electrode pad electrically connected to the base contact region 37 of the transistor 20. The first transistor pad 11 is provided at a position overlapping the transistor 20 provided in the transistor region A2 in a plan view. The first transistor pad 11 is arranged on the device top surface 10s so as to cover the entire active region A. In one example, the first transistor pad 11 is formed across a portion located above the transistor 20 and a portion located above the temperature-sensitive diode 40. The first transistor pad 11 covers the entire diode region A1 in a plan view. Therefore, the first transistor pad 11 covers the entire temperature-sensitive diode 40.

[0017] It is sufficient that at least a portion of the first transistor pad 11 is formed on the active region A. Therefore, the arrangement of the first transistor pad 11 on the device top surface 10s of the semiconductor device 10 is not limited to the above arrangement. For example, the first transistor pad 11 may have a shape that partially covers a part of the temperature-sensitive diode 40 in a planar view. Alternatively, the first transistor pad 11 may have a shape that does not include a portion that covers the temperature-sensitive diode 40 in a planar view, i.e., the first transistor pad 11 may be formed only on the transistor region A2 out of the diode region A1 and the transistor region A2. Below, as an example, a case will be described in which the first transistor pad 11 is formed across a portion located above the transistor 20 and a portion located above the temperature-sensitive diode 40, and covers the entire temperature-sensitive diode in a planar view.

[0018] The second transistor pad 12 is an electrode pad electrically connected to the electrode material in the gate trench 23A of the transistor 20. The second transistor pad 12 is provided at a position separated from the transistor 20 in a plan view.

[0019] The diode pad 13 includes an anode pad 13A and a cathode pad 13B. The anode pad 13A is an electrode pad electrically connected to the first semiconductor region 44P of the temperature sensitive diode 40. The cathode pad 13B is an electrode pad electrically connected to the second semiconductor region 45P of the temperature sensitive diode 40. The diode pad 13 is provided at a position separated from the temperature sensitive diode 40 in a plan view. The first semiconductor region 44P and the second semiconductor region 45P correspond to the anode region 44P and the cathode region 45P, respectively.

[0020] The second transistor pad 12 and the diode pads 13, that is, the anode pad 13A and the cathode pad 13B, are arranged in the peripheral region B on the device top surface 10s. The anode pad 13A and the cathode pad 13B are arranged closer to the same device side surface (e.g., device side surface 10a) as the second transistor pad 12 in the peripheral region B. In other words, the second transistor pad 12, the anode pad 13A, and the cathode pad 13B are arranged in a portion of the peripheral region B that is closer to the same device side surface (e.g., device side surface 10a).

[0021] In one example, the cathode pad 13B is adjacent to the second transistor pad 12 in the y direction. The cathode pad 13B and the second transistor pad 12 are arranged side by side in the y direction in a plan view. The anode pad 13A is adjacent to the cathode pad 13B in the y direction. The anode pad 13A and the cathode pad 13B are arranged side by side in the y direction in a plan view.

[0022] It is sufficient that the second transistor pad 12, the cathode pad 13B, and the anode pad 13A are formed on the peripheral region B. Therefore, the arrangement of the second transistor pad 12, the cathode pad 13B, and the anode pad 13A on the device top surface 10s of the semiconductor device 10 is not limited to the arrangement described above. Below, as an example, a case will be described in which the cathode pad 13B and the anode pad 13A are arranged near the device side surface 10a, the same as the second transistor pad 12 in the peripheral region B.

[0023] As shown in FIG. 1 , a protective insulating film 14 is provided on the device top surface 10s. The protective insulating film 14 is an organic protective film that protects the semiconductor device 10 and is formed, for example, from a material containing polyimide (PI). The protective insulating film 14 has a plurality of openings 14A that independently expose the central portions of the first transistor pad 11, the second transistor pad 12, the cathode pad 13B, and the anode pad 13A. The openings 14A provided in the protective insulating film 14 are spaced apart from each other in a plan view. The protective insulating film 14 covers the outer peripheries of the first transistor pad 11, the second transistor pad 12, the cathode pad 13B, and the anode pad 13A.

[0024] [Transistor Configuration] FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 1, showing an example of the cross-sectional structure of the semiconductor device 10 in the transistor region A2.

[0025] The semiconductor device 10 includes a semiconductor substrate 30. The semiconductor substrate 30 is, for example, － The semiconductor substrate 30 is made of a material containing silicon (Si) and has a thickness of, for example, 50 μm or more and 200 μm or less.

[0026] The semiconductor substrate 30 has a substrate upper surface 30s and a substrate lower surface 30r that face in opposite directions in the z direction. The semiconductor substrate 30 has p ＋ a n-type collector layer 31, an n-type buffer layer 32, and an n-type － The semiconductor device 10 has a structure in which a collector layer 31 and a drift layer 33 are stacked. A collector electrode 27 is formed on the substrate lower surface 30r. The collector electrode 27 is formed over substantially the entire surface of the substrate lower surface 30r. The surface of the collector electrode 27 opposite to the collector layer 31 forms the device back surface 10r of the semiconductor device 10.

[0027] The p-type dopant of the collector layer 31 may be, for example, boron (B) or aluminum (Al). The dopant concentration of the collector layer 31 is, for example, 1×10 １５ cm－３ 2x10 or more １９ cm －３ The following is the result.

[0028] The n-type dopant for the buffer layer 32 and the drift layer 33 may be, for example, N (nitrogen), P (phosphorus), or As (arsenic). The dopant concentration of the buffer layer 32 is, for example, 1×10 １５ cm －３ 5x10 or more １７ cm －３ The dopant concentration of the drift layer 33 is lower than that of the buffer layer 32, for example, 1×10 １３ cm －３ 5x10 or more １４ cm －３ The following is the result.

[0029] A p-type base region 34 is formed on the upper surface of the drift layer 33. The base region 34 is formed over substantially the entire surface of the substrate upper surface 30s. The dopant concentration of the base region 34 is, for example, 1×10 １６ cm －３ 1x10 or more １８ cm －３ The thickness of the base region 34 is, for example, not less than 1.0 μm and not more than 3.0 μm.

[0030] A plurality of trenches 35 are arranged side by side on the substrate upper surface 30s in the transistor region A2. Each trench 35 extends, for example, along the x direction and is spaced apart from one another in the y direction. The spacing between adjacent trenches 35 in the y direction (the center-to-center distance between the trenches 35) is, for example, 1.5 μm or more and 7.0 μm or less. The width of each trench 35 (the dimension of the trench 35 in the y direction) is, for example, 0.5 μm or more and 3.0 μm or less. Each trench 35 penetrates the base region 34 in the z direction and extends partway through the drift layer 33.

[0031] The upper surface of the base region 34 in the transistor region A2 (the upper surface 30s of the substrate) is ＋In the base region 34, emitter regions 36 are formed. The emitter regions 36 are arranged on both sides of the trench 35 in the y direction. In other words, it can be said that the emitter regions 36 are provided on both sides of the trench 35 in the arrangement direction of the trenches 35 in the base region 34. Therefore, two emitter regions 36 are arranged with a gap between them in the y direction between adjacent trenches 35 in the y direction. The depth of each emitter region 36 is, for example, 0.2 μm or more and 0.6 μm or less. The dopant concentration of each emitter region 36 is higher than that of the base region 34, for example, 1×10 １９ cm －３ 5x10 or more ２０ cm －３ The following is the result.

[0032] The upper surface of the base region 34 in the transistor region A2 (the upper surface 30s of the substrate) is ＋ A base contact region 37 of a type is formed. The base contact region 37 is provided at a position adjacent to the emitter region 36 in the y direction. In other words, the base contact region 37 is provided between two emitter regions 36 provided between adjacent trenches 35 in the y direction. Each base contact region 37 may be formed deeper than the emitter region 36. The depth of each base contact region 37 is, for example, 0.2 μm or more and 1.6 μm or less. The dopant concentration of each base contact region 37 is higher than that of the base region 34, for example, 5×10 １８ cm －３ 1x10 or more ２０ cm －３ The following is the result.

[0033] A first insulating layer 38 is integrally formed on both the inner surface of each trench 35 and the substrate upper surface 30s. The first insulating layer 38 is made of, for example, silicon oxide (SiO ２ The thickness of the first insulating layer 38 is, for example, not less than 1100 Å and not more than 1300 Å.

[0034] An electrode material including, for example, polysilicon is filled into each trench 35 via the first insulating layer 38. The electrode material filled into each trench 35 is electrically connected to either the first transistor pad 11 or the second transistor pad 12. In other words, the electrode material filled into each trench 35 forms a gate trench 23A and an emitter trench 21A. In this embodiment, the gate trenches 23A and the emitter trenches 21A are alternately provided in the arrangement direction of the multiple trenches 35. In this embodiment, both the gate trenches 23A and the emitter trenches 21A are filled up to the opening end of each trench 35.

[0035] A second insulating layer 39 is formed on the first insulating layer 38 provided on the substrate upper surface 30s. The second insulating layer 39 is made of, for example, SiO ２ The first transistor pad 11 is formed on the second insulating layer 39. In other words, the second insulating layer 39 is an interlayer insulating film that fills the gap between the first transistor pad 11 and the gate trench 23A. The second insulating layer 39 can also be said to be an interlayer insulating film that fills the gap between the first transistor pad 11 and the emitter trench 21A. The thickness of the second insulating layer 39 is 3000 Å or more and 15000 Å or less.

[0036] The first insulating layer 38 and the second insulating layer 39 are provided with a plurality of contact holes 39a that penetrate both the first insulating layer 38 and the second insulating layer 39 in the z-direction. The contact holes 39a are provided at positions that overlap the base contact regions 37 in plan view. The first transistor pad 11 is connected to the base contact regions 37 via the contact holes 39a.

[0037] The gate wiring for electrically connecting the electrode material embedded in the gate trench 23A to the second transistor pad 12 is not particularly limited. The gate wiring in this embodiment is a wiring extending from the electrode material embedded in the gate trench 23A and made of the electrode material. The gate wiring may also be a metal wiring such as a gate finger made of a metal or the like formed on the second insulating layer 39.

[0038] [Configuration of Temperature Sensitive Diode] FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 1, showing an example of the cross-sectional structure of the semiconductor device 10 in the diode region A1 and the transistor region A2.

[0039] The semiconductor device 10 includes a thin-film polysilicon layer 43 on which a temperature-sensitive diode 40 is provided. The polysilicon layer 43 is formed in a rectangular shape in a plan view. The polysilicon layer 43 is formed on a semiconductor substrate 30. More specifically, in the diode region A1, a third insulating layer 41 is formed on the upper surface of the base region 34 of the semiconductor substrate 30. The third insulating layer 41 is made of, for example, SiO ２ It has the following characteristics.

[0040] The polysilicon layer 43 is formed on an upper surface 41s of the third insulating layer 41. The third insulating layer 41 is an insulating layer formed integrally with the first insulating layer 38. In other words, the third insulating layer 41 constitutes a part of the first insulating layer 38. However, unlike the first insulating layer 38, the third insulating layer 41 has a function of insulating the polysilicon layer 43 from the semiconductor substrate 30. Therefore, the first insulating layer 38 and the third insulating layer 41 may be formed separately.

[0041] The temperature-sensitive diode 40 is formed of a polysilicon layer 43. The polysilicon layer 43 includes a first semiconductor region 44P of a first conductivity type and a second semiconductor region 45P of a second conductivity type joined to the first semiconductor region 44P. The first conductivity type is, for example, p-type, and the second conductivity type is, for example, n-type. In one example, the outer shape of the temperature-sensitive diode 40 in a plan view is rectangular.

[0042] The p-type dopant of the first semiconductor region 44P may be, for example, B or Al. The dopant concentration of the first semiconductor region 44P is, for example, 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The n-type dopant of the second semiconductor region 45P is, for example, N, P, As, or the like. The dopant concentration of the second semiconductor region 45P is, for example, 1×10 １８ cm－３ 5x10 or more ２０ cm －３ The following is the result.

[0043] The polysilicon layer 43 is covered with a fourth insulating layer 42. The fourth insulating layer 42 is made of, for example, SiO ２ The fourth insulating layer 42 has a first transistor pad 11 formed on it. Therefore, the first transistor pad 11 includes a portion formed on the temperature sensing diode 40 with the fourth insulating layer 42 sandwiched therebetween. The fourth insulating layer 42 is an interlayer insulating film that fills the gap between the first transistor pad 11 and the polysilicon layer 43. The fourth insulating layer 42 is an insulating layer formed integrally with the second insulating layer 39. In other words, the fourth insulating layer 42 constitutes a part of the second insulating layer 39.

[0044] The fourth insulating layer 42 includes an insulating layer upper surface 42A located above the temperature sensitive diode 40, i.e., above the polysilicon layer 43, and an insulating layer side surface 42B located laterally of the polysilicon layer 43 and connecting the insulating layer upper surface 42A and the third insulating layer 41. At least a part of the outer periphery of the insulating layer upper surface 42A in a plan view is inclined so that the thickness of the fourth insulating layer 42 gradually decreases toward the insulating layer side surface 42B.

[0045] In one example, the entire outer peripheral portion of the insulating layer upper surface 42A in a plan view is inclined so that the thickness of the fourth insulating layer 42 gradually decreases toward the insulating layer side surface 42B. The insulating layer side surface 42B may be a surface extending in the z direction, or may be an inclined surface that is continuous with the insulating layer upper surface 42A and inclined so that the thickness of the fourth insulating layer 42 gradually decreases toward the peripheral edge of the insulating layer upper surface 42A.

[0046] A buried wiring 46 is buried in the fourth insulating layer 42. The buried wiring 46 may be made of any conductive material including at least one of Ti (titanium), TiN (titanium nitride), W (tungsten), and Co (cobalt). The buried wiring 46 includes an anode wiring 46A and a cathode wiring 46B.

[0047] The anode wiring 46A is electrically connected to the first semiconductor region 44P of the polysilicon layer 43 and is a wiring for passing current between the temperature-sensitive diode 40 and the outside of the temperature-sensitive diode 40. The anode wiring 46A is embedded in the fourth insulating layer 42 and the second insulating layer 39, and is electrically connected to the anode pad 13A through the fourth insulating layer 42 and the second insulating layer 39. The lower end of the anode wiring 46A contacts the first semiconductor region 44P within the second insulating layer 39. In one example, multiple anode wirings 46A are provided in parallel. The number of anode wirings 46A is, for example, two to five. One example of the number of anode wirings 46A is two or more. When the number of anode wirings 46A is two or more, compared to when the number is one, the effect of reducing the current density per wiring and the effect of suppressing deformation of the shape during resist patterning can be obtained. The number of anode wirings 46A may be one.

[0048] The cathode wiring 46B is electrically connected to the second semiconductor region 45P of the polysilicon layer 43, and is a wiring for passing a current between the temperature sensing diode 40 and the outside of the temperature sensing diode 40. The cathode wiring 46B is embedded in the fourth insulating layer 42 and the second insulating layer 39, and is electrically connected to the cathode pad 13B through the fourth insulating layer 42 and the second insulating layer 39. The cathode wiring 46B has a lower end in contact with the second semiconductor region 45P within the second insulating layer 39.

[0049] In one example, multiple cathode wirings 46B are provided in parallel. The number of cathode wirings 46B is, for example, two to five. One example of the number of cathode wirings 46B is two or more. When the number of cathode wirings 46B is two or more, compared to when the number is one, the effect of reducing the current density per wiring and the effect of suppressing deformation of the shape during patterning using a resist can be obtained. Furthermore, the number of cathode wirings 46B may be one. The number of cathode wirings 46B may be the same as or different from the number of anode wirings 46A. In one example, the number of cathode wirings 46B is greater than the number of anode wirings 46A. In another example, the number of cathode wirings 46B is less than the number of anode wirings 46A.

[0050] 2, in a plan view, the anode wiring 46A connects the temperature sensing diode 40 and the anode pad 13A that is provided at a position spaced apart from the temperature sensing diode 40. In a plan view, the anode wiring 46A extends from the temperature sensing diode 40 to the anode pad 13A, passing through the transistor region A2 that surrounds the diode region A1.

[0051] In one example, the anode wiring 46A extends linearly in the x direction toward the device side surface 10a on which the anode pad 13A is formed in the peripheral region B in a plan view. The anode wiring 46A then bends at a right angle within the peripheral region B or near the peripheral region B in the active region A, extends linearly in the y direction, and then bends at a right angle near the anode pad 13A and extends to below the anode pad 13A. Note that in FIG. 2, the multiple anode wirings 46A are simplified and illustrated as a single wiring. The multiple anode wirings 46A are arranged in parallel along the dashed line indicating the anode wiring 46A in FIG. 2.

[0052] The cathode wiring 46B connects the temperature sensing diode 40 to the cathode pad 13B, which is located at a distance from the temperature sensing diode 40 in a plan view. In a plan view, the cathode wiring 46B extends from the temperature sensing diode 40 to the cathode pad 13B, passing through the transistor region A2 that surrounds the diode region A1. In one example, the cathode wiring 46B extends linearly in the x-direction toward the device side surface 10a on which the cathode pad 13B is formed in the peripheral region B in a plan view. At least a portion of the portion of the cathode wiring 46B that passes through the transistor region A2 is formed parallel to the anode wiring 46A.

[0053] The cathode wiring 46B bends at a right angle in the peripheral region B or near the peripheral region B in the active region A, extends linearly in the y direction, and bends at a right angle near the cathode pad 13B, extending to below the cathode pad 13B. Note that in Figure 2, the multiple cathode wirings 46B are simplified and illustrated as one wiring. The multiple cathode wirings 46B are arranged in parallel along the dashed line indicating the cathode wiring 46B in Figure 2.

[0054] 5 is a cross-sectional view taken along line 5-5 in FIG. 2, and schematically illustrates the cross sections of the anode wiring 46A and the cathode wiring 46B passing through the transistor region A2. As shown in FIG. 5, in the transistor region A2, the anode wiring 46A and the cathode wiring 46B are embedded in the second insulating layer 39, which is formed integrally and continuously with the fourth insulating layer 42 in the diode region. The anode wiring 46A and the cathode wiring 46B pass through the second insulating layer 39 and extend to below the anode pad 13A and below the cathode pad 13B, respectively.

[0055] FIG. 6 is a partially enlarged view of the cathode pad 13B and its vicinity in the plan view of the semiconductor device 10 shown in FIG. 1 . FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. 6 . As shown in FIG. 6 , in a plan view, the end of the cathode wiring 46B is located below the cathode pad 13B. As shown in FIG. 7 , the portion of the end of the cathode wiring 46B located below the cathode pad 13B is in contact with the lower surface 13Br of the cathode pad 13B, thereby being electrically connected to the cathode pad 13B. Note that the arrangement and connection configuration of the anode pad 13A and the anode wiring 46A are similar to the arrangement and connection configuration of the cathode pad 13B and the cathode wiring 46B shown in FIGS. 6 and 7 . Therefore, a description of the arrangement and connection configuration of the anode pad 13A and the anode wiring 46A will be omitted.

[0056] 8 and 9, the plate-shaped conductive member 50 joined to the first transistor pad 11 will be described. Note that, hereinafter, the portion of the first transistor pad 11 exposed from the opening 14A in a plan view will be referred to as the emitter electrode 11B.

[0057] 8 and 9 , the conductive member 50 is joined to the emitter electrode 11B by an adhesive layer 51. The conductive member 50 is, for example, a metal clip, and is formed by pressing a flat metal plate. Examples of the metal material that constitutes the conductive member 50 include copper (Cu) and aluminum (Al). The adhesive layer 51 is, for example, a conductive bonding material such as solder.

[0058] 8 shows an example in which, in a plan view, the conductive member 50A is arranged so as to avoid the diode region A1 in which the temperature sensing diode 40 is provided and the area in which the embedded wiring 46 connecting the temperature sensing diode 40 and the diode pad 13 is located. In this example, the conductive member 50A is formed to have a narrow width W1 so as to be arranged to avoid the above-mentioned area. Furthermore, to increase the contact area with the emitter electrode 11B, multiple conductive members 50A are joined to the emitter electrode 11B. The multiple conductive members 50A may be different tip portions of a single conductive member 50 having a branched tip.

[0059] In an example in which the conductive member 50A is disposed so as to avoid the above-described range, the conductive member 50A may be disposed near the diode region A1. For example, as shown in Fig. 8, in a plan view, a distance D1, which is the shortest distance between the conductive member 50A and the diode region A1, is shorter than a distance D2, which is the shortest distance between the conductive member 50A and the periphery of the emitter electrode 11B. Note that the distance D1 may be the same as or longer than the distance D2.

[0060] FIG. 9 shows an example in which, in a plan view, the conductive member 50B is arranged so as to overlap the diode region A1 in which the temperature-sensitive diode 40 is provided. In this example, a single conductive member 50B is used as the conductive member 50, formed with a wide width W1, to increase the contact area with the emitter electrode 11B. The conductive member 50B is connected to a portion of the first transistor pad 11 formed above the temperature-sensitive diode 40. The width W1 of the conductive member 50B is set to a value shorter than but close to the width W2 of the emitter electrode 11B in the same direction. For example, the width W1 of the conductive member 50B is set so that the difference between the width W1 and the width W2 (W2 - W1) is 0.4 mm or more and 1.0 mm or less. In this case, when the conductive member 50B is arranged on the emitter electrode 11B, a margin of 0.2 mm or more and 0.5 mm or less can be secured on both sides along the width W1. Moreover, the width W1 of the conductive member 50B is, for example, 50% or more and less than 100% of the width W2 of the emitter electrode 11B in the same direction.

[0061] [Operation] Next, the operation of the semiconductor device 10 will be described. In a semiconductor device including an IGBT and a temperature-sensitive diode, when electrical connection is formed by connecting an electrode pad formed on the upper surface of the semiconductor device to a plate-shaped conductive member, high positional accuracy is required for the placement of the conductive member. That is, a semiconductor device including an IGBT and a temperature-sensitive diode includes a diode wiring that connects the temperature-sensitive diode to the diode pad. In conventional configurations, to electrically isolate the diode wiring from the large current for the IGBT, an organic protective film is provided on the diode wiring, and the electrode pad is formed to avoid the organic protective film in a planar view. Furthermore, the conductive member connected to the electrode pad also needs to be positioned away from the diode wiring and the organic protective film so as to ensure a certain amount of clearance between the diode wiring and the conductive member in a planar view. Therefore, high positional accuracy is required for the placement of the conductive member.

[0062] In the semiconductor device 10 of this embodiment, the diode wiring connecting the temperature sensing diode 40 and the diode pad 13 is formed by the buried wiring 46 buried in the fourth insulating layer 42. The buried wiring 46 is electrically isolated from the portion through which the current for the transistor 20 flows by the fourth insulating layer 42 located above the buried wiring 46. This allows the conductive member 50 to be disposed in a plan view without having to consider avoiding the area where the diode wiring is provided, or the conductive member 50 to be disposed in a position closer to the area. In other words, the clearance can be eliminated or reduced.

[0063] In addition, the first transistor pad 11 is formed on the temperature sensing diode 40 and on the embedded wiring 46, with the fourth insulating layer 42 sandwiched therebetween. This allows for a larger area on the device top surface 10s of the semiconductor device 10 where the first transistor pad 11 is formed, in plan view. This increases the amount of misalignment that can be tolerated when arranging the conductive member 50. As a result, the degree of freedom in arranging the conductive member 50 relative to the first transistor pad 11 is greatly improved in plan view.

[0064] [Effects] The semiconductor device 10 provides the following effects. (1) The semiconductor device 10 includes a semiconductor substrate 30 having a substrate upper surface 30s and a substrate lower surface 30r facing opposite to the substrate upper surface 30s, a transistor 20 formed on the substrate upper surface 30s of the semiconductor substrate 30, a temperature-sensitive diode 40 formed on the substrate upper surface 30s of the semiconductor substrate 30, a fourth insulating layer 42 formed on the temperature-sensitive diode 40, a diode pad 13 provided at a position spaced apart from the temperature-sensitive diode 40 when viewed in the thickness direction of the semiconductor substrate 30, a buried wiring 46 embedded in the fourth insulating layer 42 and used to connect the temperature-sensitive diode 40 and the diode pad 13, and a first transistor pad 11 including a portion formed above the temperature-sensitive diode 40 across the fourth insulating layer 42 and electrically connected to the transistor 20. With this configuration, as described in the above function section, the degree of freedom in arranging the plate-shaped conductive member 50 relative to the first transistor pad 11 in a planar view is greatly improved.

[0065] (2) The first transistor pad 11 is formed across the portion located above the transistor 20 and the portion located above the temperature-sensitive diode 40. With this configuration, the first transistor pad 11 is located above the temperature-sensitive diode 40, so the first transistor pad 11 and the conductive member 50 can be connected even above the temperature-sensitive diode 40. This increases the range in which the conductive member 50 can be arranged in a plan view. Furthermore, by forming the first transistor pad 11 over a wide area, it is easy to ensure a wide contact area with the conductive member 50. Increasing the contact area between the first transistor pad 11 and the conductive member 50 improves the heat dissipation and reduces the resistance of the semiconductor device 10.

[0066] (3) The first transistor pad 11 covers the entire temperature sensitive diode 40 when viewed in the thickness direction of the semiconductor substrate 30. This configuration significantly achieves the effect of (2) above.

[0067] (4) The fourth insulating layer 42 includes an insulating layer upper surface 42A located above the temperature-sensitive diode 40 and an insulating layer side surface 42B connected to the insulating layer upper surface 42A, and at least a portion of the outer periphery of the insulating layer upper surface 42A is inclined so that the thickness of the fourth insulating layer 42 gradually decreases toward the insulating layer side surface 42B.

[0068] As shown in FIG. 2 , when a fourth insulating layer 42 is provided on the temperature-sensitive diode 40, a protruding portion 11A is formed on the first transistor pad 11 formed on the fourth insulating layer 42 due to the thickness of the fourth insulating layer 42. If the step between the protruding portion 11A and other portions on the top surface of the first transistor pad 11 is steep, the conductive bonding material may flow into unintended areas when bonding the conductive member 50 using a conductive bonding material. In other words, when the conductive bonding material, such as solder, placed on the first transistor pad 11 is softened, the conductive bonding material flows due to the step. As a result, the conductive bonding material may flow into unintended areas, for example, into a position that extends beyond the first transistor pad 11 in a plan view.

[0069] According to the above configuration, the outer peripheral portion of the insulating layer upper surface 42A, i.e., the corners of the fourth insulating layer 42, are gently inclined, so that the side surfaces of the protruding portion 11A of the first transistor pad 11 formed on the fourth insulating layer 42 also have a gently inclined shape. This makes it possible to minimize the flow of the conductive bonding material caused by the step of the protruding portion 11A. As a result, it is possible to prevent the conductive bonding material from flowing into unintended areas.

[0070] <Modifications> The above embodiment can be modified, for example, as follows. The above embodiment and each of the following modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, parts that are common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0071] In a configuration in which metal wiring such as a gate finger is used as the gate wiring for electrically connecting the electrode material buried in the gate trench 23A and the second transistor pad 12, the gate wiring may be a buried wiring. An example of this is shown in FIG.

[0072] 10 includes a transistor buried wiring 52 buried in a second insulating layer 39 formed on the gate trench 23A. The transistor buried wiring 52 is in contact with the upper surface of the electrode material buried in the gate trench 23A. The transistor buried wiring 52 passes through the second insulating layer 39 and is electrically connected to the second transistor pad 12. In the second insulating layer 39, the transistor buried wiring 52 is arranged, for example, in parallel with the buried wiring 46 (not shown) that connects the temperature sensing diode 40 and the diode pad 13.

[0073] By using the buried transistor wiring 52 as the gate wiring, the degree of freedom in arranging the conductive member 50 relative to the first transistor pad 11 is further improved. That is, with this configuration, the second insulating layer 39 located above the buried transistor wiring 52 electrically isolates the buried transistor wiring 52 from the portion through which a large current for the transistor 20 flows. This makes it possible to arrange the plate-shaped conductive member 50 without having to consider avoiding an area that overlaps the buried transistor wiring 52 in a plan view, or to arrange the conductive member 50 in a position closer to the area. Therefore, the degree of freedom in arranging the plate-shaped conductive member 50 relative to the first transistor pad 11 is further improved in a plan view.

[0074] The protective insulating film 14 may be omitted. In the above embodiment, the semiconductor device 10 is embodied as an IGBT, but the present invention is not limited to this. The semiconductor device 10 may be a reverse conducting IGBT, a SiC MOSFET (metal-oxide-semiconductor field-effect transistor), or a Si MOSFET.

[0075] The term "on" as used in this disclosure includes both the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0076] The z-direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z-direction described herein being "up" and "down" in the vertical direction. For example, the x-direction may be the vertical direction, or the y-direction may be the vertical direction.

[0077] Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and are not used to rank the objects. The statement "at least one of A and B" in the present disclosure should be understood to mean "A only, or B only, or both A and B." <Notes> The technical ideas that can be grasped from the present disclosure are described below. Note that, for the purpose of aiding understanding and not for the purpose of limitation, the components described in the notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference symbols.

[0078] [Supplementary Note 1] A semiconductor device (10) comprising: a semiconductor substrate (30) having a substrate upper surface (30s) and a substrate lower surface (30r) facing opposite to the substrate upper surface (30s); a transistor (20) formed on the substrate upper surface (30s) of the semiconductor substrate (30); a temperature-sensitive diode (40) formed on the substrate upper surface (30s) of the semiconductor substrate (30); an insulating layer (42) formed on the temperature-sensitive diode (40); a diode pad (13) provided at a position spaced apart from the temperature-sensitive diode (40) when viewed in the thickness direction of the semiconductor substrate (30); an embedded wiring (46) embedded in the insulating layer (42) and used to connect the temperature-sensitive diode (40) and the diode pad (13); and a first transistor pad (11) including a portion formed on the temperature-sensitive diode (40) with the insulating layer (42) sandwiched therebetween, and electrically connected to the transistor (20).

[0079] [Appendix 2] The semiconductor device (10) according to Appendix 1, wherein the first transistor pad (11) is formed across a portion located above the transistor (20) and a portion located above the temperature-sensitive diode (40).

[0080] [Appendix 3] The semiconductor device (10) according to appendix 1 or appendix 2, wherein the first transistor pad (11) covers the entire temperature-sensitive diode (40) when viewed in the thickness direction of the semiconductor substrate (30).

[0081] [Supplementary Note 4] The semiconductor device (10) according to any one of Supplementary Notes 1 to 3, comprising, when viewed in a thickness direction of the semiconductor substrate (30), an active region (A) located in a central portion of the semiconductor substrate (30) and in which the transistor (20) or the temperature-sensitive diode (40) is formed, and a peripheral region (B) located on the outer periphery of the semiconductor substrate (30) and surrounding the active region (A), wherein the first transistor pad (11) is formed in the active region (A), and the diode pad (13) is formed in the peripheral region (B).

[0082] [Supplementary Note 5] The semiconductor device (10) according to Supplementary Note 4, wherein the active region (A) includes a diode region (A1) in which the temperature-sensitive diode (40) is formed, and a transistor region (A2) in which the transistor (20) is formed and surrounding the diode region (A1), and the buried wiring (46) passes through the transistor region (A2) and is connected to the diode pad (13).

[0083] [Appendix 6] The semiconductor device (10) according to any one of Appendices 1 to 4, wherein the temperature-sensitive diode (40) includes a polysilicon layer (43) formed between the substrate upper surface (30s) of the semiconductor substrate (30) and the insulating layer (42), the polysilicon layer (43) includes, when viewed in the thickness direction of the semiconductor substrate (30), an anode region (44P) into which a p-type impurity has been introduced and a cathode region (45P) into which an n-type impurity has been introduced, the diode pad (13) includes an anode pad (13A) and a cathode pad (13B), and the embedded wiring (46) includes: an anode wiring (46A) connecting the anode region (44P) and the anode pad (13A), and a cathode wiring (46B) connecting the cathode region (45P) and the cathode pad (13B).

[0084] [Appendix 7] The semiconductor device (10) according to any one of Appendices 1 to 6, wherein the insulating layer (42) includes an insulating layer upper surface (42A) located above the temperature sensitive diode (40) and an insulating layer side surface (42B) connected to the insulating layer upper surface (42A), and at least a part of the outer periphery of the insulating layer upper surface (42A) is inclined so that the thickness of the insulating layer (42) gradually decreases toward the insulating layer side surface (42B).

[0085] [Appendix 8] The semiconductor device (10) according to any one of Appendices 1 to 7, wherein the insulating layer (39) includes a portion formed on the transistor (20), and includes: a second transistor pad (12) provided at a position spaced apart from the transistor (20) when viewed in the thickness direction of the semiconductor substrate (30); and a transistor buried wiring (52) buried in the insulating layer (39) and used to connect the transistor (20) and the second transistor pad (12).

[0086] [Appendix 9] The semiconductor device (10) according to any one of appendices 1 to 8, including a plate-shaped conductive member (50) connected to the first transistor pad (11) via an adhesive layer (51).

[0087] [Supplementary Note 10] The semiconductor device (10) according to Supplementary Note 9, wherein the conductive member (50) is connected to a portion of the first transistor pad (11) formed above the temperature sensitive diode (40).

[0088] [Supplementary Note 11] The semiconductor device (10) according to Supplementary Note 9, wherein the conductive member (50) is connected to a portion of the first transistor pad (11) formed on the buried wiring (46).

[0089] [Supplementary Note 12] The semiconductor device (10) according to any one of Supplementary Notes 1 to 11, wherein the first transistor pad (11) includes a portion located above the buried wiring (46).

[0090] A...active region A1...diode region A2...transistor region B...peripheral region D1...distance D2...distance T...thickness W1, W2...width 10...semiconductor device 10a-10d...side surface of device 10s...upper surface of device 10r...rear surface of device 11...first transistor pad 11B...emitter electrode 12...second transistor pad 13...diode pad 13A...anode pad 13B...cathode pad 13Br...lower surface 14...protective insulating film 14A...opening 20...transistor 21A...emitter trench 23A...gate trench 27...collector electrode 30...semiconductor substrate 30s...substrate upper surface 30r...substrate lower surface 31...collector layer 32...buffer layer 33...drift layer 34...base region 35...trench 36...emitter region 37...base contact region 38...First insulating layer 39...Second insulating layer 39a...Contact hole 40...Temperature sensitive diode 41...Third insulating layer 41s...Top surface 42...Fourth insulating layer 42A...Top surface of insulating layer 42B...Side surface of insulating layer 43...Polysilicon layer 44P...First semiconductor region 45P...Second semiconductor region 46...Buried wiring 46A...Anode wiring 46B...Cathode wiring 50, 50A, 50B...Conductive member 51...Adhesive layer 52...Buried wiring for transistor

Claims

1. A semiconductor device comprising: a semiconductor substrate having a top surface and a bottom surface facing opposite to the top surface; a transistor formed on the top surface of the semiconductor substrate; a temperature sensing diode formed on the top surface of the semiconductor substrate; an insulating layer formed on the temperature sensing diode; a diode pad provided at a position spaced apart from the temperature sensing diode when viewed in the thickness direction of the semiconductor substrate; embedded wiring embedded in the insulating layer and used to connect the temperature sensing diode and the diode pad; and a first transistor pad including a portion formed on the temperature sensing diode across the insulating layer and electrically connected to the transistor.

2. The semiconductor device according to claim 1, wherein the first transistor pad is formed across a portion located above the transistor and a portion located above the temperature sensitive diode.

3. The semiconductor device according to claim 1 or 2, wherein the first transistor pad covers the entirety of the temperature sensing diode when viewed in the thickness direction of the semiconductor substrate.

4. A semiconductor device as claimed in any one of claims 1 to 3, comprising, when viewed in a thickness direction of the semiconductor substrate, an active region located in a central portion of the semiconductor substrate and in which the transistor or the temperature sensitive diode is formed, and a peripheral region located on the outer periphery of the semiconductor substrate and surrounding the active region, wherein the first transistor pad is formed in the active region, and the diode pad is formed in the peripheral region.

5. The semiconductor device according to claim 4, wherein the active region includes a diode region in which the temperature sensitive diode is formed, and a transistor region in which the transistor is formed and surrounding the diode region, and the buried wiring is connected to the diode pad through the transistor region.

6. The semiconductor device according to any one of claims 1 to 4, wherein the temperature sensitive diode includes a polysilicon layer formed between the upper surface of the semiconductor substrate and the insulating layer, the polysilicon layer includes, when viewed in the thickness direction of the semiconductor substrate, an anode region into which a p-type impurity has been introduced and a cathode region into which an n-type impurity has been introduced, the diode pad includes an anode pad and a cathode pad, and the embedded wiring includes an anode wiring connecting the anode region and the anode pad, and a cathode wiring connecting the cathode region and the cathode pad.

7. A semiconductor device as claimed in any one of claims 1 to 6, wherein the insulating layer includes an insulating layer upper surface located above the temperature sensitive diode and an insulating layer side surface connected to the insulating layer upper surface, and at least a portion of the outer periphery of the insulating layer upper surface is inclined so that the thickness of the insulating layer gradually decreases towards the insulating layer side surface.

8. A semiconductor device according to any one of claims 1 to 7, wherein the insulating layer includes a portion formed on the transistor, a second transistor pad provided at a position spaced apart from the transistor when viewed in the thickness direction of the semiconductor substrate, and a transistor buried wiring buried in the insulating layer and used to connect the transistor and the second transistor pad.

9. The semiconductor device according to claim 1, further comprising a plate-shaped conductive member connected to the first transistor pad via an adhesive layer.

10. The semiconductor device according to claim 9, wherein the conductive member is connected to a portion of the first transistor pad formed above the temperature sensitive diode.

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