Circuit board and semiconductor package

Abstract

This circuit board comprises: a first insulating layer having cavities; a second insulating layer disposed below the first insulating layer; and a third insulating layer disposed between the first insulating layer and the second insulating layer, wherein the light absorption rate of the third insulating layer is lower than that of the first insulating layer.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, electronic product technology has been moving toward multifunctionality and high-speed operation, and to respond to this trend, semiconductor chip manufacturing technology is also developing at a rapid pace.

[0004] In particular, the thickness of circuit boards applied for miniaturization of finished electronic products is also decreasing, and technologies related to multilayer circuit boards that configure more circuit layers within a circuit board of the same thickness are being actively researched.

[0005] Typically, a multilayer circuit board can be formed by laminating a plurality of prepregs (insulators) formed by impregnating glass fibers with epoxy resin, and circuit boards including copper (Cu) circuits formed on the surface thereof.

[0006] In a multilayer circuit board, there are cases where separate components, such as memory chips, are connected to specific areas. In such cases, in order to reduce the thickness of the entire circuit board, a cavity (concave portion) is formed in the area and the components are placed inside the cavity.

[0007] Typically, cavities are formed using a laser drilling process after the outermost substrate layer has been formed. To control the cutting depth of the substrate, copper foil is placed as a stopper on the substrate layer at a predetermined depth to reflect laser light. Accordingly, after the cavity is formed by laser drilling, the copper foil is removed during the process of forming the connection circuit within the cavity.

[0008] However, due to various causes such as processing errors, the copper foil that acts as a stopper remains around the cavity after the cavity is formed, and the residual area of ​​the stopper has the problem of becoming a factor that hinders the freedom of design and signal connection within the circuit in the semiconductor field that requires miniaturization and high integration.

[0009]

[0010] The present invention provides a circuit board and semiconductor package capable of precisely controlling the dimensions of a cavity according to design dimensions, easily controlling the roughness of a cavity surface, and improving production efficiency according to the convenience of processing the cavity.

[0011]

[0012] A circuit board according to the present embodiment includes a first insulating layer in which a cavity is formed; a second insulating layer disposed under the first insulating layer; and a third insulating layer disposed between the first insulating layer and the second insulating layer, wherein the light absorption rate of the third insulating layer is lower than the light absorption rate of the first insulating layer.

[0013] The third insulating layer includes a filler dispersed in the resin, and the material of the filler may be strontium titanate (SrTiO3).

[0014] The third insulating layer may include glass fibers dispersed within the resin.

[0015] The upper surface of the third insulating layer can form the bottom surface of the cavity.

[0016] It may include a copper foil disposed on the surface of the third insulating layer.

[0017] It may include a first circuit pattern disposed on an upper portion of the first insulating layer; a second circuit pattern buried in a lower portion of the first insulating layer; a third circuit pattern buried in a lower portion of the third insulating layer; a fourth circuit pattern disposed on a lower portion of the second insulating layer; a first via penetrating the first insulating layer and connecting the first circuit pattern and the second circuit pattern; a second via penetrating the third insulating layer and connecting the second circuit pattern and the third circuit pattern; and a third via penetrating the second insulating layer and connecting the third circuit pattern and the fourth circuit pattern.

[0018] The above cavity can be formed by laser processing.

[0019] The surface of the upper surface of the third insulating layer forming the bottom surface of the cavity and the surface covered by the first insulating layer may be stepped in the vertical direction.

[0020] A semiconductor package according to the present embodiment includes: a first insulating layer in which a cavity is formed; an electronic device disposed within the cavity; a second insulating layer disposed under the first insulating layer; and a third insulating layer disposed between the first insulating layer and the second insulating layer, wherein the light absorption rate of the third insulating layer is lower than the light absorption rate of the first insulating layer.

[0021]

[0022] In this embodiment, in the process of forming a cavity using a laser, a cavity can be formed with a thickness equal to the thickness of the first insulating layer without a separate stopper or other means due to the difference in light absorption between the first insulating layer in which the cavity is formed and the third insulating layer in which the cavity is not formed, thereby making the cavity forming process simpler and having the advantage of forming a cavity with more precise dimensions.

[0023] In addition, due to the material properties of the third insulating layer, there is an advantage in that the surface roughness of the third insulating layer forming the bottom surface of the cavity can be more uniformly controlled.

[0024]

[0025] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0026] Figure 2 is a cross-sectional view of a third insulating layer according to an embodiment of the present invention.

[0027] Figure 3 is an enlarged view of the structure within the third insulating layer according to an embodiment of the present invention.

[0028] Figure 4 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0029] Fig. 5 is a cross-sectional view showing a modified example of the third insulating layer according to an embodiment of the present invention.

[0030] Figure 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0031]

[0032] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0033] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0034] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0035] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0036] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0037] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0038] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0039] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0040] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a third insulating layer according to an embodiment of the present invention, FIG. 3 is an enlarged view of a structure within the third insulating layer according to an embodiment of the present invention, FIG. 4 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 5 is a cross-sectional view showing a modified example of the third insulating layer according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0041] Referring to FIGS. 1 to 6, a circuit board (10) according to an embodiment of the present invention may include a first insulating layer (110), a second insulating layer (120), a third insulating layer (130), circuit patterns (141, 142, 143, 144), and vias (151, 152, 153).

[0042] Based on the third insulating layer (130), the first insulating layer (110) may be arranged on one surface of the third insulating layer (130), and the second insulating layer (120) may be arranged on the other surface facing the one surface of the third insulating layer (130).

[0043] The first insulating layer (110) may be arranged on the upper surface of the third insulating layer (130). The first insulating layer (110) may be a single layer or multiple layers. The first insulating layer (110) may be a substrate on which an electric circuit capable of changing wiring is formed, and may include a print, wiring board, and insulating substrate made of an insulating material capable of forming circuit patterns on the surface.

[0044] The first insulating layer (110) may include glass or plastic. The first insulating layer (110) may include chemically strengthened / semi-strengthened glass such as sodalime glass or aluminosilicate glass, or may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

[0045] A plurality of circuit patterns may be arranged on the surface of the first insulating layer (110). A first circuit pattern (141) may be arranged on the upper surface of the first insulating layer (110). A second circuit pattern (142) may be arranged under the first insulating layer (110). The second circuit pattern (142) may be embedded in the lower portion of the first insulating layer (110).

[0046] A first via (151) may be formed within the first insulating layer (110). The first via (151) may electrically connect the first circuit pattern (141) and the second circuit pattern (142). The first via (151) may be formed by filling the inside of a hole penetrating the first insulating layer (110) with a conductive material.

[0047] A cavity (160) in which an electric element (180, see FIG. 6) is placed may be formed in the first insulating layer (110). The cavity (160) may include a through hole (117) extending from the upper surface to the lower surface of the first insulating layer (110).

[0048] The vertical length of the cavity (160) may correspond to the vertical height of the electric element (180), or may be formed to be smaller or longer than it. The vertical length of the cavity (160) may correspond to the thickness of the first insulating layer (110). Alternatively, the vertical length of the cavity (160) may be longer than the thickness of the first insulating layer (110). In this case, the formation area of ​​the cavity (160) on the upper surface of the third insulating layer (130), which will be described later, may be arranged to be lower than other areas of the upper surface of the third insulating layer (130).

[0049] The first insulating layer (110) is formed of any insulator, such as a photocurable and / or thermosetting insulator. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a prepreg (PPG) including glass fibers in a resin can be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic filler may be formed of a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material formed of glass fibers or aramid fibers can be included.

[0050] The above cavity (160) can be formed by a laser processing method. The laser processing can be a UV or CO2 laser method.

[0051] The second insulating layer (120) may be arranged on the lower surface of the third insulating layer (130). The second insulating layer (120) may be a single layer or multiple layers. The second insulating layer (120) is a substrate on which an electric circuit capable of changing wiring is formed, and may include a print, wiring board, and insulating substrate made of an insulating material capable of forming circuit patterns on the surface.

[0052] The second insulating layer (120) is provided with any insulator such as photocurable and / or thermosetting. As the thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a prepreg (PPG) including glass fibers in a resin can be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic filler may be provided with a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material such as glass fiber or aramid fiber can be included.

[0053] A plurality of circuit patterns may be arranged on the surface of the second insulating layer (120). A third circuit pattern (143) may be arranged on the upper surface of the second insulating layer (120). A fourth circuit pattern (144) may be arranged on the lower surface of the second insulating layer (120).

[0054] A third via (153) may be formed within the second insulating layer (120). The third via (153) may electrically connect the third circuit pattern (143) and the fourth circuit pattern (144). The third via (153) may be formed by filling the inside of a hole penetrating the second insulating layer (120) with a conductive material.

[0055] The third insulating layer (130) may be disposed between the first insulating layer (110) and the second insulating layer (120). A portion of the upper surface of the third insulating layer (130) may form the bottom surface of the cavity (160). Another portion of the upper surface of the third insulating layer (130) may be covered by the lower surface of the first insulating layer (110).

[0056] A plurality of circuit patterns may be arranged on the surface of the third insulating layer (130). A second circuit pattern (142) may be arranged on the upper surface of the third insulating layer (130). A third circuit pattern (143) may be arranged under the third insulating layer (130). The third circuit pattern (143) may be embedded in the lower portion of the third insulating layer (130).

[0057] A second via (152) may be formed within the third insulating layer (130). The second via (152) may electrically connect the second circuit pattern (142) and the third circuit pattern (143). The second via (152) may be formed by filling the inside of a hole penetrating the third insulating layer (130) with a conductive material.

[0058] A through hole (137) may be formed in the formation region of the cavity (160) on the upper surface of the third insulating layer (130). In this case, the through hole formed in the first insulating layer (110) may be named a first through hole (117), and the through hole formed on the surface of the third insulating layer (130) may be named a second through hole (137). The second through hole (137) may have a groove shape that is formed to be lower than other regions on the surface of the third insulating layer (130). The second through hole (137) may vertically overlap the first through hole (117). The horizontal width of the second through hole (137) may be smaller than the horizontal width of the first through hole (117). The vertical length of the second through hole (137) may be shorter than the vertical length of the first through hole (117). The vertical length of the second through hole (137) may be shorter than the vertical length of the third insulating layer (130).

[0059] The second through hole (137) may form a part of the cavity (160). That is, the cavity (160) may be understood to include a first through hole (117) formed in the first insulating layer (110) and a second through hole (137) formed in the third insulating layer (130).

[0060] A portion of the upper surface of the third insulating layer (130) may be exposed above the first insulating layer (110) through the through hole (117) of the first insulating layer (110). The light absorption rate of the material constituting the third insulating layer (130) may be different from the light absorption rate of the material constituting the first insulating layer (110). The light absorption rate of the third insulating layer (130) may be lower than the light absorption rate of the first insulating layer (110). Accordingly, in the process of forming the cavity (160), the third insulating layer (130) may function as a stopper due to the difference in light absorption rates between the first insulating layer (110) and the third insulating layer (130).

[0061] Specifically, when a laser is irradiated downward from the upper region of the first insulating layer (110) to form a cavity, a cavity (160) may be formed by the laser in a set region within the first insulating layer (110). After the thickness of the cavity (160) is formed in the set region of the first insulating layer (110) to the same thickness as the first insulating layer (110), the laser may be provided to the surface of the third insulating layer (130). In this case, as described above, most of the laser provided to the third insulating layer (130) may be reflected from the surface of the third insulating layer (130) due to the low light absorption rate of the third insulating layer (130). Accordingly, the surface of the third insulating layer (130) can be minimized from damage by the laser, so that the third insulating layer (130) can function as a stopper behind the first insulating layer (110) within the circuit board (10). As illustrated in FIGS. 2 to 4, the third insulating layer (130) may be a resin for a semiconductor package. The third insulating layer (130) may include a resin (132), glass fiber (134), and a filler (136). The third insulating layer (130) may include glass fiber (134) and filler (136) dispersed within the resin (132). The third insulating layer (130) may be a prepreg in which the glass fiber (134) and filler (136) are dispersed within the resin (132).

[0062] In order for the light absorption rate of the third insulating layer (130) to be formed lower than that of the first insulating layer (110), the filler (136) may be a material having low light absorption rate. For example, the material of the filler (136) may be strontium titanate (SrTiO3). Here, the strontium titanate (SrTiO3) is a material having high light reflectivity, and the strontium titanate (SrTiO3) dispersed within the third insulating layer (130) may have the function of reflecting light irradiated into the third insulating layer (130) from the surface of the third insulating layer (130) and emitting it to the outside.

[0063] Accordingly, since the light absorption rate of the third insulating layer (130) decreases due to the material properties of the filler (136), the laser irradiated during the formation of the cavity (160) may be reflected from the surface of the third insulating layer (130). Accordingly, the height of the cavity (160) may be formed as much as the thickness of the first insulating layer (110).

[0064] A copper foil (148) for forming a circuit pattern may be placed on the upper surface of the third insulating layer (130) forming the bottom surface of the cavity (160).

[0065] As illustrated in FIGS. 3 and 4, the third insulating layer (130) may include a first layer (130A), a second layer (130B), and a third layer (130C). The third layer (130A) may be disposed between the first layer (130A) and the second layer (130B).

[0066] The first layer (130A) may form the upper portion of the third insulating layer (130). The first layer (130A) may include a resin (132) and a filler (136) dispersed within the resin (132).

[0067] The second layer (130B) may form the lower portion of the third insulating layer (130). The second layer (130B) may include a resin (132) and a filler (136) dispersed within the resin (132).

[0068] The third layer (130C) may be positioned between the first layer (130A) and the second layer (130B). The third layer (130C) may include a resin (132), and glass fibers (134) and fillers (136) dispersed within the resin (132).

[0069] The thickness (t3) of the third layer (130C) may be smaller than the thickness (t1) of the first layer (130A) or the thickness (t2) of the second layer (130B). For example, the thickness (t3) of the third layer (130C) may be less than half the thickness (t1) of the first layer (130A) or the thickness (t2) of the second layer (130B).

[0070] The thickness (T1) of the first layer (130A) may be 5 um or more.

[0071] As illustrated in Fig. 4, pores (A1, A2) may be formed in each of the first to third layers (130A, 130B, 130C). The pores (A1, A2) may be arranged in a horizontal direction perpendicular to the vertical direction in each of the first to third layers (130A, 130B, 130C). The size of the pores (A2) formed in the third layer (130C) may be smaller than the size of the pores (A1) formed in the first layer (130A) or the second layer (130B).

[0072] The thickness (t1) of the first layer (130A) may be greater than the thickness (t2) of the second layer (130B). This is in consideration of the fact that the cavity (160) is formed on the surface of the first layer (130A). Accordingly, when the electric element (180) is placed within the cavity (160), a stress-dispersing structure can be implemented through the first layer (130A).

[0073] In contrast, the thickness (t1) of the first layer (130A) may be equal to or less than the thickness (t2) of the second layer (130B).

[0074] Meanwhile, as in the modified example illustrated in FIG. 5, the glass fiber (134) within the third insulating layer (130) may be omitted. In this case, the third insulating layer (130) may only include a filler (136) dispersed within the resin (132). Accordingly, there is an advantage in that the glass fiber (134) may be omitted while maintaining the material properties of low light absorption within the third insulating layer (130).

[0075] Referring to FIG. 6, a semiconductor package (20) according to an embodiment of the present invention may include a circuit board (10) and an electronic component (180) mounted within a cavity (160) of the circuit board (10). A pad (170) for electrical connection of the electronic component (180) may be placed within the cavity (160). The pad (170) may be placed on the surface of the third insulating layer (130).

[0076] The above electronic component (180) may include an active component or a passive component, and thus may include a transistor, an IC semiconductor chip, a capacitor, a resistor, an inductor, and the like.

[0077] The semiconductor package (20) is placed within the cavity (160) and may further include a molding layer (not shown) covering the electronic component (180).

[0078] According to the structure as described above, in the process of forming a cavity using a laser, due to the difference in light absorption between the first insulating layer in which a cavity is formed and the third insulating layer in which a cavity is not formed, a cavity can be formed with the thickness of the first insulating layer without a separate means such as a stopper, so that the cavity forming process is simpler and at the same time, there is an advantage in that a cavity can be formed with more precise dimensions.

[0079] In addition, due to the material properties of the third insulating layer, there is an advantage in that the surface roughness of the third insulating layer forming the bottom surface of the cavity can be more uniformly controlled.

[0080] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0081] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A first insulating layer in which a cavity is formed; A second insulating layer disposed below the first insulating layer; and Including a third insulating layer disposed between the first insulating layer and the second insulating layer, A circuit board wherein the light absorption rate of the third insulating layer is lower than that of the first insulating layer.

2. In paragraph 1, The third insulating layer comprises a filler dispersed in the resin, A circuit board in which the material of the above filler is strontium titanate (SrTiO3).

3. In paragraph 2, A circuit board in which the third insulating layer includes glass fibers dispersed within the resin.

4. In paragraph 1, A circuit board in which the upper surface of the third insulating layer forms the bottom surface of the cavity.

5. In paragraph 4, A circuit board including copper foil arranged on the surface of the third insulating layer.

6. In paragraph 4, A circuit board including a pad arranged on the surface of the third insulating layer.

7. In paragraph 1, A first circuit pattern arranged on the upper part of the first insulating layer; A second circuit pattern embedded in the lower portion of the first insulating layer; A third circuit pattern embedded in the lower part of the third insulating layer; A fourth circuit pattern arranged below the second insulating layer; A first via penetrating the first insulating layer and connecting the first circuit pattern and the second circuit pattern; A second via penetrating the third insulating layer and connecting the second circuit pattern and the third circuit pattern; and A circuit board including a third via penetrating the second insulating layer and connecting the third circuit pattern and the fourth circuit pattern.

8. In paragraph 1, The above cavity is a circuit board formed by laser processing.

9. In paragraph 1, A circuit board in which the upper surface of the third insulating layer, which forms the bottom surface of the cavity, and the surface covered by the first insulating layer are stepped in the vertical direction.

10. First insulating layer in which a cavity is formed; Electronic components arranged within the cavity; A second insulating layer disposed below the first insulating layer; and Including a third insulating layer disposed between the first insulating layer and the second insulating layer, A semiconductor package wherein the light absorption rate of the third insulating layer is lower than that of the first insulating layer.

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