Connecting structure and manufacturing method therefor

Abstract

The present invention relates to a connecting structure included in a semiconductor package, the connecting structure comprising: an etch stop layer having a plurality of openings; a first wiring layer disposed on one surface of the etch stop layer; a conductive layer disposed on the first wiring layer; and a plurality of connection members electrically connected to the first wiring layer by means of a conductive metal material injected into the plurality of openings.

Description

Connecting structure and manufacturing method thereof

[0001] The present invention relates to a semiconductor package, and more specifically, to a connecting structure that electrically connects between a substrate and a semiconductor chip or between semiconductor chips, and a method for manufacturing the same.

[0002] A semiconductor chip is an integrated circuit made of semiconductors whose electrical conductivity is higher than that of insulators but lower than that of conductors.

[0003] Typically, semiconductor chips undergo some form of packaging after being separated from a single-crystal substrate, called a wafer. This process protects the chip from physical impact and mitigates the integration gap between the chip and the substrate on which it will be mounted, thereby increasing ease of mounting. The resulting packaged semiconductor chip is called a semiconductor package.

[0004] A semiconductor package such as this can house multiple semiconductor chips, and can be classified as 2D / 2.5D / 3D, etc., depending on the arrangement of the mounted semiconductor chips. Among these, a 2.5D semiconductor package refers to a package in which logic chips are arranged horizontally and memory chips are stacked vertically.

[0005] In addition, in a 2.5D semiconductor package, an interposer or bridge die may be provided between the substrate and the semiconductor chip (i.e., die) to increase the connection rate between the substrate and the semiconductor chip. In this case, the semiconductor chip is electrically connected to the substrate through the interposer or bridge die.

[0006] However, conventional interposers or bridge dies are relatively expensive to manufacture and have high manufacturing process complexity. Therefore, a method to address these issues is needed.

[0007] The present invention aims to solve the aforementioned problems and other problems. Another object is to provide a connecting structure with improved power supply and signal transmission characteristics and a method for manufacturing the same.

[0008] Another purpose is to provide a connecting structure and a method for manufacturing the same that can simplify the manufacturing process.

[0009] Another purpose is to provide a connecting structure and a method for manufacturing the same that can reduce manufacturing costs.

[0010] According to one aspect of the present invention to achieve the above or other purposes, a connecting structure is provided, which includes: an etching stop layer having a plurality of openings; a first wiring layer disposed on one surface of the etching stop layer; a conductive layer disposed on the first wiring layer; and a plurality of connecting members electrically connected to the first wiring layer through a conductive metal material injected into the plurality of openings.

[0011] According to another aspect of the present invention, a method for manufacturing a connecting structure is provided, comprising: forming an etch stop layer on a substrate; forming a first wiring layer on one surface of the etch stop layer; forming a plurality of fillers on the first wiring layer; forming a molding member on the first wiring layer and the plurality of fillers; removing the substrate; forming a plurality of openings in the etch stop layer; injecting a conductive metal material into the plurality of openings and forming a plurality of connecting members electrically connected to the first wiring layer through the conductive metal material; and forming a conductive layer by removing a portion of the molding member so that the plurality of fillers are exposed to the outside.

[0012] According to another aspect of the present invention, a method for manufacturing a connecting structure is provided, comprising: forming an etch stop layer on a first substrate; forming a first wiring layer on one surface of the etch stop layer; forming a conductive layer on the first wiring layer; arranging a second substrate on the conductive layer; removing the first substrate; forming a plurality of openings in the etch stop layer; injecting a conductive metal material into the plurality of openings and forming a plurality of connecting members electrically connected to the first wiring layer through the conductive metal material; and removing the second substrate.

[0013] The effects of the connecting structure and the manufacturing method thereof according to embodiments of the present invention are described as follows.

[0014] According to at least one of the embodiments of the present invention, the manufacturing process can be simplified and the manufacturing cost can be reduced because there is no need to perform an expensive TSV (Through Silicon Via) process.

[0015] In addition, according to at least one of the embodiments of the present invention, by using an etch stop layer for the purpose of protecting a wiring layer during substrate etching, a polishing process for the substrate can be omitted, thereby simplifying the manufacturing process.

[0016] In addition, according to at least one of the embodiments of the present invention, power supply characteristics and signal transmission characteristics can be improved by enabling vertical and horizontal current transmission through the wiring layer and the conductive layer.

[0017] The technical effects achieved through the present invention are not limited to the technical effects mentioned above, and other technical effects not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the present invention pertains from the description below.

[0018] FIG. 1 is a drawing showing the structure of a semiconductor package according to one embodiment of the present invention;

[0019] FIG. 2 is a drawing showing the structure of a connecting structure according to one embodiment of the present invention;

[0020] FIG. 3 is a flowchart showing a method for manufacturing a connecting structure according to a first embodiment of the present invention;

[0021] FIGS. 4A to 4J are drawings for reference to explain a method for manufacturing a connecting structure according to a first embodiment of the present invention;

[0022] FIG. 5 is a flowchart showing a method for manufacturing a connecting structure according to a second embodiment of the present invention;

[0023] FIGS. 6A to 6L are drawings for reference to explain a method for manufacturing a connecting structure according to a second embodiment of the present invention.

[0024] Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers and redundant descriptions thereof will be omitted. Hereinafter, in the description of embodiments according to the present invention, when each layer (film), region, pattern or structure is described as being formed "on" or "under" the substrate, each layer (film), region, pad or pattern, "on" and "under" include both "directly" and "indirectly" forming the structure. In addition, the reference for above / above or below / under each layer will be described based on the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not entirely reflect the actual size. The same drawing numbers indicate the same components.

[0025] In this specification, when a component (or region, layer, part, etc.) is said to be "on," "connected to," or "coupled to" another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them. In addition, in this specification, it should be understood that terms such as "comprise" or "have" are intended to specify that a feature, number, step, operation, component, part, or combination thereof described in the specification is present, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0026] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0027] In addition, when describing the embodiments disclosed in this specification, if it is determined that a detailed description of a related known technology may obscure the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included within the spirit and technical scope of the present invention.

[0028] The present invention proposes a connecting structure with improved power integrity (PI) and signal transmission characteristics (SI), and a manufacturing method thereof. Furthermore, the present invention proposes a connecting structure and a manufacturing method thereof that can simplify the manufacturing process. Furthermore, the present invention proposes a connecting structure and a manufacturing method thereof that can reduce manufacturing costs.

[0029]

[0030] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

[0031] FIG. 1 is a drawing showing the structure of a semiconductor package according to one embodiment of the present invention.

[0032] Referring to FIG. 1, a semiconductor package (100) according to one embodiment of the present invention may include a substrate (110), a conductive structure (120), a connecting structure (130), a molding member (140), a semiconductor chip (150), and an external connection member (160). The components illustrated in FIG. 1 are not essential for implementing a semiconductor package, and thus, the semiconductor package described herein may have more or fewer components than the components listed above.

[0033] The substrate (110) can perform the role of mounting various electronic components. The substrate (110) may be a printed circuit board (PCB), a flexible-PCB substrate, an IC substrate, etc., but is not necessarily limited thereto. In the following embodiment, the use of a PCB substrate as the substrate (110) will be described as an example.

[0034] The printed circuit board (110) may be formed as an organic PCB. Electronic components such as integrated circuits, resistors, or switches may be mounted on the printed circuit board (110).

[0035] The printed circuit board (110) may include a wiring circuit for electrical connection between electronic components. In addition, one or more passive components may be mounted on the upper surface and / or lower surface of the printed circuit board (110).

[0036] Meanwhile, although not shown in the drawing, an integrated passive device (IPD) may be built into the printed circuit board (110). In addition, the printed circuit board (110) may have a cavity structure for mounting a connecting structure (130). At this time, the depth of the cavity structure may be formed to be 50 um to 200 um. The connecting structure may be mounted on the conductive layer of the printed circuit board (110) provided at the lower portion of the cavity structure and may be electrically connected. The upper portion of the conductive layer of the connecting structure mounted on the cavity structure may be exposed to the outside and directly connected to the semiconductor chip without a separate additional circuit layer or redistribution layer.

[0037] The conductive structure (120) may be placed on one surface of the substrate (110). For example, a plurality of conductive structures (120) may be formed on the substrate (110).

[0038] The conductive structure (120) may be formed to extend vertically from the upper surface of the substrate (110). At this time, the conductive structure (120) may be formed to have a constant width of cross-sectional area or may be formed to have a width of cross-sectional area that gradually increases in the upward direction.

[0039] The conductive structure (120) may be formed to have a constant height. In addition, the upper portion of the conductive structure (120) may be formed by a grinding process. The conductive structure (120) may be formed on the substrate (110) to have a diameter of 20 μm to 100 μm, a height of 50 μm to 300 μm, and a pitch of 50 μm to 200 μm.

[0040] The conductive structure (120) may be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al). An insulating material may be coated around the conductive structure (120). The conductive structure (120) may be formed directly on the substrate (110) in the form of a Cu post, a Cu pin, a Cu post block, a vertical wire, or a through mold via (TMV), or may be formed first and then placed on the substrate (110).

[0041] The conductive structure (120) is arranged to be in contact with the wiring circuit of the substrate (110), and can be electrically connected to the substrate (110). In addition, the conductive structure (120) is arranged to be in contact with the semiconductor chip (150), and can be electrically connected to the semiconductor chip (150). Accordingly, the substrate (110) can be electrically connected to the semiconductor chip (150) through the conductive structure (120). In particular, the semiconductor chip (150) can be directly electrically connected to the substrate (110) through the conductive structure (120) without a separate circuit layer or redistribution layer between the conductive structure (120) and the semiconductor chip (150).

[0042] The connecting structure (130) may be placed on one surface of the substrate (110). A single or multiple connecting structures (130) may be provided.

[0043] A connecting structure (130) may be placed between conductive structures (120). The height of the connecting structure (130) may be formed to be equal to or slightly lower than the height of the conductive structure (120).

[0044] The connecting structure (130) may be formed of a silicon wafer, an active die, an IPD, or the like. The connecting structure (130) may be formed to enable electrical connection in a vertical direction and / or a horizontal direction.

[0045] The connecting structure (130) may be mounted on the substrate (110) in a flip-chip structure. After the connecting structure (130) is mounted on the substrate (110), an underfill may be filled.

[0046] The connecting structure (130) can electrically connect a plurality of different semiconductor chips (150). At this time, the connecting structure (130) can electrically connect semiconductor chips of the same type or electrically connect semiconductor chips of different types. To this end, the upper surface of the connecting structure (130) can be formed to contact the plurality of semiconductor chips (150). The connecting structure (130) can be electrically connected to the plurality of semiconductor chips (150) so as to be mutually conductive.

[0047] The connecting structure (130) can electrically connect the substrate (110) and the semiconductor chip (150). To this end, the upper surface of the connecting structure (130) can be formed to contact the semiconductor chip (150), and the lower surface of the connecting structure (130) can be formed to contact the substrate (110).

[0048] A structure can be formed in which electrical connection is directly performed between the lower surface of the semiconductor chip (150) and the upper surface of the connecting structure (130), and between the lower surface of the connecting structure (130) and the upper surface of the substrate (110) without disposing a separate circuit layer or redistribution layer.

[0049] Meanwhile, although not shown in the drawing, an underfill or a molded underfill (MUF) may be filled under the semiconductor chip (150) mounted on the substrate (110) and the connecting structure (130).

[0050] The connecting structure (130) does not need to be installed on the entire upper surface of the substrate (110), but it is sufficient to be installed on at least a portion of the overlapping area between the substrate (110) and the semiconductor chips (150). In the illustrated embodiment, the total area of ​​the connecting structure (130) may be formed to be smaller than the sum of the areas of the semiconductor chips (150) coupled to the connecting structure (130). Accordingly, the installation area of ​​the connecting structure (130) can be further reduced, which has the effect of reducing the manufacturing cost of the connecting structure (130) and the semiconductor package (100).

[0051] In addition, since the installation area of ​​the connecting structure (130) is further reduced, it is advantageous in terms of miniaturization of the connecting structure (130). Accordingly, as the space occupied by the connecting structure (130) is reduced, the entire semiconductor package can be miniaturized in a high-performance semiconductor package.

[0052] A molding member (or insulating member, 140) may be applied to one surface of the substrate (110) to electrically insulate components mounted on the substrate (110).

[0053] The molding member (140) may be formed of an insulating material. For example, the molding member (140) may be formed of a dielectric or polymer material. Examples of the polymer material that may be used include, but are not necessarily limited to, EMC (Epoxy Molding Compound), PI (polyimide), ABF (Ajinomoto Build-up Film), etc.

[0054] A semiconductor chip (150) may be placed on top of a substrate (110). More specifically, the semiconductor chip (150) may be placed on a conductive structure (120) and a connecting structure (130).

[0055] A single or multiple semiconductor chips (150) may be provided. In the present embodiment, a plurality of semiconductor chips (150) have a structure in which they are arranged horizontally or stacked vertically.

[0056] A semiconductor chip (150) may include one or more logic chips and one or more memory chips. Here, one or more logic chips may be arranged in a horizontal direction, and one or more memory chips may be arranged in a vertical direction.

[0057] A chip connection member (not shown) for electrical connection with a conductive structure (120) and / or a connecting structure (130) may be formed on the lower surface of a semiconductor chip (150). The upper portion of the chip connection member may be formed by a grinding process.

[0058] A first connecting member may be arranged between the semiconductor chip (150) and the conductive structure (120), and a second connecting member may be arranged between the semiconductor chip (150) and the connecting structure (130). The first and second connecting members may be formed of a conductive metal material. The first and second connecting members may be formed in the form of bumps. The first and second connecting members are simply passages for electrical connection, such as bumps or fillers, and are different in structure and function from a wiring layer in which a circuit is formed.

[0059] Meanwhile, although not shown in the drawing, a heat dissipation die or an active die may be additionally stacked on the upper side of the semiconductor chip (150). When the active die is stacked on the upper side of the semiconductor chip (150), a conductive connection means for electrical connection between the semiconductor chip (150) and the active die may be additionally configured.

[0060] Additionally, although not shown in the drawing, a thermal interface material (TIM) may be additionally laminated on the upper side of the semiconductor chip (150). At this time, the thermal interface material (TIM) may be disposed between the semiconductor chip (150) and the heat dissipation die (or active die). Alternatively, the thermal interface material (TIM) may be disposed on the upper surface of the heat dissipation die (or active die).

[0061] A thermal interface material (TIM) is placed on top of a semiconductor chip (150) to release heat generated from the semiconductor chip (150) to the outside. To this end, the thermal interface material (TIM) may be formed of a material having high thermal conductivity.

[0062] Through a heat dissipation die and / or a thermal interface material (TIM) placed on the upper side of a semiconductor chip (150), heat generated from the semiconductor chip (150) can be more easily dissipated, and overheating of the semiconductor chip (150) can be prevented. Furthermore, damage to the semiconductor package (100) due to overheating can be prevented, and maintenance costs incurred when the semiconductor package is damaged can also be reduced.

[0063] Furthermore, as illustrated in the drawing, since multiple semiconductor chips are individually controlled and mounted, structures and processes for surrounding the semiconductor chips with molding layers and other insulating materials are not necessarily required, simplifying the overall process and reducing costs. Furthermore, additional processes, described below, become possible, increasing process freedom. Furthermore, because semiconductor chips are individually handled, package warpage control is significantly facilitated.

[0064] An external connection member (160) may be attached to the lower surface of the substrate (110) and may serve to electrically connect the substrate (110) and an external member (not shown). The external connection member (160) may be formed in the shape of a solder ball or a metal ball.

[0065] A semiconductor package (100) having such components can protect one or more semiconductor chips (150) from physical impact and increase mounting convenience by reducing the integration difference with respect to a substrate on which the semiconductor chip (150) is to be mounted. In addition, the semiconductor package (100) can not only realize miniaturization of the semiconductor package by arranging a plurality of conductive structures (120) and connecting structures (130) between the substrate (110) and the semiconductor chip (150), but also simplify the manufacturing process of the semiconductor package, thereby reducing manufacturing costs.

[0066]

[0067] FIG. 2 is a drawing showing the structure of a connecting structure according to one embodiment of the present invention.

[0068] Referring to FIG. 2, a connecting structure (130, 200) according to one embodiment of the present invention may include an etch stop layer (210), a first wiring layer (220), a conductive layer (230), a second wiring layer (240), a UBM layer (250), and a connecting member (260). The components illustrated in FIG. 2 are not essential for implementing the connecting structure, and thus, the connecting structure described herein may have more or fewer components than the components listed above.

[0069] An etch stop layer (210) may be disposed between a first wiring layer (220) and a second wiring layer (240). A plurality of openings may be formed in the etch stop layer (210). Through a conductive metal material injected into the plurality of openings, the first wiring layer (220) and the second wiring layer (240) may be electrically connected.

[0070] The etching stop layer (210) may serve to protect the first wiring layer (220) from an etchant (or etching solution) during an etching process on the substrate. The etching stop layer (210) may be formed of a dielectric material that does not chemically react with the substrate etchant. For example, the etching stop layer (210) may be formed of an oxide or a nitride, but is not necessarily limited thereto.

[0071] A first wiring layer (220) may be disposed on one surface of an etching stop layer (210). The first wiring layer (220) may include a first wiring circuit (221) and a first insulating material (223) coated on the first wiring circuit (221).

[0072] The first wiring circuit (221) may be configured with a higher density than the wiring circuit of the substrate (110). The line / space of the first wiring circuit (221) may be formed to be 2um / 2um or less.

[0073] The first insulating material (223) may be formed of a dielectric or polymer material. Examples of the polymer material include EMC, PI, ABF, etc., but are not necessarily limited thereto.

[0074] The conductive layer (230) may be disposed on the first wiring layer (220). The conductive layer (230) may include a plurality of fillers (231) spaced apart from each other and a molding member (233) coated between the plurality of fillers (231).

[0075] The filler (231) may be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al). The filler (231) may be placed in contact with the semiconductor chip (150) and may be electrically connected to the semiconductor chip (150).

[0076] The filler (231) may be formed to have a constant height. In addition, the filler (231) may be formed to have a constant width of cross-sectional area or may be formed to have a width of cross-sectional area that gradually increases in the upward direction.

[0077] The height of the filler (231) may be formed to be smaller than the height of the conductive structure (120). In addition, the diameter of the filler (231) may be formed to be smaller than the diameter of the conductive structure (120). In addition, the spacing between the fillers (231) may be formed to be narrower than the spacing between the conductive structures (120). The filler (231) may be formed on the connecting structure (130) to have a diameter of 5 μm to 100 μm, a height of 10 μm to 50 μm, and a pitch of 10 μm to 150 μm.

[0078] A molding member (233) may be placed between a plurality of fillers (231). The height of the molding member (233) may be formed to be equal to or slightly higher than the height of the filler (231).

[0079] The molding member (233) may be formed of a dielectric or polymer material. Examples of the polymer material include EMC, PI, ABF, etc., but are not necessarily limited thereto.

[0080] The second wiring layer (240) may be placed on the other surface of the etching stop layer (210). This is because it is difficult to directly attach the connecting member (260) to the other surface of the etching stop layer (210).

[0081] The second wiring layer (240) may include a second wiring circuit (241) and a second insulating material (243) coated on the second wiring circuit (241).

[0082] The second wiring circuit (241) may be configured with a higher density than the wiring circuit of the substrate (110). The line / space of the second wiring circuit (241) may be formed to be 2um / 2um or less.

[0083] The second insulating material (243) may be formed of a dielectric or polymer material. Examples of the polymer material that may be used include EMC, PI, ABF, etc., but are not necessarily limited thereto.

[0084] The height of the second wiring layer (240) can be formed lower than the height of the first wiring layer (220).

[0085] The second wiring layer (240) is not an essential component that must be included in the connecting structure (200), and thus may be optionally configured according to an embodiment of the present invention.

[0086] The UBM (Under Bump Metallurgy) layer (250) is placed between the second wiring layer (240) and the connecting member (260), thereby improving the bonding strength between the second wiring layer (240) and the connecting member (260).

[0087] The UBM layer (250) may be provided in a single or multiple number. The UBM layer (250) is a multi-layer metal layer formed between the second wiring layer (240) and the connecting member (260), and may be composed of a bonding layer, a diffusion barrier layer, and a wettable layer.

[0088] Meanwhile, although not shown in the drawing, if the second wiring layer (240) is omitted, the UBM layer (250) may be disposed between the first wiring layer (220) and the connecting members (260), thereby strengthening the bonding strength between the first wiring layer (220) and the connecting members (260). The UBM layer (250) may be disposed below the opening of the etching stop layer (210).

[0089] A connecting member (260) may be attached to one surface of the UBM layer (250) and may serve to electrically connect the substrate (110) and the second wiring layer (240). The connecting member (260) may be provided in a single or multiple number. The connecting member (260) may be formed in the shape of a metal ball or a metal bump.

[0090] As described above, the connecting structure according to an embodiment of the present invention can simplify the manufacturing process and reduce the manufacturing cost because there is no need to perform an expensive Through Silicon Via (TSV) process. In addition, the connecting structure can simplify the manufacturing process by using an etch stop layer to protect the wiring layer during substrate etching, thereby omitting the polishing process for the substrate. In addition, the connecting structure can improve the power supply characteristics and signal transmission characteristics by enabling vertical and horizontal current conduction through the wiring layer and the conductive layer.

[0091]

[0092] FIG. 3 is a flowchart illustrating a method for manufacturing a connecting structure according to a first embodiment of the present invention, and FIGS. 4A to 4J are drawings referenced to explain the method for manufacturing a connecting structure according to the first embodiment of the present invention. In the illustrated flowchart, the method for manufacturing a connecting structure is described by dividing it into a plurality of steps, but at least some of the steps may be performed in a reversed order, combined with other steps and performed together, omitted, divided into detailed steps and performed, or one or more steps not illustrated may be added and performed.

[0093] Referring to FIGS. 3 to 4j, first, a substrate (205) for supporting a connecting structure (200) is prepared (S301). The substrate (205) may be formed of a silicon (Si) material, a glass material, a polymer material, or the like.

[0094] An etching stop layer (210) is formed on a substrate (205) (S302). The etching stop layer (210) may be formed of a dielectric material that does not chemically react with an etchant for etching the substrate (205). For example, the etching stop layer (210) may be formed of an oxide or a nitride, but is not necessarily limited thereto.

[0095] A first wiring layer (220) can be formed on one surface of the etching stop layer (210) (S303). At this time, the first wiring layer (220) can be manufactured by filling copper (Cu) by electroplating using a damascene process or can be printed in the form of a redistribution layer (RDL).

[0096] A plurality of fillers (131) can be formed on the first wiring layer (220) (S304). The plurality of fillers (131) can be formed to be spaced apart from each other by a certain distance. The plurality of fillers (131) can be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al).

[0097] More specifically, as illustrated in FIG. 4d, a UBM layer (225) may be formed on the wiring circuit of the first wiring layer (220), and a filler (231) may be formed on the UBM layer (225). Through the UBM layer (225) disposed between the first wiring layer (220) and the filler (231), the adhesive strength between the first wiring layer (220) and the filler (231) may be improved.

[0098] A molding member (233) can be formed to surround the upper surface of the first wiring layer (220) and a plurality of fillers (231) (S305). EMC, PI, ABF, etc. can be used as the molding member (233), but the present invention is not necessarily limited thereto.

[0099] The substrate (205) can be removed by sequentially performing a grinding process and an etching process on the substrate (205) (S306). During the etching process, since the etching stop layer (210) does not react with the substrate etchant, only the substrate (205) can be effectively removed.

[0100] By etching the etching stop layer (210) using an etching mask of a predetermined shape, a plurality of openings can be formed on the etching stop layer (210) (S307).

[0101] For example, as illustrated in FIG. 4g, a plurality of openings may be formed by etching a plurality of regions of the etch stop layer (210) so that the pads (225) of the first wiring layer (220) are exposed to the outside. At this time, the width (d2) of the openings formed in the etch stop layer (210) may be formed to be smaller than the width of the lower surface of the pads (225) formed in the first wiring layer (220).

[0102] A second wiring layer (240) can be formed on the other side of the etching stop layer (210) (S308). Similarly, the second wiring layer (240) can be manufactured by filling copper (Cu) by electroplating using a damascene process or printed in the form of a redistribution layer (RDL).

[0103] A plurality of UBM layers (250) can be formed on the second wiring layer (240), and a plurality of connection members (260) can be formed on the plurality of UBM layers (250) (S309). Here, the UBM layer (250) is disposed between the second wiring layer (240) and the connection member (260), thereby improving the bonding strength between the second wiring layer (240) and the connection member (260). The connection member (260) can be formed in the shape of a metal ball or a metal bump.

[0104] Thereafter, the upper region of the molding member (233) is removed so that the plurality of fillers (231) are exposed to the outside (S310). At this time, the molding member (233) can be removed through a grinding process or an etching process.

[0105] Through the processes described above, a connecting structure (200) according to the first embodiment of the present invention can be manufactured.

[0106] As described above, the method for manufacturing a connecting structure according to the first embodiment of the present invention can simplify the manufacturing process and reduce the manufacturing cost because there is no need to perform an expensive TSV process. In addition, the method for manufacturing a connecting structure can simplify the manufacturing process by using an etch stop layer to protect the wiring layer during substrate etching, thereby omitting the polishing process for the substrate. In addition, the method for manufacturing a connecting structure can improve the power supply characteristics and signal transmission characteristics of the connecting structure by enabling vertical and horizontal current conduction through the wiring layer and the conductive layer.

[0107]

[0108] FIG. 5 is a flowchart illustrating a method for manufacturing a connecting structure according to a second embodiment of the present invention, and FIGS. 6A to 6L are drawings referenced to explain a method for manufacturing a connecting structure according to the second embodiment of the present invention. In the illustrated flowchart, the method for manufacturing a connecting structure is described by dividing it into a plurality of steps, but at least some of the steps may be performed in a reversed order, combined with other steps and performed together, omitted, divided into detailed steps and performed, or one or more steps not illustrated may be added and performed.

[0109] Referring to FIGS. 5 to 6l, first, a first substrate (or support substrate, 205) for supporting a connecting structure (200) is prepared (S501). The first substrate (205) may be formed of a silicon (Si) material, a glass material, a polymer material, or the like.

[0110] An etching stop layer (210) is formed on the first substrate (205) (S502). At this time, the etching stop layer (210) may be formed of a dielectric material that does not chemically react with an etchant for etching the first substrate (205).

[0111] A first wiring layer (220) can be formed on one surface of the etching stop layer (210) (S503). At this time, the first wiring layer (220) can be manufactured by filling copper (Cu) by electroplating using a damascene process or can be printed in the form of a redistribution layer (RDL).

[0112] A plurality of fillers (131) can be formed on the first wiring layer (220) (S504). The plurality of fillers (131) can be formed to be spaced apart from each other by a certain distance. The plurality of fillers (131) can be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al).

[0113] More specifically, as illustrated in FIG. 6d, a UBM layer (225) may be formed on the wiring circuit of the first wiring layer (220), and a filler (231) may be formed on the UBM layer (225). Through the UBM layer (225) disposed between the first wiring layer (220) and the filler (231), the adhesive strength between the first wiring layer (220) and the filler (231) may be improved.

[0114] A molding member (233) can be formed to surround the upper surface of the first wiring layer (220) and a plurality of fillers (231) (S505). EMC, PI, ABF, etc. can be used as the molding member (233), but the present invention is not necessarily limited thereto.

[0115] By removing the upper region of the molding member (233), a plurality of fillers (231) are exposed to the outside (S506). At this time, the molding member (233) can be removed through a grinding process or an etching process.

[0116] A second substrate (or carrier substrate, 235) can be formed on a conductive layer (230) including a plurality of fillers (231) and a molding member (233) disposed between the plurality of fillers (231) (S507). Here, the second substrate (235) can be formed of a silicon (Si) material, a glass material, a polymer material, or the like.

[0117] The first substrate (205) can be removed by sequentially performing a grinding process and an etching process on the first substrate (205) (S508). During the etching process, since the etching stop layer (210) does not react with the substrate etchant, only the first substrate (205) can be effectively removed.

[0118] By etching the etching stop layer (210) using an etching mask of a predetermined shape, a plurality of openings can be formed on the etching stop layer (210) (S509).

[0119] For example, as illustrated in FIG. 6i, a plurality of regions of the etching stop layer (210) may be etched to form a plurality of openings so that the pads (225) of the first wiring layer (220) are exposed to the outside. At this time, the width (d2) of the openings formed in the etching stop layer (210) may be formed to be smaller than the width of the lower surface of the pads (225).

[0120] A second wiring layer (240) can be formed on the other side of the etching stop layer (210) (S510). Similarly, the second wiring layer (240) can be manufactured by filling copper (Cu) by electroplating using a damascene process or printed in the form of a redistribution layer (RDL).

[0121] A plurality of UBM layers (250) can be formed on the second wiring layer (240), and a plurality of connection members (260) can be formed on the plurality of UBM layers (250) (S511). Here, the UBM layer (250) is arranged between the second wiring layer (240) and the connection member (260), thereby improving the bonding strength between the second wiring layer (240) and the connection member (260).

[0122] Thereafter, the second substrate (512) can be removed through a grinding process or an etching process (S512).

[0123] Through the aforementioned processes, a connecting structure (200) according to the second embodiment of the present invention can be manufactured.

[0124] As described above, the method for manufacturing a connecting structure according to the second embodiment of the present invention can simplify the manufacturing process and reduce the manufacturing cost because there is no need to perform an expensive TSV process. In addition, the method for manufacturing a connecting structure can simplify the manufacturing process by using an etch stop layer to protect the wiring layer during substrate etching, thereby omitting the polishing process for the substrate. In addition, the method for manufacturing a connecting structure can improve the power supply characteristics and signal transmission characteristics of the connecting structure by enabling vertical and horizontal current conduction through the wiring layer and the conductive layer.

[0125] While specific embodiments of the present invention have been described above, it is clear that various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention is not limited to the described embodiments, but should be defined not only by the claims set forth below but also by equivalents thereof.

Claims

1. An etch stop layer having multiple apertures; A first wiring layer disposed on one side of the above etching stop layer; a conductive layer disposed on the first wiring layer; and A connecting structure including a plurality of connecting members electrically connected to the first wiring layer through conductive metal materials injected into the plurality of openings.

2. In paragraph 1, A connecting structure, characterized in that the etching stop layer is formed of a dielectric material that does not chemically react with an etching agent for etching the substrate.

3. In paragraph 1, A connecting structure, characterized in that the width of the opening formed in the etching stop layer is formed smaller than the width of the lower surface of the pad formed in the first wiring layer.

4. In paragraph 1, A connecting structure, characterized in that the first wiring layer includes a first wiring circuit and a first insulating material coated on the first wiring circuit.

5. In paragraph 1, A connecting structure, characterized in that the conductive layer includes a plurality of fillers spaced apart from each other and a molding member coated between the plurality of fillers.

6. In paragraph 1, A connecting structure further comprising a second wiring layer disposed on the other surface of the etching stop layer.

7. In paragraph 6, A connecting structure further comprising a plurality of UBM (Under Bump Metallurgy) layers arranged between the second wiring layer and the connecting members to strengthen the bonding strength between the second wiring layer and the connecting members.

8. In paragraph 6, A connecting structure, characterized in that the second wiring layer includes a second wiring circuit and a second insulating material coded to the second wiring circuit.

9. In paragraph 1, A connecting structure further comprising a plurality of UBM layers arranged between the wiring circuit of the first wiring layer and the fillers of the conductive layer to strengthen the bonding strength between the first wiring layer and the conductive layer.

10. In paragraph 1, A connecting structure further comprising a plurality of UBM (Under Bump Metallurgy) layers arranged between the first wiring layer and the connecting members to strengthen the bonding strength between the first wiring layer and the connecting members.

11. A step of forming an etching stop layer on a substrate; A step of forming a first wiring layer on one side of the above etching stop layer; A step of forming a plurality of fillers on the first wiring layer; A step of forming a molding member on the first wiring layer and the plurality of fillers; A step of removing the above substrate; A step of forming a plurality of openings in the above etching stop layer; A step of injecting a conductive metal material into the plurality of openings and forming a plurality of connecting members electrically connected to the first wiring layer through the conductive metal material; and A method for manufacturing a connecting structure, comprising the step of forming a conductive layer by removing a portion of the molding member so that the plurality of fillers are exposed to the outside.

12. In the 11th paragraph, the step of removing the substrate is: A method for manufacturing a connecting structure, characterized in that the substrate is removed by sequentially performing a grinding process and an etching process on the substrate.

13. In the 11th paragraph, the step of forming the openings is: A method for manufacturing a connecting structure, characterized in that a plurality of openings are formed in the etching stop layer by etching the etching stop layer using an etching mask of a predetermined shape.

14. In paragraph 11, A method for manufacturing a connecting structure further comprising the step of forming a second wiring layer on the other surface of the etching stop layer.

15. In paragraph 14, A method for manufacturing a connecting structure, further comprising the step of forming a plurality of UBM (Under Bump Metallurgy) layers disposed between the second wiring layer and the plurality of connecting members to strengthen the bonding strength between the second wiring layer and the plurality of connecting members.

16. A step of forming an etching stop layer on a first substrate; A step of forming a first wiring layer on one side of the above etching stop layer; A step of forming a conductive layer on the first wiring layer; A step of placing a second substrate on the conductive layer; A step of removing the first substrate; A step of forming a plurality of openings in the above etching stop layer; A step of injecting a conductive metal material into the plurality of openings and forming a plurality of connecting members electrically connected to the first wiring layer through the conductive metal material; and A method for manufacturing a connecting structure, comprising the step of removing the second substrate.

17. In the 16th paragraph, the step of removing the first substrate is: A method for manufacturing a connecting structure, characterized in that a grinding process and an etching process are sequentially performed on the first substrate to remove the first substrate.

18. In the 16th paragraph, the step of forming the openings is: A method for manufacturing a connecting structure, characterized in that a plurality of openings are formed in the etching stop layer by etching the etching stop layer using an etching mask of a predetermined shape.

19. In Article 16, A method for manufacturing a connecting structure further comprising the step of forming a second wiring layer on the other surface of the etching stop layer.

20. In paragraph 19, A method for manufacturing a connecting structure, further comprising the step of forming a plurality of UBM (Under Bump Metallurgy) layers disposed between the second wiring layer and the plurality of connecting members to strengthen the bonding strength between the second wiring layer and the plurality of connecting members.

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