UWB radar sensor chip system architecture

Abstract

The present invention relates to an ultra-wideband (UWB) radar sensor chip system architecture. The chip system architecture at least comprises N receiving channels and N transmitting channels, wherein N is a positive integer greater than 1, the N receiving channels form receiving links by means of connecting to a receiver multiplexer, the N transmitting channels form transmitting links by means of connecting to a transmitter multiplexer, and the receiving links and the transmitting links jointly form N groups of transceiving systems. The chip system architecture further comprises a serial peripheral interface, and is adjacent to an external main control chip by means of the serial peripheral interface, so as to drive, by means of a control command, the N groups of transceiving systems to operate on the basis of time division or to operate independently. The present invention introduces the concepts of time division multiplexing and multi-channel synthesis into a radar system, and provides a universal UWB radar sensor chip system architecture with a high integration level, a high performance and a low cost, thereby effectively solving the problems of a radar chip in terms of the sensitivity and transmitting power, improving the detection precision and increasing the detection distance.

Description

A UWB radar sensor chip system architecture Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a highly integrated, high-performance, and low-cost UWB radar sensor chip system architecture. Background Art

[0002] Ultra-wideband signals feature strong interference resistance, high transmission rates, high resolution, strong penetration, simple system structure, low power consumption, and high security. They are widely applicable in military, healthcare, medical, and security fields, boasting a wide range of application scenarios and promising market prospects. To date, academic research on ultra-wideband radar chips has achieved some success both domestically and internationally, but due to technological gaps, commercialization remains some distance away. While research and industrialization of ultra-wideband radar systems are relatively mature, they essentially all utilize discrete components for the UWB RF front-end transceiver system, resulting in high costs, low reliability, and significant challenges in large-scale commercialization. Driven by major electronic equipment manufacturers, the industrialization of UWB chips is primarily focused on UWB positioning systems, which primarily leverage UWB's superior communication performance for indoor and complex environments. These systems differ from UWB radar chips in terms of system architecture and performance. Highly integrated, cost-effective ultra-wideband radar chips are still lacking both domestically and internationally, despite the growing demand for ultra-wideband radar applications in military, aerospace, industrial, medical, and consumer electronics. Therefore, it is necessary and urgent to develop a highly integrated, high-performance ultra-wideband radar chip.

[0003] Summary of the Invention

[0004] The purpose of the present invention is to provide a UWB radar sensor chip system architecture, introduce the concepts of time-division multiplexing and multi-channel synthesis into the radar system, and propose a highly integrated, high-performance, low-cost universal ultra-wideband radar sensor chip system architecture, which effectively solves the problems of radar chip sensitivity and transmission power, and improves detection accuracy and distance.

[0005] The present invention is implemented through the following technical solution: a UWB radar sensor chip system architecture, characterized in that: the chip system architecture includes at least N receiving channels and N transmitting channels, where N is a positive integer greater than 1; the N receiving channels are connected to a receiving-end multiplexer to form a receiving chain, and the N transmitting channels are connected to a transmitting-end multiplexer to form a transmitting chain, and the receiving chain and the transmitting chain together constitute N groups of transceiver systems;

[0006] The chip system architecture also includes a serial peripheral interface, and is adjacent to an external main control chip through the serial peripheral interface, thereby controlling commands to drive N groups of transceiver systems to work in time-sharing or independently.

[0007] Compared with the prior art, the present invention has the following beneficial effects:

[0008] 1. The concepts of time-division multiplexing and multiplexing are introduced into the radar sensor chip system architecture, resulting in a highly integrated, high-performance, and low-cost wideband radar sensor chip. The versatility and functionality of the UWB radar chip system architecture enable the corresponding radar sensor to be applied to 3D positioning and 3D imaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a schematic diagram of the overall structure of the architecture of the present invention;

[0010] FIG2 is a detailed structural connection diagram of a direct digital frequency synthesizer and a pulse generation module;

[0011] FIG3 is a detailed structural connection diagram of the transmission channel;

[0012] Figure 4 is a detailed structural connection diagram of the receiving channel. DETAILED DESCRIPTION

[0013] The present invention is described in detail below with reference to the accompanying drawings:

[0014] As shown in Figure 1: A UWB radar sensor chip system architecture, characterized in that: the chip system architecture includes at least N receiving channels RX1-RXN and N transmitting channels TX1-TXN, where N is a positive integer greater than 1; the N receiving channels are connected to a receiving end multiplexer to form a receiving chain, and the N transmitting channels are connected to a transmitting end multiplexer to form a transmitting chain. The receiving chain and the transmitting chain together constitute a transceiver system;

[0015] The chip system architecture also includes a serial peripheral interface SPI, and is adjacent to an external main control chip through the serial peripheral interface SPI. The control commands of the main control chip drive N groups of transceiver systems to work in time-sharing or independently.

[0016] Figure 1 specifically uses the currently used four transmit channels and four receive channels, connected via corresponding selectors, to form a transceiver system. This system is connected to an external master control chip via a serial peripheral interface (SPI). External control commands drive the four transceiver systems to operate in time-sharing or independently. This increases the versatility and functionality of the proposed UWB radar chip system architecture, enabling the radar sensor developed in this project to be applied to 3D positioning and 3D imaging.

[0017] The present invention also includes a direct digital frequency synthesizer (DDS), which generates two clock signals, one clock signal is transmitted to a transmitting link, and the other clock signal is transmitted to a receiving link.

[0018] The clock signals of the four-way transmitting and receiving channels of the present invention are generated by a direct digital frequency synthesizer (DDS) circuit. The DDS circuit generates two-channel clock signals, one of which is sent to the transmitting link and the other is sent to the receiving link.

[0019] The present invention further comprises a first pulse generating module and a differentiator connected to each other; the first pulse generating module is connected to a direct digital frequency synthesizer DDS, and the differentiator is connected to a transmitting end multiplexer;

[0020] Any of the transmitting channels includes a power amplifier and a transmitting antenna, and the transmitting antenna is connected to the transmitting end multiplexer via the power amplifier.

[0021] Under the clock signal of the direct digital synthesizer (DDS), the first pulse generator module generates a Gaussian envelope pulse signal. The differentiator shapes the Gaussian envelope pulse signal to meet the UWB spectrum density requirements. The shaped pulse signal is sent to the corresponding power amplifier (PA) for amplification through the transmitter multiplexer and finally radiated outward through the transmitting antenna, thus achieving one-to-many signal transmission.

[0022] The device also includes a second pulse generating module, a mixer, a low-pass filter, an automatic gain amplifier, and an analog-to-digital converter connected in sequence; the analog-to-digital converter is connected to a serial peripheral interface SPI; the second pulse generating module is connected to a direct digital frequency synthesizer DDS, and the mixer is connected to a receiving end multiplexer;

[0023] Any of the receiving channels includes a low noise amplifier and a receiving antenna, and the receiving antenna is connected to the receiving end multiplexer via the low noise amplifier.

[0024] The received multi-channel pulse signals (the receiving antenna receives the reflected pulse signals and sends them to the corresponding low-noise amplifier for amplification) are transmitted to the RF end of the mixer through the receiving end multiplexer; at the same time, under the action of the clock signal generated by the direct digital frequency synthesizer DDS, the second pulse generation module generates a Gaussian envelope pulse signal as the local oscillator signal of the mixer to participate in the mixing work of the mixer, and finally obtains the intermediate frequency signal that protects the azimuth information of the detected object; the intermediate frequency signal is processed by the low-pass filter and amplified by the automatic gain amplifier to make its signal amplitude reach a certain level, and then it is quantized by the analog-to-digital converter. Finally, the quantized digital signal is sent to the outside of the chip through the serial peripheral interface SPI for baseband signal processing.

[0025] As shown in FIG2 , the direct digital frequency synthesizer includes a phase accumulator, a phase-amplitude converter, and a digital-to-analog converter connected in sequence. The phase accumulator is connected to a reference clock, and the digital-to-analog converter is connected to a first pulse generating module and a second pulse generating module.

[0026] The direct digital frequency synthesizer (DDS) is the core module of the present invention and consists of three main components: a phase accumulator, a phase-to-amplitude converter, and a digital-to-analog converter (DAC). It enables adaptive clock selection, which automatically selects an appropriate frequency division value based on the DDS output frequency, the frequency control word, and the number of bits in the phase accumulator to divide the input reference clock, ensuring that the frequency of the generated DDS clock signal meets specific requirements. The frequency word serves as the input to the phase accumulator and is accumulated under the triggering of the reference clock (Clock Generator) until the accumulator overflows, representing a complete cycle. After each accumulation, the accumulator calculates a phase (or angle) address and sends it to the phase-to-amplitude converter, which outputs the digital signal amplitude, which serves as the input signal to the digital-to-analog converter (DAC) and is converted into an analog amplitude value by the DAC.

[0027] The DDS architecture uses a 14-bit primary DDS core, a 10-bit first auxiliary DDS core, and a 9-bit second auxiliary DDS core. This architecture enables predistortion, allowing the two auxiliary DDS cores to cancel harmonics of the primary DDS core output to the greatest extent possible.

[0028] The first pulse generating module and the second pulse generating module are both pulse signal generator circuits, and the pulse signal generator circuit includes an adjustable pulse width rectangular pulse generator and a high-frequency LC oscillator connected to each other;

[0029] The adjustable pulse width rectangular pulse generator of the first pulse generating module is connected to the direct digital frequency synthesizer, and the high frequency LC oscillator is connected to the differentiator;

[0030] The adjustable pulse width rectangular pulse generator of the second pulse generating module is connected to the direct digital frequency synthesizer, and the high frequency LC oscillator is connected to the mixer.

[0031] The adjustable pulse width rectangular pulse generator, based on the characteristics of the XOR gate logic, allows one clock signal and the same clock signal to be input into the XOR gate after being delayed for XOR operation. The high-frequency LC oscillator can generate a sine wave signal with a maximum frequency of 10GHz, and the oscillation frequency is tunable. Frequency tunability is achieved by controlling the voltage to change the capacitance of the variable capacitor. The negative impedance provided by the cross-coupled transistor provides the energy to maintain the oscillation of the high-frequency LC oscillator. The bias current of the high-frequency LC oscillator is controlled by the output pulse signal of the adjustable pulse width rectangular pulse generator. The high-frequency LC oscillator only operates normally and outputs a differential oscillation signal when the output signal of the rectangular pulse generator is high; when the output signal of the rectangular pulse generator is low, the high-frequency LC oscillator is in standby mode.

[0032] As shown in Figure 3: the power amplifier includes an input impedance matching network, a resistive negative feedback common-source common-gate amplifier, an inter-stage impedance matching network, a common-source stage amplifier and an on-chip transformer connected in sequence. The input impedance matching network is connected to the differentiator, and the on-chip transformer is connected to the transmitting antenna.

[0033] The input impedance matching network, combined with the resistive negative feedback structure of the resistive negative feedback cascode amplifier, achieves impedance matching over a wide bandwidth. The interstage impedance matching network, placed between the output of the resistive negative feedback cascode amplifier and the input of the common-source stage amplifier, performs impedance matching, improves gain, and improves linearity. The common-source stage amplifier uses an inductive peaking load common-source stage amplifier structure, which can achieve a larger output voltage margin while compensating the low-frequency gain of the entire power amplifier, achieving higher output power and improving the detection range of the radar sensor. The on-chip transformer, serving as the output stage of the power amplifier, converts the differential output signal into a single-ended signal and isolates the active amplifier section from the package leads.

[0034] As shown in FIG4 , the low noise amplifier includes a common-gate low noise amplifier, an inter-stage impedance matching circuit, and a common-source differential amplifier connected in sequence; the common-gate low noise amplifier is connected to a receiving antenna, and the common-source differential amplifier is connected to a mixer.

[0035] Low-noise amplifiers (LNAs) feature wide-band impedance matching, low noise, high gain, and single-ended signal input and differential output. The LNA's single-ended input and differential output structure allows it to function as a single-ended-to-differential converter, avoiding the use of passive on-chip transformers that degrade the overall noise performance of the receive link. This LNA comprises two amplifier stages. The first stage is a cascode LNA, which employs cascode noise cancellation technology to achieve a lower noise figure and wideband input impedance matching. The interstage impedance matching circuit transforms the impedance between the low output impedance of the first-stage amplifier and the high input impedance of the second-stage amplifier, increasing the overall gain and reducing the noise figure. The second-stage amplifier, a cascode differential amplifier, offers wide operating bandwidth, low noise figure, and effective suppression of common-mode signals in the first-stage output signal.

[0036] The chip also includes a temperature sensor connected to the serial peripheral interface. This temperature sensor provides a relatively accurate operating temperature reading for the chip's system architecture, enabling performance calibration of key internal circuit modules (such as the direct digital synthesizer (DDS) and power amplifier (PA). The serial peripheral interface (SPI) serves as the interface between the chip and an external master control chip, allowing the external master control chip to configure the chip's operating mode and the performance of each module.

[0037] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A UWB radar sensor chip system architecture, characterized in that: the chip system architecture includes at least N receiving channels and N transmitting channels, where N is a positive integer greater than 1; the N receiving channels form a receiving link by connecting to a receiving - end multiplexer, and the N transmitting channels form a transmitting link by connecting to a transmitting - end multiplexer, and the receiving link and the transmitting link together form a transceiver system; the chip system architecture further includes a serial peripheral interface, and is adjacent to an external master control chip through the serial peripheral interface, and drives the transceiver system to work in a time - sharing manner or independently under the control command of the master control chip.

2. A UWB radar sensor chip system architecture according to claim 1, characterized in that: it further includes a direct digital frequency synthesizer, and the direct digital frequency synthesizer generates two clock signals, one clock signal is sent to the transmitting link, and the other clock signal is sent to the receiving link.

3. A UWB radar sensor chip system architecture according to claim 2, characterized in that: it further includes a first pulse generation module and a differentiator connected to each other; the first pulse generation module is connected to the direct digital frequency synthesizer, and the differentiator is connected to the transmitting - end multiplexer; under the action of the clock signal of the direct digital frequency synthesizer, the first pulse generation module generates a Gaussian envelope pulse signal, and the Gaussian envelope pulse signal is shaped by the differentiator to meet the requirements of the UWB spectrum density, and the shaped pulse signal realizes one - to - many signal transmission through the transmitting - end multiplexer; meanwhile, it also includes a second pulse generation module, a mixer, a low - pass filter, an automatic gain amplifier, and an analog - to - digital converter connected in sequence; the analog - to - digital converter is connected to the serial peripheral interface; the second pulse generation module is connected to the direct digital frequency synthesizer, and the mixer is connected to the receiving - end multiplexer; the received multi - path pulse signals are sent to the RF end of the mixer through the receiving - end multiplexer; at the same time, under the action of the clock signal of the direct digital frequency synthesizer, the second pulse generation module generates a Gaussian envelope pulse signal as the local oscillator signal of the mixer to participate in the mixing work of the mixer, and finally an intermediate - frequency signal for protecting the azimuth information of the detected object is obtained; the intermediate - frequency signal is amplified by the automatic gain amplifier after being processed by the low - pass filter to make its signal amplitude reach a certain level, then is quantized by the analog - to - digital converter, and finally the quantized digital signal is sent to the outside of the chip through the serial peripheral interface SPI for baseband signal processing.

4. A UWB radar sensor chip system architecture according to claim 3, characterized in that: any of the transmitting channels includes a power amplifier and a transmitting antenna, and the transmitting antenna is connected to the transmitting - end multiplexer through the power amplifier; any of the receiving channels includes a low - noise amplifier and a receiving antenna, and the receiving antenna is connected to the receiving - end multiplexer through the low - noise amplifier.

5. A UWB radar sensor chip system architecture according to claim 3, characterized in that: The direct digital frequency synthesizer includes a phase accumulator, a phase-amplitude converter, and a digital-to-analog converter connected in sequence. The phase accumulator is connected to a reference clock, and the digital-to-analog converter is connected to a first pulse generation module and a second pulse generation module; such that the phase accumulator accumulates until overflow under the trigger of the reference clock to form a complete cycle; After each accumulation, the phase accumulator calculates the address of a phase and sends it to the phase-amplitude converter to output the signal amplitude of the digital quantity, which serves as the input signal of the digital-to-analog converter and is converted into an analog amplitude value by the digital-to-analog converter.

6. The system architecture of a UWB radar sensor chip according to claim 3, characterized in that: The architecture of the direct digital frequency synthesizer adopts a 14-bit main direct digital frequency synthesizer, a 10-bit first auxiliary direct digital frequency synthesizer, and a 9-bit second auxiliary direct digital frequency synthesizer.

7. The system architecture of a UWB radar sensor chip according to claim 3, characterized in that: Both the first pulse generation module and the second pulse generation module are pulse signal generator circuits. The pulse signal generator circuit includes an adjustable pulse width rectangular pulse generator and a high-frequency LC oscillator connected to each other; The adjustable pulse width rectangular pulse generator of the first pulse generation module is connected to the direct digital frequency synthesizer, and the high-frequency LC oscillator is connected to a differentiator; The adjustable pulse width rectangular pulse generator of the second pulse generation module is connected to the direct digital frequency synthesizer, and the high-frequency LC oscillator is connected to a mixer.

8. The system architecture of a UWB radar sensor chip according to claim 4, characterized in that: The power amplifier includes an input impedance matching network, a resistor negative feedback cascode amplifier, an inter-stage impedance matching network, a common-source amplifier, and an on-chip transformer connected in sequence. The input impedance matching network is connected to the differentiator, and the on-chip transformer is connected to the transmitting antenna.

9. The system architecture of a UWB radar sensor chip according to claim 4, characterized in that: The low-noise amplifier includes a common-gate common-source low-noise amplifier, an inter-stage impedance matching circuit, and a common-gate common-source differential amplifier connected in sequence; the common-gate common-source low-noise amplifier is connected to the receiving antenna, and the common-gate common-source differential amplifier is connected to the mixer.

10. The system architecture of a UWB radar sensor chip according to claim 4, characterized in that: It further includes a temperature sensor, and the temperature sensor is connected to a serial peripheral interface.

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