Semiconductor structure, radio-frequency amplifier, radio-frequency front-end module, and communication device

Abstract

A semiconductor structure, a radio-frequency amplifier, a radio-frequency front-end module, and a communication device, which relate to the technical field of electronics and are used for improving the linearity of radio-frequency amplifiers. The radio-frequency amplifier comprises at least one first transistor and at least one second transistor, wherein a first gate electrode of the first transistor is coupled to a second gate electrode of the second transistor; a first source electrode of the first transistor and a second source electrode of the second transistor are both coupled to a reference ground voltage end, and a first drain electrode of the first transistor is coupled to a second drain electrode of the second transistor; and same is equivalent to the first transistor and the second transistor being connected in parallel. The threshold voltage of each first transistor is less than the threshold voltage of each second transistor, and the sum of the widths of gate electrodes of the at least one first transistor is greater than the sum of the widths of gate electrodes of second transistors having the same threshold voltage, such that a positive inter-modulation signal of a first transistor and a negative inter-modulation signal of a second transistor are perfectly canceled out, thereby improving the linearity of the radio-frequency amplifier.

Description

Semiconductor structures, RF amplifiers, RF front-end modules, communication equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 30, 2023, with application number 202311638655.7 and application name “Semiconductor structure, radio frequency amplifier, radio frequency front-end module, communication equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a semiconductor structure, a radio frequency amplifier, a radio frequency front-end module, and a communication device. Background Art

[0003] Linearity is a key performance metric for RF amplifiers. For example, in RF front-end systems, low-noise amplifiers (LNAs) should maximize their linearity to minimize the impact of signal sensitivity from the transmit channel entering the receive channel. With the advent of fifth-generation mobile communication technology (5G), the requirements for LNA linearity are becoming increasingly stringent.

[0004] Therefore, the linearity of RF amplifiers is a hot topic that continues to attract attention of those skilled in the art.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a semiconductor structure, a radio frequency amplifier, a radio frequency front-end module, and a communication device for improving the linearity of the radio frequency amplifier.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present application, a semiconductor structure is provided for use in a radio frequency amplifier; the semiconductor structure includes: a gate pad, a source pad, a drain pad, at least one first transistor, and at least one second transistor. Each first transistor includes a first gate, a first source, and a first drain, and the first gate is coupled to the gate pad, the first source is coupled to the source pad, and the first drain is coupled to the drain pad. Each second transistor includes a second gate, a second source, and a second drain, and the second gate is coupled to the gate pad, the second source is coupled to the source pad, and the second drain is coupled to the drain pad. The threshold voltage of the first transistor is less than the threshold voltage of the second transistor, and the sum of the gate widths of at least one first transistor is greater than the sum of the gate widths of one or more second transistors having the same threshold voltage in the at least one second transistor.

[0009] In an embodiment of the present application, the semiconductor structure includes a first transistor and a second transistor, wherein the width of the first gate of the first transistor affects the amplitude of the total signal transmitted by the first transistor (including the main signal and the intermodulation signal), and the width of the second gate of the second transistor affects the amplitude of the total signal transmitted by the second transistor (including the main signal and the intermodulation signal). The threshold voltages of the first transistor and the second transistor affect the phase of the intermodulation signal output by the first transistor and the second transistor under the condition of the same gate voltage. In the present application, the first gate and the second gate are both coupled to the gate pad and receive the same gate bias voltage. Under the same gate bias voltage, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor, so the first transistor provides a negative intermodulation signal and the second transistor provides a positive intermodulation signal. Although the positive intermodulation signal provided by the transistor under the same conditions will be greater than the negative intermodulation signal, the width of the first gate is always set to be greater than the sum of the widths of the second gate in the present application, so that the first transistor and the second transistor can output two sets of equal and opposite intermodulation signals to achieve cancellation. Therefore, the embodiments of the present application utilize different threshold voltages to achieve a cancellation effect by providing the same gate bias voltage to the first and second transistors. This reduces the design complexity of the semiconductor structure, simplifies the structure, and occupies a small area. Furthermore, the stability of the threshold voltage difference is utilized to control the gate bias state, resulting in a stable cancellation effect.

[0010] In one possible implementation, the semiconductor structure includes multiple second transistors; the multiple second transistors include a first group of second transistors and a second group of second transistors, and the threshold voltage of the second transistors in the first group is different from the threshold voltage of the second transistors in the second group.

[0011] By setting up a variety of second transistors with different threshold voltages for matching, a relatively good cancellation effect can be achieved in a certain area, that is, the width of the cancellation zone is increased. This improves the tolerance to environmental conditions such as process fluctuations and temperature, so as to improve the process consistency of the semiconductor structure production process. In addition, by setting up second transistors with different threshold voltages and matching them with different numbers of second transistors, the linearity of the RF amplifier can be improved in the drain current range of 40mA / mm to 120mA / mm.

[0012] In one possible implementation, the number of at least one first transistor is greater than the number of second transistors in the first group and greater than the number of second transistors in the second group. By varying the total gate width of transistors by the number of transistors, the gate width of each transistor can be reduced, simplifying the manufacturing process. When a semiconductor structure includes transistors with multiple threshold voltages, there is no necessary correlation between the number of transistors with different threshold voltages.

[0013] In one possible implementation, the threshold voltages of at least one first transistor are the same, the threshold voltages of at least one second transistor are the same, and the number of the at least one first transistor is greater than the number of the at least one second transistor. By varying the number of transistors, the total gate width of each transistor can be reduced, simplifying the manufacturing process.

[0014] In one possible implementation, the width of the first gate is equal to the width of the second gate. The gate widths of each transistor in the semiconductor structure are equal, and the total gate width is changed only by the number of transistors, resulting in a simple process and high integration.

[0015] In one possible implementation, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first gate is in Schottky contact with the first barrier layer, and the first source and first drain are in ohmic contact with the first barrier layer; the second gate is in Schottky contact with the second barrier layer, and the second source and second drain are in ohmic contact with the second barrier layer; the first thickness of the portion of the first barrier layer in contact with the first gate is greater than the second thickness of the portion of the second barrier layer in contact with the second gate. By varying the thickness of the first and second barrier layers, the threshold voltage of the first transistor is made lower than the threshold voltage of the second transistor, resulting in a simple process and easy implementation.

[0016] In one possible implementation, the difference between the first thickness and the second thickness ranges from 1 nm to 6 nm. Setting the difference between the first thickness and the second thickness within the range of 1 nm to 6 nm can meet the different threshold voltage requirements of the first transistor and the second transistor with lower process difficulty.

[0017] In one possible implementation, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first gate includes a first Schottky metal layer in Schottky contact with the first barrier layer, and the second gate includes a second Schottky metal layer in Schottky contact with the second barrier layer; the work function of the first Schottky metal layer is less than the work function of the second Schottky metal layer. By changing the materials of the first and second Schottky metal layers, the threshold voltage of the first transistor is made lower than the threshold voltage of the second transistor, which simplifies the process and is easy to implement.

[0018] In one possible implementation, the difference between the work function of the second Schottky metal layer and the work function of the first Schottky metal layer is in the range of 0.1 eV to 0.4 eV. By setting the work function difference in the range of 0.1 eV to 0.4 eV, the difficulty of material selection can be reduced.

[0019] In one possible implementation, the first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; the first barrier layer includes a first gate metal diffusion region in contact with the first gate Schottky layer; the second barrier layer includes a second gate metal diffusion region in contact with the second gate Schottky layer; and the third thickness of the first gate metal diffusion region is less than the fourth thickness of the second gate metal diffusion region. By varying the thicknesses of the first and second gate metal diffusion regions, the threshold voltage of the first transistor is made lower than the threshold voltage of the second transistor, resulting in a simple process and easy implementation.

[0020] In one possible implementation, the difference between the fourth thickness and the third thickness ranges from 1 nm to 6 nm. Setting the difference between the fourth thickness and the third thickness within the range of 1 nm to 6 nm can meet the different threshold voltage requirements of the first transistor and the second transistor with lower process difficulty.

[0021] In one possible implementation, a first gate length of the first gate is smaller than a second gate length of the second gate. By changing the gate lengths of the first gate and the second gate, the threshold voltage of the first transistor is made smaller than the threshold voltage of the second transistor. This is a simple process and easy to implement.

[0022] In one possible implementation, the difference between the second gate length and the first gate length ranges from 0.1 μm to 1 μm. Setting the difference between the second gate length and the first gate length within the range of 0.1 μm to 1 μm can meet the different threshold voltage requirements of the first transistor and the second transistor with lower process difficulty.

[0023] In one possible implementation, the source pad includes a first pad and a second pad, the first source is coupled to the first pad, and the second source is coupled to the second pad. Depending on the layout requirements of the semiconductor structure, one or more source pads can be provided, and multiple pads can be coupled or uncoupled, providing a flexible layout for the semiconductor structure and a wide range of applications.

[0024] In one possible implementation, a semiconductor structure includes a plurality of first transistors and a plurality of second transistors; along a first direction, the first gates of the plurality of first transistors are arranged sequentially, the first sources and the first drains are arranged alternately, and the first gates are located above the gaps between adjacent first sources and first drains; along the first direction, the second gates of the plurality of second transistors are arranged sequentially, the second sources and the second drains are arranged alternately, and the second gates are located above the gaps between adjacent second sources and second drains; the first direction is the length direction of the first gates; along the width direction of the first gates, the gate pads and the drain pads are located on both sides of the first transistors. Since the gate pads and the drain pads generally transmit non-zero voltages, arranging the gate pads and the drain pads on the sides of the regions where the source, drain, and gate are located can reduce the parasitic parameters of the first transistors and the second transistors and optimize the performance of the first transistors and the second transistors.

[0025] In a possible implementation, gaps are provided between the plurality of first transistors and the plurality of second transistors, and the source pads are located above the gaps.

[0026] By placing the source pad in the gap between the plurality of first transistors and the plurality of second transistors, the connection portion of the first source coupling and the connection portion of the second source coupling can be connected to the same source pad, thereby reducing the number of source pads. In addition, to reduce parasitic interference, the size of the gap is larger than the size of the source pad. The larger gap can reduce the manufacturing difficulty of the plurality of first transistors and the plurality of second transistors.

[0027] In a possible implementation, the first pad is located on a side of the first transistor away from the second transistor, and the second pad is located on a side of the second transistor away from the first transistor.

[0028] A first pad is set outside the multiple first transistors, and a second pad is set outside the multiple second transistors. There is no need to reserve a gap corresponding to the source pad between the multiple first transistors and the multiple second transistors. The size of the gap between the multiple first transistors and the multiple second transistors can be reduced, so as to reduce the occupied area of ​​the first transistors and the second transistors and improve the integration of the semiconductor structure.

[0029] In one possible implementation, a first source and a second source are disposed between adjacent first and second gates. Thus, the first transistor and the second transistor do not share a source or drain, and the plurality of first transistors and the plurality of second transistors can be considered as two independent core modules, reducing the difficulty of association.

[0030] In one possible implementation, a first source is provided between adjacent first and second gates, and the first source is reused as the second source; the source pad is located on the side of the first transistor away from the second transistor; or, the source pad is located on the side of the second transistor away from the first transistor. Then, multiple first transistors and multiple second transistors can be considered as a core module. This arrangement can reduce the gap between the first transistor and the second transistor, reduce the occupied area of ​​the semiconductor structure, and improve the integration of the semiconductor structure.

[0031] A second aspect of an embodiment of the present application provides a radio frequency amplifier, comprising a capacitor and the semiconductor structure according to any one of the first aspects; one end of the capacitor is coupled to the input terminal of the radio frequency amplifier, and the other end of the capacitor is coupled to the gate pad; the source pad is coupled to the reference ground voltage terminal, and the drain pad is coupled to the output terminal of the radio frequency amplifier. The radio frequency amplifier provided in the second aspect of the present application includes the semiconductor structure according to the first aspect, and its beneficial effects are the same as those of the semiconductor structure, and are not further described here.

[0032] A third aspect of the present application provides a radio frequency front-end module, comprising: a filter and a low-noise amplifier; the low-noise amplifier comprising the radio frequency amplifier of the second aspect; and a radio frequency input of the radio frequency amplifier coupled to an input of the filter. The radio frequency front-end module provided in the third aspect includes the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure and are not further described here.

[0033] A fourth aspect of the present application provides a communication device comprising the RF front-end module of the third aspect and an antenna, wherein the antenna is coupled to the RF front-end module. The communication device provided in the fourth aspect of the present application comprises the semiconductor structure of the first aspect, and its beneficial effects are the same as those of the semiconductor structure, which are not further described here.

[0034] According to a fifth aspect of the embodiments of the present application, a linear cancellation circuit is provided, comprising: a capacitor, wherein a first terminal of the capacitor is coupled to an input terminal, and a second terminal of the capacitor is coupled to a first node; an amplification module, comprising at least one first transistor, wherein a first gate of the first transistor is coupled to the first node; and a cancellation module, comprising at least one second transistor, wherein a second gate of the second transistor is coupled to the first node; a first source of the first transistor and a second source of the second transistor are both coupled to a reference ground voltage terminal, a first drain of the first transistor is coupled to a second node, a second drain of the second transistor is coupled to a second node, and the second node is coupled to an output terminal; wherein a threshold voltage of the first transistor is less than a threshold voltage of each second transistor, and a sum of widths of the first gate of at least one first transistor is greater than a sum of widths of the second gate of at least one second transistor. The advantageous effects of the linear cancellation circuit provided in the fifth aspect of the present application are the same as the advantageous effects of the semiconductor structure in the first aspect, and are not further elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0036] FIG2 is a schematic structural diagram of a radio frequency front-end module provided in an embodiment of the present application;

[0037] FIG3A is a schematic diagram of a topological structure of a linear cancellation circuit provided in an embodiment of the present application;

[0038] FIG3B is a schematic diagram of gm3 and third-order intermodulation cancellation provided by an embodiment of the present application;

[0039] FIG4 is a schematic diagram of the structure of a linear cancellation circuit provided in an embodiment of the present application;

[0040] 5-7 are schematic diagrams of layouts of a semiconductor structure provided in an embodiment of the present application;

[0041] 8 and 9 are schematic diagrams of layouts of another semiconductor structure provided in an embodiment of the present application;

[0042] 10 to 13 are cross-sectional views taken along the line A1-A2 in FIG. 6 provided in an embodiment of the present application;

[0043] FIG14 is a schematic diagram of gm3 and third-order intermodulation cancellation provided by an embodiment of the present application;

[0044] FIG15A is a schematic diagram of a method for obtaining OIP3 provided in an embodiment of the present application;

[0045] FIG15B is a schematic diagram of an OIP3 curve of an LNA provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0047] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0048] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0049] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0050] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0051] In this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0052] The technical solution of the present application can be applied to various communication devices including power amplifiers. The communication device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted. It can also be deployed on water (such as on ships). It can also be deployed in the air (for example, on aircraft, balloons, and satellites). For example, the channel device can be a terminal, base station, or routing device. For example, the terminal includes but is not limited to: mobile phones, tablet computers, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smart watches, smart bracelets, pedometers, etc.), vehicle-mounted equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed railways, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flight equipment (such as intelligent robots, hot air balloons, drones, airplanes), RF front-end modules, etc.

[0053] Figure 1 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application, using a mobile phone as an example. The communication device includes a radio frequency (RF) front-end module 101, a memory 102, a processor 103, a sensor component 104, a multimedia component 105, a power supply component 106, and an input / output interface 107.

[0054] The following is a detailed introduction to the various components of the mobile phone in conjunction with Figure 1:

[0055] The RF front-end module 101 can be used to receive and send signals during information transmission or calls. In particular, after receiving downlink information from the communication device, it is sent to the processor 103 for processing, and uplink data is sent to the communication device.

[0056] The memory 102 may be used to store data, software programs, and modules. The mobile phone may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0057] The processor 103 is the control center of the mobile phone. It uses various interfaces and lines to connect various parts of the entire device. By running or executing software programs and / or modules stored in the memory 102 and calling data stored in the memory 102, it performs various functions of the mobile phone and processes data, thereby monitoring the mobile phone as a whole.

[0058] Sensor assembly 104 includes one or more sensors for assessing various aspects of the phone's status. Sensor assembly 104 may include an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, or a temperature sensor. Sensor assembly 104 can detect the phone's acceleration / deceleration, orientation, open / closed state, relative positioning of components, or temperature changes. Sensor assembly 104 may also include a light sensor for use in imaging applications.

[0059] The multimedia component 105 provides a screen as an output interface between the mobile phone and the user. The screen may be a touch panel, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. In addition, the multimedia component 105 also includes at least one camera, for example, the multimedia component 105 includes a front camera and / or a rear camera.

[0060] The power supply component 106 is used to provide power to various components of the mobile phone. The power supply component 106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the mobile phone.

[0061] The input / output interface 107 provides an interface between the processor 103 and a peripheral interface module, for example, the peripheral interface module may be a keyboard, a mouse, etc.

[0062] Although not shown, the mobile phone may further include an audio component and a communication module, for example, the audio component includes a microphone and a speaker, and the communication module may include one or more of a wireless fidelity (WiFi) module, a Bluetooth module, a near field communication (NFC) module, a global navigation satellite system (GNSS) module, or a frequency modulation (FM) module, which will not be described in detail in the embodiments of the present application. Those skilled in the art will understand that the mobile phone structure shown in FIG1 does not constitute a limitation on the mobile phone, and may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0063] FIG2 is a schematic structural diagram of a radio frequency front-end module provided in an embodiment of the present application.

[0064] Exemplarily, as shown in FIG2 , the RF front-end module 101 includes but is not limited to a RF switch, a duplexer, a filter, a power amplifier (PA), a low noise amplifier (LNA), and the like.

[0065] The RF front-end module 101 may include a transmitter (TX) and a receiver (RX). The transmitter TX includes a PA and a filter. The PA's RF input is coupled to a digital-to-analog converter (DAC), and the PA's RF output is coupled to the filter's input. The receiver includes an LNA and a filter. The filter's output is coupled to the LNA's RF input, and the LNA's RF output is coupled to an analog-to-digital converter (ADC).

[0066] The duplexer is responsible for duplex switching of the frequency division duplex system and filtering of the RF signals of the transmit channel TX / receive channel RX, while the RF switch is responsible for switching between the transmit channel TX and the receive channel RX.

[0067] The baseband signal is transmitted by the transceiver to the transmit channel TX. The transmit channel TX amplifies the received RF signal and outputs it to the antenna for transmission. The PA is responsible for amplifying the RF signal of the transmit channel TX, and the filter is responsible for filtering the RF signal of the transmit channel TX.

[0068] It should be explained that when an electronic device includes multiple antennas, one antenna may correspond to one PA, one antenna may correspond to multiple PAs, or multiple antennas may share one PA. The application scenarios in the relevant technologies are all applicable to the embodiments of this application.

[0069] The RX channel receives the RF signal from the antenna, amplifies it, and transmits it to the baseband via the transceiver. The LNA amplifies the RX RF signal, while the filter filters it.

[0070] The antenna frequencies applicable to the embodiments of the present application may include sub6G bands and other bands with relatively high bandwidth requirements. Of course, other bands such as sub3G bands and Wi-Fi bands (such as 2.4G bands, 5G bands, and 6G bands) may also be applicable.

[0071] In the RF front-end module 101, the transmit channel TX and the receive channel RX operate at different frequencies and share antennas through a duplexer. To reduce the impact of signals leaking from the transmit channel TX into the receive channel RX on receiver sensitivity, the linearity of the LNA should be maximized.

[0072] FIG3A is a schematic diagram of a topological structure of a linear cancellation circuit provided in an embodiment of the present application.

[0073] In the art, there are many methods to improve LNA linearity, and circuit linear cancellation design is a simple and effective means. As shown in Figure 3A, the linear cancellation circuit includes a first transistor M1, a second transistor M2, a first capacitor C1, and a second capacitor C2.

[0074] The first transistor M1 includes a first gate G1, a first source S1, and a first drain D1. The second transistor M2 includes a second gate G2, a second source S2, and a second drain D2. A first capacitor C1 is coupled between the LNA's RF input RFi and the first gate G1, while a second capacitor C2 is coupled between the LNA's RF input RFi and the second gate G2. Both the first source S1 and the second source S2 are coupled to the reference ground voltage GND. The first drain D1 and the second drain D2 are coupled to the LNA's RF output RFo after being combined at node A. The first transistor M1 functions as a main amplifier, while the second transistor M2 functions as a cancellation transistor.

[0075] The voltage of the first gate G1 of the first transistor M1 is Vg1, and the voltage of the second gate G2 of the second transistor M2 is Vg2. By controlling the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2, the first transistor M1 and the second transistor M2 can be placed in different bias states, and the first transistor M1 and the second transistor M2 can generate completely equal and opposite intermodulation signals. The first transistor M1 and the second transistor M2 are connected in parallel, and the intermodulation signal generated by the first transistor M1 and the intermodulation signal generated by the second transistor M2 are canceled at node A and output from the RF output terminal RFo.

[0076] FIG3B is a schematic diagram of gm3 and third-order intermodulation cancellation provided in an embodiment of the present application.

[0077] Taking the third-order intermodulation distortion (IM3) signal as an example, the IM3 signal is related to the third-order transconductance (gm3) of the transistor. As shown in Figure 3B, the horizontal axis is the gate voltage and the vertical axis is the third-order transconductance of the transistor. The dotted line is the third-order transconductance curve gm3 of the first transistor M1. M1 The dotted line is the third-order transconductance curve gm3 of the second transistor M2 M2The solid line is the comprehensive third-order transconductance curve gm3 after the first transistor M1 and the second transistor M2 are combined. M1 +gm3 M2 In the cancellation effective region (usually the range of the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2 when the LNA is operating normally), the two equal and opposite third-order intermodulation signals generated by the first transistor M1 and the second transistor M2 are canceled, thereby improving the linearity of the LNA.

[0078] Although the design principle of the linear cancellation circuit is relatively simple, many problems may be encountered during actual application. Controlling the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2 is the most critical step in achieving the cancellation goal.

[0079] As shown in Figure 3A, one control method is to connect a first voltage source to the first gate G1 and a second voltage source to the second gate G2. The first and second voltage sources precisely control the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2. However, in practice, two additional power supply voltages are required, which increases system cost.

[0080] Another approach uses on-chip voltage divider resistors to provide two different gate voltages from one voltage source, thus reducing the supply voltage. However, the resistors commonly used on chips in the industry currently have large temperature coefficients, resulting in designs using voltage divider resistors being significantly affected by ambient temperature. At high and low temperatures, the voltage Vg1 of the first gate G1 and the voltage Vg2 of the second gate G2 may deviate from the optimal cancellation operating point, causing the cancellation effect to weaken, disappear, or even deteriorate.

[0081] In addition, the actual effect of the linear cancellation design shown in FIG. 3A is also affected by the process consistency of the first transistor M1 and the second transistor M2 , so the device yield is low.

[0082] The embodiments of the present application provide a linear cancellation circuit. This linear cancellation circuit can be applied to the aforementioned LNA. The linear cancellation circuit can also be applied to any radio frequency amplifier requiring high linearity. When the radio frequency amplifier provided by this application is applied to a communication device provided by an embodiment of this application, the communication device can be any communication device requiring a high linearity radio frequency amplifier. The linear cancellation circuit provided by the embodiments of this application is not limited to application in LNAs or communication devices including LNAs; the above description uses LNAs as an example.

[0083] FIG4 is a schematic diagram of the structure of a linear cancellation circuit provided in an embodiment of the present application.

[0084] As shown in FIG4 , the linear cancellation circuit includes a capacitor C, an amplification module, and a cancellation module.

[0085] A first terminal of capacitor C is coupled to the input terminal I of the linear cancellation circuit, and a second terminal of capacitor C is coupled to the first node A1. Capacitor C is used to block DC signals and pass AC signals. Capacitor C can be understood as a DC blocking capacitor.

[0086] The amplifying module includes at least one first transistor M1. Figure 4 shows an example of an amplifying module including one first transistor M1. Each first transistor M1 includes a first gate G1, a first source S1, and a first drain D1. The first gate G1 of the first transistor M1 is coupled to a first node A1.

[0087] The cancellation module includes at least one second transistor M2. The amplification module includes one second transistor M2 as an example in Figure 4. Each second transistor M2 includes a second gate G2, a second source S2, and a second drain D2. The second gate G2 of the second transistor M2 is also coupled to the first node A1.

[0088] The first source S1 of the first transistor M1 and the second source S2 of the second transistor M2 are both coupled to the reference ground voltage terminal GND. For example, the first source S1 and the second source S2 are both coupled to a third node A3, which is then coupled to the reference ground voltage terminal GND. Alternatively, for example, the first source S1 is coupled to the reference ground voltage terminal GND, and the second source S2 is also coupled to the reference ground voltage terminal GND, but the first source S1 and the second source S2 are not coupled to each other. In the embodiment of the present application, the coupling of the first source S1 and the second source S2 is used as an example for illustration.

[0089] The first drain D1 of the first transistor M1 is coupled to the second node A2. The second drain D2 of the second transistor M2 is also coupled to the second node A2. The second node A2 is coupled to the output terminal O of the linear cancellation circuit D.

[0090] In other words, the first transistor M1 and the second transistor M2 are coupled in parallel, and the first gate G1 of the first transistor M1 and the second gate G2 of the second transistor M2 both receive the bias voltage of the first node A1. That is, the voltage Vg1 of the first gate G1 is equal to the voltage Vg2 of the second gate G2.

[0091] However, the threshold voltage (Vth) of each first transistor M1 is smaller than the threshold voltage of each second transistor M2. For example, the difference between the threshold voltage of the first transistor M1 and the threshold voltage of the second transistor M2 is greater than 0.1V.

[0092] For example, the cancellation module includes a plurality of second transistors M2, the threshold voltages of the plurality of second transistors M2 are equal, and the threshold voltages of the plurality of first transistors M1 are equal. Then, the threshold voltage of the first transistor M1 is lower than the threshold voltage of the second transistor M2.

[0093] Alternatively, for example, the cancellation module includes multiple second transistors M2 with unequal threshold voltages and the multiple first transistors M1 with equal threshold voltages. Then, the threshold voltage of the first transistor M1 is lower than the smallest threshold voltage of the multiple second transistors M2.

[0094] In some embodiments, the amplification module includes a plurality of first transistors M1, and the threshold voltages of the plurality of first transistors M1 are equal. The threshold voltages can be used to distinguish the first transistors M1 and the second transistors M2 in the linear cancellation circuit.

[0095] Furthermore, the sum of widths of the first gate G1 of the at least one first transistor M1 is greater than the sum of widths of one or more second gates G2 of the at least one second transistor M2 having the same threshold voltage.

[0096] The sum of the gate widths of at least one first transistor M1 (the sum of the widths of the first gate G1) can be understood as follows: when the amplification module includes one first transistor M1, the width of the first gate G1 of the first transistor M1 is the sum of the widths of the first gate G1 of the at least one first transistor M1. When the amplification module includes multiple first transistors M1, the sum of the widths of the multiple first transistors M1 is the sum of the widths of the first gate G1 of the at least one first transistor M1.

[0097] Similarly, the sum of the gate widths of one or more second transistors M2 with the same threshold voltage (the sum of the widths of the second gates G2) in the at least one second transistor M2 can be understood as follows: when the amplification module includes one second transistor M2, the width of the second gate G2 of the second transistor M2 is the sum of the widths of the one or more second gates G2 with the same threshold voltage. When the amplification module includes multiple second transistors M2, when the threshold voltages of the multiple second transistors M2 are the same, the sum of the widths of the second gates G2 of the multiple second transistors M2 is the sum of the widths of the one or more second gates G2 with the same threshold voltage. The sum of the widths of the first gate G1 of at least one first transistor M1 is greater than the sum of the widths of the second gates G2 of the multiple second transistors M2. When the threshold voltages of the multiple second transistors M2 are different, the sum of the widths of the second gates G2 of the one or more second transistors M2 with the same threshold voltage is a value of a sum of widths, and the value of each width sum is less than the sum of the widths of the first gate G1 of the at least one first transistor M1. However, the sum of the multiple widths is not necessarily smaller than the sum of the widths of the first gate G1 of at least one first transistor M1 .

[0098] In some embodiments, the first transistor M1 and the second transistor M2 are high electron mobility transistors (HEMTs).

[0099] In some other embodiments, the first transistor M1 and the second transistor M2 are pseudomorphic high electron mobility transistors (pHEMTs).

[0100] The structures of the amplification module and the cancellation module in the linear cancellation circuit are schematically described below.

[0101] 5-7 are schematic diagrams of the layout of a semiconductor structure provided in an embodiment of the present application.

[0102] The present invention also provides a semiconductor structure that can be used in the radio frequency amplifier provided in the present invention. As shown in FIG5 , the semiconductor structure includes a gate pad G, a source pad S, a drain pad D, at least one first transistor M1, and at least one second transistor M2. The gate pad G, source pad S, drain pad D, at least one first transistor M1, and at least one second transistor M2 can be disposed on a substrate, for example.

[0103] 5 is illustrated by taking a semiconductor structure including ten first transistors M1 and six second transistors M2 as an example. The number of first transistors M1 in the semiconductor structure can be determined by the number of first gates G1, and the number of second transistors M2 in the semiconductor structure can be determined by the number of second gates G2.

[0104] Each first transistor M1 includes a first gate G1, a first source S1, and a first drain D1. The first gate G1 is coupled to the gate pad G, the first source S1 is coupled to the source pad S, and the first drain D1 is coupled to the drain pad D. If the semiconductor structure includes multiple first transistors M1, the multiple first transistors M1 are equivalent to being coupled in parallel.

[0105] Each second transistor M2 includes a second gate G2, a second source S2, and a second drain D2. The second gate G2 is coupled to the gate pad G, the second source S2 is coupled to the source pad S, and the second drain D2 is coupled to the drain pad D. If the semiconductor structure includes multiple second transistors M2, the multiple second transistors M2 are equivalent to being coupled in parallel.

[0106] In addition, the first gate G1 and the second gate G2 are both coupled to the gate pad G, the first source S1 and the second source S2 are both coupled to the source pad S, and the first drain D1 and the second drain D2 are both coupled to the drain pad D. Therefore, it is equivalent to the first transistor M1 and the second transistor M2 being coupled in parallel. That is, in the semiconductor structure, at least one first transistor M1 and at least one second transistor M2 are coupled in parallel. If the semiconductor structure includes multiple first transistors M1, the multiple first transistors M1 are also coupled in parallel. If the semiconductor structure includes multiple second transistors M2, the multiple second transistors M2 are also coupled in parallel.

[0107] In some embodiments, the first gate G1 and the second gate G2 are fabricated from the same layer and material in the same process, the first source S1 and the second source S2 are fabricated from the same layer and material in the same process, and the first drain D1 and the second drain D2 are fabricated from the same layer and material in the same process. For example, the first source S1 and the first drain D1 can also be fabricated from the same layer and material in the same process.

[0108] For example, multiple first gates G1 and multiple second gates G2 are directly coupled in parallel at the layer where the gates are located, and then transferred to the gate pad G through vias. Multiple first drains D1 and multiple second drains D2 are directly coupled in parallel at the layer where the drains are located, and then transferred to the drain pad D through vias. Multiple first sources S1 are transferred to other layers through vias (small boxes within the projection of the first source S1), and coupled with the connecting parts (dashed boxes) located in other layers to achieve parallel coupling of multiple first sources S1. Similarly, multiple second sources S2 are transferred to other layers through vias (small boxes within the projection of the second source S2), and coupled with the connecting parts (dashed boxes) located in other layers to achieve parallel coupling of multiple second sources S2. Then, the transfer part is transferred to the source pad S through a via.

[0109] In some embodiments, as shown in FIG. 5 and FIG. 6 , the semiconductor structure includes a source pad S, and the first source S1 and the second source S2 are both coupled to the source pad S.

[0110] In other embodiments, as shown in FIG7 , the source pad S includes a first pad S-1 and a second pad S-2, with the first source S1 coupled to the first pad S-1, and the second source S2 coupled to the second pad S-2. Of course, although the semiconductor structure includes the first pad S-1 and the second pad S-2, the first source S1 and the second source S2 are not coupled. However, the first pad S-1 and the second pad S-2 are coupled to voltage terminals that transmit the same signal, and ultimately the first source S1 and the second source S2 receive the same source bias voltage, which is equivalent to the first source S1 and the second source S2 being coupled. For example, the first pad S-1 and the second pad S-2 are both coupled to the reference ground voltage terminal GND, and ultimately the first source S1 and the second source S2 both receive the reference ground voltage of the reference ground voltage terminal GND.

[0111] Of course, the above-mentioned diagrams of the gate pad G, source pad S and drain pad D are only for illustration and are not intended to limit the above-mentioned operation. The first gate G1 and the second gate G2 receive the same gate bias voltage, the first source S1 and the second source S2 receive the same source bias voltage, and the intermodulation signal output by the first drain D1 and the intermodulation signal output by the second drain D2 are canceled.

[0112] In some embodiments, as shown in FIG5 , the first direction X is the length of the first gate G1, which is also the direction from the first source S1 to the first drain D1. The second direction Y is the width of the first gate G1. The first gate G1 and the second gate G2 are arranged along the first direction X, or it can be understood that the first gate G1 and the second gate G2 are adjacently arranged along the first direction X.

[0113] In some embodiments, the semiconductor structure includes a plurality of first transistors M1 and a plurality of second transistors M2 .

[0114] The first gates G1 of the plurality of first transistors M1 are sequentially arranged along the first direction X. For example, the plurality of first gates G1 are arranged along the first direction X at equal intervals.

[0115] The second gates G2 of the plurality of second transistors M2 are sequentially arranged along the first direction X. For example, the plurality of second gates G2 are arranged along the first direction X at equal intervals.

[0116] Overall, the plurality of first gates G1 and the plurality of second gates G2 are arranged along the first direction X. As shown in FIG5 , the plurality of first gates G1 are distributed in the first region, and the plurality of second gates G2 are distributed in the second region. Alternatively, the first gates G1 and the second gates G2 may be arranged in a mixed manner, which is merely an example in the present embodiment.

[0117] Continuing with FIG5 , in some embodiments, the first source electrodes S1 and the first drain electrodes D1 are alternately arranged along the first direction X. The projection of the first gate electrode G1 on the substrate is located between the projection of the adjacent first source electrode S1 and the projection of the adjacent first drain electrode D1 on the substrate. For example, the first gate electrode G1 is located above the gap between the adjacent first source electrode S1 and the adjacent first drain electrode D1.

[0118] Then, two adjacent first transistors M1 share a first source S1 or a first drain D1. The number of first sources S1 is less than the number of first gates G1, and the number of first drains D1 is also less than the number of first gates G1. Taking Figure 5 as an example, from left to right, the first first transistor M1 and the second first transistor M1 share a first drain D1, and the second first transistor M1 and the third first transistor M1 share a first source S1. Of course, the first sources S1 and the first drains D1 are arranged alternately. From left to right, as shown in Figure 5, the first source S1 can be arranged first, followed by the first drain D1. Alternatively, the first drain D1 can be arranged first, followed by the first source S1.

[0119] In some embodiments, the second source electrodes S2 and the second drain electrodes D2 are alternately arranged along the first direction X. The projection of the second gate electrode G2 on the substrate is located between the projection of the adjacent second source electrode S2 and the projection of the second drain electrode D2 on the substrate. For example, the second gate electrode G2 is located above the gap between the adjacent second source electrode S2 and the second drain electrode D2.

[0120] Then, two adjacent second transistors M2 share a second source S2 or a second drain D2. The number of second sources S2 is less than the number of second gates G2, and the number of second drains D2 is also less than the number of second gates G2. Taking Figure 5 as an example, from left to right, the first second transistor M2 and the second second transistor M2 share a second drain D2, and the second second transistor M2 and the third second transistor M2 share a second source S2. Of course, the second source S2 and the second drain D2 are arranged alternately. From left to right, the second source S2 can be arranged first, followed by the second drain D2 as shown in Figure 5. Alternatively, the second drain D2 can be arranged first, followed by the second source S2.

[0121] In some embodiments, the width of each first gate G1 is equal. In some embodiments, the width of each second gate G2 is equal. In some embodiments, the width of the first gate G1 is equal to the width of the second gate G2. This simplifies the design and reduces the difficulty of the process.

[0122] In some embodiments, along the second direction Y, the gate pad G and the drain pad D are located on both sides of the first transistor M1. Of course, the specific positions of the gate pad G and the drain pad D are not limited in the embodiments of the present application. Taking the gate pad G as an example, along the second direction Y, the gate pad G can be located on one side of the first gate G1. However, when viewed from the first direction X, the gate pad G can be located near the first region where the multiple first gates G1 are arranged, the gate pad G can also be located near the second region where the multiple second gates G2 are arranged, or the gate pad G can be located between the first region and the second region.

[0123] Since the gate pad G and the drain pad D usually transmit a non-zero voltage, setting the gate pad G and the drain pad D on the sides of the source, drain, and gate areas can reduce the parasitic parameters of the first transistor M1 and the second transistor M2 and optimize the performance of the first transistor M1 and the second transistor M2.

[0124] 5 , a gap exists between the plurality of first transistors M1 and the plurality of second transistors M2, and a projection of the source pad S on the substrate is located within the gap. For example, from a cross-sectional view, the source pad S may be located above the gap.

[0125] In other words, the plurality of first transistors M1 and the plurality of second transistors M2 are two separate arrangement blocks, and the two only share the gate pad G, the source pad S, and the drain pad D.

[0126] Then, the first transistor M1 and the second transistor M2 do not share a source or drain. Taking Figure 5 as an example, a first source S1 and a second source S2 are provided between the adjacent first gate G1 and the second gate G2, and there is a gap between the first source S1 and the second source S2. Of course, depending on the arrangement, a first drain D1 and a second drain D2 may also be provided between the adjacent first gate G1 and the second gate G2. Alternatively, a first source S1 and a second drain D2 may also be provided between the adjacent first gate G1 and the second gate G2. Alternatively, a first drain D1 and a second source S2 may also be provided between the adjacent first gate G1 and the second gate G2.

[0127] By disposing the source pad S in the gap between the plurality of first transistors M1 and the plurality of second transistors M2, the connection portion coupled to the first source S1 and the connection portion coupled to the second source S2 can be connected to the same source pad S, thereby reducing the number of source pads S. In addition, to reduce parasitic interference, the size of the gap is larger than the size of the source pad S. The larger gap can reduce the manufacturing difficulty of the plurality of first transistors M1 and the plurality of second transistors M2.

[0128] In other embodiments, as shown in Figure 6, there is a gap between the multiple first transistors M1 and the multiple second transistors M2, and the source pad S includes a first pad S-1 and a second pad S-2, the first pad S-1 is located on the side of the first transistor M1 away from the second transistor M2, and the second pad S-2 is located on the side of the second transistor M2 away from the first transistor M1.

[0129] A first pad S-1 is set outside the multiple first transistors M1, and a second pad S-2 is set outside the multiple second transistors M2. There is no need to reserve a gap corresponding to the source pad S between the multiple first transistors M1 and the multiple second transistors M2. The size of the gap between the multiple first transistors M1 and the multiple second transistors M2 can be reduced, so as to reduce the occupied area of ​​the first transistors M1 and the second transistors M2 and improve the integration of the semiconductor structure.

[0130] In some other embodiments, as shown in FIG. 7 , a first source S1 is disposed between the adjacent first gate G1 and the second gate G2 , and the first source S1 is reused as the second source S2 .

[0131] Alternatively, a first source S1 is provided between the adjacent first gate G1 and the second gate G2, and the first drain D1 is reused as the second drain D2.

[0132] Then, it is equivalent to saying that the multiple first transistors M1 and the multiple second transistors M2 can be regarded as an integral block.

[0133] Multiple gates are arranged sequentially along a first direction X, with some serving as first gates G1 and the remaining serving as second gates G2. Multiple sources and drains are arranged alternately along the first direction, with the source and drain located on either side of the first gate G1 serving as the first source S1 and first drain D1, and the source and drain located on either side of the second gate G2 serving as the second source S2 and second drain D2. If a source exists between adjacent first gates G1 and G2, the first and second gates G1 and G2 share the same source. If a drain exists between adjacent first gates G1 and G2, the first and second gates G1 and G2 share the same drain.

[0134] For example, the source pad S is located on the side of the first transistor M1 away from the second transistor M2. Alternatively, for example, the source pad S is located on the side of the second transistor M2 away from the first transistor M1. Since there is no reserved gap between the first transistor M1 and the second transistor M2, the source pad S can only be arranged along the first direction X on the side of the first transistor M1 and the second transistor M2.

[0135] This arrangement can reduce the gap between the first transistor M1 and the second transistor M2, reduce the occupied area of ​​the semiconductor structure, and improve the integration of the semiconductor structure.

[0136] The above is an illustration of the design of the first transistor M1 and the second transistor M2 . The physical characteristics of the first transistor M1 and the second transistor M2 are described below.

[0137] In some embodiments, the sum of widths of the first gate G1 of at least one first transistor M1 is greater than the sum of widths of the second gate G2 of at least one second transistor M2 having the same threshold voltage.

[0138] The sum of the widths of the first gate G1 of at least one first transistor M1 can be understood as follows: when the amplification module includes one first transistor M1, the width of the first gate G1 of the first transistor M1 is the sum of the widths of the first gate G1 of the at least one first transistor M1. When the amplification module includes multiple first transistors M1, the sum of the widths of the multiple first transistors M1 is the sum of the widths of the first gate G1 of the at least one first transistor M1.

[0139] Similarly, the sum of the widths of the second gate G2 of at least one second transistor M2 with the same threshold voltage can be understood as follows: when the amplification module includes one second transistor M2, the width of the second gate G2 of the second transistor M2 is the sum of the widths of the second gate G2 of the at least one second transistor M2. When the amplification module includes multiple second transistors M2, and the multiple second transistors M2 have the same threshold voltage, the sum of the widths of the first gate G1 of at least one first transistor M1 is greater than the sum of the widths of the second gate G2 of the multiple second transistors M2. When the multiple second transistors M2 have different threshold voltages, the sum of the widths of the second transistors M2 for each threshold voltage is less than the sum of the widths of the first gate G1 of the at least one first transistor M1.

[0140] The width of the first gate G1 is the size of the first gate G1 along the second direction Y, and the sum of the widths of the plurality of first gates G1 is the sum of the sizes of the plurality of first gates G1 along the second direction Y.

[0141] In some embodiments, the semiconductor structure includes a plurality of first transistors M1 connected in parallel and a plurality of second transistors M2 connected in parallel.

[0142] When the total gate width is fixed, multiple transistors with small gate widths have better RF performance than a transistor with a large gate width and are less difficult to process.

[0143] In some embodiments, a threshold voltage of the first transistor M1 is less than a threshold voltage of each of the second transistors M2 .

[0144] For example, when the semiconductor structure includes a plurality of first transistors M1 , the threshold voltages of the plurality of first transistors M1 are the same.

[0145] For example, the semiconductor structure includes a second transistor M2 , and a threshold voltage of the first transistor M1 is lower than a threshold voltage of the second transistor M2 .

[0146] Alternatively, for example, the semiconductor structure includes a plurality of second transistors M2.

[0147] For example, if the threshold voltages of the plurality of second transistors M1 are the same, the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistor M2. Optionally, the width of the first gate G1 is equal to the width of the second gate G2, and the number of at least one first transistor M1 (i.e., the total number of first transistors M1) is greater than the number of at least one second transistor M2 (i.e., the total number of second transistors M2).

[0148] For example, if the threshold voltages of the second transistors M2 are different, the threshold voltage of the first transistor M1 is lower than the threshold voltage of each second transistor M2 , that is, the threshold voltage of the first transistor M1 is lower than the minimum threshold voltage of the second transistors M2 .

[0149] 8 and 9 are schematic diagrams of the layout of another semiconductor structure provided in an embodiment of the present application.

[0150] In some embodiments, as shown in FIG. 8 , the plurality of second transistors M2 include a first group of second transistors M2 and a second group of second transistors M2 , and the threshold voltage of the second transistors M2 in the first group is different from the threshold voltage of the second transistors M2 in the second group.

[0151] Then, the threshold voltage of the first transistor M1 is lower than the threshold voltage of the second transistor M2 in the first group, and the threshold voltage of the first transistor M1 is also lower than the threshold voltage of the second transistor M2 in the second group.

[0152] Of course, the plurality of second transistors M2 may further include a third group or more groups of second transistors M2 , and the threshold voltages of the second transistors M2 in each group are different.

[0153] The embodiment of the present application does not limit the number of second transistors M2 included in each group. The number of second transistors M2 in each group is related to the threshold voltage of the second transistors M2 in the group.

[0154] For example, as shown in FIG8 , the semiconductor structure includes ten first transistors M1 and three groups of second transistors M2 .

[0155] The first group includes three second transistors M2, and the difference between the threshold voltage of the second transistors M2 in the first group and the threshold voltage of the first transistor M1 is 0.12 V. The second group includes one second transistor M2, and the difference between the threshold voltage of the second transistor M2 in the second group and the threshold voltage of the first transistor M1 is 0.16 V. The third group includes four second transistors M2, and the difference between the threshold voltage of the second transistor M2 in the third group and the threshold voltage of the first transistor M1 is 0.22 V.

[0156] Alternatively, for example, as shown in FIG9 , the semiconductor structure includes ten first transistors M1 and three groups of second transistors M2 .

[0157] The first group includes four second transistors M2, and the difference between the threshold voltage of the second transistors M2 in the first group and the threshold voltage of the first transistor M1 is 0.22 V. The second group includes two second transistors M2, and the difference between the threshold voltage of the second transistors M2 in the second group and the threshold voltage of the first transistor M1 is 0.32 V. The third group includes four second transistors M2, and the difference between the threshold voltage of the second transistors M2 in the third group and the threshold voltage of the first transistor M1 is 0.42 V.

[0158] Of course, the embodiment of the present application does not limit the grouping of the plurality of second transistors M2. The plurality of second transistors M2 can be divided into multiple groups, and the threshold voltages of the second transistors M2 in different groups can be different. The number of second transistors M2 included in each group is also not limited, and can be set in combination with the threshold voltage adaptability of the second transistor M2. In addition, the second transistors M2 belonging to the same group are not limited to being arranged adjacent to each other in sequence. Figures 8 and 9 are only a schematic diagram. Whether the second transistor M2 belongs to the same group is determined by the threshold voltage of the second transistor M2, rather than by position. Similarly, the threshold voltage is used to determine whether it is the first transistor M1 or the second transistor M2, rather than the position.

[0159] By configuring a variety of second transistors M2 with different threshold voltages, a relatively good cancellation effect can be achieved across a certain region. This increases the width of the cancellation zone, thereby improving tolerance to environmental conditions such as process fluctuations and temperature, thereby enhancing process consistency during the semiconductor structure production process. Furthermore, by configuring second transistors M2 with different threshold voltages and configuring different numbers of second transistors M2, the linearity of the RF amplifier can be improved within a drain current range of 40mA / mm to 120mA / mm.

[0160] When the second transistors M2 are divided into multiple groups, the sum of the widths of the first gates G1 of the first transistors M1 is greater than the sum of the widths of the second gates G2 of the second transistors M2 in the first group. The sum of the widths of the first gates G1 of the first transistors M1 is also greater than the sum of the widths of the second gates G2 of the second transistors M2 in the second group. However, the sum of the widths of the first gates G1 of the first transistors M1 is not necessarily greater than the sum of the widths of the second gates G2 of all the second transistors M2.

[0161] For example, as shown in Figures 8 and 9, the number of at least one first transistor M1 (that is, the total number of first transistors M1) is greater than the number of second transistors M2 in the first group, greater than the number of second transistors M2 in the second group, and greater than the number of second transistors M2 in the third group. However, as shown in Figure 9, the total number of first transistors M1 is not necessarily greater than the total number of second transistors M2. The total number of first transistors M1 may be greater than, equal to, or less than the total number of second transistors M2.

[0162] In an embodiment of the present application, the semiconductor structure includes a first transistor M1 and a second transistor M2, wherein the width of the first gate G1 of the first transistor M1 affects the amplitude of the total signal transmitted by the first transistor M1 (including the main signal and the negative intermodulation signal), and the width of the second gate G1 of the second transistor M2 affects the amplitude of the total signal transmitted by the second transistor M2 (including the main signal and the positive intermodulation signal). The threshold voltages of the first transistor M1 and the second transistor M2 affect the phase of the intermodulation signal output by the first transistor M1 and the second transistor M2 under the condition of the same gate voltage. In the present application, the first gate G1 and the second gate G2 are both coupled to the gate pad G and receive the same gate bias voltage. Under the same gate bias voltage, the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistor M2, so the first transistor M1 provides a negative intermodulation signal and the second transistor M2 provides a positive intermodulation signal. Although the positive intermodulation signal provided by the transistor under the same conditions will be greater than the negative intermodulation signal, in this application, the width of the first gate G1 is always set to be greater than the sum of the widths of the second gate G2, so that the first transistor M1 and the second transistor M2 can output two sets of equal and opposite intermodulation signals to achieve cancellation. Therefore, the embodiment of the present application adopts a design with different threshold voltages to achieve the effect of cancellation by providing the same gate bias voltage to the first transistor M1 and the second transistor M2. The design complexity of the semiconductor structure is low, the structure is simple, and the occupied area is small. In addition, the stability of the threshold voltage difference is used to control the gate bias state, and the cancellation effect is stable.

[0163] The following is a schematic illustration of a method for achieving different threshold voltages of the first transistor M1 and the second transistor M2.

[0164] 10-13 are cross-sectional views taken along the line A1-A2 in FIG. 6 provided in an embodiment of the present application.

[0165] In some embodiments, as shown in FIG10 , the first transistor M1 further includes a first substrate 11 and a first channel layer 12 and a first barrier layer 13 sequentially stacked on the first substrate 11, wherein the first channel layer 12 and the first barrier layer 13 form a heterojunction. The second transistor M2 further includes a second substrate 21 and a second channel layer 22 and a second barrier layer 23 sequentially stacked on the second substrate 21, wherein the second channel layer 22 and the second barrier layer 23 form a heterojunction.

[0166] For example, the first substrate 11 and the second substrate 21 are integrally formed structures, the first channel layer 12 and the second channel layer 22 are integrally formed structures, and the first barrier layer 13 and the second barrier layer 23 are integrally formed structures.

[0167] The material of the first substrate 11 is, for example, a silicon (Si) substrate or a silicon carbide (SiC) substrate.

[0168] The material of the first channel layer 12 may include, for example, one or more of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), scandium aluminum nitride (ScAlN), and gallium arsenide (GaAs).

[0169] The material of the first barrier layer 13 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, ScAlN, and GaAs.

[0170] In some embodiments, the first barrier layer 13 further includes a first gate metal diffusion region 131. The material of the first gate metal diffusion region 131 is different from that of other regions in the first barrier layer 13. The first gate metal diffusion region 131 is located below the first gate G1 and is in Schottky contact with the first gate G1.

[0171] The first gate G1 is in Schottky contact with the first barrier layer 13 , and the first source S1 and the first drain D1 are in ohmic contact with the first barrier layer 13 .

[0172] The first transistor M1 may be a HEMT device or a pHEMT device. The materials of the first channel layer 12 and the first barrier layer 13 may be different depending on the type of transistor.

[0173] In some embodiments, the material of the first gate G1 may be, for example, Au or Pd.

[0174] In some embodiments, the materials of the first source electrode S1 and the first drain electrode D1 may be, for example, a titanium (Ti) layer, an Al layer, a nickel (Ni) layer, and a gold (Au) layer stacked in sequence, i.e., Ti / Al / Ni / Au. Alternatively, the materials of the first source electrode S1 and the first drain electrode D1 may be a Ti layer, an Al layer, a platinum (Pt) layer, and an Au layer stacked in sequence, i.e., Ti / Al / Pt / Au. Alternatively, the materials of the first source electrode S1 and the first drain electrode D1 may be a Ti layer, a tantalum (Ta) layer, and a Ti layer stacked in sequence, i.e., Ti / Ta / Ti. Alternatively, the materials of the first source electrode S1 and the first drain electrode D1 may be Au or palladium (Pd).

[0175] Of course, the structure of the first transistor M1 in the embodiment of the present application is merely illustrative, and the structures of HEMT devices and pHEMT devices in related technologies are applicable to the first transistor M1 in the embodiment of the present application. For example, the first transistor M1 may also include a nucleation layer, a buffer layer, a cap layer, a field plate, and other structures, which are not limited in the embodiment of the present application.

[0176] The structure of the second transistor M2 can refer to the relevant description of the first transistor M1 and will not be repeated here.

[0177] In some embodiments, the second barrier layer 23 includes a second gate metal contact region 231. The material of the second gate metal contact region 231 is different from that of other regions in the second barrier layer 23. The second gate metal contact region 231 is located below the second gate G2 and is in Schottky contact with the second gate G2.

[0178] The second gate G2 makes Schottky contact with the second barrier layer 23 , and the second source S2 and the second drain D2 make ohmic contact with the second barrier layer 23 .

[0179] In some embodiments, as shown in FIG. 10 , a first thickness H1 of a portion of the first barrier layer 13 in contact with the first gate G1 is greater than a second thickness H2 of a portion of the second barrier layer 23 in contact with the second gate G2 .

[0180] For example, the difference between the first thickness H1 and the second thickness H2 ranges from 1 nm to 6 nm. For example, the difference between the first thickness H1 and the second thickness H2 ranges from 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, and 6 nm.

[0181] When the semiconductor structure includes second transistors M2 with various threshold voltages, the thickness of the second barrier layer 23 contacting different second gates G2 may be different.

[0182] By changing the thickness of the first barrier layer 13 and the second barrier layer 23 , the threshold voltage of the first transistor M1 is made lower than the threshold voltage of the second transistor M2 . This process is simple and easy to implement.

[0183] In other embodiments, as shown in FIG11 , the first gate G1 includes multiple stacked metal layers. FIG11 illustrates an example in which the first gate G1 includes a first Schottky metal layer G1-1 in contact with the first barrier layer 13 and a first upper metal layer G1-2. The second gate G2 includes multiple stacked metal layers. FIG11 illustrates an example in which the second gate G2 includes a second Schottky metal layer G2-1 in Schottky contact with the second barrier layer 23 and a second upper metal layer G2-2.

[0184] The work function of the first Schottky metal layer G1-1 is smaller than the work function of the second Schottky metal layer G2-1. The materials of the first upper metal layer G1-2 and the second upper metal layer G2-2 may be the same or different.

[0185] For example, the difference between the work function of the second Schottky metal layer G2-2 and the work function of the first Schottky metal layer G1-2 ranges from 0.1 eV to 0.4 eV. For example, the difference between the work function of the second Schottky metal layer G2-2 and the work function of the first Schottky metal layer G1-2 ranges from 0.1 eV, 0.15 eV, 0.2 eV, 0.25 eV, 0.3 eV, 0.35 eV, and 0.4 eV.

[0186] For example, the material of the first Schottky metal layer G1-1 is platinum (Pt), and the work function is 5.65 eV. The material of the second Schottky metal layer G2-1 is nickel (Ni), and the work function is 5.15 eV.

[0187] By changing the materials of the first Schottky metal layer G1 - 1 and the second Schottky metal layer G2 - 1 , the threshold voltage of the first transistor M1 is made lower than the threshold voltage of the second transistor M2 . This process is simple and easy to implement.

[0188] In yet another embodiment, as shown in FIG. 12 , the third thickness H3 of the first gate metal diffusion region 131 is smaller than the fourth thickness H4 of the second gate metal contact region 231 .

[0189] For example, the difference between the fourth thickness H4 and the third thickness H3 ranges from 1 nm to 6 nm, and the difference between the fourth thickness H4 and the third thickness H3 ranges from 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, and 6 nm.

[0190] By changing the thickness of the first gate metal diffusion region 131 and the second gate metal contact region 231 , the threshold voltage of the first transistor M1 is made lower than the threshold voltage of the second transistor M2 . This process is simple and easy to implement.

[0191] In yet another embodiment, as shown in FIG13 , the first gate length L1 of the first gate G1 is smaller than the second gate length L2 of the second gate G2 .

[0192] For example, the difference between the second gate length L2 and the first gate length L1 ranges from 0.1um to 1um. For example, the difference between the second gate length L2 and the first gate length L1 is 0.1um, 0.2um, 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, or 1um.

[0193] By changing the gate lengths of the first gate G1 and the second gate G2 , the threshold voltage of the first transistor M1 is made smaller than the threshold voltage of the second transistor M2 . This process is simple and easy to implement.

[0194] When the semiconductor structure provided in the embodiments of the present application is applied to a radio frequency amplifier, a DC blocking capacitor can be coupled to the gate pad G at the radio frequency input terminal of the radio frequency amplifier. The first drain D1 and the second drain D2 are then coupled to the output terminal of the radio frequency amplifier. Of course, other peripheral circuits may also be included. The structures of radio frequency amplifiers in related arts are all applicable to the embodiments of the present application. The embodiments of the present application only modify the structures of the amplification module and the cancellation module in the radio frequency amplifier.

[0195] As shown in Figure 14, in the embodiment of the present application, by designing the threshold voltage of the first transistor M1 and the threshold voltage of the second transistor M2 to be different, it is possible to reduce gm3 within the transistor operating region, reducing the amplitude of the third-order intermodulation signal, thereby achieving the same linearity improvement effect as the cancellation circuit. As shown in Figure 14, through simulation, it was found that the signal after cancellation output by the semiconductor structure provided in the embodiment of the present application is basically close to 0 when the gate voltage is around -3.3V, which can achieve the effect of improving linearity.

[0196] For example, when the semiconductor structure provided by the embodiments of the present application is applied to an LNA, the third-order intercept point output power (OIP3) is often used in the art to describe the linearity of the LNA. As shown in FIG15A, the horizontal axis represents input power and the vertical axis represents output power. The OIP3 value is obtained from the LNA's RF input-output curve by plotting. Two curves are plotted: the solid line plots the amplified signal power at the input frequency against the input power, and the dashed line plots the third-order intermodulation signal against the input power. In a logarithmic coordinate system, the linear amplified signal curve is represented by a straight line with a slope of 1 (solid line), and the third-order intermodulation signal curve is represented by a straight line with a slope of 3 (dashed line). The output signal power corresponding to their intersection is the OIP3 value. As shown in FIG15B, the horizontal axis represents drain current and the vertical axis represents OIP3. The solid line represents the OIP3 curve of the LNA provided by the embodiments of the present application, and the dashed line represents the OIP3 curve of the LNA in the related art. The OIP3 of the LNA provided by the present application can improve the linearity of the body tube by more than 5dB.

[0197] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that, Applied to a radio frequency amplifier; The semiconductor structure includes: A gate pad; A source pad; A drain pad; At least one first transistor; each of the first transistors includes a first gate, a first source, and a first drain, and the first gate is coupled to the gate pad, the first source is coupled to the source pad, and the first drain is coupled to the drain pad; At least one second transistor; each of the second transistors includes a second gate, a second source, and a second drain, and the second gate is coupled to the gate pad, the second source is coupled to the source pad, and the second drain is coupled to the drain pad; Wherein, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor, and the total gate width of the at least one first transistor is greater than the total gate width of one or more of the second transistors having the same threshold voltage.

2. The semiconductor structure according to claim 1, wherein The semiconductor structure includes a plurality of the second transistors; the plurality of the second transistors include a first group of second transistors and a second group of second transistors, and the threshold voltages of the second transistors in the first group are different from the threshold voltages of the second transistors in the second group.

3. The semiconductor structure according to claim 2, wherein The number of the at least one first transistor is greater than the number of the second transistors in the first group and greater than the number of the second transistors in the second group.

4. The semiconductor structure according to claim 1, wherein The threshold voltages of the at least one first transistor are the same, the threshold voltages of the at least one second transistor are the same, and the number of the at least one first transistor is greater than the number of the at least one second transistor.

5. The semiconductor structure according to any one of claims 2-4, characterized in that, The width of the first gate is equal to the width of the second gate.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; The first gate is in Schottky contact with the first barrier layer, and the first source and the first drain are in ohmic contact with the first barrier layer; The second gate is in Schottky contact with the second barrier layer, and the second source and the second drain are in ohmic contact with the second barrier layer; A first thickness of a portion of the first barrier layer in contact with the first gate is greater than a second thickness of a portion of the second barrier layer in contact with the second gate.

7. The semiconductor structure according to claim 6, wherein, The value range of the difference between the first thickness and the second thickness is 1 nm - 6 nm.

8. The semiconductor structure according to any one of claims 1-7, characterized in that, The first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; The first gate includes a first Schottky metal layer in Schottky contact with the first barrier layer, and the second gate includes a second Schottky metal layer in Schottky contact with the second barrier layer; the work function of the first Schottky metal layer is less than the work function of the second Schottky metal layer.

9. The semiconductor structure according to claim 8, wherein The value range of the difference between the work function of the second Schottky metal layer and the work function of the first Schottky metal layer is 0.1 eV - 0.4 eV.

10. The semiconductor structure according to any one of claims 1-9, characterized in that, The first transistor further includes a first barrier layer; the second transistor further includes a second barrier layer; The first barrier layer includes a first gate metal diffusion region in Schottky contact with the first gate, the second barrier layer includes a second gate metal diffusion region in Schottky contact with the second gate, and a third thickness of the first gate metal diffusion region is less than a fourth thickness of the second gate metal diffusion region.

11. The semiconductor structure according to claim 10, wherein, A value range of a difference between the fourth thickness and the third thickness is 1 nm - 6 nm.

12. The semiconductor structure according to any one of claims 1-11, characterized in that, A first gate length of the first gate is less than a second gate length of the second gate.

13. The semiconductor structure according to claim 12, wherein, A value range of a difference between the second gate length and the first gate length is 0.1 um - 1 um.

14. The semiconductor structure according to any one of claims 1-13, characterized in that, The source pad includes a first pad and a second pad, the first source is coupled to the first pad, and the second source is coupled to the second pad.

15. The semiconductor structure according to any one of claims 1 to 14, characterized in that, The semiconductor structure includes a plurality of first transistors and a plurality of second transistors; Along a first direction, first gates of the plurality of first transistors are arranged in sequence, first sources and first drains are arranged alternately, and the first gates are located above gaps between adjacent first sources and first drains; Along the first direction, second gates of the plurality of second transistors are arranged in sequence, second sources and second drains are arranged alternately, and the second gates are located above gaps between adjacent second sources and second drains; the first direction is a length direction of the first gate; Along a width direction of the first gate, the gate pad and the drain pad are located on two sides of the first transistor.

16. The semiconductor structure according to claim 15, wherein, There is a gap between the plurality of first transistors and the plurality of second transistors, and the source pad is located above the gap.

17. The semiconductor structure according to claim 15, wherein The first pad is located on a side of the first transistor away from the second transistor, and the second pad is located on a side of the second transistor away from the first transistor.

18. The semiconductor structure according to claim 16 or 17, characterized in that, The first source and the second source are disposed between adjacent first gate and second gate.

19. The semiconductor structure according to claim 15, wherein, The first source is disposed between adjacent first gate and second gate, and the first source is multiplexed as the second source; the source pad is located on a side of the first transistor away from the second transistor; or the source pad is located on a side of the second transistor away from the first transistor.

20. A radio frequency amplifier, characterized in that, Including a capacitor and the semiconductor structure according to any one of claims 1 - 19; One end of the capacitor is coupled to an input end of the RF amplifier, and the other end of the capacitor is coupled to the gate pad; the source pad is coupled to a reference ground voltage terminal, and the drain pad is coupled to an output end of the RF amplifier.

21. A radio frequency front-end module, characterized in that, Including: A filter and a low noise amplifier; the low noise amplifier includes the RF amplifier according to claim 20; an RF input end of the RF amplifier is coupled to an input end of the filter.

22. A communication device, characterized in that, Including the RF front-end module according to claim 21 and an antenna, and the antenna is coupled to the RF front-end module.

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