Memory manufacturing method, memory, and electronic device

Abstract

The present disclosure relates to the technical field of integrated circuits, and relates to a memory manufacturing method, a memory, and an electronic device. In order to manufacture as many device units as possible on a limited substrate, the memory manufacturing method comprises: on a substate (100), forming a stack structure (200) in which first sub-layers (210) and second sub-layers (210) are alternately arranged; forming an isolation trench (130) to divide the stack structure (200) into strip-shaped structures (300); in a direction perpendicular to the substrate (100), forming first trenches (121) between adjacent first sub-layers (210); using the strip-shaped structures (300) to block trench walls of the first trenches (121); forming a first semiconductor channel (161) and a first gate dielectric layer (171) in each first trench (121); and removing all film layers outside the first trenches (121) by etching, thereby preventing conductive film layers remained outside the first trenches (121) from forming a parasitic device affecting the performance of the memory. The number of layers of a three-dimensional stack of a memory can be increased, and the integration density can be improved.

Description

Method for manufacturing memory, memory, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application number 202311640776.5, filed on December 1, 2023, entitled “Method for manufacturing memory and memory, electronic device”, and the entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuits, and in particular to a method for manufacturing a memory, a memory, and an electronic device. Background Art

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0005] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0006] Summary of the Invention

[0007] According to some embodiments, the present disclosure provides a method for manufacturing a memory, comprising the following steps:

[0008] Providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising alternately stacked first sub-layers and second sub-layers, and defining a memory cell region and a bit line region in the stacked structure;

[0009] forming an isolation trench, the isolation trench penetrating the stacked structure along a direction perpendicular to the substrate, the isolation trench extending along a first direction and dividing the stacked structure of the memory cell area into at least one strip structure extending along the first direction, wherein the first direction is parallel to the substrate;

[0010] Etching a middle region of the strip structure to remove a portion of the strip structure, and forming a first trench between adjacent first sub-layers along a direction perpendicular to the substrate;

[0011] forming a first semiconductor channel and a first gate dielectric layer in the first trench, wherein the first semiconductor channel covers a trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel;

[0012] A first word line is formed, wherein the first word line includes a first horizontal portion formed in the first trench and a first vertical portion formed in the isolation trench, wherein the first horizontal portion covers the first gate dielectric layer, the first vertical portion is vertically arranged on the substrate, and the first horizontal portion and the first vertical portion are connected.

[0013] According to some embodiments, forming a first trench between adjacent first sub-layers includes:

[0014] forming an isolation layer in the isolation trench;

[0015] forming a second trench in the isolation layer, wherein a sidewall of the second trench exposes a portion of the surface of the middle region of the strip structure;

[0016] The strip structures exposed by the second trenches are removed by etching to form the first trenches. The first trenches and the first sub-layers in the middle region are alternately arranged along a direction perpendicular to the substrate.

[0017] According to some embodiments, forming a first semiconductor channel and a first gate dielectric layer in the first trench includes:

[0018] forming a semiconductor material layer, wherein the semiconductor material layer covers the trench wall of the first trench and the trench wall of the second trench;

[0019] forming a gate dielectric material layer, wherein the gate dielectric material layer covers the semiconductor material layer;

[0020] The semiconductor material layer and the gate dielectric material layer in the second trench are removed, the semiconductor material layer in the first trench forms the first semiconductor channel, and the gate dielectric material layer in the first trench forms the first gate dielectric layer.

[0021] According to some embodiments, forming a first word line includes:

[0022] forming a first horizontal portion in the first trench, the first horizontal portion covering the first gate dielectric layer and filling the first trench, and a sidewall of the second trench exposing a portion of a surface of the first horizontal portion;

[0023] The first vertical portion is formed to contact the exposed surface of the first horizontal portion and fill the second trench.

[0024] According to some embodiments, forming the first horizontal portion in the first trench includes:

[0025] After forming the gate dielectric material layer, forming a first gate conductive layer, wherein the first gate conductive layer covers the gate dielectric material layer and fills the first trench and the second trench;

[0026] The first gate conductive layer in the second trench is removed by etching, and the first gate conductive layer in the first trench is retained to form the first horizontal portion.

[0027] According to some embodiments, the manufacturing method includes:

[0028] The first gate conductive layer, the gate dielectric material layer, and the semiconductor material layer in the second trench are sequentially etched and removed to expose the second trench.

[0029] According to some embodiments, the manufacturing method includes:

[0030] Etching and removing a portion of the isolation layer around the second trench to form a third trench, wherein the third trench exposes the semiconductor material layer located in the second trench;

[0031] The semiconductor material layer, the gate dielectric material layer and the first gate conductive layer in the second trench are removed by etching the third trench.

[0032] According to some embodiments, forming the first vertical portion includes:

[0033] A second gate conductive layer is formed, wherein the second gate conductive layer at least fills the second trench to form the first vertical portion.

[0034] According to some embodiments, along the first direction, the first trench and the bit line region are spaced apart by a predetermined distance.

[0035] According to some embodiments, a selection region is defined in the stacked structure, the memory cell region and the bit line region are arranged along the first direction, and the selection region is located at one end of the bit line region along a second direction, wherein the second direction is parallel to the substrate and intersects with the first direction; the manufacturing method further includes:

[0036] The bit line region is etched to remove a portion of the stacked structure in the bit line region, and a fourth trench is formed between adjacent first sub-layers in the bit line region along a direction perpendicular to the substrate, wherein the fourth trench is disposed close to the selection region.

[0037] According to some embodiments, the manufacturing method further includes:

[0038] While forming the first semiconductor channel and the first gate dielectric layer in the first trench, a second semiconductor channel and a second gate dielectric layer are formed in the fourth trench, wherein the second semiconductor channel covers a trench wall of the fourth trench, and the second gate dielectric layer covers the second semiconductor channel;

[0039] At the same time as the first word line is formed, a second word line is formed, the second word line including a second horizontal portion formed in the fourth trench and a second vertical portion formed in the isolation trench, the second horizontal portion covering the second gate dielectric layer and filling the fourth trench, the second vertical portion being vertically arranged on the substrate, and the second horizontal portion and the second vertical portion being connected.

[0040] According to some embodiments, the first sublayer is a silicon oxide layer, the second sublayer is a semiconductor doped layer, and after forming the isolation trench, the semiconductor doped layer in the bit line region forms a bit line extending along a second direction, which is parallel to the substrate and intersects with the first direction.

[0041] According to some embodiments, the manufacturing method further includes:

[0042] Etching and removing a portion of the first sub-layer away from one end of the bit line region to expose a portion of the surface of the semiconductor doped layer away from the one end of the bit line region;

[0043] forming a dielectric layer, the dielectric layer covering the exposed surface of the semiconductor doping layer;

[0044] An upper electrode is formed, wherein the upper electrode covers the dielectric layer.

[0045] According to some embodiments, the first sub-layer is a silicon oxide layer, and the second sub-layer is a silicon nitride layer; after forming the isolation trench in the memory cell area, the manufacturing method includes:

[0046] etching and removing the entire second sub-layer, and forming an air layer in the area where the second sub-layer is removed;

[0047] forming a bit line in the air layer of the bit line region, wherein the bit line extends along a second direction parallel to the substrate and intersecting the first direction;

[0048] A conductor layer is formed, the conductor layer filling the area where the air layer is not filled.

[0049] According to some embodiments, the manufacturing method further includes:

[0050] Etching and removing a portion of the first sub-layer away from one end of the bit line region to expose a portion of the surface of the conductor layer away from the one end of the bit line region;

[0051] forming a dielectric layer, the dielectric layer covering the exposed surface of the conductor layer;

[0052] An upper electrode is formed, wherein the upper electrode covers the dielectric layer.

[0053] According to some embodiments, the present disclosure further provides a memory, comprising:

[0054] substrate;

[0055] at least one first word line, the first word line comprising a first vertical portion and at least one first horizontal portion, the first vertical portion being vertically disposed on the substrate, and at least one first horizontal portion being spaced apart and connected to the first vertical portion in a direction perpendicular to the substrate;

[0056] at least one memory cell column, the memory cell column comprising at least one memory cell spaced apart and arranged in a direction perpendicular to the substrate;

[0057] The memory cell includes a cell transistor, the first horizontal portion serves as a gate of the cell transistor, the cell transistor includes a first gate dielectric layer and a first semiconductor channel sequentially arranged in a direction away from the first horizontal portion, and the cell transistor also includes a first source / drain and a second source / drain relatively arranged on both sides of the first semiconductor channel along a first direction, wherein the first direction is parallel to the substrate.

[0058] According to some embodiments, in a plane parallel to the first direction and perpendicular to the substrate, the first semiconductor channel surrounds the first horizontal portion.

[0059] According to some embodiments, the first semiconductor channel includes a connection channel located on one side of the first horizontal portion in a second direction, where the second direction is parallel to the substrate and intersects the first direction.

[0060] According to some embodiments, the first semiconductor channel is cup-shaped, and the first semiconductor channel is disposed on the first horizontal portion.

[0061] According to some embodiments, the memory cell further includes a capacitor, and along the first direction, the capacitor is disposed on one side of the cell transistor, and the capacitor is connected to the first source / drain of the cell transistor.

[0062] According to some embodiments, the capacitor includes a lower electrode, a dielectric layer, and an upper electrode, the lower electrode is connected to the first source / drain, and the dielectric layer is disposed between the upper electrode and the lower electrode.

[0063] According to some embodiments, in a plane parallel to the substrate, the upper electrodes of a plurality of the capacitors are connected to each other to form a closed pattern.

[0064] According to some embodiments, a common upper electrode plate is provided in the closed pattern, and the common upper electrode plate is connected to the upper electrode.

[0065] According to some embodiments, the memory further comprises:

[0066] At least one bit line, at least one of the bit lines is arranged at intervals along a direction perpendicular to the substrate, the bit line extends along a second direction, the bit line is connected to the second source / drain of the unit transistor arranged along the second direction, and the second direction is parallel to the substrate and intersects with the first direction.

[0067] According to some embodiments, the memory further comprises:

[0068] a second word line, the second word line comprising a second vertical portion and at least one second horizontal portion, the second vertical portion being vertically disposed on the substrate, and the at least one second horizontal portion being spaced apart in a direction perpendicular to the substrate and connected to the second vertical portion;

[0069] At least one selection transistor, at least one of the selection transistors is arranged at intervals along a direction perpendicular to the substrate, the second horizontal portion serves as a gate of the selection transistor, the selection transistor includes a second gate dielectric layer and a second semiconductor channel sequentially arranged in a direction away from the second horizontal portion, and the selection transistor further includes a third source / drain and a fourth source / drain relatively arranged on both sides of the second semiconductor channel along the second direction; the third source / drain of the selection transistor is connected to the bit line in a one-to-one correspondence.

[0070] According to some embodiments, the memory further comprises:

[0071] At least one selection line is arranged at intervals along a direction perpendicular to the substrate, the selection line extends along the first direction, and the selection line is connected to the fourth source / drain of the selection transistor in a one-to-one correspondence.

[0072] According to some embodiments, another aspect of the present disclosure provides an electronic device, such as the memory described in the second aspect.

[0073] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0075] FIG1 is a flow chart of a method for manufacturing a memory provided in some embodiments.

[0076] FIG2 is a flow chart of a method for manufacturing a memory provided in some embodiments.

[0077] FIG3 is a flowchart of a method for manufacturing a memory provided in some embodiments.

[0078] FIG. 4 is a schematic diagram of a structure in which a stacked structure is formed on a substrate in some embodiments.

[0079] FIG. 5 is a top view of a stacked structure in some embodiments.

[0080] FIG. 6 is a schematic diagram of a structure after isolation trenches are formed in some embodiments.

[0081] FIG. 7 is a top view after isolation trenches are formed in some embodiments.

[0082] FIG8 is a schematic diagram of a structure after an isolation layer is formed in some embodiments.

[0083] FIG. 9 is a schematic diagram of a structure after the first sub-trench is formed in some embodiments.

[0084] FIG. 10 is a top view after forming the first sub-trench in some embodiments.

[0085] FIG. 11 is a top view after the first sub-layer of the second region is removed in some embodiments.

[0086] FIG12 is a schematic structural diagram of the second region from one viewing angle after the first sub-layer is removed in some embodiments.

[0087] FIG. 13 is a schematic structural diagram of the second region from one perspective after a dielectric layer is formed in some embodiments.

[0088] FIG. 14 is a schematic structural diagram of a second region after forming an upper electrode in some embodiments from one viewing angle.

[0089] FIG15 is a schematic structural diagram of a second region from one perspective after a common upper electrode plate is formed in some embodiments.

[0090] FIG. 16 is a schematic diagram of a structure after a second trench is formed in some embodiments.

[0091] FIG. 17 is a cross-sectional view parallel to the substrate along line AA in FIG. 16 after forming the second trench in some embodiments.

[0092] FIG. 18 is a cross-sectional view perpendicular to the substrate taken along line BB and line CC in FIG. 16 after forming the second trench in some embodiments.

[0093] FIG. 19 is a cross-sectional view parallel to the substrate along line AA in FIG. 16 after forming the first trench in some embodiments.

[0094] FIG. 20 is a cross-sectional view perpendicular to the substrate taken along line BB and line CC in FIG. 16 after forming the first trench in some embodiments.

[0095] FIG. 21 is a cross-sectional view perpendicular to the substrate taken along line BB and line CC in FIG. 16 after forming a semiconductor material layer in some embodiments.

[0096] FIG. 22 is a cross-sectional view perpendicular to the substrate along line BB and line CC in FIG. 16 after a gate dielectric material layer is formed in some embodiments.

[0097] FIG. 23 is a cross-sectional view perpendicular to the substrate along line BB and line CC in FIG. 16 after forming a first gate conductive layer in some embodiments.

[0098] FIG. 24 is a cross-sectional view perpendicular to the substrate along line BB and line CC in FIG. 16 after the first gate conductive layer in the second trench and the fifth trench is removed in some embodiments.

[0099] FIG25 is a cross-sectional view perpendicular to the substrate along line BB and line CC in FIG16 after the gate dielectric material layer in the second trench and the fifth trench is removed in some embodiments.

[0100] FIG. 26 is a cross-sectional view perpendicular to the substrate taken along line BB and line CC in FIG. 16 after forming the first horizontal portion and the second horizontal portion in some embodiments.

[0101] FIG. 27 is a cross-sectional view perpendicular to the substrate taken along line BB and line CC in FIG. 16 after forming a second gate conductive layer in some embodiments.

[0102] FIG. 28 is a cross-sectional view perpendicular to the substrate along line BB and line CC in FIG. 16 after forming the first word line and the second word line in some embodiments.

[0103] FIG. 29 is a cross-sectional view parallel to the substrate along line AA in FIG. 16 after forming the third trench and the sixth trench in some embodiments.

[0104] FIG30 is a cross-sectional view perpendicular to the substrate taken along line BB and line CC in FIG16 after forming the third trench and the sixth trench in some embodiments.

[0105] FIG. 31 is a cross-sectional view parallel to the substrate along line AA in FIG. 16 after forming the first horizontal portion and the second horizontal portion in some embodiments.

[0106] FIG. 32 is a cross-sectional view perpendicular to the substrate along line BB and line CC in FIG. 16 after forming the first horizontal portion and the second horizontal portion in some embodiments.

[0107] FIG. 33 is a cross-sectional view parallel to the substrate along line AA in FIG. 16 after forming the first word line and the second word line in some embodiments.

[0108] FIG. 34 is a cross-sectional view perpendicular to the substrate along line BB and line CC in FIG. 16 after forming the first word line and the second word line in some embodiments.

[0109] FIG35 is a schematic diagram of a structure in which a stacked structure is formed on a substrate in some embodiments.

[0110] FIG36 is a schematic diagram of the structure after the isolation trench is formed in some embodiments.

[0111] FIG37 is a schematic diagram of the structure after the first isolation layer is formed in some embodiments.

[0112] FIG. 38 is a top view after forming a first isolation layer in some embodiments.

[0113] FIG39 is a schematic diagram of the structure after the second sub-groove is formed in some embodiments.

[0114] FIG. 40 is a top view after forming the second sub-trench in some embodiments.

[0115] FIG. 41 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 40 after forming a second sub-trench in some embodiments.

[0116] FIG. 42 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 40 after an air layer is formed in some embodiments.

[0117] FIG. 43 is a cross-sectional view perpendicular to the substrate along line DD in FIG. 40 after a conductor layer is formed in some embodiments.

[0118] FIG44 is a schematic diagram of the structure after the second isolation layer is formed in some embodiments.

[0119] FIG. 45 is a cross-sectional view parallel to the substrate along line EE in FIG. 44 after forming the first sub-trench in some embodiments.

[0120] Figure 46 is a schematic diagram of the structure after removing the first sublayer of the second region in some embodiments.

[0121] FIG47 is a schematic structural diagram of a second region from one perspective after capacitors are formed in some embodiments.

[0122] FIG48 is a schematic structural diagram of a second region from one perspective after a common upper electrode plate is formed in some embodiments.

[0123] FIG. 49 is a cross-sectional view parallel to the substrate along line EE in FIG. 44 after forming the second trench and the fifth trench in some embodiments.

[0124] FIG. 50 is a cross-sectional view parallel to the substrate along line EE in FIG. 44 after forming the first trench and the fourth trench in some embodiments.

[0125] FIG. 51 is a cross-sectional view parallel to the substrate along line EE in FIG. 44 after forming the first horizontal portion and the second horizontal portion in some embodiments.

[0126] Figure 52 is a schematic diagram of the structure of the memory provided in some embodiments.

[0127] FIG53 is a cross-sectional view parallel to the substrate along line FF in FIG52 of the memory provided in some embodiments.

[0128] FIG54 is a cross-sectional view perpendicular to the substrate along line GG and line HH in FIG52 of the memory provided in some embodiments.

[0129] FIG55 is a cross-sectional view perpendicular to the substrate along line II in FIG52 of the memory provided in some embodiments.

[0130] FIG56 is a cross-sectional view perpendicular to the substrate along line JJ in FIG52 of the memory provided in some embodiments.

[0131] FIG57 is a cross-sectional view perpendicular to the substrate along line II in FIG52 of the memory provided in some embodiments.

[0132] FIG58 is a cross-sectional view perpendicular to the substrate along line JJ in FIG52 of the memory provided in some embodiments.

[0133] Description of reference numerals:

[0134] 100, substrate; 130, isolation trench; 131, first sub-trench; 132, second sub-trench; 200, stacked structure; 210, first sub-layer; 220, second sub-layer; 220a, semiconductor doped layer; 230, isolation layer; 231, first isolation layer; 232, second isolation layer; 240, air layer; 250, conductor layer; 300, stripe structure; 410, semiconductor material layer; 420, gate dielectric material layer; 430, first gate conductive layer; 440, second gate conductive layer; 121, first trench; 221 , second trench; 321, third trench; 421, fourth trench; 521, fifth trench; 621, sixth trench; 161, first semiconductor channel; 1611, connecting channel; 171, first gate dielectric layer; 261, second semiconductor channel; 271, second gate dielectric layer; 181, first source / drain; 182, second source / drain; 281, third source / drain; 282, fourth source / drain; 600, capacitor; 610, dielectric layer; 620, top electrode; 630, bottom electrode; 640, common top plate;

[0135] BL, bit line; WL1, first word line; WL2, second word line; HS1, first horizontal portion; VP1, first vertical portion; HS2, second horizontal portion; VP2, second vertical portion; SUC, memory cell column; SU, memory cell; MCT, cell transistor; G1, gate of cell transistor; ST, select transistor; G2, gate of select transistor; SL, select line;

[0136] Z1, memory cell area; Z2, bit line area; Z3, selection area; A1, first area; A2, second area; A11, middle area;

[0137] D1, first direction; D2, second direction; D3, third direction. DETAILED DESCRIPTION

[0138] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0139] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0140] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0141] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0142] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0143] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0144] A method for manufacturing a memory is provided in an exemplary embodiment of the present disclosure, as shown in FIG1 . FIG1 shows a flow chart of a method for manufacturing a memory provided according to an exemplary embodiment of the present disclosure. This embodiment does not limit the semiconductor structure. The memory will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. The memory in this embodiment may also be other types of memory, such as static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), and magnetic random access memory (MRAM).

[0145] As shown in FIG1 , some embodiments of the present disclosure provide a method for manufacturing a memory, comprising the following steps:

[0146] Step S110: providing a substrate, forming a stacked structure on the substrate, wherein the stacked structure includes first sub-layers and second sub-layers alternately spaced apart, and defining a memory cell region and a bit line region in the stacked structure.

[0147] Step S120: forming an isolation trench, the isolation trench penetrating the stacked structure in a direction perpendicular to the substrate, the isolation trench extending along a first direction, dividing the stacked structure of the memory cell area into at least one strip structure extending along the first direction parallel to the substrate.

[0148] Step S130: etching the middle region of the strip structure to remove part of the strip structure, and forming a first trench between adjacent first sub-layers along a direction perpendicular to the substrate.

[0149] Step S140 : forming a first semiconductor channel and a first gate dielectric layer in the first trench, wherein the first semiconductor channel covers a trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel.

[0150] Step S150: forming a first word line, the first word line including a first horizontal portion formed in the first trench and a first vertical portion formed in the isolation trench, the first horizontal portion covering the first gate dielectric layer, the first vertical portion being vertically arranged on the substrate, and the first horizontal portion and the first vertical portion being connected.

[0151] In step S110, referring to FIG. 4 or FIG. 35 , substrate 100 may be a semiconductor substrate. The material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Substrate 100 may have a single-layer structure or a multi-layer structure.

[0152] 4 or 35 , the stacked structure 200 includes first sublayers 210 and second sublayers 220 alternately stacked in a direction perpendicular to the top surface of the substrate 100 (third direction D3). In some embodiments, referring to FIG4 , the first sublayer 210 is a silicon oxide layer, and the second sublayer 220 is a semiconductor doped layer (e.g., a polysilicon layer). In other embodiments, referring to FIG35 , the first sublayer 210 is a silicon oxide layer, and the second sublayer 220 is a silicon nitride layer.

[0153] The second sub-layer 220 of the stacked structure 200 is disposed at a position for subsequently forming a memory unit SU. In this embodiment, both the top and bottom layers of the stacked structure 200 are the first sub-layer 210 .

[0154] 5 , a memory cell region Z1 and a bit line region Z2 are divided on the stacked structure 200. The memory cell region Z1 is used to form memory cells SU arrayed above the substrate 100, and the bit line region Z2 is used to form bit lines BL. The memory cell region Z1 and the bit line region Z2 are arranged along a first direction D1. As shown in FIG5 , along the first direction D1, an independent memory cell region Z1 can be defined on both sides of the bit line region Z2.

[0155] In step S120, referring to Figures 5, 6, 7 or 36, a mask layer (not shown in the figures) is formed on the top surface of the stacked structure 200, the patterned mask layer exposes a portion of the top surface of the stacked structure 200 of the storage cell area Z1, the stacked structure 200 exposed by the patterned mask layer is etched away, and isolation trenches 130 are formed in the stacked structure 200, the isolation trenches 130 expose a portion of the top surface of the substrate 100, and the isolation trenches 130 divide the stacked structure 200 of the storage cell area Z1 into a plurality of strip structures 300, the strip structures 300 extend along the first direction D1, and the plurality of strip structures 300 are arranged at intervals along the second direction D2, that is, along the second direction D2, the strip structures 300 and the isolation trenches 130 are alternately arranged.

[0156] In step S130, referring to FIG. 17 , FIG. 19 , FIG. 20 , or FIG. 50 , the middle region A11 of the strip structure 300 can be etched based on the isolation trench 130 (see FIG. 6 or FIG. 36 ). First trenches 121 spaced apart along a third direction D3 are formed in the middle region A11 of the strip structure 300. The first trenches 121 are arranged parallel to the substrate 100, and the strip structures 300 surrounding the first trenches 121 shield the first trenches 121. After the first trenches 121 are formed, the middle region A11 of the strip structure 300, the first sublayer 210 (see FIG. 20 ), and the first trenches 121 are alternately arranged along the third direction D3.

[0157] In some embodiments, along the first direction D1 , the first trench 121 and the bit line region Z2 are spaced apart by a preset distance to prevent a subsequently formed first word line from being too close to the bit line region Z2 , thereby preventing electrical isolation between devices in the memory from being affected.

[0158] In step S140, referring to Figures 20 to 26, or Figures 29 to 32, or Figure 51, a first semiconductor channel 161 and a first gate dielectric layer 171 are formed in the first trench 121 (refer to Figure 19 or Figure 50). A suitable deposition process can be used to sequentially deposit a semiconductor material layer 410 and a gate dielectric material layer 420. The semiconductor material layer 410 and the gate dielectric material layer 420 are stacked to cover the trench wall of the first trench 121 and the exposed surface of the strip structure 300, the isolation trench 130, and the stacked structure 200 of the bit line area Z2.

[0159] Then, an etching process is used to etch the semiconductor material layer 410 and the gate dielectric material layer 420, and the strip structure 300 forms a shield on the groove wall of the first trench 121 (refer to Figure 19 or Figure 50). The semiconductor material layer 410 and the gate dielectric material layer 420 in the first trench 121 are etched and retained, and a first semiconductor channel 161 and a first gate dielectric layer 171 are formed in the first trench 121. The semiconductor material layer 410 and the gate dielectric material layer 420 covering the groove wall of the first trench 121 and the exposed surface of the strip structure 300, the isolation trench 130 and the stacked structure 200 of the bit line area Z2 are all etched away, thereby ensuring that there is no residual semiconductor material layer 410 and gate dielectric material layer 420 in the area outside the first trench 121.

[0160] In step S150, referring to Figures 27, 28, 33, 34, 52, and 53, the first horizontal portion HS1 and the first vertical portion VP1 of the first word line WL1 can be formed separately in different processes. For example, the first horizontal portion HS1 can be formed in the same process step as the first semiconductor channel 161 and the first gate dielectric layer 171; then, the first vertical portion VP1 is formed in the isolation trench 130; or, in some embodiments, the first horizontal portion HS1 and the first vertical portion VP1 of the first word line WL1 can be formed in the same process step.

[0161] The manufacturing method of the memory disclosed in the present invention forms a first trench arranged parallel to the substrate in a strip structure. During the process of manufacturing the first semiconductor channel and the first gate dielectric layer, the film layer forming the first semiconductor channel and the film layer forming the first gate dielectric layer cover the exposed surfaces of the first trench and other structures. The strip structure is used to block the groove wall of the first trench, and the film layer in the first trench is retained to form the first semiconductor channel and the first gate dielectric layer. The film layer outside the first trench is completely etched away to prevent the residual conductive film layer outside the first trench from forming a parasitic device in the storage unit, thereby preventing the parasitic device from affecting the performance of the memory. The number of layers of the three-dimensional stack of the memory can be further increased, thereby improving the integration density of the memory.

[0162] In some embodiments, step S130 of forming a first trench between adjacent first sub-layers includes the following steps:

[0163] Step S131 : forming an isolation layer in the isolation trench.

[0164] Step S132: forming a second trench in the isolation layer, wherein a sidewall of the second trench exposes a portion of the surface of the middle region of the strip structure.

[0165] Step S133: etching and removing the strip structures exposed by the second trenches to form first trenches. The first trenches and the first sub-layers in the middle region are alternately arranged along a direction perpendicular to the substrate.

[0166] In step S131, referring to FIG9 , any suitable deposition process may be used to form an isolation layer 230. The isolation layer 230 fills the isolation trench 130. The material of the isolation layer 230 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. It will be appreciated that the isolation layer 230 may be formed by a single deposition process or by multiple deposition processes.

[0167] In step S132 , referring to FIG. 17 or FIG. 49 , a portion of the isolation layer 230 close to the strip structure 300 is removed by etching to form a second trench 221 . The second trench 221 exposes a portion of the surface of the middle area A11 of the strip structure 300 .

[0168] In step S133, referring to FIG. 19 or FIG. 50 , the strip-shaped structure 300 is etched based on the second trenches 221 to remove a portion of the structure in the middle region A11. Spaced first trenches 121 are formed in the middle region A11 along the third direction D3. The first trenches 121 and the first sub-layer 210 are alternately arranged along the third direction D3. In some embodiments, a wet etching process can be used to form the first trenches 121. An etchant is injected into the second trenches 221 to remove a portion of the structure in the middle region A11. The etchant can remove the second sub-layer 220 or other film layers originally formed in the second sub-layer 220.

[0169] The manufacturing method of the memory disclosed in the present invention forms a second groove near the strip structure in the isolation layer, and then etches the strip structure based on the sidewall of the second groove to form a first groove, thereby reducing the process of etching the stacked structure to form a hole or groove that penetrates the stacked structure, reducing the process difficulty, and can not only improve process efficiency and reduce process costs, but also improve product yield.

[0170] In some embodiments, step S140: forming a first semiconductor channel and a first gate dielectric layer in the first trench includes the following steps:

[0171] Step S141 : forming a semiconductor material layer, where the semiconductor material layer covers the walls of the first trench and the second trench.

[0172] Step S142: forming a gate dielectric material layer, where the gate dielectric material layer covers the semiconductor material layer.

[0173] Step S143 : removing the semiconductor material layer and the gate dielectric material layer in the second trench, forming the semiconductor material layer in the first trench into a first semiconductor channel, and forming the gate dielectric material layer in the first trench into a first gate dielectric layer.

[0174] In step S141 , as shown in FIG. 20 and FIG. 21 , an atomic layer deposition (ALD) process may be used to deposit a semiconductor material layer 410 , which covers the walls of the first trench 121 , the walls of the second trench 221 , and the top surface of the stacked structure 200 .

[0175] The semiconductor material layer 410 may be single crystal silicon or polycrystalline silicon, or an oxide semiconductor layer. The material of the oxide semiconductor layer 410 may include indium gallium zinc oxide. For example, the material of the oxide semiconductor layer 410 may include at least one of the following materials: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), tungsten-doped indium oxide (IWO), zinc oxide (ZnO x ), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), indium zinc oxide (InSnO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y Oz ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium oxide zinc tin (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO).

[0176] In step S142, as shown in FIG22 , an atomic layer deposition process may be used to deposit a gate dielectric material layer 420, which covers the semiconductor material layer 410. The gate dielectric material layer may include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO); or, the gate dielectric material layer may include at least one of hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), and zirconium silicate nitride (SrSiON).

[0177] In step S143 , in some examples, referring to FIG. 24 , FIG. 25 , and FIG. 26 , the gate dielectric material layer 420 and the semiconductor material layer 410 in the second trench 221 are removed sequentially from the center of the second trench 221 toward the trench wall.

[0178] In other examples, as shown in Figure 29, a third trench 321 is formed on the periphery of the second trench 221 to expose the semiconductor material layer 410 in the second trench 221, and the semiconductor material layer 410 and the gate dielectric material layer 420 in the second trench 221 are removed sequentially from the groove wall of the second trench 221 toward the center.

[0179] In some embodiments, step S150, forming a first word line, includes the following steps:

[0180] Step S151 : forming a first horizontal portion in the first trench, wherein the first horizontal portion covers the first gate dielectric layer and fills the first trench, and a sidewall of the second trench exposes a portion of the surface of the first horizontal portion.

[0181] Step S152 : forming a first vertical portion, the first vertical portion contacting the exposed surface of the first horizontal portion and filling the second trench.

[0182] In step S151, a first horizontal portion is formed in the first trench, including the following steps:

[0183] Step S1511: forming a first gate conductive layer, the first gate conductive layer covering the gate dielectric material layer and filling the first trench and the second trench.

[0184] This step is performed after forming the gate dielectric material layer 420 in step S142. Referring to FIG. 23 , a first gate conductive layer 430 may be formed by depositing the first gate conductive layer 430 using any one of chemical vapor deposition (CVD), atomic layer deposition, and sputtering processes. The first gate conductive layer 430 fills the second trench 221 and the unfilled area of ​​the first trench 121.

[0185] Step S1512: etching and removing the first gate conductive layer in the second trench, retaining the first gate conductive layer in the first trench, and forming a first horizontal portion.

[0186] This step may be performed before step S143 or after step S143.

[0187] In some examples, as shown in FIG. 24 to FIG. 26 , the first gate conductive layer 430 , the gate dielectric material layer 420 , and the semiconductor material layer 410 in the second trench 221 may be sequentially etched and removed to expose the second trench 221 .

[0188] In some examples, as shown in FIG. 29 , a portion of the isolation layer 230 around the second trench 221 is first etched away to form a third trench 321 , wherein the third trench 321 exposes the semiconductor material layer 410 in the second trench 221 ; then, the semiconductor material layer 410 , the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 are etched away based on the third trench 321 .

[0189] In step S152 , a first vertical portion VP1 is formed, including forming a second gate conductive layer 440 , wherein the second gate conductive layer 440 at least fills the second trench 221 to form the first vertical portion VP1 .

[0190] 23 and 27 , the material of the first gate conductive layer 430 and the material of the second gate conductive layer 440 may be selected from at least one of titanium or a titanium compound, tantalum or a tantalum compound, tungsten or a tungsten compound, and copper or a copper compound. The materials of the first gate conductive layer 430 and the second gate conductive layer 440 may be the same or different.

[0191] In some embodiments, as shown in Figure 4, while the memory cell area Z1 and the bit line area Z2 are defined in step S120, a selection area Z3 is defined in the stacked structure 200, the memory cell area Z1 and the bit line area Z2 are arranged along the first direction D1, and the selection area Z3 is at one end of the bit line area Z2 along the second direction D2, and the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1.

[0192] In some embodiments, the method for manufacturing a memory further includes the following steps:

[0193] As shown in Figures 18 and 50, with reference to Figure 4, the bit line region Z2 is etched to remove a portion of the stacked structure 200 in the bit line region Z2. A fourth trench 421 is formed between adjacent first sub-layers 210 in the bit line region Z2 along a direction perpendicular to the substrate 100. The fourth trench 421 is located near the selection region Z3. The above steps can be performed simultaneously with step S130. First, a portion of the isolation layer 230 near the selection region Z3 is etched away to form a fifth trench 521. The fifth trench 521 exposes a portion of the stacked structure 200 in the bit line region Z2. The stacked structure 200 in the bit line region Z2 is etched based on the fifth trench 521, forming a fourth trench 421 in the bit line region Z2.

[0194] As shown in Figures 31 and 51, while a first semiconductor channel 161 and a first gate dielectric layer 171 are formed in the first trench 121, a second semiconductor channel 261 and a second gate dielectric layer 271 are formed in the fourth trench 421. The second semiconductor channel 261 covers the groove wall of the fourth trench 421, and the second gate dielectric layer 271 covers the second semiconductor channel 261.

[0195] As shown in Figures 33, 52 and 53, the second word line WL2 is formed at the same time as the first word line WL1 is formed. The second word line WL2 includes a second horizontal portion HS2 formed in the fourth trench 421 and a second vertical portion VP2 formed in the isolation trench 130. The second horizontal portion HS2 covers the second gate dielectric layer 271 and fills the fourth trench 421. The second vertical portion VP2 is vertically arranged on the substrate 100, and the second horizontal portion HS2 is connected to the second vertical portion VP2.

[0196] Some embodiments of the present disclosure provide a method for manufacturing a memory. As shown in FIG2 , FIG2 is a flow chart of the method for manufacturing a memory according to some embodiments of the present disclosure. FIG4 to FIG34 are schematic diagrams of various stages of the method for manufacturing a memory. The method for manufacturing a memory is described below in conjunction with FIG4 to FIG34 and with reference to FIG52 to FIG56 . As shown in FIG2 , the method for manufacturing a memory includes the following steps:

[0197] Step S210: Provide a substrate and form a stacked structure on the substrate, the stacked structure including alternating first sub-layers and second sub-layers, defining a memory cell region, a bit line region and a selection region in the stacked structure, the memory cell region and the bit line region are arranged along a first direction, and the selection region is at one end of the bit line region along a second direction.

[0198] 4 , the substrate 100 of this embodiment is the same as the substrate 100 in step S110 , and will not be described again herein.

[0199] As shown in Figures 4 and 5, the stacked structure 200 includes first sublayers 210 and second sublayers 220 alternately stacked along a third direction D3. The first sublayer 210 is a silicon oxide layer, and the second sublayer 220 is a semiconductor doped layer. The semiconductor doped layer is a conductively doped polysilicon layer, and the semiconductor doped layer can have P-type or N-type conductivity. The top and bottom layers of the stacked structure 200 are both the first sublayer 210.

[0200] The stacked structure 200 is formed on the substrate 100, and the following embodiments may be used:

[0201] 4 and 5 , a chemical vapor deposition process, an atomic layer deposition process, or a sputtering process can be used to alternately deposit silicon oxide layers and semiconductor doping layers, and the cycle can be repeated several times to form a stacked structure 200. The silicon oxide layers and semiconductor doping layers of the stacked structure 200 can be stacked alternately in multiple layers.

[0202] 5 , a stacked structure 200 is laid out according to the structure of the memory to be formed. A memory cell region Z1, a bit line region Z2, and a selection region Z3 are defined on the stacked structure 200. In some embodiments, a memory cell region Z1 is defined on either side of the bit line region Z2 along a first direction D1, and a selection region Z3 is defined at one end of the bit line region Z2 along a second direction D2. The first direction D1 is parallel to the substrate 100, and the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1.

[0203] Step S220: forming an isolation trench, the isolation trench penetrating the stacked structure in a direction perpendicular to the substrate, the isolation trench extending along a first direction, dividing the stacked structure of the memory cell area into at least one strip structure extending along the first direction, the semiconductor doping layer in the bit line area forming a bit line extending along the second direction, and the semiconductor doping layer in the selection area forming a selection line extending along the first direction.

[0204] As shown in Figures 6 and 7, referring to Figures 4 and 5, a first mask layer (not shown in the figures) is formed on the top surface of the stacked structure 200. The first mask layer exposes a portion of the top surface of the stacked structure 200 in the memory cell area Z1 and a portion of the top surface of the stacked structure 200 in the selection area Z3. The stacked structure 200 exposed by the mask layer is etched away to form isolation trenches 130. The isolation trenches 130 divide the stacked structure 200 in the memory cell area Z1 into strip structures 300 extending along the first direction D1 and arranged at intervals along the second direction D2. At the same time, the retained second sublayer 220 of the bit line area Z2 (hereinafter collectively referred to as the semiconductor doping layer) is directly formed into bit lines BL extending along the second direction D2 and arranged at intervals along the third direction D3 (refer to Figure 33). The retained semiconductor doping layer is directly formed into select lines SL extending along the first direction D1 and arranged at intervals along the third direction D3 (refer to Figure 33), and the select lines SL in the selection area Z3 and the strip structures 300 in the memory cell area Z1 are arranged at intervals along the second direction D2.

[0205] Step S230 : forming an isolation layer in the isolation trench.

[0206] 8 , referring to FIG6 and FIG7 , a chemical vapor deposition process or an atomic layer deposition process may be selected to deposit an isolation layer 230, which fills the isolation trench 130. The isolation layer 230 may be made of at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0207] Step S240: forming a capacitor at one end of the memory cell region away from the bit line region.

[0208] Forming a capacitor at one end of the memory cell region away from the bit line region includes the following steps:

[0209] Step S241 : etching and removing a portion of the first sub-layer away from one end of the bit line region to expose a portion of the surface of the semiconductor doped layer away from the one end of the bit line region.

[0210] The etching process may be performed to remove a portion of the first sub-layer 210 away from the end of the bit line region Z2 by the following steps:

[0211] Along the first direction D1, the strip structure 300 in the memory cell area Z1 defines a first area A1 and a second area A2 (see FIG. 11 ) arranged in sequence away from the bit line area Z2. The first area A1 is close to the bit line area Z2, and the second area A2 is away from the bit line area Z2.

[0212] As shown in Figures 9 and 10, a second mask layer (not shown in the figures) is formed on the top surface of the structure, and the second mask layer exposes the top surface of the isolation layer 230 connected to the second area A2. The isolation layer 230 is etched based on the second mask layer, and the isolation layer 230 connected to the second area A2 is etched away to expose part of the isolation trench 130 away from the bit line area Z2. The isolation trench 130 exposed in this step is defined as a first sub-trench 131, and the first sub-trench 131 exposes the surface of the strip structure 300 of the second area A2.

[0213] Then, referring to FIG. 11 and FIG. 12 , the strip structure 300 is etched based on the first sub-trench 131 to remove the first sub-layer 210 (hereinafter collectively referred to as the silicon oxide layer) in the second area A2 , exposing the surface of the semiconductor doping layer in the second area A2 .

[0214] For example, the silicon oxide layer in the second area A2 may be removed by etching using a dry process or a wet process.

[0215] Step S242: forming a dielectric layer, where the dielectric layer covers the exposed surface of the semiconductor doping layer.

[0216] As shown in FIG13 , referring to FIG12 , a dielectric layer 610 is deposited and formed by an atomic layer deposition process. The dielectric layer 610 uniformly covers the exposed surface of the semiconductor doping layer in the second region A2. The material of the dielectric layer 610 may include at least one of strontium titanate (SrTiO 3 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), or hafnium oxide (HfO 2 ).

[0217] Step S243: forming an upper electrode, where the upper electrode covers the dielectric layer.

[0218] As shown in Figure 14, referring to Figure 13, an atomic layer deposition process can be used to deposit and form an upper electrode 620, which covers the surface of the dielectric layer 610. The material of the upper electrode 620 may include a high melting point metal, such as at least one of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W) and / or molybdenum (Mo); or, the material of the upper electrode 620 may also include a metal nitride, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride.

[0219] The semiconductor doped layer covered by the dielectric layer 610 (i.e., the semiconductor doped layer of the second region A2), the dielectric layer 610, and the upper electrode 620 form a capacitor 600 at one end of the storage cell region Z1 away from the bit line region Z2 (i.e., the second region A2), and the semiconductor doped layer covered by the dielectric layer 610 (i.e., the semiconductor doped layer of the second region A2) serves as the lower electrode 630 of the capacitor 600.

[0220] In some embodiments, the following steps are further performed after step S243:

[0221] Step S244: forming a common upper electrode plate, which covers the upper electrode and fills the unfilled areas between the semiconductor doping layers and the unfilled areas in the first sub-trench.

[0222] As shown in Figure 15, referring to Figure 14, a common upper plate 640 can be formed by any one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or sputtering process, and the common upper plate 640 covers the surface of the upper electrode 620 of each capacitor 600 and fills the unfilled area between the semiconductor doping layers of the second area A2 and the unfilled area in the first sub-groove 131.

[0223] The material of the common top plate 640 may include a semiconductor material doped with conductive ions or a conductive metal. For example, the material of the common top plate 640 may include single crystal silicon or polycrystalline silicon. The material of the common top plate 640 may also include at least one of tungsten, cobalt, titanium, and / or nickel. In this way, the memory area can be fully utilized and the storage capacity of the memory can be increased.

[0224] Step S250: forming a second trench in the isolation layer, wherein a sidewall of the second trench exposes a portion of the surface of the middle region of the strip structure; and forming a fifth trench in the isolation layer, wherein a sidewall of the fifth trench exposes a portion of the surface of the stacked structure of the bit line region.

[0225] As shown in Figures 16, 17, and 18, a third mask layer (not shown) is formed on the top surface of the structure. The third mask layer defines a pattern of the second trench 221 and the fifth trench 521. The third mask layer is etched away to expose the isolation layer 230, forming the second trench 221 and the fifth trench 521, respectively. The second trench 221 is located in the memory cell region Z1 (see Figure 5) and exposes a portion of the surface of the middle region A11 of the strip structure 300. In this embodiment, the middle region A11 of the strip structure 300 refers to the middle region A11 of the first region A1 (see Figure 11). The fifth trench 521 is located near the selection region Z3 (see Figure 5) and exposes a portion of the surface of the stacked structure 200 in the bit line region Z2.

[0226] Step S260: Etching the middle area of ​​the strip structure to remove part of the strip structure, forming a first groove between adjacent first sub-layers along a direction perpendicular to the substrate, and at the same time etching the bit line area to remove part of the stacked structure in the bit line area, forming a fourth groove between adjacent first sub-layers in the bit line area along a direction perpendicular to the substrate, and the fourth groove is set close to the selection area.

[0227] As shown in Figures 19 and 20, referring to Figures 17 and 18, the stacked structure 200 can be etched using a wet process to remove the semiconductor doped layer exposed by the second trench 221. A first trench 121 is formed in the middle area A11 of the first area A1 (refer to Figure 11). The first trench 121 is connected to the second trench 221. The first trench 121 divides the semiconductor doped layer of the memory cell area Z1 into two sections independently arranged on both sides of the first trench 121 along the first direction D1. As shown in Figures 52, 55, and 56, in the first area A1, the semiconductor doped layer located on the left side of the first trench 121 serves as the first source / drain 181 of the cell transistor MCT in the subsequently formed memory cell SU, and the semiconductor doped layer located on the right side of the first trench 121 serves as the second source / drain 182 of the cell transistor MCT in the subsequently formed memory cell SU. It can be seen that the first source / drain 181 is connected to the capacitor 600, and the second source / drain 182 is connected to the bit line BL.

[0228] At the same time, as shown in Figures 19 and 20, with reference to Figures 17 and 18, the semiconductor doped layer exposed by the fifth trench 521 is etched away, forming a fourth trench 421 in the middle region A11 of the bit line region Z2. The fourth trench 421 is connected to the fifth trench 521, and the fourth trench 421 divides the semiconductor doped layer of the bit line region Z2 into two sections independently disposed along the second direction D2 on either side of the fourth trench 421. Referring to Figures 52, 55, and 56, the portion near the bit line BL serves as the third source / drain 281 of the subsequently formed select transistor ST, and the portion near the select region Z3 serves as the fourth source / drain 282 of the subsequently formed select transistor ST. It can be seen that the third source / drain 281 is connected to the bit line BL, and the fourth source / drain 282 is connected to the select line SL.

[0229] Step S270: A first semiconductor channel and a first gate dielectric layer are formed in the first trench, wherein the first semiconductor channel covers the trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel. At the same time, a second semiconductor channel and a second gate dielectric layer are formed in the fourth trench, wherein the second semiconductor channel covers the trench wall of the fourth trench, and the second gate dielectric layer covers the second semiconductor channel.

[0230] The following implementation method can be adopted, as shown in Figures 21, 22 and 23, to sequentially form a semiconductor material layer 410, a gate dielectric material layer 420 and a first gate conductive layer 430, the semiconductor material layer 410 covers the groove wall of the first trench 121, the groove wall of the second trench 221, the groove wall of the fourth trench 421 and the groove wall of the fifth trench 521, the gate dielectric material layer 420 covers the semiconductor material layer 410, and the first gate conductive layer 430 covers the gate dielectric material layer 420 and fills the unfilled area of ​​the first trench 121, the unfilled area of ​​the second trench 221, the unfilled area of ​​the fourth trench 421 and the unfilled area of ​​the fifth trench 521.

[0231] As shown in Figure 26 or Figure 32, the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 and the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the fifth trench 521 are etched away, and the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the first trench 121 are retained, and the first semiconductor channel 161, the first gate dielectric layer 171 and the first horizontal portion HS1 of the first word line WL1 are respectively formed, and the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the fourth trench 421 are retained, and the second semiconductor channel 261, the second gate dielectric layer 271 and the second horizontal portion HS2 of the second word line WL2 are respectively formed.

[0232] In some embodiments, the semiconductor material layer 410 , the gate dielectric material layer 420 , and the first gate conductive layer 430 in the second trench 221 and the fifth trench 521 are removed by the following implementation:

[0233] As shown in FIG24 , with reference to FIG23 , the first gate conductive layer 430 in the second trench 221 is removed by a wet etching process, and the first gate conductive layer 430 in the fifth trench 521 is removed simultaneously, exposing the gate dielectric material layer 420 in the second trench 221 and the fifth trench 521. Then, as shown in FIG25 , with reference to FIG24 , the gate dielectric material layer 420 in the second trench 221 is removed by a wet etching process, and the gate dielectric material layer 420 in the fifth trench 521 is removed simultaneously, exposing the semiconductor material layer 410 in the second trench 221 and the fifth trench 521. Next, as shown in FIG26 , with reference to FIG25 , the semiconductor material layer 410 in the second trench 221 is removed by a wet etching process, and the semiconductor material layer 410 in the fifth trench 521 is removed simultaneously, exposing the second trench 221 and the fifth trench 521.

[0234] The first gate conductive layer 430 , the gate dielectric material layer 420 and the semiconductor material layer 410 are removed layer by layer from the center of the trench toward the trench wall. This simplifies the process, reduces the process steps, saves process time and reduces process costs.

[0235] In some embodiments, the semiconductor material layer 410 , the gate dielectric material layer 420 , and the first gate conductive layer 430 in the second trench 221 and the fifth trench 521 are removed by the following implementation:

[0236] First, as shown in Figures 29 and 30, part of the isolation layer 230 around the second trench 221 is etched away to form a third trench 321, which exposes the semiconductor material layer 410 located in the second trench 221. At the same time, part of the isolation layer 230 around the fifth trench 521 is etched away to form a sixth trench 621, which exposes the semiconductor material layer 410 located in the sixth trench 621.

[0237] A fourth mask layer can be formed on the top surface of the structure, exposing part of the top surface of the isolation layer 230 around the second trench 221 and part of the top surface of the isolation layer 230 around the fifth trench 521, and etching away the isolation layer 230 exposed by the fourth trench 421 to form a third trench 321 around the second trench 221, and at the same time forming a sixth trench 621 around the fifth trench 521.

[0238] Then, as shown in Figure 31, referring to Figure 30, the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 are removed layer by layer by etching based on the third trench 321, and at the same time, the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the fifth trench 521 are removed layer by layer by etching based on the sixth trench 621.

[0239] A wet process can be used to sequentially etch away the semiconductor material layer 410, gate dielectric material layer 420, and first gate conductive layer 430 in the second trench 221 and the fifth trench 521. Etching the film layers in the second trench 221 and the fifth trench 521 from the trench walls toward the center ensures that the semiconductor material layer 410 in the second trench 221 and the fifth trench 521 is completely etched away, preventing residual semiconductor material layer 410 in the second trench 221 or the fifth trench 521 from forming parasitic devices in the memory, further improving the performance and quality of the memory. Furthermore, in this embodiment, the formation of the third trench 321 outside the second trench 221 increases the size of the subsequently formed first vertical portion VP1, thereby reducing the resistance of the first word line WL1. Similarly, this embodiment also reduces the resistance of the second word line WL2.

[0240] Step S280 : forming a first word line and forming a second word line at the same time.

[0241] As shown in Figures 33 and 34, the first word line WL1 includes a first horizontal portion HS1 formed in the first trench 121 and a first vertical portion VP1 formed in the isolation trench 130. The first horizontal portion HS1 covers the first gate dielectric layer 171. The first vertical portion VP1 is vertically arranged on the substrate 100 and fills the second trench 221. The first horizontal portion HS1 and the first vertical portion VP1 are connected.

[0242] As shown in Figures 33 and 34, the second word line WL2 includes a second horizontal portion HS2 formed in the fourth trench 421 and a second vertical portion VP2 formed in the isolation trench 130. The second horizontal portion HS2 covers the second gate dielectric layer 271. The second vertical portion VP2 is vertically arranged on the substrate 100 and fills the fifth trench 521. The second horizontal portion HS2 is connected to the second vertical portion VP2.

[0243] 26 , 31 and 32 , the first horizontal portion HS1 of the first word line WL1 and the first horizontal portion HS1 of the second word line WL2 have been formed in step S270 , and only the first vertical portion VP1 of the first word line WL1 and the second vertical portion VP2 of the second word line WL2 need to be formed.

[0244] As shown in Figure 27, any one of the deposition processes including chemical vapor deposition, atomic layer deposition, physical vapor deposition or sputtering can be used to deposit and form the second gate conductive layer 440, and the second gate conductive layer 440 fills the second trench 221 and the fifth trench 521 respectively. It can be understood that in the embodiment of forming the third trench 321 and the sixth trench 621, the second gate conductive layer 440 also fills the third trench 321 and the sixth trench 621.

[0245] As shown in Figure 28, the second gate conductive layer 440 covering the top surface of the structure is removed by etching. The second gate conductive layer 440 in the second trench 221 forms a first vertical portion VP1. The first vertical portion VP1 covers the first horizontal portion HS1. The first horizontal portion HS1 and the first horizontal portion HS1 together form the first word line WL1. In some embodiments, the second gate conductive layer 440 in the second trench 221 and the third trench 321 together form the first vertical portion VP1.

[0246] The second gate conductive layer 440 in the fifth trench 521 forms a second vertical portion VP2, which covers the second horizontal portion HS2 and together forms the second word line WL2. In some embodiments, the second gate conductive layer 440 in the fifth trench 521 and the sixth trench 621 together form the second vertical portion VP2.

[0247] The manufacturing method of the memory of this embodiment forms a three-dimensional architecture based on a stacked structure formed by silicon oxide and a semiconductor doping layer. When forming the semiconductor doping layer, the conductive ions in the semiconductor doping layer are activated by in-situ doping to make the semiconductor doping layer conductive. In this way, after the isolation trench is formed, the semiconductor doping layer in the bit line area directly forms the bit line, and the semiconductor doping layer in the selection area forms the selection line. There is no need to perform the step of replacing the conductive material, thereby improving the process efficiency.

[0248] The manufacturing method of the memory of this embodiment forms a second trench and a fifth trench in the isolation layer, reducing the steps of etching the stacked structure; at the same time, the stacked structure is used to protect the first trench and the fourth trench, and the semiconductor material layer, the gate dielectric material layer and the first gate conductive layer in the second trench and the fifth trench are removed from the inside to the outside or from the outside to the inside, thereby avoiding the formation of parasitic devices by residual conductive material and preventing the parasitic devices from affecting the performance of the memory. The number of three-dimensional stacked layers of the memory can be further increased, thereby improving the integration density of the memory.

[0249] The manufacturing method of the memory of this embodiment has a transistor with a lower off-state current formed in the memory, which can reduce the leakage of the memory, which is beneficial to reducing the power consumption of the memory, reducing the size of the device in the memory, and improving the array density of the device in the memory.

[0250] Some embodiments of the present disclosure provide a method for manufacturing a memory, as shown in FIG3 , which shows a flow chart of the method for manufacturing a memory according to some embodiments of the present disclosure. FIG35 to FIG53 are schematic diagrams of various stages of the method for manufacturing a memory. The method for manufacturing a memory is described below in conjunction with FIG35 to FIG53 and with reference to FIG52 , FIG57 , and FIG58 . As shown in FIG3 , the method for manufacturing a memory includes the following steps:

[0251] Step S310: Provide a substrate and form a stacked structure on the substrate, the stacked structure including alternating first sub-layers and second sub-layers, defining a memory cell region, a bit line region and a selection region in the stacked structure, the memory cell region and the bit line region are arranged along a first direction, and the selection region is at one end of the bit line region along a second direction.

[0252] 35 , the stacked structure 200 includes first sublayers 210 and second sublayers 220 alternately stacked along a third direction D3. The first sublayers 210 are silicon oxide layers, and the second sublayers 220 are silicon nitride layers. Both the top and bottom layers of the stacked structure 200 are first sublayers 210 (i.e., silicon oxide layers).

[0253] In some embodiments, the stacked structure 200 is formed on the substrate 100 by using the following implementation methods:

[0254] 35 , a chemical vapor deposition process, an atomic layer deposition process, or a sputtering process can be used to alternately deposit silicon oxide layers and silicon nitride layers, and the cycle can be repeated several times to form a stacked structure 200. The silicon oxide layers and silicon nitride layers of the stacked structure 200 can be alternately stacked in 2 to 1024 layers or more. For example, the silicon oxide layers and silicon nitride layers can be alternately stacked in 48 layers, 64 layers, 128 layers, 256 layers, or 512 layers.

[0255] Referring to Figure 5 , a stacked structure 200 is laid out according to the structure of the memory to be formed. A memory cell region Z1, a bit line region Z2, and a selection region Z3 are defined on the stacked structure 200. In this embodiment, a memory cell region Z1 is defined on either side of the bit line region Z2 along a first direction D1, and a selection region Z3 is defined at one end of the bit line region Z2 along a second direction D2. The first direction D1 is parallel to the substrate 100, and the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1.

[0256] Step S320 : forming an isolation trench, wherein the isolation trench vertically penetrates the stacked structure and extends along a first direction to divide the stacked structure of the memory cell area into at least one strip structure extending along the first direction.

[0257] The implementation of forming the isolation trench is the same as that in step S220 in the above embodiment, and will not be repeated here.

[0258] The difference between some embodiments and the above-mentioned embodiments is that, as shown in Figure 36, referring to Figure 36, the stacked structure 200 includes alternating silicon oxide layers and silicon nitride layers. Therefore, after the isolation trench 130 is formed, the stacked structure 200 in which the bit line area Z2 is retained extends along the second direction D2, and the stacked structure 200 in which the selection area Z3 is retained extends along the first direction D1.

[0259] Step S330: etching and removing the entire second sub-layer, and forming an air layer in the area where the second sub-layer is removed.

[0260] In this embodiment, etching to remove the entire second sub-layer includes the following steps:

[0261] Step S331 : forming a first isolation layer, wherein the first isolation layer fills a portion of the isolation trench.

[0262] As shown in FIG. 37 , a chemical vapor deposition process or a physical vapor deposition process may be selected to deposit the first isolation layer 231 , and the material of the first isolation layer 231 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0263] Step S332: etching and removing a portion of the first isolation layer to form a second sub-trench in the isolation trench, wherein the second sub-trench exposes a portion of the sidewall of the stacked structure.

[0264] As shown in FIG38 , along the first direction D1 , the strip structure 300 in the memory cell region Z1 defines a first region A1 and a second region A2 arranged in sequence away from the bit line region Z2 . The first region A1 is close to the bit line region Z2 , and the second region A2 is away from the bit line region Z2 .

[0265] In this embodiment, as shown in Figures 39, 40, and 41, a fifth mask layer (not shown in the figures) is formed on the top surface of the structure, the fifth mask layer exposes a portion of the top surface of the first isolation layer 231, and the first isolation layer 231 exposed by the fifth mask layer is etched away to expose a portion of the isolation trench 130. In some embodiments, the isolation trench 130 exposed in this step is defined as a second sub-trench 132, and the second sub-trench 132 exposes a portion of the side wall of the stacked structure 200 of the first area A1. The retained first isolation layer 231 is used to support the architecture of the stacked structure 200.

[0266] Step S333: etching and removing the entire second sub-layer based on the second sub-trench.

[0267] As shown in Figure 42, referring to Figure 39, Figure 40, and Figure 41, an etching solution is injected into the second sub-groove 132. The etching solution can be a phosphoric acid solution. The entire second sub-layer 220 (that is, the silicon nitride layer, hereinafter collectively referred to as the silicon nitride layer) is dissolved and removed by the etching solution. The entire silicon nitride layer is removed, and an air layer 240 is formed at the original position of the silicon nitride layer. Along the third direction D3, the silicon oxide layer and the air layer 240 are alternately arranged.

[0268] Step S340 : forming a bit line in the air layer of the bit line region, wherein the bit line extends along a second direction parallel to the substrate and intersecting the first direction.

[0269] The bit line BL is formed in the air layer 240 of the bit line region Z2 using the following methods:

[0270] 42 and 53 , an atomic layer deposition process or a chemical vapor deposition process may be used to deposit a conductive metal material layer, which fills the air layer 240 and a portion of the second sub-trench 132. The conductive metal material layer outside the bit line region Z2 is then removed by etching, leaving the conductive metal material layer in the air layer 240 in the bit line region Z2 to form the bit lines BL. The bit lines BL extend along the second direction D2 and are spaced apart along the third direction D3.

[0271] The material of the bit line BL may include at least one of titanium or a titanium compound, tantalum or a tantalum compound, tungsten or a tungsten compound, and copper or a copper compound. In some embodiments, the material of the bit line BL includes metallic tungsten, so that the resistance of the bit line BL is lower and the conductivity is better.

[0272] Step S350: forming a conductor layer, where the conductor layer fills the area not filled by the air layer.

[0273] As shown in FIG43 , referring to FIG42 , an atomic layer deposition process or a chemical vapor deposition process can be used to deposit material for a conductive layer 250 to fill the unfilled area of ​​the air layer and the second sub-trench 132. The conductive layer material in the second sub-trench 132 is then removed by etching, and a conductive layer 250 is formed in the unfilled area of ​​the air layer 240. Referring to FIG53 , the conductive layer 250 in the selection zone Z3 forms selection lines SL, which extend along the first direction D1 and are spaced apart along the third direction D3.

[0274] The material of the conductive layer 250 may include titanium or a titanium compound, tantalum or a tantalum compound. In some embodiments, the material of the conductive layer 250 includes titanium nitride.

[0275] As shown in FIG. 44 , referring to FIG. 43 , a second isolation layer 232 is then filled in the second sub-trench 132 .

[0276] Step S360: forming a capacitor at one end of the memory cell region away from the bit line region.

[0277] In some embodiments, forming a capacitor at one end of the memory cell region away from the bit line region includes the following steps:

[0278] Step S361 : etching and removing a portion of the first sub-layer away from one end of the bit line region, exposing a portion of the surface of the conductive layer away from the one end of the bit line region.

[0279] As shown in Figure 45, referring to Figure 44, a second mask layer (not shown in the figure) is formed on the top surface of the structure, and the second mask layer exposes the top surface of the first isolation layer 231 connected to the second area A2. The first isolation layer 231 connected to the second area A2 is etched and removed based on the second mask layer to form a first sub-groove 131 connected to the second area A2, and the sidewalls of the first sub-groove 131 expose part of the surface of the silicon oxide layer and the conductor layer 250 of the second area A2.

[0280] Then, as shown in FIG. 46 , referring to FIG. 45 , the silicon oxide layer in the second region A2 is removed by etching based on the first sub-trench 131 , exposing the surface of the conductor layer 250 in the second region A2 .

[0281] Step S362: forming a dielectric layer, where the dielectric layer covers the surface exposed by the conductive layer.

[0282] 47 , a dielectric layer 610 is deposited by atomic layer deposition to uniformly cover the exposed surface of the semiconductor doped layer in the second region A2. The material of the dielectric layer 610 is the same as that used to form the dielectric layer 610 in step S242 in the above embodiment, and will not be further described here.

[0283] Step S363: forming an upper electrode, where the upper electrode covers the dielectric layer.

[0284] As shown in Figure 47, an atomic layer deposition process can be used to deposit and form an upper electrode 620, which covers the surface of the dielectric layer 610. The material of the upper electrode 620 is the same as the material of the upper electrode 620 formed in step S243 in the above embodiment, and will not be repeated here.

[0285] The conductive layer 250 covered by the dielectric layer 610 (i.e., the conductive layer 250 of the second area A2), the dielectric layer 610 and the upper electrode 620 form a capacitor 600 at one end of the storage cell area Z1 away from the bit line area Z2 (i.e., the second area A2), and the conductive layer 250 covered by the dielectric layer 610 (i.e., the conductive layer 250 of the second area A2) serves as the lower electrode 630 of the capacitor 600.

[0286] In some embodiments, the following steps are further performed after step S363:

[0287] Step S364 : forming a common upper electrode plate, which covers the upper electrode and fills the unfilled areas between the conductive layers 250 and the unfilled areas in the first sub-trench.

[0288] 48 , in some embodiments, the process for forming the common upper electrode plate 640 and the materials and selection of the common upper electrode plate 640 are the same as those in S244 in the above embodiment and are not described again herein.

[0289] Step S370 : forming a second trench, wherein the second trench exposes a portion of the sidewall of the first region, and forming a fifth trench, wherein a sidewall of the fifth trench exposes a portion of the sidewall of the bit line region.

[0290] As shown in Figure 49, a third mask layer (not shown in the figure) is formed on the top surface of the structure. The third mask layer defines the pattern of the second groove 221 and the fifth groove 521. The third mask layer is etched and removed to expose the first isolation layer 231 and the second isolation layer 232, forming the second groove 221 and the fifth groove 521, respectively.

[0291] Along the first direction D1 , the second trench 221 and the bit line region Z2 are spaced apart by a predetermined distance. The second trench 221 is disposed close to the strip structure 300 and exposes a portion of the sidewall of the strip structure 300 .

[0292] Along the second direction D2, the fifth trench 521 is spaced apart from the selection zone Z3 by a predetermined distance. The fifth trench 521 is disposed close to the stack of the bit line zone Z2 and exposes a portion of a sidewall of the stack of the bit line zone Z2.

[0293] Step S380: Etching the middle area of ​​the strip structure to remove part of the strip structure, forming a first groove between adjacent first sub-layers along a direction perpendicular to the substrate, and at the same time etching the bit line area to remove part of the stacked structure in the bit line area, forming a fourth groove between adjacent first sub-layers in the bit line area along a direction perpendicular to the substrate, and the fourth groove is set close to the selection area.

[0294] As shown in FIG50 , the strip structure 300 is etched based on the second trench 221, and the conductive layer 250 exposed by the second trench 221 is removed by etching to form the first trench 121. Referring to FIG52 , FIG57 , and FIG58 , the first trench 121 divides the conductive layer 250 of the memory cell region Z1 into two sections independently disposed on either side of the first trench 121 along a first direction D1. As shown in FIG55 , in the first region A1, the conductive layer 250 on the left side of the first trench 121 serves as the first source / drain 181 of the cell transistor MCT in the subsequently formed memory cell SU, while the conductive layer 250 on the right side of the first trench 121 serves as the second source / drain 182 of the cell transistor MCT in the subsequently formed memory cell SU. It can be seen that the first source / drain 181 is connected to the capacitor 600, and the second source / drain 182 is connected to the bit line.

[0295] As shown in Figure 50, the bit line region Z2 is etched based on the fifth trench 521, and the conductive metal material layer exposed by the fifth trench 521 is removed to form a fourth trench 421. Referring to Figures 52, 57, and 58, the fourth trench 421 divides the conductive metal material layer in the bit line region Z2 into two sections independently arranged on either side of the fourth trench 421 along the second direction D2. The section away from the select line SL serves as the third source / drain 281 of the subsequently formed select transistor ST, and the section near the select region Z3 serves as the fourth source / drain 282 of the subsequently formed select transistor ST. It can be seen that the third source / drain 281 is connected to the bit line BL, and the fourth source / drain 282 is connected to the select line SL.

[0296] Step S390: A first semiconductor channel and a first gate dielectric layer are formed in the first trench, wherein the first semiconductor channel covers the trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel. At the same time, a second semiconductor channel and a second gate dielectric layer are formed in the fourth trench, wherein the second semiconductor channel covers the trench wall of the fourth trench, and the second gate dielectric layer covers the second semiconductor channel.

[0297] Step S400 : forming a first word line and forming a second word line at the same time.

[0298] 51 , 52 , and 53 , the implementation methods of steps S390 and S400 in some embodiments are the same as those of steps S270 and S280 in the above-mentioned embodiments, and are not described again herein.

[0299] The memory manufacturing method of this embodiment can form a three-dimensional memory based on a stacked structure formed by silicon oxide and silicon nitride layers, or can form a three-dimensional memory based on a stacked structure formed by silicon oxide and semiconductor doping layers. The memory manufacturing method has a wide range of applications.

[0300] According to an exemplary embodiment, a memory is provided. Referring to Figures 52, 55, 56, 57, and 58, and to Figures 33 and 53, the memory includes a substrate 100, at least one first word line WL1, and at least one column of memory cell columns SUC; the first word line WL1 includes a first vertical portion VP1 and at least one first horizontal portion HS1, the first vertical portion VP1 is vertically arranged on the substrate 100, and the at least one first horizontal portion HS1 is spaced apart in a direction perpendicular to the substrate 100 and connected to the first vertical portion VP1; at least one column of memory cell columns SUC, the memory The cell column SUC includes at least one memory cell SU arranged in a direction perpendicular to the substrate 100. Each memory cell SU includes a cell transistor MCT. A first horizontal portion HS1 serves as a gate G1 of the cell transistor MCT. The cell transistor MCT includes a first gate dielectric layer 171 and a first semiconductor channel 161 disposed sequentially in a direction away from the first horizontal portion HS1. The cell transistor MCT also includes a first source / drain 181 and a second source / drain 182 disposed on opposite sides of the first semiconductor channel 161 along a first direction D1 parallel to the substrate 100. The memory device has no conductive film layers left over from the manufacturing process and is free of parasitic devices, thereby improving the response speed of the semiconductor structure, avoiding response delays, and enhancing the yield and electrical performance of the semiconductor structure.

[0301] The first word line WL1 includes a first vertical portion VP1 and at least one first horizontal portion HS1. The first horizontal portion HS1 serves as the gate G1 of the cell transistor MCT. The first horizontal portion HS is not limited by the length of the first vertical portion VP1 of the first word line WL1. The first horizontal portion HS can increase the length of the gate G1 of the cell transistor MCT, thereby enhancing the control capability of the gate G1 of the cell transistor MCT. In addition, the first semiconductor channel 161 at the position of the first horizontal portion HS1 can be protected to avoid damage to the first semiconductor channel 161 at the position of the first horizontal portion HS1 when the parasitic channel is removed.

[0302] 52 and 53 , in a plane parallel to the first direction D1 and perpendicular to the substrate 100 , the first semiconductor channel 161 surrounds the first horizontal portion HS1 . This configuration can enhance the control capability of the gate G1 of the cell transistor MCT.

[0303] In some embodiments, referring to Figures 52 and 53, the first semiconductor channel 161 includes a connecting channel 1611, which is located on one side of the first horizontal portion HS1 in the second direction D2. The second direction D2 is parallel to the substrate 100 and intersects with the first direction D1. This configuration allows the first semiconductor channel 161 to further cover the first horizontal portion HS1, further enhancing the control capability of the gate G1 of the cell transistor MCT.

[0304] In some embodiments, referring to FIG. 52 and FIG. 53 , and referring to FIG. 33 and FIG. 53 , the first semiconductor channel 161 is cup-shaped, and the first semiconductor channel 161 is sleeved on the first horizontal portion HS1 .

[0305] One side of the first horizontal portion HS1 is connected to the first vertical portion VP1. Except for the area connected to the first vertical portion VP1, the entire outer peripheral surface of the first horizontal portion HS1 is covered by the first semiconductor channel 161. For example, referring to Figures 52 and 53, in some embodiments, the cross-sectional view of the first horizontal portion HS1 along the direction parallel to the substrate 100 is a square or a rectangle, the side surface of one side of the first horizontal portion HS1 is connected to the first vertical portion VP1, and the remaining five surfaces of the first horizontal portion HS1 are covered by the first semiconductor channel 161. The first semiconductor channel 161 covers a larger area of ​​the first horizontal portion HS1, and the control capability of the gate G1 of the unit transistor MCT is greater.

[0306] In some embodiments, as shown in Figures 55 and 56, the storage unit SU also includes a semiconductor doping layer 220a, the semiconductor doping layer 220a includes two sections arranged on both sides of the first semiconductor channel 161 relatively along the first direction D1, and the first source / drain 181 and the second source / drain 182 are respectively arranged in the semiconductor doping layer 220a on both sides of the first semiconductor channel 161.

[0307] In some embodiments, as shown in Figures 57 and 58, the storage unit SU also includes a conductor layer 250, the conductor layer 250 includes two sections arranged on both sides of the first semiconductor channel 161 relatively along the first direction D1, and the first source / drain 181 and the second source / drain 182 are respectively arranged in the conductor layer 250 on both sides of the first semiconductor channel 161.

[0308] In some embodiments, the memory unit SU further includes a memory device for storing data. The memory device for storing data may be a capacitor 600 or a magnetic tunnel junction or a phase change element.

[0309] 52 , 55 , 56 , 57 , and 58 , the memory unit SU further includes a capacitor 600 , which is disposed on one side of the cell transistor MCT along the first direction D1 , and is connected to the first source / drain 181 of the cell transistor MCT.

[0310] 52 , 55 , 56 , 57 , and 58 , the capacitor 600 includes a lower electrode 630, a dielectric layer 610, and an upper electrode 620. The lower electrode 630 is connected to the first source / drain 181, and the dielectric layer 610 is disposed between the upper electrode 620 and the lower electrode 630. The dielectric layer 610 covers the lower electrode 630, and the upper electrode 620 covers the dielectric layer 610.

[0311] In some embodiments, referring to Figures 52, 55, 56, 57, and 58, the lower electrode 630 of the capacitor 600 is arranged in the semiconductor doping layer 220a, the lower electrode 630 of the capacitor 600 and the first source / drain 181 are arranged on the same side, the first source / drain 181 is arranged close to the first semiconductor channel 161, and the lower electrode 630 of the capacitor 600 is arranged away from the first semiconductor channel 161.

[0312] In some embodiments, referring to Figures 52, 55, 56, 57, and 58, the lower electrode 630 of the capacitor 600 is arranged in the conductive layer 250. Similarly, the lower electrode 630 of the capacitor 600 and the first source / drain 181 are arranged on the same side, the first source / drain 181 is arranged close to the first semiconductor channel 161, and the lower electrode 630 of the capacitor 600 is arranged away from the first semiconductor channel 161.

[0313] In some embodiments, referring to Figures 52, 55, 56, 57, and 58, in a plane parallel to the substrate 100, the upper electrodes 620 of multiple capacitors 600 are interconnected to form a closed pattern. This arrangement can increase the relative area of ​​the upper electrode 620 and the lower electrode 630, thereby increasing the capacitance.

[0314] In some embodiments, referring to Figures 52, 55, 56, 57, and 58, a common upper electrode plate 640 is provided in the closed figure, and the common upper electrode plate 640 is connected to the upper electrode 620. Such a setting can increase the volume ratio of the capacitor 600 in the memory and increase the storage capacitance of the memory.

[0315] In some embodiments, referring to Figures 52, 55, 56, 57, and 58, the memory further includes at least one bit line BL, which is arranged at intervals along a direction perpendicular to the substrate 100, and extends along a second direction D2. The bit line BL is connected to the second source / drain of a plurality of cell transistors MCT arranged along the second direction D2, and the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1. The bit line BL is used to perform a read or write operation on the memory cell SU where the cell transistor MCT is located when the cell transistor MCT is turned on.

[0316] In some embodiments, referring to Figures 52, 55, 56, 57, and 58, the memory also includes a second word line WL2, the second word line WL2 includes a second vertical portion VP2 and at least one second horizontal portion HS2, the second vertical portion VP2 is vertically arranged on the substrate 100, and the at least one second horizontal portion HS2 is arranged at intervals in a direction perpendicular to the substrate 100 and connected to the second vertical portion VP2.

[0317] 52 , 55 , 56 , 57 , and 58 , the memory further includes at least one selection transistor ST, which is arranged at intervals along a direction perpendicular to the substrate 100. The second horizontal portion HS2 serves as the gate G2 of the selection transistor ST. The selection transistor ST includes a second gate dielectric layer 271 and a second semiconductor channel 261 sequentially arranged in a direction away from the second horizontal portion HS2. The selection transistor ST further includes a third source / drain 281 and a fourth source / drain 282 relatively arranged on both sides of the second semiconductor channel 261 along the second direction D2. The third source / drain 281 of the selection transistor ST is connected to the bit line BL in a one-to-one correspondence.

[0318] 52, 55, 56, 57, and 58, the memory device further includes at least one select line SL. The at least one select line SL is arranged at intervals perpendicular to the substrate 100. The select line SL extends along a first direction D1 and is connected one-to-one to the fourth source / drain 282 of the select transistor ST. The select line SL is used to provide a voltage to the select transistor ST and control the on / off state of the select transistor ST via the voltage, thereby controlling the connected memory cell SU via the bit line BL.

[0319] According to an exemplary embodiment, an electronic device is provided, which includes the memory in the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0320] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0321] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for manufacturing a memory, comprising the following steps: Providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising first sub-layers and second sub-layers stacked alternately, and defining a memory cell region and a bit line region in the stacked structure; forming an isolation trench, wherein the isolation trench penetrates the stacked structure along a direction perpendicular to the substrate, the isolation trench extending along a first direction and dividing the stacked structure of the memory cell area into at least one strip structure extending along the first direction, wherein the first direction is parallel to the substrate; Etching a middle region of the strip structure to remove a portion of the strip structure, and forming a first groove between adjacent first sub-layers along a direction perpendicular to the substrate; forming a first semiconductor channel and a first gate dielectric layer in the first trench, wherein the first semiconductor channel covers a trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel; A first word line is formed, wherein the first word line includes a first horizontal portion formed in the first trench and a first vertical portion formed in the isolation trench, wherein the first horizontal portion covers the first gate dielectric layer, the first vertical portion is vertically disposed on the substrate, and the first horizontal portion is connected to the first vertical portion.

2. The method for manufacturing a memory according to claim 1, wherein: Forming a first trench between adjacent first sub-layers, comprising: forming an isolation layer in the isolation trench; forming a second trench in the isolation layer, wherein a sidewall of the second trench exposes a portion of the surface of the middle region of the strip structure; The strip structure exposed by the second trench is removed by etching to form the first trench, and the first trench and the first sublayer in the middle region are alternately arranged along a direction perpendicular to the substrate.

3. The method for manufacturing a memory according to claim 2, wherein: Forming a first semiconductor channel and a first gate dielectric layer in the first trench, comprising: forming a semiconductor material layer, wherein the semiconductor material layer covers the groove wall of the first groove and the groove wall of the second groove; forming a gate dielectric material layer, wherein the gate dielectric material layer covers the semiconductor material layer; The semiconductor material layer and the gate dielectric material layer in the second trench are removed, the semiconductor material layer in the first trench forms the first semiconductor channel, and the gate dielectric material layer in the first trench forms the first gate dielectric layer.

4. The method for manufacturing a memory according to claim 3, wherein: Forming a first word line, comprising: forming the first horizontal portion in the first trench, the first horizontal portion covering the first gate dielectric layer and filling the first trench, and a sidewall of the second trench exposing a portion of a surface of the first horizontal portion; The first vertical portion is formed to contact the exposed surface of the first horizontal portion and fill the second trench.

5. The method for manufacturing a memory according to claim 4, wherein: Forming the first horizontal portion in the first trench includes: After forming the gate dielectric material layer, forming a first gate conductive layer, the first gate conductive layer covers the gate dielectric material layer and fills the first trench and the second trench; The first gate conductive layer in the second trench is removed by etching, and the first gate conductive layer in the first trench is retained to form the first horizontal portion.

6. The method for manufacturing a memory according to claim 5, wherein: The production method comprises: The first gate conductive layer, the gate dielectric material layer and the semiconductor material layer in the second trench are sequentially etched and removed to expose the second trench.

7. The method for manufacturing a memory according to claim 5, wherein: The production method comprises: Etching and removing a portion of the isolation layer around the second trench to form a third trench, wherein the third trench exposes the semiconductor material layer located in the second trench; The semiconductor material layer, the gate dielectric material layer and the first gate conductive layer in the second trench are removed based on the third trench etching.

8. The method for manufacturing a memory according to claim 4, wherein: Forming the first vertical portion includes: A second gate conductive layer is formed, wherein the second gate conductive layer at least fills the second trench to form the first vertical portion.

9. The method for manufacturing a memory according to any one of claims 1 to 8, wherein: Along the first direction, the first trench and the bit line region are spaced apart by a predetermined distance.

10. The method for manufacturing a memory according to any one of claims 1 to 8, wherein: A selection area is defined in the stacked structure, the memory cell area and the bit line area are arranged along the first direction, the selection area is at one end of the bit line area along a second direction, and the second direction is parallel to the substrate and intersects with the first direction; The production method further comprises: The bit line region is etched to remove a portion of the stacked structure in the bit line region, and a fourth trench is formed between adjacent first sub-layers in the bit line region along a direction perpendicular to the substrate, wherein the fourth trench is disposed close to the selection region.

11. The method for manufacturing a memory according to claim 10, wherein: The production method further comprises: While forming the first semiconductor channel and the first gate dielectric layer in the first trench, forming a second semiconductor channel and a second gate dielectric layer in the fourth trench, wherein the second semiconductor channel covers a trench wall of the fourth trench, and the second gate dielectric layer covers the second semiconductor channel; While forming the first word line, a second word line is formed, the second word line includes a second horizontal portion formed in the fourth trench and a second vertical portion formed in the isolation trench, the second horizontal portion covers the second gate dielectric layer and fills the fourth trench, the second vertical portion is vertically arranged on the substrate, and the second horizontal portion and the second vertical portion are connected.

12. The method for manufacturing a memory according to claim 1, wherein: The first sublayer is a silicon oxide layer, the second sublayer is a semiconductor doping layer, and after the isolation trench is formed, the semiconductor doping layer in the bit line region forms a bit line extending along a second direction, and the second direction is parallel to the substrate and intersects with the first direction.

13. The method for manufacturing a memory according to claim 12, wherein: The production method further comprises: Etching and removing a portion of the first sub-layer away from one end of the bit line region to expose a portion of the surface of the semiconductor doped layer away from one end of the bit line region; forming a dielectric layer, the dielectric layer covering the exposed surface of the semiconductor doped layer; An upper electrode is formed, the upper electrode covering the dielectric layer.

14. The method for manufacturing a memory according to claim 1, wherein: The first sublayer is a silicon oxide layer, and the second sublayer is a silicon nitride layer; After forming an isolation trench in the memory cell region, the manufacturing method includes: etching to remove the entire second sub-layer, and forming an air layer in the area where the second sub-layer is removed; forming a bit line in the air layer of the bit line region, wherein the bit line extends along a second direction parallel to the substrate and intersecting with the first direction; A conductor layer is formed, the conductor layer filling the area where the air layer is not filled.

15. The method for manufacturing a memory according to claim 14, wherein: The production method further comprises: Etching and removing a portion of the first sub-layer away from one end of the bit line region to expose a portion of the surface of the conductor layer away from one end of the bit line region; forming a dielectric layer, the dielectric layer covering the exposed surface of the conductor layer; An upper electrode is formed, the upper electrode covering the dielectric layer.

16. A memory, comprising: substrate; at least one first word line, the first word line comprising a first vertical portion and at least one first horizontal portion, the first vertical portion being vertically disposed on the substrate, and at least one first horizontal portion being arranged at intervals in a direction perpendicular to the substrate and connected to the first vertical portion; at least one memory cell column, the memory cell column comprising at least one memory cell spaced apart and arranged in a direction perpendicular to the substrate; The storage cell includes a cell transistor, the first horizontal portion serves as a gate of the cell transistor, the cell transistor includes a first gate dielectric layer and a first semiconductor channel sequentially arranged in a direction away from the first horizontal portion, and the cell transistor also includes a first source / drain and a second source / drain relatively arranged on both sides of the first semiconductor channel along a first direction, and the first direction is parallel to the substrate.

17. The memory according to claim 16, wherein: In a plane parallel to the first direction and perpendicular to the substrate, the first semiconductor channel surrounds the first horizontal portion.

18. The memory according to claim 17, wherein: The first semiconductor channel includes a connection channel, and the connection channel is located on one side of the first horizontal portion in a second direction, and the second direction is parallel to the substrate and intersects with the first direction.

19. The memory according to claim 17, wherein: The first semiconductor channel is cup-shaped and is sleeved on the first horizontal portion.

20. The memory according to claim 16, wherein: The memory cell further includes a capacitor, which is disposed on one side of the cell transistor along the first direction, and is connected to the first source / drain of the cell transistor.

21. The memory according to claim 20, wherein: The capacitor includes a lower electrode, a dielectric layer and an upper electrode, wherein the lower electrode is connected to the first source / drain, and the dielectric layer is disposed between the upper electrode and the lower electrode.

22. The memory according to claim 21, wherein: In a plane parallel to the substrate, the upper electrodes of a plurality of the capacitors are connected to each other to form a closed pattern.

23. The memory according to claim 22, wherein: A common upper electrode plate is provided in the closed pattern, and the common upper electrode plate is connected to the upper electrode.

24. The memory according to claim 16, wherein: The memory also includes: At least one bit line, at least one of the bit lines is arranged at intervals along a direction perpendicular to the substrate, the bit line extends along a second direction, the bit line is connected to the second source / drain of a plurality of the unit transistors arranged along the second direction, and the second direction is parallel to the substrate and intersects with the first direction.

25. The memory according to claim 24, wherein: The memory also includes: a second word line, the second word line comprising a second vertical portion and at least one second horizontal portion, the second vertical portion being vertically disposed on the substrate, and at least one second horizontal portion being arranged at intervals in a direction perpendicular to the substrate and connected to the second vertical portion; At least one selection transistor, at least one of the selection transistors is arranged at intervals along a direction perpendicular to the substrate, the second horizontal portion serves as a gate of the selection transistor, the selection transistor includes a second gate dielectric layer and a second semiconductor channel sequentially arranged in a direction away from the second horizontal portion, and the selection transistor also includes a third source / drain and a fourth source / drain relatively arranged on both sides of the second semiconductor channel along the second direction; the third source / drain of the selection transistor is connected to the bit line in a one-to-one correspondence.

26. The memory according to claim 25, wherein: The memory also includes: At least one selection line, at least one of the selection lines is arranged at intervals along a direction perpendicular to the substrate, the selection line extends along the first direction, and the selection line is connected to the fourth source / drain of the selection transistor in a one-to-one correspondence.

27. An electronic device comprising the memory according to any one of claims 16 to 26.

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