Computing system, data processing method, network interface card, host and storage medium

Abstract

Provided in the embodiments of the present disclosure are a computing system, a data processing method, a network interface card, a host and a storage medium. A hardware processing unit is added to the network interface card and is used for performing check code calculation on target application data to be transmitted. The check code calculation for the target application data is offloaded to hardware for completion, so that not only can serial processing resources of the host be released, but hardware acceleration for the check code calculation can also be realized, thereby improving the processing efficiency of the check code calculation. In addition, the network interface card is located on a transmission link of the target application data, and therefore a check code of the target application data is calculated in the hardware processing unit of the network interface card, so that in-path offloading of the check code calculation to the hardware is realized, which can shorten a data link of the application data and further improve the efficiency of the check code calculation for the application data.

Description

Computing system, data processing method, network card, host and storage medium

[0001] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on November 27, 2023, with application number 202311598344.2 and application name “Computing system, data processing method, network card, host and storage medium”, all contents of which are incorporated by reference in this disclosure. Technical Field

[0002] The embodiments of the present disclosure relate to the field of communication technologies, and in particular to a computing system, a data processing method, a network card, a host, and a storage medium. Background Art

[0003] For cloud computing platforms' storage services, the consistency and correctness of stored data are crucial. During data transmission and storage, ensuring the accuracy of the data being transmitted and stored is crucial to the effectiveness and reliability of storage services. Currently, the industry generally performs checksum calculations on the transmitted data at the sending end and performs accuracy verification on the received data at the receiving end to ensure data correctness.

[0004] In existing solutions, the central processing unit (CPU) of a computing device is often used to calculate the check code of the data to be sent and verify the accuracy of the received data. The CPU software performs the check code calculation and verification of the data, which has low processing efficiency.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a computing system, a data processing method, a network card, a host, and a storage medium, which are used to implement hardware offloading of data check code calculations, thereby helping to improve the efficiency of data check code calculations.

[0007] In a first aspect, an embodiment of the present disclosure provides a computing system, comprising: a host and a network card; the host and the network card are communicatively connected; the network card comprises: a hardware processing unit and a network interface; the computing system further comprises: a serial processing unit; the serial processing unit is disposed on the network card or the host; the serial processing unit is communicatively connected to the hardware processing unit;

[0008] The serial processing unit runs a network protocol stack, is used to obtain memory address information of target application data of the application program, and generate a network protocol header through the network protocol stack; and provides the memory address information of the target application data and the network protocol header to the hardware processing unit;

[0009] The hardware processing unit is used to read the target application data from the host's memory using a direct memory access (DMA) method according to the memory address information of the target application data, and calculate a check code for the target application data; assemble the target application data, the check code for the target application data, and the network protocol header into a first message; and send the first message to a receiving end through the network interface.

[0010] Optionally, the hardware processing unit or the serial processing unit is further configured to:

[0011] receiving a target message sent by a sending end through the network interface;

[0012] Obtaining payload data and a check code of the payload data from the target message;

[0013] The accuracy of the payload data is checked using the check code of the payload data.

[0014] In a second aspect, an embodiment of the present disclosure further provides a data processing method, applicable to a hardware processing unit on a network card, the network card being used for communication with a host; the method comprising:

[0015] Acquire memory address information and a network protocol header of target application data of an application program provided by a serial processing unit; the serial processing unit is provided in the host or the network card;

[0016] Reading the target application data from the host's memory using a direct memory access (DMA) method according to the memory address information of the target application data;

[0017] Calculating a check code of the target application data; assembling the target application data, the check code of the target application data, and the network protocol header into a first message;

[0018] The first message is sent to a receiving end through the network interface of the network card.

[0019] In a third aspect, an embodiment of the present disclosure further provides a data processing method, applicable to a serial processing unit on a network card or a host, wherein the network card is communicatively connected to the host; the method comprises:

[0020] Get the memory address information of the target application data of the application;

[0021] Generate a network protocol header by running the network protocol stack;

[0022] The memory address information of the target application data and the network protocol header are provided to the hardware processing unit of the network card, so that the hardware processing unit can read the target application data from the memory of the host using a direct memory access (DMA) method according to the memory address information of the target application data and calculate a check code for the target application data; the target application data, the check code for the target application data and the network protocol header are assembled into a first message; and the first message is sent to a receiving end through the network interface of the network card.

[0023] In a fourth aspect, an embodiment of the present disclosure further provides a data processing method applicable to a hardware processing unit on a network card, comprising:

[0024] Obtaining a target message received by the network interface of the network card;

[0025] Obtaining payload data and a check code of the payload data from the target message;

[0026] The accuracy of the payload data is checked using the check code of the payload data.

[0027] In a fifth aspect, an embodiment of the present disclosure further provides a network card, comprising: a hardware processing unit and a network interface; the network card is used to communicate with a host;

[0028] The hardware processing unit is communicatively connected to the serial processing unit; the serial processing unit is arranged on the network card or the host;

[0029] The hardware processing unit is used to execute the steps of the data processing method provided in the second aspect and / or the fourth aspect above;

[0030] The serial processing unit is used to execute the steps in the data processing method provided in the third aspect above.

[0031] In a sixth aspect, an embodiment of the present disclosure further provides a host, comprising: a memory and a processor; wherein the memory is used to store a computer program; the host is used to communicate with a network card;

[0032] The processor is coupled to the memory and is configured to execute the computer program to perform the steps in the data processing method provided in the third aspect.

[0033] In the seventh aspect, an embodiment of the present disclosure also provides a computer-readable storage medium storing computer instructions, which, when executed by one or more processors, causes the one or more processors to execute the steps in the data processing method provided in the second aspect and / or the third aspect and / or the fourth aspect above.

[0034] In an eighth aspect, an embodiment of the present disclosure further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps in the data processing method provided in the second aspect and / or the third aspect and / or the fourth aspect.

[0035] In the embodiment of the present disclosure, a hardware processing unit is added to the network card to perform check code calculation on the target application data to be transmitted. On the one hand, offloading the check code calculation of the target application data to the hardware can not only release the serial processing resources of the host, but also realize hardware acceleration of the check code calculation, thereby improving the processing efficiency of the check code calculation. On the other hand, the network card is located on the transmission link of the target application data. Therefore, calculating the check code of the target application data on the hardware processing unit of the network card realizes the hardware offloading of the check code calculation, which can shorten the data link of the application data and further improve the efficiency of the check code calculation of the application data.

[0036] These and other aspects of the present disclosure will become more apparent from the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figures 1a, 1b, 2a and 2b are schematic diagrams of the structure of a computing device in a traditional storage system;

[0039] Figures 3a, 3b, 4a and 4b are schematic diagrams of the structure of a computing system provided by an embodiment of the present disclosure;

[0040] FIG5 is a schematic diagram of the data segmentation principle provided by an embodiment of the present disclosure;

[0041] FIG6 is a schematic diagram of a data processing process according to an embodiment of the present disclosure;

[0042] FIG7 is a schematic diagram of data segmentation results provided by an embodiment of the present disclosure;

[0043] 8a and 8b are schematic diagrams of a data processing process when the computing system provided by an embodiment of the present disclosure serves as a receiving end;

[0044] FIG8c is a flow chart of a data processing method provided by an embodiment of the present disclosure;

[0045] 9 and 10 are flowcharts of other data processing methods provided by embodiments of the present disclosure;

[0046] FIG11 is a schematic diagram of the structure of a network card provided in an embodiment of the present disclosure;

[0047] FIG12 is a schematic diagram of the structure of a host provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the specific embodiments of the present disclosure and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0049] Figures 1a and 1b are schematic diagrams of the structure of a traditional storage system. As shown in Figures 1a and 1b, the storage system includes: a user-side computing device and a storage service device. Both the user-side computing device and the storage service device may include: a serial processing unit and a network card. The serial processing unit is generally a central processing unit (CPU). The serial processing unit and the network card can be connected to each other via a data bus. The data bus can be a serial interface data bus, such as a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interface, a universal serial bus (USB) serial interface, an RS485 interface, or an RS232 interface, etc., but is not limited thereto.

[0050] The serial processing unit 101 of the user-side computing device runs an application. An application is a computer program designed to complete one or more specific tasks and runs at the application layer. The application data generated by the application is considered user data and is typically encapsulated in the payload portion of a message, also known as payload data. To ensure data accuracy, a checksum is typically calculated on the data to be transmitted at the sending end, and the received data is checked for accuracy at the receiving end to ensure data correctness.

[0051] The serial processing units of the computing device and storage service device on the user side can run the storage service. In the computing device shown in FIG1a, the check code calculation and verification of the application data to be transmitted, as well as the network protocol stack are all performed by the serial processing unit. As shown in FIG1a, when the computing device on the user side needs to write data, it can act as a sending end, and its serial processing unit 101 can obtain the target application data to be transmitted of the application program; and the storage service run by the serial processing unit 101 performs a cyclic redundancy check (CRC) calculation on the target application data to obtain the CRC check code of the target application data; then, the target application data and the CRC check code are encapsulated through the network protocol stack to obtain the message to be transmitted; then, the message to be transmitted is sent to the storage service device as the receiving end through the network card 201.

[0052] The storage service device can receive the message to be transmitted through the network card 202 and transmit the message to be transmitted to the serial processing unit 102 of the storage service device. The serial processing unit 102 performs protocol parsing on the message to be transmitted through the network protocol stack to obtain the target application data and the CRC check code of the target application data. The serial processing unit 102 then uses the CRC check code to verify the accuracy of the target application data through the storage service.

[0053] Specifically, the serial processing unit 102 may calculate the CRC check code of the target application data using the same calculation method as the sender calculates the check code of the target application data. The calculated CRC check code is then compared with the CRC check code parsed from the message to be transmitted. If the two are the same, the target application data is determined to have passed the accuracy check; if the two are different, the target application data is determined to have failed the accuracy check.

[0054] For target application data that passes the accuracy check, the target application data may be stored in a storage medium through a storage service.

[0055] As shown in Figure 1b, when the computing device on the user side needs to read data, the storage service device can act as the sending end, and its serial processing unit 102 can obtain the application data to be read by the application in the computing device as the target application data to be transmitted by the application; and perform CRC calculation on the target application data through the target service run by the serial processing unit 102 to obtain the CRC check code of the target application data; then, encapsulate the target application data and the CRC check code through the network protocol stack to obtain the message to be transmitted; then, send the message to be transmitted to the storage service device as the receiving end through the network card 202.

[0056] The user's computing device can receive the message to be transmitted via the network card 201 and transmit it to the serial processing unit 101 of the storage service device. The serial processing unit 101 performs protocol parsing on the message to be transmitted through the network protocol stack to obtain the target application data and the CRC checksum of the target application data. The serial processing unit 101 then verifies the accuracy of the target application data using the CRC checksum through the target service.

[0057] The target application data that passes the accuracy check may be provided to the application program for use.

[0058] The CRC calculation and CRC verification methods in the storage system shown in Figures 1a and 1b are implemented by the serial processing unit software and consume the computing device's serial processing unit resources, such as CPU resources. When network throughput is high, performing checksum calculation and verification on every message introduces significant CPU resource overhead, resulting in lower checksum calculation and verification processing efficiency. Furthermore, in scenarios where the data path directly passes through hardware, the services running on the serial processing unit can only obtain some metadata and cannot perform checksum calculation and verification on the complete target application data.

[0059] To improve processing performance and reduce processing latency, some traditional solutions, as shown in Figures 2a and 2b, introduce dedicated hardware into the computing device, and implement CRC checksum calculation and verification based on the dedicated hardware, bypassing the interaction between software and hardware. Specifically, as shown in Figure 2a, when the computing device on the user side needs to write data, it can act as the sending end. After receiving the target application data, the storage service in its serial processing unit 101 sends the memory starting address and length of the target application data to the dedicated hardware 301.

[0060] The dedicated hardware 301 reads the target application data from the computing device's memory 401 based on the target application data's memory starting address and length, and calculates the CRC checksum for the target application data. Subsequently, the dedicated hardware 301 sends the CRC checksum for the target application data to the storage service within the serial processing unit 101. Furthermore, the serial processing unit 101, through the storage service, provides the target application data and its CRC checksum to the network protocol stack running within the serial processing unit 101. The network protocol stack then encapsulates the target application data and its CRC checksum into a message to be transmitted. The message to be transmitted is then sent to the receiving end via the network card 201.

[0061] For the storage service device acting as the receiving end, its network card 202 receives the message to be transmitted and sends it to the serial processing unit 102. The serial processing unit 102 performs protocol parsing on the message to be transmitted through the network protocol stack to obtain the target application data and the CRC check code of the target application data. The target application data and the CRC check code of the target application data are then stored in the memory 402. Furthermore, the serial processing unit 102 sends the memory starting address and length of the target application data and the CRC check code of the target application data to the dedicated hardware 302 through the storage service.

[0062] The dedicated hardware 302 retrieves the target application data and its CRC check code from the memory 402 based on the memory starting address and length of the target application data and its CRC check code. The dedicated hardware 302 then verifies the accuracy of the target application data based on the CRC check code. If the verification passes, the dedicated hardware 302 sends the verification result to the storage service. If the verification result is positive, the storage service may store the target application data in the storage medium.

[0063] As shown in Figure 2b, when a user-side computing device needs to read data, the storage service device acts as the sender. The storage service within its serial processing unit 102 retrieves the application data to be read from the storage medium as the target application data. The storage service within serial processing unit 102 then sends the target application data's memory starting address and length to dedicated hardware 302.

[0064] Dedicated hardware 302 reads the target application data from the computing device's memory 402 based on the target application data's memory starting address and length, and calculates a CRC checksum for the target application data. Dedicated hardware 302 then sends the CRC checksum for the target application data to the storage service within serial processing unit 102. Furthermore, serial processing unit 102, through the storage service, provides the target application data and its CRC checksum to the network protocol stack running within serial processing unit 102. The network protocol stack then encapsulates the target application data and its CRC checksum into a message to be transmitted. The message to be transmitted is then sent to the receiving end via network card 202.

[0065] For the computing device acting as the receiving end, its network card 201 receives the message to be transmitted and sends it to the serial processing unit 101. The serial processing unit 101 performs protocol parsing on the message to be transmitted through the network protocol stack to obtain the target application data and its CRC checksum. The target application data and its CRC checksum are then stored in the memory 401. Furthermore, the serial processing unit 101 sends the memory starting address and length of the target application data and its CRC checksum to the dedicated hardware 301 via the storage service.

[0066] The dedicated hardware 301 retrieves the target application data and its CRC check code from the memory 401 based on the memory starting address and length of the target application data and its CRC check code. The dedicated hardware 301 then verifies the accuracy of the target application data based on the CRC check code. If the verification passes, the dedicated hardware 301 sends the verification result to the storage service. If the verification result is positive, the storage service may store the target application data in the storage medium.

[0067] According to the CRC checksum calculation and CRC verification process based on dedicated hardware to implement software and hardware bypass interaction provided in Figures 2a and 2b above, for the sending end, before the target application data reaches the network card, dedicated hardware is required to first obtain the target application data for checksum calculation, and then the calculated checksum is sent to the network card by the serial processing unit. This undoubtedly increases the number of software and hardware interactions and the length of the data link, resulting in low processing efficiency for checksum calculation. Similarly, at the receiving end, before the target application data is stored in the memory, dedicated hardware is also required to perform accuracy verification, and then the target application data that passes the verification is stored in the memory. This will also increase the number of software and hardware interactions and the length of the data link, resulting in low verification efficiency for the target application data.

[0068] In order to solve the above technical problems, a method for offloading the calculation of the check code on the link is proposed in some embodiments of the present disclosure. Specifically, a hardware processing unit is added to the network card to perform check code calculation on the target application data to be transmitted. On the one hand, offloading the calculation of the check code of the target application data to the hardware can not only release the serial processing resources of the host, but also realize hardware acceleration of the check code calculation, thereby improving the processing efficiency of the check code calculation. On the other hand, the network card is located on the transmission link of the target application data. Therefore, the check code of the target application data is calculated on the hardware processing unit of the network card, which realizes the offloading of the check code calculation by the hardware on the link, shortens the data link of the application data, and further improves the efficiency of the check code calculation of the application data.

[0069] The technical solutions provided by various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0070] It should be noted that the same reference numerals denote the same objects in the following drawings and embodiments, and therefore, once an object is defined in one drawing or embodiment, it does not need to be further discussed in the subsequent drawings and embodiments.

[0071] Figures 3a, 3b, 4a, and 4b are schematic diagrams of the computing system provided by embodiments of the present disclosure. Referring to Figures 3a, 3b, 4a, and 4b, the computing system may include a host S10 and a network interface card 20. Host S10 may be implemented as any computer device with computing and storage capabilities, such as a server or terminal device. A terminal device may be a computer, workstation, or mobile phone.

[0072] The host S10 may include a serial processing unit 10a and a memory 40. In this embodiment, the number of serial processing units 10a is not limited. There may be one or more serial processing units 10a. "More than one" means two or more. Each serial processing unit 10a may be a single-core processing unit or a multi-core processing unit.

[0073] In this embodiment, the serial processing unit 10a is generally a processing chip provided on the mainboard of the host S10, such as the central processing unit (CPU) of the host S10. The CPU may be a standalone chip, a CPU integrated into a system on a chip (SoC), or a CPU integrated into a microcontroller unit (MCU).

[0074] The network card 20 is a network card equipped with a hardware processing unit 20a. The hardware processing unit 20a can be a hardware processor that uses a hardware description language (HDL) for data processing, or an application-specific integrated circuit (ASIC). The hardware description language can be a very-high-speed integrated circuit hardware description language (VHDL), Verilog HDL, System Verilog, or System C. Accordingly, the hardware processing unit 20a can be a field-programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), or a complex programmable logic device (CPLD).

[0075] In this embodiment, the host S10 is communicatively connected with the network card 20. In some embodiments, the network card 20 may be integrated on the motherboard of the host S10, or may be installed on the host S10 in a removable manner and be communicatively connected with the motherboard of the host S10 (specifically, the serial processing unit 10). Optionally, the network card 20 may be installed on the host S10 via a bus interface. The bus interface may be a serial bus interface, such as a Peripheral Component Interconnect Express (PCIe), a PCI interface, an Ultra Path Interconnect (UPI) interface, a Universal Serial Bus (USB) serial bus interface, an RS485 interface, or an RS232 interface, etc., but is not limited thereto. Preferably, the serial bus is a PCIe bus interface, which can increase the data transmission rate between the host S20 and the network card 20.

[0076] The bus interface of the host S10 can be expanded according to the specifications of the host S10. Generally, the host S10 has multiple communication interfaces. Multiple refers to two or more. When the network card 20 is connected to the host S10 via the bus interface, the network card 20 can be multiple, enabling expansion of the network card 20.

[0077] In this embodiment, in conjunction with Figures 3a, 3b, 4a, and 4b, the computing system may further include: a serial processing unit 10. As shown in Figures 4a and 4b, the serial processing unit 10 may include: a serial processing unit 10a on the host S10 (defined as a first serial processing unit 10a). Alternatively, as shown in Figures 3a and 3b, the serial processing unit 10 includes: a serial processing unit 10a on the host S10 and a serial processing unit 10b on the network card 20 (defined as a second serial processing unit 10b). Regarding the implementation of the second serial processing unit 10b, please refer to the relevant content of the implementation of the serial processing unit on the host S10 described above, which will not be repeated here.

[0078] In this embodiment, referring to Figures 3a, 3b, 4a, and 4b, the serial processing unit 10 runs a network protocol stack. A network protocol stack is a crucial component in a computer network, responsible for handling the transmission and processing of network data packets between different protocol layers. As shown in Figures 4a and 4b, the serial processing unit 10 running the network protocol stack can be the second serial unit 10b on the network card 20. As shown in Figures 3a and 3b, the serial processing unit 10 running the network protocol stack can be the first serial unit 10a on the host S10.

[0079] In this embodiment, as shown in Figures 3b and 4b , when the computing system is implemented as a user-side computing device, the host S10 runs an application. Specifically, the application runs on the first serial processing unit 10a of the host S10. The application needs to send and / or receive data through the network card 20. In this embodiment, the data that the application needs to send or receive is collectively referred to as application data.

[0080] The network card 20 can send and / or receive application data through the network interface 20b of the network card. In this embodiment, the communication component in the network interface 20b is configured to facilitate wired or wireless communication between the device where it is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as Wireless Fidelity (WiFi), 2G or 3G, 4G, 5G or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be implemented based on Near Field Communication (NFC) technology, Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology or other technologies.

[0081] In this embodiment, the computing system can be implemented as a transmitter, used to send application data from an application; it can also be implemented as a receiver, receiving application data sent to the application from other devices. The following describes the data processing methods provided in the embodiments of the present disclosure from the perspective of the computing system being implemented as a transmitter and a receiver, respectively.

[0082] In conjunction with Figures 3a, 3b, 4a, and 4b, when the computing system is implemented as a transmitter, the serial processing unit 10 (the first serial processing unit 10a or the second serial processing unit 10b) can obtain the memory address information of the target application data of the application program (corresponding to step 1 in Figures 3a, 3b, 4a, and 4b). The target application data is the application data to be sent. The memory address information of the target application data is used to identify the storage location of the target application data in the memory 40 of the host S10, and may include: the memory starting address of the target application data and the length of the target application data.

[0083] Specifically, in conjunction with Figures 3a, 3b, 4a and 4b, the serial processing unit 10 (the first serial processing unit 10a or the second serial processing unit 10b) runs a target service that processes the application data of the application. Among them, the target service can be a storage service, a computing service, a communication service or a data processing service. The target application data to be transmitted is generally determined according to the needs of these services. In Figures 3a and 3b, the serial processing unit that runs the target service and the network protocol stack is illustrated as the second serial processing unit 10b on the network card 20, and in Figures 4a and 4b, the serial processing unit that runs the target service and the network protocol stack is illustrated as the first serial processing unit 10a on the host side. Of course, the target service and the network protocol stack can also run on the first serial processing unit 10a on the host S10; or, the target service runs on the first serial processing unit 10a on the host S10, and the network protocol stack runs on the second serial processing unit 10b on the network card 20; or, the network protocol stack runs on the first serial processing unit 10a on the host S10, and the target service runs on the second serial processing unit 10b on the network card 20, etc.

[0084] Preferably, if the computing system is implemented as a computing device on the user side, the target service and the network protocol stack are both running on the second serial processing unit 10b on the network card 20 (as shown in Figure 3b). In this way, the target service and the network protocol stack can be unloaded from the host to the network card, which can reduce the resource consumption of the first serial processing unit 10a of the host S10 by the operation of the target service and the network protocol stack, such as reducing the CPU resource consumption of the host S10 by the operation of the target service and the network protocol stack, thereby saving the processing resources of the host S10.

[0085] If the computing system is implemented as a computing device that provides a target service (defined as a target service device), such as a storage device that provides storage services, the target service and the network protocol stack are both run on the first serial processing unit 10a on the host S10 (as shown in Figure 4a). This is mainly because the CPU resources on the host S10 side of the target service device do not need to be provided to the user to run application programs and can therefore be used to run the target service and the network protocol stack.

[0086] In this embodiment, in conjunction with Figures 3a, 3b, 4a, and 4b, the serial processing unit 10 (the first serial processing unit 10a or the second serial processing unit 10b) can obtain the memory address information of the target application data of the application program through the target service (corresponding to step 1 in Figures 3a, 3b, 4a, and 4b); and can also generate a network protocol header through the network protocol stack (corresponding to step 2 in Figures 3a, 3b, 4a, and 4b). The network protocol header is obtained by processing between different protocol layers of the network protocol stack.

[0087] Generally, the computing system shown in Figures 3b and 4b is generally implemented as a computing device on the user side, which is used to provide application data to the target service device and request the target service device to process the application data. For example, the target service is a storage service, and the computing device on the user side can write data to the storage device, that is, send the target application data to the target service device, and the target service device stores the target application data. Accordingly, in conjunction with Figures 3b and 4b, the serial processing unit 10 (the first serial processing unit 10a or the second serial processing unit 10b) can obtain the application data to be sent by the application as the target application data; and obtain the memory address information of the target application data (corresponding to step 1 in Figures 3b and 4b).

[0088] The computing system shown in Figures 3a and 4a is generally implemented as a target service device for providing a target service. The computing device on the user side can request target application data from the target service device according to the needs of the target service, and the target service device can read the application data requested by the computing device on the user side from the stored target application data as the target application data. Accordingly, in conjunction with Figures 3a and 4a, the serial processing unit 10 (the first serial processing unit 10a or the second serial processing unit 10b) can obtain the application data requested to be read by the computing device on the user side from the stored application data as the target application data; and obtain the memory address information of the target application data (corresponding to step 1 in Figures 3a and 4a).

[0089] Furthermore, the serial processing unit 10 (the first serial processing unit 10a or the second serial processing unit 10b) can provide the memory address information and network protocol header of the target application data to the hardware processing unit 20a (corresponding to step 2 in Figures 3a, 3b, 4a and 4b).

[0090] The hardware processing unit 20a can read the target application data from the host's memory 40 using direct memory access (DMA) according to the memory address information of the target application data (corresponding to steps 3 and 4 in Figures 3a, 3b, 4a, and 4b); and calculate the check code of the target application data (corresponding to step 5 in Figures 3a, 3b, 4a, and 4b).

[0091] In the disclosed embodiments, the specific implementation of the hardware processing unit 20a for calculating the checksum of the target application data is not limited. In some embodiments, the hardware processing unit 20a may calculate the checksum of the target application data using a checksum algorithm. The checksum algorithm may be a cyclic redundancy check (CRC) algorithm, a parity check algorithm, an XOR check algorithm, or a message digest (MD) algorithm, such as the MD5 checksum algorithm.

[0092] As for the CRC algorithm, the target application data can be encrypted using the CRC algorithm to obtain a CRC check code of the target application data, that is, a check code of the target application data.

[0093] Furthermore, the hardware processing unit 20a may assemble the target application data, the checksum of the target application data, and the network protocol header into a message to be sent (defined as a first message) (corresponding to step 6 in Figures 3a, 3b, 4a, and 4b). Specifically, the hardware processing unit 20a may assemble the network protocol header, the target application data, and the checksum of the target application data into the first message according to the message format. Furthermore, the hardware processing unit 20a may send the first message to the receiving end via the network interface 20b (corresponding to step 7 in Figures 3a, 3b, 4a, and 4b).

[0094] In this embodiment, a hardware processing unit is added to the network card to perform checksum calculations on the target application data to be transmitted. Offloading the checksum calculations for the target application data to the hardware not only frees up the host's serial processing resources but also enables hardware acceleration of the checksum calculations, improving their processing efficiency. Furthermore, since the network card is located on the transmission link for the target application data, calculating the checksum for the target application data on the network card's hardware processing unit implements hardware-in-line offload of the checksum calculations, shortening the data link for the application data and further improving the efficiency of the checksum calculations for the application data.

[0095] In the embodiment of the present disclosure, the data sent by the target service at the sending end to the target service at the receiving end includes, in addition to application data, metadata of the target service, such as the protocol header of the protocol followed by the target service. For example, if the target service is a storage service, the metadata of the storage service may include the protocol header of the storage protocol followed by the storage service. Therefore, the target service will also provide the metadata of the target service to the network protocol stack. However, the network protocol stack and the hardware processing unit cannot perceive which part of the incoming data is application data and which part is the metadata of the target service. Therefore, the metadata of the target service will be mixed with the target application data for checksum calculation, but the target service usually does not want to do this.

[0096] Furthermore, during data transmission, the network protocol layer splits the incoming target service metadata and target application data together based on parameters such as the network card's Maximum Transmission Unit (MTU). This can result in a data fragment containing both the target service metadata and some application data, disrupting the original data structure of the upper layer. Therefore, if the network protocol stack and hardware processing unit can distinguish between the target service metadata and application data, this technical problem can be resolved.

[0097] In this embodiment, in order to enable the network protocol stack and hardware processing unit to distinguish between the metadata and application data of the target service, as shown in Figure 5, an input / output (IO) vector (IO Vector, IOV) and a scatter gather list (SGL) are introduced. Among them, the IO vector is a data structure that defines a vector element, and the data structure is used as an array of multiple elements. The IO vector may include: pointers iov_base and iov_len. Among them, for each transmitted element, the pointer iov_base points to a buffer, which stores the received data or the data to be sent. iov_len represents the length of the received data or the length of the data to be sent. That is, the IO vector may include: the address (iov_base) and length (iov_len) of the data. The scatter gather list (SGL) is a linked list composed of multiple IO vectors.

[0098] In this embodiment, the serial processing unit 10 can also obtain the memory address information of the metadata of the target service. The memory address information may include: the memory starting address of the metadata of the target service and the length of the metadata of the target service. The memory address information of the metadata of the target service is the memory address information of the memory corresponding to the serial processing unit where the target service is deployed. For example, as shown in Figures 3a and 3b, the serial processing unit where the target service is deployed is the second serial processing unit 10b on the network card 20, then the memory address information of the metadata of the target service is the address information of the metadata of the target service in the memory on the network card 20 (not shown in the drawings), including: the memory starting address of the metadata of the target service in the memory on the network card 20 and the length of the metadata of the target service.

[0099] The memory address information of the target application data is the address information of the target application data in the memory 40 on the host S10, including: the memory start address of the target application data in the memory 40 on the host side and the length of the metadata of the target service.

[0100] Based on the IO vector and SGL, in this embodiment, as shown in FIG5 , in order to distinguish the metadata of the target service from the target application data, the serial processing unit 10 may add the memory address information of the metadata of the target service to the first IO vector (IOV[0]); and add the memory address information of the target application data to the second IO vector. The first IO vector and the second IO vector are different IO vectors. The second IO vector may be one or more. Multiple refers to two or more.

[0101] In some embodiments, the length of the target application data may be long, such as exceeding the MTU of the network card. Therefore, the target service is generally provided with a data segmentation requirement. For example, the logical block address (LBA) is required to be aligned according to the memory page size. Among them, LBA is a common mechanism for describing the block where the data is located on the computer storage device. The memory page size is generally 4kB. The data segmentation requirement is to align the data according to the memory page size so that the data volume of the data segment is an integer multiple of the memory page size. For another example, if the length of a single message does not exceed the MTU of the network card, the data segmentation requirement is to segment the data according to the MTU of the network card so that the data volume of each data segment is less than or equal to the MTU.

[0102] Based on the data segmentation requirements of the target service, the serial processing unit 10 can determine the memory address information of the multiple data slices into which the target application data is to be segmented according to the data segmentation requirements and the memory address information of the target application data. Multiple refers to two or more data slices, and the specific number is determined by the data segmentation requirements and the length of the target application data. For example, as shown in Figure 5, if the data segmentation requirement is to segment data according to the memory page size of 4kB alignment, and the length of the target application data is 13kB, then the 13kB target application data can be segmented into two data slices of 1kB and 12kB.

[0103] Furthermore, in conjunction with FIG5 and FIG6 , the serial processing unit 10 may add the memory address information of the metadata of the target service to a first IO vector (e.g., IOV[0]); and add the memory address information of multiple data slices to multiple second IO vectors (e.g., IOV[1] and IOV[2]). The second IO vectors correspond one-to-one to the data slices, i.e., one second IO vector stores the memory address information of one data slice.

[0104] Further, in combination with Figures 5 and 6, the serial processing unit 10 can generate a scatter list (SGL) based on the first IO vector and the second IO vector. Since the scatter list is a linked list composed of IO vectors. For the network protocol stack deployed by the serial processing unit 10, a single IO vector can be obtained through the scatter list, and the memory address information recorded by the IO vector can be provided to the hardware processing unit 20a. Since the memory address information of the metadata of the target service and the memory address information of the data fragments to be split from the target application data are independently stored in different IO vectors. Therefore, when the serial processing unit 10 provides the memory address information of the metadata of the target service and the memory address information of the target application data to the hardware processing unit 20a through the network protocol stack, it can obtain the memory address information of the metadata of the target service or the memory address information of the data fragments to be split from the target application data by reading the corresponding IO vector, without mixing the memory address information of the metadata of the target service with the memory address information of the data fragments to be split from the target application data, thereby realizing the distinction between the metadata of the target service and the target application data. Furthermore, when the hardware processing unit 20a reads corresponding data according to the memory address information, it will not read the mixed metadata and application data, thus meeting the upper-layer requirements of the target service.

[0105] Specifically, in conjunction with Figures 5 and 6, when the serial processing unit 10 provides the memory address information and network protocol header of the target application data to the hardware processing unit 20a, it can obtain a second IO vector from the scatter gather list (SGL) and provide the memory address information and network protocol header recorded by the second IO vector to the hardware processing unit 20a. Accordingly, the hardware processing unit 20a can use DMA to read the target application data from the host's memory 40 based on the memory address information recorded by the second IO vector and calculate the checksum of the target application data. Figure 6 only illustrates the calculation of the CRC checksum of the target application data as an example, but does not constitute a limitation. Afterwards, the hardware processing unit 20a assembles the network protocol header, the target application data, and the checksum of the target application data into a first message and sends the first message to the receiving end via the network interface 20b. The IO vector read from the SGL in Figure 6 can be the first IO vector or the second IO vector. Accordingly, the information recorded by the first IO vector is the memory address information of the metadata of the target service; the information recorded by the second IO vector is the memory address information of the data slice corresponding to the second IO vector.

[0106] For the aforementioned embodiment requiring the target application data to be divided into multiple data slices, there are multiple second IO vectors. Accordingly, when the serial processing unit 10 provides the memory address information and network protocol header of the target application data to the hardware processing unit 20a, as shown in FIG6 , the serial processing unit 10 can obtain multiple second IO vectors from the scatter-gather list and provide the memory address information and network protocol headers recorded by the multiple second IO vectors to the hardware processing unit 20a.

[0107] Accordingly, for any data slice A among the multiple data slices, the hardware processing unit 20a can use DMA to read data slice A from the host's memory 40 based on the memory address information recorded by the second IO vector corresponding to data slice A, and calculate the checksum of data slice A. For the specific implementation of calculating the checksum of data slice A, please refer to the relevant content of calculating the checksum of the target application data above, and will not be repeated here.

[0108] Further, in combination with Figures 6 and 7, the hardware processing unit 20a can assemble the network protocol header, data fragment A and the check code of data fragment A into a first message corresponding to data fragment A; and send the first message corresponding to data fragment A to the receiving end through the network interface 20b.

[0109] The hardware processing unit 20a performs the same processing on each data slice. The above embodiment uses data slice A as an example for illustration. The hardware processing unit 20a can obtain a first message corresponding to each data slice in the same manner, i.e., obtain multiple first messages, and send the multiple first messages to the receiving end in batches.

[0110] In the disclosed embodiment, since the target service's metadata is also required data for the target service, the sender must also perform a checksum calculation on the target service's metadata. Specifically, referring to Figures 5 and 6 , the serial processing unit 10 can retrieve the first IO vector from the scatter-gather list and send the memory address information of the target service's metadata, recorded in the first IO vector, to the hardware processing unit 20a.

[0111] Accordingly, the hardware processing unit 20a can read the metadata of the target service from the memory corresponding to the serial processing unit 10 in a DMA manner according to the memory address information of the metadata of the target service recorded by the first IO vector. In the embodiment where the target service is deployed on the first serial processing unit 10a on the host S10 side, the serial processing unit 10 is the first serial processing unit 10a, and its corresponding memory is the host-side memory 40. In the embodiment where the target service is deployed on the second serial processing unit 10b on the network card 20 side, the serial processing unit 10 is the first serial processing unit 10b, and its corresponding memory is the memory on the network card (not shown in the drawings).

[0112] Furthermore, the hardware processing unit 20a can calculate the checksum of the metadata of the target service. For the specific implementation of calculating the checksum of the metadata of the target service, please refer to the relevant content of calculating the checksum of the target application data above, which will not be repeated here.

[0113] Further, in combination with Figures 6 and 7, the hardware processing unit 20a can assemble the network protocol header, the metadata of the target service, and the check code of the metadata of the target service into a message corresponding to the metadata of the target service (defined as a second message); and send the second message to the receiving end through the network interface 20b.

[0114] When a receiving end receives a message, both the serial processing unit 10 and the hardware processing unit 20a at the receiving end can perform accuracy verification on the message's payload data. The serial processing unit 10 can perform accuracy verification on the message's payload data using the network protocol stack or the target service. The following describes an example process for the hardware processing unit 20a and the serial processing unit 10 to perform accuracy verification on the message's payload data.

[0115] In conjunction with Figures 8a, 8b, and 6, at the receiving end, the hardware processing unit 20a or the serial processing unit 10 can receive a message (defined as a target message) sent by the sending end through the network interface 20b. The target message can be a message encapsulated with target application data by the sending end in the manner provided by the aforementioned embodiment, or a message encapsulated with data fragments of the target application data, or a message encapsulated with metadata of the target service. The target application data, data fragments of the target application data, or metadata of the target service encapsulated in the target message is the payload data of the target message.

[0116] Furthermore, the hardware processing unit 20a or the serial processing unit 10 may obtain the payload data and the check code of the payload data from the received target message, and use the check code of the payload data to perform accuracy verification on the payload data.

[0117] Specifically, the hardware processing unit 20a or the serial processing unit 10 can calculate a checksum for the payload data using the same checksum algorithm as the transmitting end; and compare the calculated checksum with the checksum encapsulated in the message to see if they are consistent. If they are consistent, the payload data is determined to have passed the accuracy check; if they are inconsistent, the payload data is determined to have failed the accuracy check. Figures 8a and 8b illustrate the hardware processing unit 20a performing an accuracy check on the payload data as an example, but are not intended to be limiting.

[0118] For the serial processing unit 10, the network protocol stack running on the serial processing unit 10 can be used to perform protocol parsing on the message received by the network card 20 to obtain the payload data and the check code of the payload data; and the target service running on the network protocol stack or the serial processing unit 10 can be used to use the check code of the payload data to verify the accuracy of the payload data.

[0119] Furthermore, if the payload data passes the accuracy check, the serial processing unit 10 may process the payload data through the target service running thereon. For example, in an embodiment where the computing system is implemented as a target service device, the target service is a storage service, and the serial processing unit 10 may store the payload data to a storage medium through the target service. For another example, if the target service is a computing service, the serial processing unit 10 may perform computing on the payload data through the target service.

[0120] For another example, in an embodiment where the computing system is implemented as a computing device on the user side, the serial processing unit 10 may provide payload data to an application through a target service, and the application may perform related operations based on the payload data, and so on.

[0121] In this embodiment, the serial processing unit 10 may be the second serial processing unit 10b on the network card 20, or the first serial processing unit 10a on the host side. Figures 8a and 8b only illustrate the example of the hardware processing unit 20a verifying the payload data of the target message, but do not constitute a limitation. Specifically, the computing system shown in Figure 8a is generally implemented as a computing device on the user side. The first serial processing unit 10a of the host S10 runs an application. When the computing system requests data from the target service device, it can read data from the target service device and be implemented as a receiving end. The computing system shown in Figure 8b is generally implemented as a target service device. When the application running on the computing device on the user side needs to write data, the data can be sent to the target service device, and the computing system is implemented as a receiving end.

[0122] As shown in Figures 8a and 8b, hardware processing unit 20a can receive the target message sent by the sender via network interface 20b (corresponding to steps 1 and 2 of Figures 8a and 8b). Furthermore, as shown in step 3 of Figures 8a and 8b, hardware processing unit 20a can obtain the payload data and the checksum of the payload data from the received target message; and use the checksum of the payload data to verify the accuracy of the payload data. For the specific implementation of how hardware processing unit 20a verifies the accuracy of the payload data, please refer to the relevant content of the above embodiment and will not be repeated here.

[0123] Further, when the payload data passes the accuracy check, as shown in step 4 of Figures 8a and 8b, the hardware processing unit 20a can provide the target message to the DMA engine in the hardware processing unit 20a (i.e., the DMA in Figures 8a and 8b).

[0124] Next, as shown in step 5 of Figures 8a and 8b, the network protocol stack running in the serial processing unit 10 can provide the memory address information of the payload data and the memory address information of the network protocol header to the DMA engine. The network protocol stack in Figure 8a runs in the second serial processing unit 10b of the network card, while the network protocol stack in Figure 8b runs in the first serial processing unit 10a of the host.

[0125] Furthermore, the hardware processing unit 20a can store the payload data in the memory 40 of the host S10 via DMA (corresponding to step 6 in Figures 8a and 8b); and provide the network protocol header of the target message and the checksum encapsulated in the target message to the network protocol stack via DMA (corresponding to step 7 in Figures 8a and 8b). The serial processing unit 10 can provide the memory address information and checksum of the payload data to the target service via the network protocol stack running on it (corresponding to step 8 in Figures 8a and 8b). Furthermore, the serial processing unit 10 can process the payload data via the target service running on it.

[0126] For an embodiment in which the computing system is implemented as a target service device, the target service is a storage service, and the serial processing unit 10 can use the target service to store the payload data to a storage medium, etc. For another example, if the target service is a computing service, the serial processing unit 10 can use the target service to perform computing on the payload data, etc.

[0127] In embodiments where the computing system is implemented as a user-side computing device, the serial processing unit 10 can provide payload data to an application via a target service, which then performs related operations based on the payload data. In FIG8 a , the target service runs on the second serial processing unit 10 b of the network card; in FIG8 b , the target service runs on the first serial processing unit 10 a of the host.

[0128] In the disclosed embodiments, a hardware processing unit is added to the receiving end network card to verify the payload data of the message received by the network card. On the one hand, offloading the verification of the payload data to the hardware not only frees up the host's serial processing resources, but also achieves hardware acceleration of data verification, thereby improving the processing efficiency of data verification. On the other hand, the network card is located on the transmission link of the target application data. Therefore, verifying the payload data of the message on the network card's hardware processing unit realizes the function of hardware offloading data verification, shortening the data link of the payload data and further improving the verification efficiency of the payload data.

[0129] In the embodiment (not shown in Figures 8a and 8b) where the second serial processing unit on the receiving end network card verifies the payload data of the message received by the network card, on the one hand, offloading the payload data verification to the network card's serial resources can free up the host's serial processing resources. On the other hand, since the network card is located on the transmission link of the target application data, verifying the payload data of the message on the network card's serial processing unit implements the function of offloading data verification along the link, shortening the payload data data link and improving the efficiency of payload data verification.

[0130] It is worth noting that the computing system provided in the aforementioned embodiment can be implemented as a computing device on the user side, or as a computing device on the service side for providing the target service. Preferably, the computing system provided in Figures 3a, 3b and 8a is implemented as a computing device on the user side. The application runs on the first serial processing unit 10a of the host; the target service and the network protocol stack run on the second serial processing unit 10b of the network card. In this way, the target service and the network protocol stack can be unloaded from the host to the network card, which can reduce the resource consumption of the first serial processing unit 10a of the host S10 by the operation of the target service and the network protocol stack, such as reducing the CPU resource consumption of the host S10 by the operation of the target service and the network protocol stack, which can save the processing resources of the host S10.

[0131] The computing system provided in Figures 4a and 8b is implemented as a computing device on the user side. The computing system is implemented as a computing device that provides a target service (defined as a target service device), such as a storage device that provides storage services, etc. The target service and network protocol stack run on the first serial processing unit 10a on the host S10 (as shown in Figures 4a and 4b). This is mainly because the CPU resources on the host S10 side of the target service device do not need to be provided to the user to run the application, so they are used to run the target service and the network protocol stack, and will not preempt the computing resources required for the application. In addition to the above-mentioned computing system, the embodiment of the present disclosure also provides a data processing method, and the data processing method provided by the embodiment of the present disclosure is exemplified below.

[0132] FIG8c is a flow chart of a data processing method provided by an embodiment of the present disclosure. The data processing method shown in FIG8c is applicable to a serial processing unit on a network card or a host. The network card and the host are in communication connection. As shown in FIG8c, the data processing method includes:

[0133] 801. Obtain memory address information of target application data of an application program.

[0134] 802. Generate a network protocol header by running the network protocol stack.

[0135] 803. Provide the memory address information and the network protocol header of the target application data to the hardware processing unit of the network card, so that the hardware processing unit can read the target application data from the host's memory using DMA according to the memory address information of the target application data, and calculate the check code of the target application data; assemble the target application data, the check code of the target application data, and the network protocol header into a first message; and send the first message to the receiving end through the network interface of the network card.

[0136] FIG9 is a flow chart of another data processing method provided by an embodiment of the present disclosure. The data processing method shown in FIG9 is applicable to a hardware processing unit in a network card. The network card is in communication with a host. As shown in FIG9 , the data processing method includes:

[0137] 901. Obtain memory address information and a network protocol header of target application data of an application program provided by a serial processing unit; the serial processing unit is set in a host or a network card.

[0138] 902. Read the target application data from the host memory using DMA according to the memory address information of the target application data.

[0139] 903. Calculate the check code of the target application data.

[0140] 904. Assemble the target application data, the check code of the target application data, and the network protocol header into a first message.

[0141] 905. Send the first message to the receiving end through the network interface of the network card.

[0142] Regarding the structure and implementation of the network card and the host, please refer to the relevant content of the above system embodiment, which will not be repeated here. In this embodiment, the target application and network protocol stack can be deployed for the serial processing unit.

[0143] In step 801, the serial processing unit on the transmitting end may obtain memory address information of the target application data of the application program. The target application data is the application data to be transmitted. The memory address information of the target application data is used to identify the storage location of the target application data in the host memory and may include the memory starting address of the target application data and the length of the target application data.

[0144] Furthermore, in step 802, the target application data memory address information of the application program can be obtained through the target service. In step 803, the network protocol header can also be generated by the running network protocol stack. The network protocol header is obtained by the network protocol stack processing between different protocol layers.

[0145] Furthermore, in step 804 , the memory address information and the network protocol header of the target application data may be provided to the hardware processing unit of the network card.

[0146] For the hardware processing unit, in step 901, the memory address information and network protocol header of the target application data provided by the serial processing unit can be obtained; and in step 902, according to the memory address information of the target application data, the target application data is read from the host's memory using the DMA method; and in step 903, the check code of the target application data is calculated.

[0147] In the embodiments of the present disclosure, the specific implementation method of the hardware processing unit calculating the checksum of the target application data is not limited. In some embodiments, a checksum algorithm can be used to calculate the checksum of the target application data. The checksum algorithm can be a CRC algorithm, a parity check algorithm, an XOR check algorithm, or an MD algorithm, such as the MD5 checksum algorithm.

[0148] As for the CRC algorithm, the target application data can be encrypted using the CRC algorithm to obtain a CRC check code of the target application data, that is, a check code of the target application data.

[0149] Furthermore, in step 904, the target application data, the checksum of the target application data and the network protocol header are assembled into a message to be sent (defined as a first message). Furthermore, in step 905, the first message can be sent to the receiving end through the network interface of the network card.

[0150] In this embodiment, a hardware processing unit is added to the network card to perform checksum calculations on the target application data to be transmitted. Offloading the checksum calculations for the target application data to the hardware not only frees up the host's serial processing resources but also enables hardware acceleration of the checksum calculations, improving their processing efficiency. Furthermore, since the network card is located on the transmission link for the target application data, calculating the checksum for the target application data on the network card's hardware processing unit implements hardware-in-line offload of the checksum calculations, shortening the data link for the application data and further improving the efficiency of the checksum calculations for the application data.

[0151] In the disclosed embodiment, the data sent from the target service at the sending end to the target service at the receiving end includes, in addition to application data, metadata of the target service, such as the protocol header of the protocol followed by the target service. Therefore, the target service also provides the metadata of the target service to the network protocol stack. However, the network protocol stack and the hardware processing unit cannot perceive which part of the incoming data is application data and which part is metadata of the target service. Therefore, the metadata of the target service is mixed with the target application data to calculate the checksum, but the target service generally does not want to do this.

[0152] Furthermore, during data transmission, the network protocol layer splits the incoming target service metadata and target application data together based on parameters such as the network card's MTU. This can result in a data fragment containing both the target service metadata and some application data, disrupting the original data structure of the upper layer. Therefore, if the network protocol stack and hardware processing unit can distinguish between the target service metadata and application data, this technical problem can be resolved.

[0153] In this embodiment, in order to enable the network protocol stack and the hardware processing unit to distinguish metadata of the target service from application data, IO vectors and scatter gather lists (SGLs) are introduced.

[0154] In this embodiment, the serial processing unit may also obtain the memory address information of the target service's metadata. This memory address information may include the memory starting address of the target service's metadata and the length of the target service's metadata. The memory address information of the target service's metadata is the memory address information of the memory corresponding to the serial processing unit where the target service is deployed.

[0155] Based on the IO vector and SGL, in this embodiment, to distinguish between the metadata of the target service and the target application data, for the serial processing unit, the memory address information of the metadata of the target service can be added to the first IO vector; and the memory address information of the target application data can be added to at least one second IO vector. The first IO vector and the second IO vector are different IO vectors.

[0156] In some embodiments, the target application data may be long, such as exceeding the MTU of the network card. Therefore, the target service generally has data segmentation requirements. Based on the target service's data segmentation requirements, the serial processing unit can determine the memory address information of the multiple data slices into which the target application data is to be segmented, based on the data segmentation requirements and the memory address information of the target application data. Multiple refers to two or more data slices, with the specific number determined by the data segmentation requirements and the length of the target application data.

[0157] Furthermore, the memory address information of the metadata of the target service can be added to the first IO vector, and the memory address information of multiple data shards can be added to multiple second IO vectors. The second IO vectors correspond to the data shards one-to-one, that is, each second IO vector stores the memory address information of one data shard.

[0158] Furthermore, for the serial processing unit, a scatter list (SGL) can be generated based on the first IO vector and the second IO vector. Since the scatter list is a linked list composed of IO vectors. For the network protocol stack deployed by the serial processing unit, a single IO vector can be obtained through the scatter list, and the memory address information recorded by the IO vector can be provided to the hardware processing unit. Since the memory address information of the metadata of the target service and the memory address information of the data fragments to be split from the target application data are independently stored in different IO vectors. Therefore, when the serial processing unit provides the memory address information of the metadata of the target service and the memory address information of the target application data to the hardware processing unit through the network protocol stack, it can obtain the memory address information of the metadata of the target service or the memory address information of the data fragments to be split from the target application data by reading the corresponding IO vector, without mixing the memory address information of the metadata of the target service with the memory address information of the data fragments to be split from the target application data, thereby achieving the distinction between the metadata of the target service and the target application data. Furthermore, when the hardware processing unit reads the corresponding data based on the memory address information, it will not read the mixed metadata and application data, which can meet the upper-layer requirements of the target service.

[0159] Specifically, for the serial processing unit, when the memory address information and network protocol header of the target application data are provided to the hardware processing unit, a second IO vector can be obtained from the scatter gather list (SGL); and the memory address information and network protocol header recorded by the second IO vector are provided to the hardware processing unit. Correspondingly, for the hardware processing unit, the target application data can be read from the host's memory using the DMA method based on the memory address information recorded by the second IO vector; and the check code of the target application data is calculated. Afterwards, the network protocol header, the target application data, and the check code of the target application data are assembled into a first message; and the first message is sent to the receiving end through the network interface.

[0160] For the aforementioned embodiment requiring the target application data to be divided into multiple data slices, there are multiple second IO vectors. Accordingly, when the serial processing unit provides the memory address information and network protocol header of the target application data to the hardware processing unit, it can obtain multiple second IO vectors from the scatter-gather list and provide the memory address information and network protocol header recorded by the multiple second IO vectors to the hardware processing unit.

[0161] Accordingly, the hardware processing unit can read any data slice A from the host's memory using DMA, based on the memory address information recorded by the second IO vector corresponding to data slice A, for any data slice A among the multiple data slices. The hardware processing unit can also calculate the checksum for data slice A using DMA. The specific implementation of calculating the checksum for data slice A can be found in the aforementioned section on calculating the checksum for the target application data, and will not be further elaborated here.

[0162] Furthermore, the network protocol header, data fragment A and the check code of data fragment A can be assembled into a first message corresponding to data fragment A; and the first message corresponding to data fragment A can be sent to the receiving end through the network interface.

[0163] The hardware processing unit performs the same processing on each data slice. The above embodiment uses data slice A as an example for illustration. The hardware processing unit can obtain the first message corresponding to each data slice in the same manner, i.e., obtain multiple first messages, and send the multiple first messages to the receiving end in batches.

[0164] In the disclosed embodiment, since the target service's metadata is also required by the target service, the sending end must also perform a checksum calculation on the target service's metadata. Specifically, for the serial processing unit, the first IO vector can be obtained from the scatter-gather list, and the memory address information of the target service's metadata recorded in the first IO vector can be sent to the hardware processing unit.

[0165] Accordingly, for the hardware processing unit, the metadata of the target service can be read from the memory corresponding to the serial processing unit in a DMA manner based on the memory address information of the metadata of the target service recorded by the first IO vector. In the embodiment of the first serial processing unit in which the target service is deployed on the host side, the serial processing unit is the first serial processing unit, and the corresponding memory is the memory on the host side. In the embodiment of the second serial processing unit in which the target service is deployed on the network card side, the serial processing unit is the second serial processing unit, and the corresponding memory is the memory on the network card.

[0166] Furthermore, the check code of the metadata of the target service can be calculated. For the specific implementation of calculating the check code of the metadata of the target service, please refer to the relevant content of calculating the check code of the target application data above, which will not be repeated here.

[0167] Furthermore, the network protocol header, the metadata of the target service and the check code of the metadata of the target service can be assembled into a message corresponding to the metadata of the target service (defined as a second message); and the second message can be sent to the receiving end through the network interface.

[0168] When the receiving end receives a message, both the serial processing unit and the hardware processing unit of the receiving end can perform accuracy verification on the payload data of the message. Figure 10 is a flow chart of another data processing method provided by an embodiment of the present disclosure. The data processing method shown in Figure 10 is applicable to a serial processing unit or a hardware processing unit on a network card. As shown in Figure 10, the data processing method is mainly used for the receiving end to perform accuracy verification on the payload data of the received message. As shown in Figure 10, the data processing method may include:

[0169] 1001. Obtain a target message received by a network interface of a network card.

[0170] 1002. Obtain payload data and a check code of the payload data from the target message.

[0171] 1003. Use the check code of the payload data to verify the accuracy of the payload data.

[0172] At the receiving end, the hardware processing unit or serial processing unit can obtain a message (defined as a target message) sent by the sending end and received by the network interface of the network card in step 1001. The target message can be a message encapsulated with target application data, a message encapsulated with data fragments of the target application data, or a message encapsulated with metadata of the target service, provided by the sending end using the method provided in the aforementioned embodiment. The target application data, data fragments of the target application data, or metadata of the target service encapsulated in the target message is the payload data of the message.

[0173] Furthermore, in step 1002, the payload data and the check code of the payload data may be obtained from the received target message; and in step 1003, the accuracy of the payload data may be checked using the check code of the payload data.

[0174] Specifically, the check code of the payload data can be calculated using the same check algorithm as the sending end; and the calculated check code is compared with the check code encapsulated in the message to see if they are consistent. If they are consistent, it is determined that the payload data has passed the accuracy check; if they are inconsistent, it is determined that the payload data has not passed the accuracy check.

[0175] For the serial processing unit, the network protocol stack running on the serial processing unit can be used to perform protocol parsing on the message received by the network card to obtain the payload data and the check code of the payload data; and the target service running on the network protocol stack or the serial processing unit can be used to use the check code of the payload data to verify the accuracy of the payload data.

[0176] Furthermore, when the payload data passes the accuracy check, the payload data can be processed by the target service running thereon.

[0177] In this embodiment, the serial processing unit may be a second serial processing unit on the network card, or may be a first serial processing unit on the host side.

[0178] Among them, in the embodiment of adding a hardware processing unit to the receiving end network card to verify the payload data of the message received by the network card, on the one hand, offloading the verification of the payload data to the hardware can not only free up the host's serial processing resources, but also realize hardware acceleration of data verification, improving the processing efficiency of data verification. On the other hand, the network card is located on the transmission link of the target application data. Therefore, verifying the payload data of the message on the hardware processing unit of the network card realizes the function of hardware offloading data verification, shortening the data link of the payload data and further improving the verification efficiency of the payload data.

[0179] In embodiments where the second serial processing unit on the receiving end network card verifies the payload data of messages received by the network card, on the one hand, offloading the payload data verification to the network card's serial resources frees up serial processing resources on the host computer. On the other hand, since the network card is located on the transmission link for target application data, verifying the payload data of messages on the network card's serial processing unit implements the function of offloading data verification along the link, shortening the payload data data link and improving payload data verification efficiency.

[0180] It is worth noting that the data processing method in the process of sending data by the sending end and the data processing method in the process of receiving data by the receiving end can be deployed on different devices; they can also be deployed on the same device.

[0181] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of steps 801 and 802 can be device A; for another example, the execution entity of step 801 can be device A, and the execution entity of step 802 can be device B; and so on.

[0182] In addition, some of the processes described in the above embodiments and the accompanying drawings include multiple operations that appear in a specific order. However, it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The sequence numbers of the operations, such as 801 and 802, are merely used to distinguish between different operations and do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel.

[0183] Accordingly, an embodiment of the present disclosure also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the data processing method provided in the above embodiments.

[0184] Figure 11 is a schematic diagram of the structure of a network card provided by an embodiment of the present disclosure. As shown in Figure 11, the network card includes: a hardware processing unit 20a and a network interface 20b. The network card is used to communicate with the host.

[0185] The hardware processing unit 20a is in communication with the serial processing unit 10. The serial processing unit 10 is provided in a network card or a host. FIG11 only illustrates the serial processing unit 10 provided in the network card.

[0186] In this embodiment, the serial processing unit 10 is used to obtain the memory address information of the target application data of the application; generate a network protocol header by running the network protocol stack; and provide the memory address information of the target application data and the network protocol header to the hardware processing unit 20a of the network card.

[0187] The hardware processing unit 20a is used to read the target application data from the host's memory using DMA according to the memory address information of the target application data, and calculate the check code of the target application data; assemble the target application data, the check code of the target application data and the network protocol header into a first message; and send the first message to the receiving end through the network interface 20b.

[0188] In some embodiments, the serial processing unit 10 is further used to obtain memory address information of metadata of a target service run by the serial processing unit; add the memory address information of the metadata of the target service to a first IO vector; add the memory address information of the target application data to a second IO vector; and generate a scatter list based on the first IO vector and the second IO vector.

[0189] There are multiple second IO vectors. The serial processing unit 10 is further configured to determine the memory address information of the multiple data slices into which the target application data is to be split based on the data segmentation requirements and the memory address information of the target application data. Accordingly, when adding the memory address information of the target application data to the second IO vector, the serial processing unit 10 is specifically configured to add the memory address information of the multiple data slices to the multiple second IO vectors; the second IO vectors correspond one-to-one to the data slices.

[0190] Accordingly, when the serial processing unit 10 provides the memory address information and network protocol header of the target application data to the hardware processing unit, it is specifically used to: obtain multiple second IO vectors from the scatter list; and provide the memory address information and network protocol header recorded by the multiple second IO vectors to the hardware processing unit.

[0191] For any data slice among the multiple data slices, the hardware processing unit 20a is used to read any data slice from the host's memory using DMA according to the memory address information recorded by the second IO vector corresponding to any data slice; calculate the check code of any data slice; assemble any data slice, the check code of any data slice and the network protocol header into a first message corresponding to any data slice; and send the first message corresponding to any data slice to the receiving end through the network interface 20b.

[0192] In some embodiments, the serial processing unit 10 is further configured to: obtain a first IO vector from the scatter-gather list; and provide memory address information of metadata of a target service recorded by the first IO vector to the hardware processing unit.

[0193] Correspondingly, the hardware processing unit 20a is also used to: read the metadata of the target service from the memory corresponding to the serial processing unit according to the memory address information of the metadata of the target service; and calculate the check code of the metadata of the target service; assemble the network protocol header, the metadata of the target service and the check code of the metadata of the target service into a second message; and send the second message to the receiving end through the network interface 20b.

[0194] Optionally, when calculating the check code of the target application data, the hardware processing unit 20a is specifically configured to: utilize a CRC encryption algorithm to encrypt the target application data to obtain the check code of the target application data.

[0195] Accordingly, when calculating the check code of the metadata of the target service, the hardware processing unit 20a is specifically configured to: utilize a CRC encryption algorithm to encrypt the metadata of the target application data to obtain the check code of the metadata of the target application data.

[0196] In some embodiments, the hardware processing unit 20a or the serial processing unit 10 is further used to: receive a target message through the network interface 20b; obtain payload data and a check code of the payload data from the target message; and use the check code of the payload data to verify the accuracy of the payload data.

[0197] Optionally, the hardware processing unit 20a or the serial processing unit 10 is further configured to: process the payload data through a target service running on the serial processing unit 10 when the payload data passes the accuracy check.

[0198] The network card provided in this embodiment is additionally provided with a hardware processing unit for performing checksum calculation on the target application data to be transmitted. On the one hand, offloading the checksum calculation of the target application data to the hardware not only releases the serial processing resources of the host, but also realizes hardware acceleration of the checksum calculation, thereby improving the processing efficiency of the checksum calculation. On the other hand, the network card is located on the transmission link of the target application data. Therefore, calculating the checksum of the target application data on the hardware processing unit of the network card realizes the hardware offloading of the checksum calculation, which can shorten the data link of the application data and further improve the efficiency of the checksum calculation of the application data.

[0199] FIG12 is a schematic diagram of the structure of a host provided by an embodiment of the present disclosure. As shown in FIG12 , the host may include: a memory 120 a and a processor 120 b. The memory 120 a is used to store computer programs; the host is used to communicate with the network card 20.

[0200] The processor 120b is coupled to the memory 120a, and is used to execute a computer program for: obtaining memory address information of target application data of an application program; generating a network protocol header by running a network protocol stack; providing the memory address information of the target application data and the network protocol header to a hardware processing unit of the network card, so that the hardware processing unit reads the target application data from the host memory using a direct memory access (DMA) method according to the memory address information of the target application data, and calculates a check code of the target application data; assembling the target application data, the check code of the target application data, and the network protocol header into a first message; and sending the first message to a receiving end through a network interface of the network card.

[0201] In some embodiments, the processor 120b is further used to: obtain memory address information of metadata of the target service run by the processor 120b; add the memory address information of the metadata of the target service to a first IO vector; add the memory address information of the target application data to at least one second IO vector; and generate a scatter list based on the first IO vector and the at least one second IO vector.

[0202] In some embodiments, there are multiple second IO vectors. Processor 120b is further configured to: determine the memory address information of the multiple data slices into which the target application data is to be split based on the data segmentation requirements and the memory address information of the target application data. Accordingly, when adding the memory address information of the target application data to the second IO vector, processor 120b is specifically configured to: add the memory address information of the multiple data slices to the multiple second IO vectors; the second IO vectors correspond one-to-one to the data slices.

[0203] Accordingly, when the processor 120b provides the memory address information and network protocol header of the target application data to the hardware processing unit of the network card, it is specifically used to: obtain multiple second IO vectors from the scatter list; and provide the memory address information and network protocol headers recorded by the multiple second IO vectors to the hardware processing unit.

[0204] Optionally, the processor 120b is also used to: obtain a first IO vector from a scatter list; provide the memory address information of the metadata of the target service recorded by the first IO vector to the hardware processing unit, so that the hardware processing unit reads the metadata of the target service from the memory corresponding to the serial processing unit according to the memory address information of the metadata of the target service; and calculate the check code of the metadata of the target service; and assemble the network protocol header, the metadata of the target service and the check code of the metadata of the target service into a second message; and send the second message to the receiving end through the network interface.

[0205] In some embodiments, the processor 120b is further used to: obtain a target message received by the network interface of the network card; obtain payload data and a check code of the payload data from the target message; and use the check code of the payload data to verify the accuracy of the payload data.

[0206] In some optional embodiments, as shown in FIG12 , the host may further include components such as a communication component 120c and a power supply component 120d. In some embodiments, the host may be implemented as a terminal device such as a computer or workstation. Accordingly, the host may further include components such as a display component 120e and an audio component 120f. FIG12 schematically illustrates only some components, and does not mean that the host must include all of the components shown in FIG12 , nor does it mean that the host can only include the components shown in FIG12 .

[0207] The host provided in this embodiment, when connected to a network card equipped with a hardware processing unit, can offload the calculation of the checksum of the target application data to the hardware processing unit of the network card. This not only frees up the host's serial processing resources but also enables hardware acceleration of the checksum calculation, improving the processing efficiency of the checksum calculation. Furthermore, since the network card is located on the transmission link of the target application data, calculating the checksum of the target application data on the hardware processing unit of the network card implements hardware-based offloading of the checksum calculation, shortening the data link of the application data and further improving the efficiency of the checksum calculation of the application data.

[0208] In the embodiments of the present disclosure, the memory is used to store computer programs and can be configured to store various other data to support operations on the device where it is located. The processor can execute the computer program stored in the memory to implement the corresponding control logic. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0209] In the embodiments of the present disclosure, the processor may be any hardware processing device that can execute the logic of the above method. Optionally, the processor may be a central processing unit (CPU), a graphics processing unit (GPU), or a microcontroller unit (MCU); or a programmable device such as a field programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), a complex programmable logic device (CPLD); or an advanced reduced instruction set (RISC) processor (Advanced RISC Machines, ARM) or a system on chip (SoC), etc., but is not limited thereto.

[0210] In an embodiment of the present disclosure, the communication component is configured to facilitate wired or wireless communication between the device in which it is located and other devices. The device in which the communication component is located can access a wireless network based on a communication standard, such as Wireless Fidelity (WiFi), 2G or 3G, 4G, 5G or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be based on Near Field Communication (NFC) technology, Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology or other technologies.

[0211] In an embodiment of the present disclosure, the display component may include a liquid crystal display (LCD) and a touch panel (TP). If the display component includes a touch panel, the display component may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor may not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0212] In an embodiment of the present disclosure, a power supply component is configured to provide power to various components of the device in which it is located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply component is located.

[0213] In an embodiment of the present disclosure, the audio component may be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC), and when the device where the audio component is located is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal may be further stored in a memory or sent via a communication component. In some embodiments, the audio component further includes a speaker for outputting an audio signal. For example, for a device with a language interaction function, voice interaction with a user may be achieved through the audio component.

[0214] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0215] It should also be noted that the descriptions such as "first" and "second" in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit "first" and "second" to different types.

[0216] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) containing computer-usable program code.

[0217] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0218] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0219] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0220] In a typical configuration, a computing device includes one or more processors (CPU, etc.), input / output interfaces, network interfaces, and memory.

[0221] Memory may include non-permanent storage in a computer-readable medium, random-access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0222] Computer storage media is readable storage media, also known as computer-readable media. Computer-readable storage media include permanent and non-permanent, removable and non-removable media that can be implemented using any method or technology to store information. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

[0223] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus comprising the aforementioned elements.

[0224] The above contents are merely examples of the present disclosure and are not intended to limit the present disclosure. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure are intended to be included within the scope of the claims of the present disclosure.

Claims

1. A computing system, wherein: include: Host and network card; The host is in communication connection with the network card; The network card includes: a hardware processing unit and a network interface; the computing system also includes: a serial processing unit; the serial processing unit is arranged on the network card or the host; the serial processing unit is communicatively connected with the hardware processing unit; The serial processing unit runs a network protocol stack for obtaining memory address information of target application data of an application program and generating a network protocol header through the network protocol stack; and providing the memory address information of the target application data and the network protocol header to the hardware processing unit; The hardware processing unit is used to read the target application data from the host's memory using a direct memory access (DMA) method according to the memory address information of the target application data, and calculate a check code for the target application data; assemble the target application data, the check code for the target application data, and the network protocol header into a first message; and send the first message to a receiving end through the network interface.

2. The system according to claim 1, wherein: The hardware processing unit or the serial processing unit is further used for: Obtaining a target message received by the network interface; Obtaining payload data and a check code of the payload data from the target message; The accuracy of the payload data is checked using the check code of the payload data.

3. A data processing method, applicable to a hardware processing unit on a network card, wherein: The network card is used to communicate with the host; the method includes: Acquire memory address information and network protocol header of target application data of an application program provided by a serial processing unit; the serial processing unit is arranged in the host or the network card; Reading the target application data from the memory of the host using a direct memory access (DMA) method according to the memory address information of the target application data; Calculating the check code of the target application data; assembling the target application data, the check code of the target application data and the network protocol header into a first message; The first message is sent to a receiving end through the network interface of the network card.

4. The method according to claim 3, wherein: The memory address information of the metadata of the target service run by the serial processing unit and the memory address information of the target application data are added by the serial processing unit to the first IO vector and the second IO vector respectively; the first IO vector and the second IO vector constitute a scatter list; Acquiring memory address information of target application data of the application program provided by the serial processing unit, including: Memory address information of a second IO vector record read from the scatter list provided by the serial processing unit is obtained.

5. The method according to claim 4, wherein: There are multiple second IO vectors, each of which records memory address information of multiple data slices of the target application data; the memory address information of the multiple data slices is determined by the serial processing unit according to the data segmentation requirements and the memory address information of the target application data; According to the memory address information of the target application data, a direct memory access DMA method is used to access the target application data. The target application data is read from the memory of the host, including: For any data slice among the multiple data slices, according to the memory address information recorded by the second IO vector corresponding to the any data slice, read the any data slice from the memory of the host by using the DMA method; The calculating the check code of the target application data includes: calculating the check code of any of the data slices; The step of assembling the target application data, the check code of the target application data and the network protocol header into a first message includes: Assembling any one of the data fragments, the check code of any one of the data fragments, and the network protocol header into a first message corresponding to any one of the data fragments; The sending the first message to the receiving end through the network interface of the network card includes: The first message corresponding to any one of the data fragments is sent to the receiving end through the network interface.

6. The method according to claim 4, wherein: The method further comprises: Acquire memory address information of metadata of the target service recorded by the first IO vector in the scatter list provided by the serial processing unit; According to the memory address information of the metadata of the target service, the metadata of the target service is read from the memory corresponding to the serial processing unit; and a check code of the metadata of the target service is calculated; Assembling the network protocol header, the metadata of the target service, and a checksum of the metadata of the target service into a second message; The second message is sent to the receiving end through the network interface.

7. The method according to any one of claims 3 to 6, wherein: Also includes: Receiving a target message sent by a sending end through the network interface; Obtaining payload data and a check code of the payload data from the target message; The accuracy of the payload data is checked using the check code of the payload data.

8. A data processing method, applicable to a serial processing unit on a network card or a host, wherein: The network card is connected to the host for communication; the method comprises: Get the memory address information of the target application data of the application; Generate network protocol headers by running the network protocol stack; The memory address information of the target application data and the network protocol header are provided to the hardware processing unit of the network card, so that the hardware processing unit can read the target application data from the memory of the host computer using a direct memory access (DMA) method according to the memory address information of the target application data, and calculate a checksum of the target application data; assemble the target application data, the checksum of the target application data and the network protocol header into a first message; and send the first message to a receiving end through the network interface of the network card.

9. The method according to claim 8, wherein: Also includes: Obtaining memory address information of metadata of a target service run by the serial processing unit; Add the memory address information of the metadata of the target service to the first IO vector; The memory address information of the data is added to at least one second IO vector; generating a scatter-gather list according to the first IO vector and the at least one second IO vector; The step of providing the memory address information of the target application data and the network protocol header to the hardware processing unit of the network card includes: Obtain the at least one second IO vector from the scatter-gather list; The memory address information of the at least one second IO vector record and the network protocol header are provided to the hardware processing unit.

10. The method according to claim 9, wherein: There are multiple second IO vectors; and the method further includes: Determine the memory address information of a plurality of data slices into which the target application data is to be segmented according to the data segmentation requirement and the memory address information of the target application data; The adding the memory address information of the target application data to at least one second IO vector comprises: The memory address information of the multiple data slices is added to multiple second IO vectors; the second IO vectors correspond to the data slices one by one.

11. The method according to claim 9, wherein: Also includes: Obtain the first IO vector from the scatter-gather list; Providing the memory address information of the metadata of the target service recorded by the first IO vector to the hardware processing unit, so that the hardware processing unit reads the metadata of the target service from the memory corresponding to the serial processing unit according to the memory address information of the metadata of the target service; and calculating a checksum of the metadata of the target service; and assembling the network protocol header, the metadata of the target service, and a checksum of the metadata of the target service into a second message; And send the second message to the receiving end through the network interface.

12. The method according to any one of claims 8 to 11, wherein: Also includes: Obtaining a target message received by the network interface of the network card; Obtaining payload data and a check code of the payload data from the target message; The accuracy of the payload data is checked using the check code of the payload data.

13. A data processing method, applicable to a hardware processing unit on a network card, wherein: include: Obtaining a target message received by the network interface of the network card; Obtaining payload data and a check code of the payload data from the target message; The accuracy of the payload data is checked using the check code of the payload data.

14. A network card, wherein: The network card comprises: a hardware processing unit and a network interface; the network card is used for communication connection with the host; The hardware processing unit is communicatively connected with the serial processing unit; the serial processing unit is arranged in the network card or the host; The hardware processing unit is used to execute the steps of the method according to any one of claims 3 to 7 and 13; The serial processing unit is used to execute the steps in the method according to any one of claims 8 to 12.

15. A host, wherein: include: A memory and a processor; wherein the memory is used to store computer programs; the host is used to communicate with the network card; The processor is coupled to the memory and configured to execute the computer program to perform the steps of the method according to any one of claims 8 to 12.

16. A computer-readable storage medium storing computer instructions, wherein: When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the method according to any one of claims 3 to 13.

17. A computer program product, wherein: The method comprises a computer program, which, when executed by a processor, implements the steps in the method according to any one of claims 3 to 13.

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