Pixel driving circuit and display panel

Abstract

The present disclosure belongs to the technical field of display. Provided are a pixel driving circuit and a display panel. The pixel driving circuit comprises a driving transistor (T3) for generating a driving current, the material of a channel region of the driving transistor (T3) is a metal oxide semiconductor material, and the driving transistor (T3) only has one of a top gate and a bottom gate. In the pixel driving circuit and the display panel, a top-and-bottom double-gate structure of a driving transistor (T3) in the pixel driving circuit can be changed to have only one of a top gate and a bottom gate, such that the electron mobility of the driving transistor (T3) is reduced, and thus the subthreshold swing of the driving transistor (T3) is increased, and the low-grayscale image quality of the display panel can be improved.

Description

Pixel driving circuit and display panel

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311595472.1, filed on November 27, 2023, and entitled “Pixel Driving Circuit and Display Panel.” The entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0004] AMOLED (active-light-emitting diode), especially flexible AMOLED, has become the preferred screen material for smartphones and smartwatches. As OLED display manufacturing technology matures and yield rates continue to improve, OLED costs are declining, allowing OLED to be used in more applications, such as medium- and large-sized IT applications. However, the declining yield of LTPS (low-temperature polycrystalline silicon) in these applications remains high, leading to the industry's increasing interest in pure oxide TFT (metal oxide thin-film transistor) backplanes as driver backplanes for medium- and large-sized OLEDs.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

[0006] Summary of the Invention

[0007] The present disclosure aims to provide a pixel driving circuit and a display panel to improve the low grayscale image quality of OLED.

[0008] To achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0009] According to a first aspect of the present disclosure, a pixel driving circuit is provided, which is arranged on a display panel to drive a light-emitting element. The pixel driving circuit includes a driving transistor for generating a driving current, the material of the channel region of the driving transistor is a metal oxide semiconductor material, and the driving transistor has only one of a top gate and a bottom gate.

[0010] In an exemplary embodiment of the present disclosure, the display panel comprises a base substrate, a light-shielding metal layer, an inorganic buffer layer, a first gate layer, a first gate insulating layer, and a semiconductor layer stacked in sequence;

[0011] The active layer of the driving transistor is located in the semiconductor layer; the driving transistor has a bottom gate located in the first gate layer;

[0012] The pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is located on the light-shielding metal layer of the display panel, and a second electrode plate of the storage capacitor is the bottom gate of the driving transistor.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes at least one switching transistor, and a material of a channel region of the switching transistor is a metal oxide semiconductor material.

[0014] In an exemplary embodiment of the present disclosure, the switch transistor has a top gate and a bottom gate.

[0015] In an exemplary embodiment of the present disclosure, the display panel comprises a base substrate, a light-shielding metal layer, an inorganic buffer layer, a first gate layer, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, a second gate layer, a planarization layer, and a source / drain metal layer, which are sequentially stacked.

[0016] The driving transistor includes a bottom gate located in the first gate layer and an active layer located in the semiconductor layer; the active layer of the driving transistor includes a channel region and a first conductive region and a second conductive region respectively located on both sides of the channel region; each of the switching transistors includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer and a top gate located in the second gate layer; the active layer of the switching transistor includes a channel region and a first conductive region and a second conductive region respectively located on both sides of the channel region.

[0017] In an exemplary embodiment of the present disclosure, the switching transistor includes a first light emitting control transistor;

[0018] The first light emission control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer;

[0019] The top gate and the bottom gate of the first light emitting control transistor are both used to load a first light emitting control signal;

[0020] The first conductive region of the first light emitting control transistor is used to apply a first driving power supply voltage;

[0021] The second conductive region of the first light emitting control transistor is electrically connected to the first conductive region of the driving transistor through a conductive structure.

[0022] In an exemplary embodiment of the present disclosure, the switching transistor includes a data writing transistor for loading a data voltage and a gate reset transistor for resetting a bottom gate of the driving transistor;

[0023] The data writing transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and the bottom gate of the data writing transistor are both used to load a first scanning signal; the first conductive region of the data writing transistor is used to load a data voltage;

[0024] The gate reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the gate reset transistor are both used to load a second scanning signal; the first conductive region of the gate reset transistor is used to load a first initialization voltage;

[0025] The second conductive region of the data writing transistor, the second conductive region of the gate reset transistor, and the bottom gate of the driving transistor are electrically connected to each other through a conductive structure;

[0026] The pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located on the light-shielding metal layer.

[0027] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer;

[0028] The switching transistor includes an electrode reset transistor for resetting the pixel electrode; the electrode reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and the bottom gate of the electrode reset transistor are both used to load a third scanning signal; the first conductive region of the electrode reset transistor is used to load a second initialization voltage;

[0029] The second conductive region of the electrode reset transistor, the second electrode plate of the storage capacitor, the second conductive region of the driving transistor, and the pixel electrode are electrically connected via a conductive structure.

[0030] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer;

[0031] The switching transistor includes a threshold compensation transistor and a gate reset transistor for resetting the bottom gate of the driving transistor;

[0032] The threshold compensation transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and the bottom gate of the threshold compensation transistor are both used to load a first scanning signal; the second conductive region of the threshold compensation transistor is electrically connected to the first conductive region of the driving transistor;

[0033] The gate reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the gate reset transistor are both used to load a first reset control signal; the first conductive region of the gate reset transistor is used to load a first initialization voltage;

[0034] The bottom gate of the driving transistor, the first conductive region of the threshold compensation transistor, and the second conductive region of the gate reset transistor are electrically connected to each other through a conductive structure.

[0035] In an exemplary embodiment of the present disclosure, the switching transistor includes a threshold compensation transistor and a first light emission control transistor;

[0036] The threshold compensation transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and the bottom gate of the threshold compensation transistor are both used to load a first scanning signal; the first conductive region of the threshold compensation transistor is electrically connected to the bottom gate of the driving transistor;

[0037] The first light emission control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the first light emission control transistor are both used to apply a first light emission control signal; and the first conductive region of the first light emission control transistor is used to apply a first driving power supply voltage;

[0038] The first conductive region of the driving transistor, the second conductive region of the first light emission control transistor, and the second conductive region of the threshold compensation transistor are electrically connected to each other through a conductive structure.

[0039] In an exemplary embodiment of the present disclosure, the switch transistor includes a data writing transistor and a second light emission control transistor;

[0040] The data writing transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the data writing transistor are both used to load a second scanning signal; the first conductive region of the data writing transistor is used to load a data voltage;

[0041] The second light emission control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the second light emission control transistor are both used to load a first light emission control signal; and a second conductive region of the second light emission control transistor is electrically connected to the pixel electrode;

[0042] The second conductive region of the driving transistor, the second conductive region of the data writing transistor, and the first conductive region of the second light emitting control transistor are electrically connected via a conductive structure.

[0043] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer;

[0044] The switch transistor includes a second light emitting control transistor and an electrode reset transistor for resetting the pixel electrode;

[0045] The second light emission control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the second light emission control transistor are both used to load a first light emission control signal; the first conductive region of the second light emission control transistor is electrically connected to the second conductive region of the driving transistor;

[0046] The electrode reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and the bottom gate of the electrode reset transistor are both used to load a second reset control signal; the first conductive region of the electrode reset transistor is used to load a second initialization voltage;

[0047] The second conductive region of the electrode reset transistor, the second electrode plate of the storage capacitor, the second conductive region of the second light emitting control transistor, and the pixel electrode are electrically connected via a conductive structure.

[0048] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a storage capacitor; the storage capacitor includes a first electrode plate located on the first gate layer and a second electrode plate located on the light-shielding metal layer;

[0049] The switch transistor includes a second light emitting control transistor, a gate reset transistor and a data writing transistor;

[0050] The second light emission control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the second light emission control transistor are both used to load a second light emission control signal;

[0051] The gate reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the gate reset transistor are both used to load a second reset control signal; the first conductive region of the gate reset transistor is used to load a first initialization voltage;

[0052] The second conductive region of the second light emitting control transistor, the second conductive region of the gate reset transistor and the bottom gate of the driving transistor are electrically connected via a conductive structure;

[0053] The data write transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the data write transistor are both used to load a first scan signal, and the first conductive region of the data write transistor is used to load a data voltage;

[0054] The second conductive region of the data writing transistor, the first conductive region of the second light emitting control transistor, and the first electrode plate of the storage capacitor are electrically connected to each other through a conductive structure.

[0055] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes an auxiliary capacitor and a storage capacitor; the auxiliary capacitor includes a first electrode plate located on the first gate layer and a second electrode plate located on the light-shielding metal layer; the storage capacitor includes a first electrode plate located on the first gate layer and a second electrode plate located on the light-shielding metal layer;

[0056] The switching transistor includes a voltage stabilizing transistor, a data writing transistor, and an electrode reset transistor;

[0057] The voltage-stabilizing transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the voltage-stabilizing transistor are both used to load a second reset control signal; the first conductive region of the voltage-stabilizing transistor is used to load a first initialization voltage;

[0058] The data writing transistor is used for loading a data voltage onto the first electrode plate of the storage capacitor in response to a first scanning signal;

[0059] The electrode reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and the top gate of the electrode reset transistor are both used to load a first reset control signal; the first conductive region of the electrode reset transistor is used to load a second initialization voltage;

[0060] The second electrode plate of the auxiliary capacitor, the second electrode plate of the storage capacitor, and the second conductive region of the voltage-stabilizing transistor are electrically connected to each other through a conductive structure.

[0061] In an exemplary embodiment of the present disclosure, the conductive structure is located in one or more of the light-shielding metal layer, the first gate layer, the second gate layer, the semiconductor layer, and the source-drain metal layer.

[0062] According to a second aspect of the present disclosure, a display panel is provided, comprising the above-mentioned pixel driving circuit.

[0063] The pixel driving circuit and display panel provided by the present disclosure change the upper and lower dual-gate structure of the driving transistor in the pixel driving circuit to only one of the top gate or bottom gate, thereby reducing the electron mobility of the driving transistor and increasing the SS (subthreshold swing of the thin film transistor) of the driving transistor, which can better match the capabilities of the driver IC (driver chip) and improve the low grayscale image quality of the OLED display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0065] FIG1 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0066] FIG2 is an equivalent circuit diagram of a 5T1C pixel driving circuit in one embodiment of the present disclosure.

[0067] FIG3-1 is a cross-sectional view of a 5T1C pixel driving circuit in one embodiment of the present disclosure.

[0068] FIG3-2 is a cross-sectional view of a 5T1C pixel driving circuit in one embodiment of the present disclosure.

[0069] FIG4 is an equivalent circuit diagram of a 7T1C pixel driving circuit in one embodiment of the present disclosure.

[0070] FIG5-1 is a cross-sectional view of a 7T1C pixel driving circuit in one embodiment of the present disclosure.

[0071] FIG5-2 is a cross-sectional view of a 7T1C pixel driving circuit in one embodiment of the present disclosure.

[0072] FIG6 is an equivalent circuit diagram of a 7T2C pixel driving circuit in one embodiment of the present disclosure.

[0073] FIG7-1 is a cross-sectional view of a 7T2C pixel driving circuit in one embodiment of the present disclosure.

[0074] FIG7-2 is a cross-sectional view of a 7T2C pixel driving circuit in one embodiment of the present disclosure.

[0075] FIG8-1 is a cross-sectional view of a 7T2C pixel driving circuit in one embodiment of the present disclosure.

[0076] FIG8-2 is a cross-sectional view of a 7T2C pixel driving circuit in one embodiment of the present disclosure.

[0077] FIG9 is a graph showing an output curve of a single-gate metal oxide transistor.

[0078] The main components in the figure are marked as follows: T1, gate reset transistor; T2, electrode reset transistor; T3, driving transistor; T4, data writing transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7a, threshold compensation transistor; T7b, voltage-stabilizing transistor; CST1, storage capacitor; CST2, auxiliary capacitor; N1, first node; N2, second node; N3, third node; N4, fourth node; N5, fifth node; OLED, light-emitting element; VDD, first driving power supply voltage; VSS, second driving power supply; Vdata, data voltage; Gate1, first scan signal; Gate2, second scan signal; Gate 3. Third scanning signal; EM, first light-emitting control signal; EM2, second light-emitting control signal; RST1, first reset control signal; RST2, second reset control signal; Vinit1, first initialization voltage; Vinit2, second initialization voltage; SUB, base substrate; LS, light-shielding metal layer; BUF, inorganic buffer layer; GT1, first gate layer; GI1, first gate insulating layer; SCL, semiconductor layer; GI2, second gate insulating layer; GT2, second gate layer; PLN, planarization layer; SD, source and drain metal layer. DETAILED DESCRIPTION

[0079] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present disclosure.

[0080] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0081] The terms "a," "an," and "the" are used to indicate the presence of one or more elements / components; the terms "including" and "having" are used to indicate an open-ended inclusiveness and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first," "second," etc. are used merely as labels and do not limit the quantity of the items to which they refer.

[0082] In the embodiment of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region through which current mainly flows. In the embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first conductive region of the transistor, and the other is referred to as the second conductive region of the transistor.

[0083] The present disclosure provides a pixel driving circuit and a display panel using the pixel driving circuit. The pixel driving circuit is provided in the display panel to drive a light-emitting element (OLED) to emit light. As shown in FIG1 , the pixel driving circuit includes a driving transistor T3 for generating a driving current, at least one switching transistor, a storage capacitor CST1, and the light-emitting element OLED. In the present disclosure, to reduce leakage current, the channel regions of the driving transistor T3 and the switching transistor are both made of a metal oxide semiconductor material, such as IGZO (indium gallium zinc oxide) semiconductor material.

[0084] The driving transistors of each pixel driving circuit are all metal oxide transistors, which can ensure that the pixel driving circuits in different areas of the display panel have good uniformity; compared with the display panel using low-temperature polysilicon transistor + metal oxide transistor technology (LTPO), the display panel of the embodiment of the present disclosure has a lower preparation cost.

[0085] In one example, each transistor of the display driving circuit is a metal oxide transistor.

[0086] In one embodiment of the present disclosure, the switching transistors are all dual-gate transistors, that is, they all have a top gate and a bottom gate. This can reduce the subthreshold swing of the switching transistor, thereby improving the response speed of the switching transistor. In this embodiment of the present disclosure, if the gate of the transistor is located between the channel region of the transistor and the substrate, the gate is the bottom gate of the transistor; if the gate of the transistor is located between the channel region of the transistor and the side away from the substrate, the gate is the top gate of the transistor.

[0087] In one embodiment of the present disclosure, the driving transistor T3 has only one of a top gate and a bottom gate, and the switching transistor has a top gate and a bottom gate.

[0088] In this embodiment, the driving transistor T3 is set to a single-gate structure, which can reduce the electron mobility of the driving transistor T3, thereby increasing the SS (subthreshold swing of the thin film transistor) of the driving transistor T3, which can better match the capabilities of the driving IC and improve the low grayscale image quality of the OLED display panel; and the switching transistor has a dual-gate structure, which can improve the response rate of the switching transistor and realize precise control of the switching transistor.

[0089] In one example, the driving transistor T3 has a top gate, and the switching transistor has a top gate and a bottom gate.

[0090] In another example, the driving transistor T3 has a bottom gate, and the switching transistor has a top gate and a bottom gate.

[0091] In the present disclosure, the driving transistor T3 and each switching transistor can be either N-type or P-type. The present disclosure will be described below taking N-type transistors as an example.

[0092] In one embodiment of the present disclosure, as shown in FIG3-1 , a display panel includes a base substrate SUB, a light-shielding metal layer LS, an inorganic buffer layer BUF, a first gate layer GT1, a first gate insulating layer GI1, a semiconductor layer SCL, a second gate insulating layer GI2, a second gate layer GT2, a planarization layer PLN, and a source / drain metal layer SD, which are stacked in sequence. The semiconductor layer SCL is made of a metal oxide semiconductor material. It is understood that at least a portion of the semiconductor layer SCL may be conductive.

[0093] In an example, the material of the first gate insulating layer GI1 is silicon oxide, such as a dense SiOx material.

[0094] In one example, the inorganic buffer layer BUF material is SiNx (silicon nitride) material.

[0095] In an example, the material of the second gate insulating layer GI2 is silicon oxide, such as a dense SiOx material.

[0096] In the above example, the materials of the first gate insulating layer GI1 and the second gate insulating layer GI2 are dense SiOx materials, which can reduce the diffusion of hydrogen, thereby improving the performance of the metal oxide thin film transistor.

[0097] In the example of FIG3-1 , the driving transistor T3 is a bottom-gate transistor. The driving transistor T3 includes a bottom gate located on the first gate layer GT1 and an active layer located on the semiconductor layer SCL. The active layer of the driving transistor T3 includes a channel region and first and second conductive regions located on either side of the channel region. Each switching transistor includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. The active layer of the switching transistor includes a channel region and first and second conductive regions located on either side of the channel region.

[0098] In the example of Figure 3-2, the driving transistor T3 is a top-gate transistor; the driving transistor T3 includes a top gate located in the second gate layer GT2 and an active layer located in the semiconductor layer SCL; the active layer of the driving transistor T3 includes a channel region and a first conductive region and a second conductive region respectively located on both sides of the channel region.

[0099] The following takes a 5T1C pixel driving circuit (as shown in FIG2 ) as an example to exemplarily introduce the pixel driving circuit.

[0100] In the example of FIG2 , the pixel driving circuit includes a gate reset transistor T1, an electrode reset transistor T2, a driving transistor T3, a data write transistor T4, a first emission control transistor T5, and a storage capacitor CST1. In this pixel driving circuit, the gate reset transistor T1, the electrode reset transistor T2, the data write transistor T4, and the first emission control transistor T5 are all switching transistors. The gate reset transistor T1 has one end for applying a first initialization voltage Vinit1, the other end electrically connected to the first node N1, and a control end for applying a second scan signal Gate2. The electrode reset transistor T2 has one end for applying a second initialization voltage Vinit2, the other end electrically connected to the third node N3, and a control end for applying a third scan signal Gate3. The driving transistor T3 has one end electrically connected to the second node N2, the other end electrically connected to the third node N3, and a control end electrically connected to the first node N1. The data write transistor T4 has one end for applying a data voltage Vdata, the other end electrically connected to the first node N1, and a control end for applying the first scan signal Gate1. The first light-emitting control transistor T5 has one terminal for applying the first driving power supply voltage VDD, the other terminal electrically connected to the second node N2, and a control terminal for applying the first light-emitting control signal EM. The storage capacitor CST1 has one terminal electrically connected to the first node N1, and the other terminal electrically connected to the third node N3.

[0101] In one example of this pixel driving circuit, as shown in Figures 2 and 3-1 (where the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a first emission control transistor T5 for conducting a first driving power supply voltage VDD. The first emission control transistor T5 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top and bottom gates of the first emission control transistor T5 are used to apply a first emission control signal EM. The first conductive region of the first emission control transistor T5 is used to apply the first driving power supply voltage VDD. In this embodiment, the first driving power supply voltage VDD is at a high level. The second conductive region of the first emission control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 via a conductive structure, forming a second node N2.

[0102] In one example of this pixel driving circuit, as shown in Figures 2 and 3-1 (where the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a gate reset transistor T1 for resetting the bottom gate of the driving transistor T3 and a data write transistor T4 for applying a data voltage Vdata. The data write transistor T4 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top and bottom gates of the data write transistor T4 are used to apply a first scan signal Gate1, and a first conductive region of the data write transistor T4 is used to apply the data voltage Vdata. The gate reset transistor T1 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom and top gates of the gate reset transistor T1 are used to apply a second scan signal Gate2, and the first conductive region of the gate reset transistor T1 is used to apply a first initialization voltage Vinit1. The second conductive region of the data writing transistor T4 , the second conductive region of the gate reset transistor T1 , and the bottom gate of the driving transistor T3 are electrically connected to each other through a conductive structure to form a first node N1 .

[0103] In one example of this pixel driving circuit, as shown in Figures 2 and 3-1 (where the driving transistor T3 is a bottom-gate transistor), the first electrode plate of the storage capacitor CST1 serves as the bottom gate of the driving transistor T3, and the second electrode plate of the storage capacitor CST1 is located on the light-shielding metal layer LS. The first electrode plate of the storage capacitor CST1 is electrically connected to the first node N1. This reduces the thickness of the display panel, achieving a thinner and lighter display.

[0104] In one example of the pixel driving circuit, as shown in Figures 2 and 3-1 (where the driving transistor T3 is a bottom-gate transistor), the switching transistor further includes an electrode reset transistor T2 for resetting the pixel electrode. The electrode reset transistor T2 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. The top gate and bottom gate of the electrode reset transistor T2 are both used to apply the third scan signal Gate3. The first conductive region of the electrode reset transistor T2 is used to apply the second initialization voltage Vinit2. The second conductive region of the electrode reset transistor T2, the second electrode plate of the storage capacitor CST1, the second conductive region of the driving transistor T3, and the pixel electrode are electrically connected via a conductive structure to form a third node N3, thereby resetting the pixel electrode of the light-emitting element OLED and eliminating the influence of residual voltage on the light-emitting element OLED.

[0105] The anode of the light emitting element OLED is electrically connected to the first conductive region of the driving transistor T3 , and the cathode is connected to the second driving power supply VSS voltage. Specifically, the second driving power supply VSS voltage is a low level.

[0106] In another example of the pixel driving circuit, as shown in Figures 2 and 3-2 (where the driving transistor T3 is a top-gate transistor), the switching transistor includes a first emission control transistor T5 for conducting a first driving power supply voltage VDD. The first emission control transistor T5 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top and bottom gates of the first emission control transistor T5 are used to apply a first emission control signal EM. The first conductive region of the first emission control transistor T5 is used to apply the first driving power supply voltage VDD. In this embodiment, the first driving power supply voltage VDD is at a high level. The second conductive region of the first emission control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 via a conductive structure, forming a second node N2.

[0107] In another example of the pixel driving circuit, as shown in Figures 2 and 3-2 (where the driving transistor T3 is a top-gate transistor), the switching transistor includes a gate reset transistor T1 for resetting the top gate of the driving transistor T3 and a data write transistor T4 for applying a data voltage Vdata. The data write transistor T4 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top and bottom gates of the data write transistor T4 are used to apply a first scan signal Gate1, and a first conductive region of the data write transistor T4 is used to apply the data voltage Vdata. The gate reset transistor T1 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom and top gates of the gate reset transistor T1 are used to apply a second scan signal Gate2, and the first conductive region of the gate reset transistor T1 is used to apply a first initialization voltage Vinit1. The second conductive region of the data writing transistor T4 , the second conductive region of the gate reset transistor T1 , and the top gate of the driving transistor T3 are electrically connected to each other through a conductive structure to form a first node N1 .

[0108] In another example of the pixel driving circuit, as shown in Figures 2 and 3-2 (where the driving transistor T3 is a top-gate transistor), the second electrode plate of the storage capacitor CST1 is located on the light-shielding metal layer LS, and the first electrode plate of the storage capacitor CST1 is electrically connected to the first node N1. This reduces the thickness of the display panel, achieving a thinner and lighter display panel.

[0109] In another example of the pixel driving circuit, as shown in Figures 2 and 3-2 (where the driving transistor T3 is a top-gate transistor), the switching transistor further includes an electrode reset transistor T2 for resetting the pixel electrode. The electrode reset transistor T2 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. The top gate and bottom gate of the electrode reset transistor T2 are both used to apply the third scan signal Gate3. The first conductive region of the electrode reset transistor T2 is used to apply the second initialization voltage Vinit2. The second conductive region of the electrode reset transistor T2, the second electrode plate of the storage capacitor CST1, the second conductive region of the driving transistor T3, and the pixel electrode are electrically connected via a conductive structure to form a third node N3, thereby resetting the pixel electrode of the light-emitting element OLED and eliminating the influence of residual voltage on the light-emitting element OLED.

[0110] The anode of the light emitting element OLED is electrically connected to the first conductive region of the driving transistor T3 , and the cathode is connected to the second driving power supply VSS voltage. Specifically, the second driving power supply VSS voltage is a low level.

[0111] In the example of FIG5-1, the driving transistor T3 is a bottom-gate transistor. It is understood that in other examples of the present disclosure, the driving transistor T3 may also be a top-gate transistor. For example, in the example of FIG5-2, the driving transistor T3 is a top-gate transistor.

[0112] Taking the pixel driving circuit of 7T1C (as shown in FIG4 ) as an example, the pixel driving circuit is exemplarily introduced.

[0113] In the example of FIG4 , the pixel driving circuit includes a gate reset transistor T1, an electrode reset transistor T2, a driving transistor T3, a data write transistor T4, a first emission control transistor T5, a second emission control transistor T6, a threshold compensation transistor T7a, and a storage capacitor CST1. In this pixel driving circuit, the gate reset transistor T1, the electrode reset transistor T2, the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the threshold compensation transistor T7a are all switching transistors. The gate reset transistor T1 has one end for applying a first initialization voltage Vinit1, the other end electrically connected to the first node N1, and a control end for applying a first reset control signal RST1. The electrode reset transistor T2 has one end for applying a second initialization voltage Vinit2, the other end electrically connected to the fourth node N4, and a control end for applying a second reset control signal RST2. The driving transistor T3 has one end electrically connected to the second node N2, the other end electrically connected to the third node N3, and a control end electrically connected to the first node N1. One end of the data write transistor T4 is used to apply the data voltage Vdata, the other end is electrically connected to the third node N3, and the control end is used to apply the second scan signal Gate2. One end of the first emission control transistor T5 is used to apply the first driving power supply voltage VDD, the other end is electrically connected to the second node N2, and the control end is used to apply the first emission control signal EM. One end of the second emission control transistor T6 is electrically connected to the third node N3, the other end is electrically connected to the fourth node N4, and the control end is used to apply the first emission control signal EM. One end of the threshold compensation transistor T7a is electrically connected to the second node N2, the other end is electrically connected to the first node N1, and the control end is used to apply the first scan signal Gate1. One end of the storage capacitor CST1 is electrically connected to the first node N1, and the other end is electrically connected to the fourth node N4.

[0114] In one example of the pixel driving circuit, as shown in Figures 4 and 5-1 (where the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a gate reset transistor T1 for resetting the bottom gate of the driving transistor T3 and a threshold compensation transistor T7a. The threshold compensation transistor T7a includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top and bottom gates of the threshold compensation transistor T7a are used to apply the first scan signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The gate reset transistor T1 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom and top gates of the gate reset transistor T1 are used to apply the first reset control signal RST1, and the first conductive region of the gate reset transistor T1 is used to apply the first initialization voltage Vinit1. The first electrode plate of the storage capacitor CST1 serves as the bottom gate of the drive transistor T3, and the second electrode plate of the storage capacitor CST1 is located on the light-shielding metal layer LS. The bottom gate of the drive transistor T3, the first conductive region of the threshold compensation transistor T7a, the second conductive region of the gate reset transistor T1, and the first electrode plate of the storage capacitor CST1 are electrically connected via a conductive structure to form a first node N1. The threshold compensation transistor T7a facilitates compensation for the threshold voltage of the drive transistor T3.

[0115] In an example of the pixel driving circuit, as shown in Figures 4 and 5-1 (the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a threshold compensation transistor T7a and a first light-emitting control transistor T5; the threshold compensation transistor T7a includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; wherein the top gate and the bottom gate of the threshold compensation transistor T7a are both used to load the first scanning signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The first light-emitting control transistor T5 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; wherein, the bottom gate and the top gate of the first light-emitting control transistor T5 are both used to load the first light-emitting control signal EM, and the first conductive region of the first light-emitting control transistor T5 is used to load the first driving power supply voltage VDD, where the driving power supply voltage is a high level; the first conductive region of the driving transistor T3, the second conductive region of the first light-emitting control transistor T5, and the second conductive region of the threshold compensation transistor T7a are electrically connected to each other via a conductive structure to form a second node N2.

[0116] In one example of this pixel driving circuit, as shown in Figures 4 and 5-1 (where the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a data write transistor T4 and a second emission control transistor T6. The data write transistor T4 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and top gate of the data write transistor T4 are used to apply the second scan signal Gate2, and the first conductive region of the data write transistor T4 is used to apply the data voltage Vdata. The second emission control transistor T6 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and top gate of the second emission control transistor T6 are used to apply the first emission control signal EM, and the second conductive region of the second emission control transistor T6 is electrically connected to the pixel electrode. The second conductive region of the driving transistor T3, the second conductive region of the data write transistor T4, and the first conductive region of the second emission control transistor T6 are electrically connected via a conductive structure, forming a third node N3.

[0117] In one example of the pixel driving circuit, as shown in Figures 4 and 5-1 (where the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a second emission control transistor T6 and an electrode reset transistor T2 for resetting the pixel electrode. The second emission control transistor T6 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and the top gate of the second emission control transistor T6 are used to apply the first emission control signal EM, and the second conductive region of the second emission control transistor T6 is electrically connected to the pixel electrode. The electrode reset transistor T2 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top gate and the bottom gate of the electrode reset transistor T2 are used to apply the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used to apply the second initialization voltage Vinit2.

[0118] The first electrode plate of the storage capacitor CST1 serves as the bottom gate of the drive transistor T3, and the second electrode plate of the storage capacitor CST1 is located on the light-shielding metal layer LS. The second conductive region of the electrode reset transistor T2, the second electrode plate of the storage capacitor CST1, the second conductive region of the second light-emission control transistor T6, and the pixel electrode are electrically connected via a conductive structure to form a fourth node N4, thereby resetting the pixel electrode of the light-emitting element OLED and eliminating the effects of residual voltage on the light-emitting element OLED.

[0119] In addition, the anode of the light emitting element OLED is electrically connected to the second conductive region of the second light emitting control transistor T6, and the cathode is connected to the second driving power supply VSS voltage. Specifically, the second driving power supply VSS voltage is a low level.

[0120] In another example of this pixel driving circuit, as shown in Figures 4 and 5-2 (where the driving transistor T3 is a top-gate transistor), the switching transistor includes a gate reset transistor T1 for resetting the top gate of the driving transistor T3 and a threshold compensation transistor T7a. The threshold compensation transistor T7a includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top and bottom gates of the threshold compensation transistor T7a are used to apply the first scanning signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The gate reset transistor T1 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom and top gates of the gate reset transistor T1 are used to apply the first reset control signal RST1, and the first conductive region of the gate reset transistor T1 is used to apply the first initialization voltage Vinit1. The second electrode plate of the storage capacitor CST1 is located on the light-shielding metal layer LS. The top gate of the driving transistor T3, the first conductive region of the threshold compensation transistor T7a, the second conductive region of the gate reset transistor T1, and the second electrode plate of the storage capacitor CST1 are electrically connected to each other via a conductive structure to form a first node N1. The threshold compensation transistor T7a facilitates compensation of the threshold voltage of the driving transistor T3.

[0121] In another example of the pixel driving circuit, as shown in Figures 4 and 5-2 (the driving transistor T3 is a top-gate transistor), the switching transistor includes a threshold compensation transistor T7a and a first light-emitting control transistor T5; the threshold compensation transistor T7a includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; wherein the top gate and the bottom gate of the threshold compensation transistor T7a are both used to load the first scanning signal Gate1, and the second conductive region of the threshold compensation transistor T7a is electrically connected to the first conductive region of the driving transistor T3. The first light-emitting control transistor T5 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; wherein, the bottom gate and the top gate of the first light-emitting control transistor T5 are both used to load the first light-emitting control signal EM, and the first conductive region of the first light-emitting control transistor T5 is used to load the first driving power supply voltage VDD, where the driving power supply voltage is a high level; the first conductive region of the driving transistor T3, the second conductive region of the first light-emitting control transistor T5, and the second conductive region of the threshold compensation transistor T7a are electrically connected to each other via a conductive structure to form a second node N2.

[0122] In another example of this pixel driving circuit, as shown in Figures 4 and 5-2 (where the driving transistor T3 is a top-gate transistor), the switching transistor includes a data write transistor T4 and a second emission control transistor T6. The data write transistor T4 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and top gate of the data write transistor T4 are used to apply the second scan signal Gate2, and the first conductive region of the data write transistor T4 is used to apply the data voltage Vdata. The second emission control transistor T6 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and top gate of the second emission control transistor T6 are used to apply the first emission control signal EM, and the second conductive region of the second emission control transistor T6 is electrically connected to the pixel electrode. The second conductive region of the driving transistor T3, the second conductive region of the data write transistor T4, and the first conductive region of the second emission control transistor T6 are electrically connected via a conductive structure, forming a third node N3.

[0123] In another example of the pixel driving circuit, as shown in Figures 4 and 5-2 (where the driving transistor T3 is a top-gate transistor), the switching transistor includes a second emission control transistor T6 and an electrode reset transistor T2 for resetting the pixel electrode. The second emission control transistor T6 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and the top gate of the second emission control transistor T6 are used to apply the first emission control signal EM, and the second conductive region of the second emission control transistor T6 is electrically connected to the pixel electrode. The electrode reset transistor T2 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the top gate and the bottom gate of the electrode reset transistor T2 are used to apply the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used to apply the second initialization voltage Vinit2.

[0124] The second electrode plate of the storage capacitor CST1 is located on the light-shielding metal layer LS. The second conductive region of the reset transistor T2, the first electrode plate of the storage capacitor CST1, the second conductive region of the second light-emission control transistor T6, and the pixel electrode are electrically connected via a conductive structure to form a fourth node N4. This resets the pixel electrode of the light-emitting element OLED and eliminates the effects of residual voltage on the light-emitting element OLED.

[0125] In addition, the anode of the light emitting element OLED is electrically connected to the second conductive region of the second light emitting control transistor T6, and the cathode is connected to the second driving power supply VSS voltage. Specifically, the second driving power supply VSS voltage is a low level.

[0126] In the examples of Figures 7-1 and 8-1, the driving transistor T3 is a bottom-gate transistor. It is understood that in other examples of the present disclosure, the driving transistor T3 may also be a top-gate transistor. For example, in the examples of Figures 7-2 and 8-2, the driving transistor T3 is a top-gate transistor.

[0127] Taking the 7T2C pixel driving circuit (as shown in FIG6 ) as an example, the pixel driving circuit is exemplarily introduced.

[0128] In the example of FIG6 , the pixel driving circuit includes a gate reset transistor T1, an electrode reset transistor T2, a driving transistor T3, a data write transistor T4, a first emission control transistor T5, a second emission control transistor T6, a voltage regulator transistor T7b, a storage capacitor CST1, and an auxiliary capacitor CST2. In this pixel driving circuit, the gate reset transistor T1, the electrode reset transistor T2, the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the voltage regulator transistor T7b are all switching transistors. The gate reset transistor T1 has one end for applying a first initialization voltage Vinit1, the other end electrically connected to the first node N1, and a control end for applying a second reset control signal RST2. The electrode reset transistor T2 has one end for applying the second initialization voltage Vinit2, the other end electrically connected to the third node N3, and a control end for applying the first reset control signal RST1. The driving transistor T3 has one end electrically connected to the second node N2, the other end electrically connected to the third node N3, and a control end electrically connected to the first node N1. One end of the data write transistor T4 is used to apply the data voltage Vdata, the other end is electrically connected to the fifth node N5, and the control end is used to apply the first scan signal Gate1. One end of the first emission control transistor T5 is used to apply the first driving power supply voltage VDD, the other end is electrically connected to the second node N2, and the control end is used to apply the first emission control signal EM. One end of the second emission control transistor T6 is electrically connected to the first node N1, the other end is electrically connected to the fifth node N5, and the control end is used to apply the second emission control signal EM2. One end of the voltage regulator transistor T7b is used to apply the first initialization voltage Vinit1, the other end is electrically connected to the fourth node N4, and the control end is used to apply the second reset control signal RST2. One end of the storage capacitor CST1 is electrically connected to the fifth node N5, and the other end is electrically connected to the fourth node N4. One end of the auxiliary capacitor CST2 is electrically connected to the third node N3, and the other end is electrically connected to the fourth node N4.

[0129] In one example of this pixel driving circuit, as shown in Figures 6, 7-1 (where the driving transistor T3 is a bottom-gate transistor), and 8-1 (where the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a second emission control transistor T6, a gate reset transistor T1, and a data write transistor T4. The second emission control transistor T6 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and the top gate of the second emission control transistor T6 are used to apply the second emission control signal EM2. The gate reset transistor T1 includes a bottom gate located in the first gate layer GT1, an active layer located in the semiconductor layer SCL, and a top gate located in the second gate layer GT2; wherein, the bottom gate and the top gate of the gate reset transistor T1 are both used to load the second reset control signal RST2, and the first conductive region of the gate reset transistor T1 is used to load the first initialization voltage Vinit1; the second conductive region of the second light emitting control transistor T6, the second conductive region of the gate reset transistor T1, and the bottom gate of the driving transistor T3 are all electrically connected through a conductive structure to form a first node N1.

[0130] In one example of this pixel driving circuit, as shown in Figures 6 and 8-1 (where the driving transistor T3 is a bottom-gate transistor), the data write transistor T4 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; wherein the bottom gate and top gate of the data write transistor T4 are both used to load the first scan signal Gate1, and the first conductive region of the data write transistor T4 is used to load the data voltage Vdata. The storage capacitor CST1 includes a first electrode plate located on the first gate layer GT1 and a second electrode plate located on the light-shielding metal layer LS. The second conductive region of the data write transistor T4, the first conductive region of the second light-emitting control transistor T6, and the first electrode plate of the storage capacitor CST1 are electrically connected to each other via a conductive structure to form a fifth node N5.

[0131] In an example of the pixel driving circuit, as shown in Figure 6 (the driving transistor T3 is a bottom-gate transistor), the switching transistor includes a first light-emitting control transistor T5, which includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; the top gate and the bottom gate of the first light-emitting control transistor T5 are both used to load the first light-emitting control signal EM, and the first conductive region of the first light-emitting control transistor T5 is used to load the first driving power supply voltage VDD. In this embodiment, the first driving power supply voltage VDD is a high level; the second conductive region of the first light-emitting control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 through a conductive structure to form a second node N2.

[0132] In one example of the pixel driving circuit, as shown in Figures 6, 7-1, and 8-1 (where the driving transistor T3 is a bottom-gate transistor), the pixel driving circuit further includes an auxiliary capacitor CST2, which includes a first electrode plate located on the first gate layer GT1 and a second electrode plate located on the light-shielding metal layer LS. The switching transistor includes a voltage-stabilizing transistor T7b, a data-writing transistor T4, and an electrode reset transistor T2; wherein the voltage-stabilizing transistor T7b includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; the bottom gate and top gate of the voltage-stabilizing transistor T7b are both used to apply the second reset control signal RST2, and the first conductive region of the voltage-stabilizing transistor T7b is used to apply the first initialization voltage Vinit1.

[0133] The data write transistor T4 includes a bottom gate located in the first gate layer GT1, an active layer located in the semiconductor layer SCL, and a top gate located in the second gate layer GT2; wherein, the bottom gate and the top gate of the data write transistor T4 are both used to load the first scan signal Gate1, and the first conductive area of ​​the data write transistor T4 is used to load the data voltage Vdata.

[0134] The second electrode plate of the auxiliary capacitor CST2, the second electrode plate of the storage capacitor CST1, and the second conductive region of the voltage regulator transistor T7b are electrically connected to each other through a conductive structure to form a fourth node N4.

[0135] In one example of the pixel driving circuit, the electrode reset transistor T2 includes a bottom gate located in the first gate layer GT1, an active layer located in the semiconductor layer SCL, and a top gate located in the second gate layer GT2; wherein, the top gate and the bottom gate of the electrode reset transistor T2 are both used to load the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used to load the second initialization voltage Vinit2.

[0136] In an example of the pixel driving circuit, as shown in Figures 6 and 8-1 (the driving transistor T3 is a bottom-gate transistor), the second conductive region of the electrode reset transistor T2, the second conductive region of the driving transistor T3, the first electrode plate of the auxiliary capacitor CST2, and the pixel electrode of the light-emitting element OLED are all electrically connected through a conductive structure to form a third node N3, so as to reset the pixel electrode of the light-emitting element OLED and eliminate the influence of the residual voltage on the light-emitting element OLED.

[0137] In addition, the anode of the light emitting element OLED is electrically connected to the second conductive region of the second light emitting control transistor T6, and the cathode is connected to the second driving power supply VSS voltage. Specifically, the second driving power supply VSS voltage is a low level.

[0138] It should be noted that, since the driving transistor T3 and each switching transistor are described as N-type transistors, the first conductive regions of the driving transistor T3 and each switching transistor are sources, and the second conductive regions are drains.

[0139] In another example of the pixel driving circuit, as shown in Figures 6, 7-2 (where the driving transistor T3 is a top-gate transistor), and 8-2 (where the driving transistor T3 is a top-gate transistor), the switching transistor includes a second emission control transistor T6, a gate reset transistor T1, and a data write transistor T4. The second emission control transistor T6 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and the top gate of the second emission control transistor T6 are used to apply the second emission control signal EM2. The gate reset transistor T1 includes a bottom gate located in the first gate layer GT1, an active layer located in the semiconductor layer SCL, and a top gate located in the second gate layer GT2; wherein, the bottom gate and the top gate of the gate reset transistor T1 are both used to load the second reset control signal RST2, and the first conductive region of the gate reset transistor T1 is used to load the first initialization voltage Vinit1; the second conductive region of the second light-emitting control transistor T6, the second conductive region of the gate reset transistor T1, and the top gate of the driving transistor T3 are all electrically connected through a conductive structure to form a first node N1.

[0140] In another example of this pixel driving circuit, as shown in Figures 6 and 8-2 (where the driving transistor T3 is a top-gate transistor), the data write transistor T4 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2. Both the bottom gate and the top gate of the data write transistor T4 are used to apply the first scan signal Gate1, and the first conductive region of the data write transistor T4 is used to apply the data voltage Vdata. The storage capacitor CST1 includes a first electrode plate located on the first gate layer GT1 and a second electrode plate located on the light-shielding metal layer LS. The second conductive region of the data write transistor T4, the first conductive region of the second light-emitting control transistor T6, and the first electrode plate of the storage capacitor CST1 are electrically connected to each other via a conductive structure, forming a fifth node N5.

[0141] In another example of the pixel driving circuit, as shown in Figure 6 (the driving transistor T3 is a top-gate transistor), the switching transistor includes a first light-emitting control transistor T5, which includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; the top gate and the bottom gate of the first light-emitting control transistor T5 are both used to load the first light-emitting control signal EM, and the first conductive region of the first light-emitting control transistor T5 is used to load the first driving power supply voltage VDD. In this embodiment, the first driving power supply voltage VDD is at a high level; the second conductive region of the first light-emitting control transistor T5 is electrically connected to the first conductive region of the driving transistor T3 through a conductive structure to form a second node N2.

[0142] In another example of the pixel driving circuit, as shown in Figures 6, 7-2, and 8-2 (where the driving transistor T3 is a top-gate transistor), the pixel driving circuit further includes an auxiliary capacitor CST2, which includes a first electrode plate located on the first gate layer GT1 and a second electrode plate located on the light-shielding metal layer LS. The switching transistor includes a voltage-stabilizing transistor T7b, a data-writing transistor T4, and an electrode reset transistor T2; wherein the voltage-stabilizing transistor T7b includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; the bottom gate and top gate of the voltage-stabilizing transistor T7b are both used to load the second reset control signal RST2, and the first conductive region of the voltage-stabilizing transistor T7b is used to load the first initialization voltage Vinit1.

[0143] The data write transistor T4 includes a bottom gate located in the first gate layer GT1, an active layer located in the semiconductor layer SCL, and a top gate located in the second gate layer GT2; wherein, the bottom gate and the top gate of the data write transistor T4 are both used to load the first scan signal Gate1, and the first conductive area of ​​the data write transistor T4 is used to load the data voltage Vdata.

[0144] The second electrode plate of the auxiliary capacitor CST2, the second electrode plate of the storage capacitor CST1, and the second conductive region of the voltage regulator transistor T7b are electrically connected to each other through a conductive structure to form a fourth node N4.

[0145] In another example of the pixel driving circuit (the driving transistor T3 is a top-gate transistor), the electrode reset transistor T2 includes a bottom gate located on the first gate layer GT1, an active layer located on the semiconductor layer SCL, and a top gate located on the second gate layer GT2; wherein the top gate and the bottom gate of the electrode reset transistor T2 are both used to load the second reset control signal RST2, and the first conductive region of the electrode reset transistor T2 is used to load the second initialization voltage Vinit2.

[0146] In another example of the pixel driving circuit, as shown in Figures 6 and 8-2 (the driving transistor T3 is a top-gate transistor), the second conductive region of the electrode reset transistor T2, the second conductive region of the driving transistor T3, the first electrode plate of the auxiliary capacitor CST2, and the pixel electrode of the light-emitting element OLED are all electrically connected through a conductive structure to form a third node N3, so as to reset the pixel electrode of the light-emitting element OLED and eliminate the influence of the residual voltage on the light-emitting element OLED.

[0147] In addition, the anode of the light emitting element OLED is electrically connected to the second conductive region of the second light emitting control transistor T6, and the cathode is connected to the second driving power supply VSS voltage. Specifically, the second driving power supply VSS voltage is a low level.

[0148] It should be noted that, since the driving transistor T3 and each switching transistor are described as N-type transistors, the first conductive regions of the driving transistor T3 and each switching transistor are sources, and the second conductive regions are drains.

[0149] In one embodiment of the present disclosure, the conductive structure is located in one or more of the light-shielding metal layer LS, the first gate layer GT1, the second gate layer GT2, the semiconductor layer SCL, and the source / drain metal layer SD, as long as the various transistors are electrically connected.

[0150] In one embodiment of the present disclosure, the driving transistor T3 and each switching transistor can adopt a back channel etching process (BCE); preferably, the driving transistor T3 and each switching transistor preferably adopt an etch stop layer preparation process (ESL) to reduce the impact on the semiconductor layer SCL during the etching process.

[0151] In the embodiments of the present disclosure, the SS of the dual-gate MOS transistor is relatively small. As shown in FIG9 , the SS of the single-gate MOS transistor is greater than that of the dual-gate MOS transistor, indicating that the switching characteristics of the single-gate MOS transistor are lower than those of the dual-gate MOS transistor, facilitating the development of low grayscale displays. For example, when the drain current of the thin-film transistor changes by an order of magnitude (10 times), the corresponding gate voltage change of the single-gate MOS transistor is smaller than that of the dual-gate MOS transistor.

[0152] As shown in Figure 9, the drain voltage of a single-gate metal oxide transistor is divided into two states: 0.1V and 1V. It can be seen that under the same gate voltage, the drain current when the drain voltage is 1V is greater than the drain current when the drain voltage is 0.1V, but the change in the drain current is small; for example, when the gate voltage is 0.4V, the drain current in both states is close to 10 -9A, although the drain voltage spans an order of magnitude, the drain current of the driving transistor T3 changes very slightly.

[0153] The present disclosure also provides a display panel including the aforementioned pixel driver circuit. The display panel includes: a plurality of scan lines for providing scan signals; a plurality of data lines for providing data signals; and a plurality of pixel driver circuits electrically connected to the scan lines and data lines; at least one of the pixel driver circuits includes any of the aforementioned pixel driver circuits in this exemplary embodiment. Because this pixel driver circuit reduces the electron mobility of the driver transistor T3, thereby increasing the SS of the driver transistor T3, it can better match the capabilities of the driver IC, thereby improving the low-grayscale image quality of the OLED display panel.

[0154] The display device using the display panel may include, for example, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0155] It should be noted that although the steps of the method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additional or alternative steps, such as omitting certain steps, combining multiple steps into one step, and / or decomposing a step into multiple steps, should all be considered part of this disclosure.

[0156] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A pixel driving circuit, provided in a display panel to drive a light emitting element, characterized in that: The pixel driving circuit includes a driving transistor for generating a driving current. The material of a channel region of the driving transistor is a metal oxide semiconductor material. The driving transistor has only one of a top gate and a bottom gate.

2. The pixel driving circuit according to claim 1, characterized in that: The display panel comprises a base substrate, a light shielding metal layer, an inorganic buffer layer, a first gate layer, a first gate insulating layer and a semiconductor layer which are stacked in sequence; The active layer of the driving transistor is located in the semiconductor layer; the driving transistor has a bottom gate located in the first gate layer; The pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is located on the light-shielding metal layer of the display panel, and a second electrode plate of the storage capacitor is a bottom gate of the driving transistor.

3. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes at least one switch transistor, and a material of a channel region of the switch transistor is a metal oxide semiconductor material.

4. The pixel driving circuit according to claim 3, characterized in that: The switching transistor has a top gate and a bottom gate.

5. The pixel driving circuit according to claim 4, characterized in that: The display panel comprises a base substrate, a light shielding metal layer, an inorganic buffer layer, a first gate layer, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, a second gate layer, a planarization layer and a source-drain metal layer which are stacked in sequence; The driving transistor includes a bottom gate located at the first gate layer and an active layer located at the semiconductor layer; the active layer of the driving transistor includes a channel region and a first conductive region and a second conductive region respectively located at both sides of the channel region; each of the switching transistors includes a bottom gate located at the first gate layer, an active layer located at the semiconductor layer and a top gate located at the second gate layer; the active layer of the switching transistor includes a channel region and a first conductive region and a second conductive region respectively located at both sides of the channel region.

6. The pixel driving circuit according to claim 5, characterized in that: The switch transistor includes a first light emitting control transistor; The first light emission control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; The top gate and the bottom gate of the first light emitting control transistor are both used to load the first light emitting control signal; The first conductive region of the first light emitting control transistor is used to load a first driving power supply voltage; The second conductive region of the first light emission control transistor is electrically connected to the first conductive region of the driving transistor through a conductive structure.

7. The pixel driving circuit according to claim 5, characterized in that: The switch transistor includes a data writing transistor for loading a data voltage and a gate reset transistor for resetting a bottom gate of the driving transistor; The data writing transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer and a top gate located at the second gate layer; the top gate and the bottom gate of the data writing transistor are both used to load a first scanning signal; the first conductive area of ​​the data writing transistor is used to load a data voltage; The gate reset transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the gate reset transistor are both used to load a second scanning signal; the first conductive region of the gate reset transistor is used to load a first initialization voltage; The second conductive region of the data writing transistor, the second conductive region of the gate reset transistor, and the bottom gate of the driving transistor are electrically connected to each other through a conductive structure; The pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located on the light-shielding metal layer.

8. The pixel driving circuit according to claim 5, characterized in that: The pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer; The switch transistor includes an electrode reset transistor for resetting the pixel electrode; the electrode reset transistor includes a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the top gate and the bottom gate of the electrode reset transistor are both used to load a third scanning signal; the first conductive area of ​​the electrode reset transistor is used to load a first 2. Initialization voltage; The second conductive region of the electrode reset transistor, the second electrode plate of the storage capacitor, the second conductive region of the driving transistor, and the pixel electrode are electrically connected via a conductive structure.

9. The pixel driving circuit according to claim 5, characterized in that: The pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer; The switch transistor includes a threshold compensation transistor and a gate reset transistor for resetting the bottom gate of the drive transistor; The threshold compensation transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the top gate and the bottom gate of the threshold compensation transistor are both used to load a first scanning signal; the second conductive region of the threshold compensation transistor is electrically connected to the first conductive region of the driving transistor; The gate reset transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the gate reset transistor are both used to load a first reset control signal; the first conductive region of the gate reset transistor is used to load a first initialization voltage; The bottom gate of the driving transistor, the first conductive region of the threshold compensation transistor, and the second conductive region of the gate reset transistor are electrically connected to each other through a conductive structure.

10. The pixel driving circuit according to claim 5, characterized in that: The switch transistor includes a threshold compensation transistor and a first light emission control transistor; The threshold compensation transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the top gate and the bottom gate of the threshold compensation transistor are both used to load a first scanning signal; the first conductive region of the threshold compensation transistor is electrically connected to the bottom gate of the driving transistor; The first light emission control transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the first light emission control transistor are both used to load a first light emission control signal; the first conductive region of the first light emission control transistor is used to load a first driving power supply voltage; The first conductive region of the driving transistor, the second conductive region of the first light emission control transistor, and the second conductive region of the threshold compensation transistor are electrically connected to each other through a conductive structure.

11. The pixel driving circuit according to claim 5, characterized in that: The switch transistor includes a data writing transistor and a second light emission control transistor; The data writing transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer and a top gate located at the second gate layer; the bottom gate and the top gate of the data writing transistor are both used to load a second scanning signal; the first conductive area of ​​the data writing transistor is used to load a data voltage; The second light emission control transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the second light emission control transistor are both used to load the first light emission control signal; the second conductive region of the second light emission control transistor is electrically connected to the pixel electrode; The second conductive region of the driving transistor, the second conductive region of the data writing transistor, and the first conductive region of the second light emitting control transistor are electrically connected through a conductive structure.

12. The pixel driving circuit according to claim 5, characterized in that: The pixel driving circuit further includes a storage capacitor, a first electrode plate of the storage capacitor is reused as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer; The switch transistor includes a second light emitting control transistor and an electrode reset transistor for resetting the pixel electrode; The second light emission control transistor includes a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the second light emission control transistor are both used to load a first light emission control signal; the first conductive region of the second light emission control transistor is electrically connected to the second conductive region of the driving transistor; The electrode reset transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the top gate and the bottom gate of the electrode reset transistor are both used to load a second reset control signal; the first conductive region of the electrode reset transistor is used to load a second initialization voltage; The second conductive area of ​​the electrode reset transistor, the second electrode plate of the storage capacitor, the second conductive area of ​​the second light emitting control transistor, and the pixel electrode are electrically connected through a conductive structure.

13. The pixel driving circuit according to claim 5, characterized in that: The pixel driving circuit includes a storage capacitor; the storage capacitor includes a first electrode plate located at the first gate layer and a second electrode plate located at the light-shielding metal layer; The switch transistor includes a second light emitting control transistor, a gate reset transistor and a data writing transistor; The second light emission control transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the second light emission control transistor are both used to load a second light emission control signal; The gate reset transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the gate reset transistor are both used to load a second reset control signal; the first conductive region of the gate reset transistor is used to load a first initialization voltage; The second conductive region of the second light emitting control transistor, the second conductive region of the gate reset transistor and the bottom gate of the driving transistor are electrically connected via a conductive structure; The data writing transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer and a top gate located at the second gate layer; the bottom gate and the top gate of the data writing transistor are both used to load a first scanning signal, and the first conductive area of ​​the data writing transistor is used to load a data voltage; The second conductive region of the data writing transistor, the first conductive region of the second light emitting control transistor, and the first electrode plate of the storage capacitor are electrically connected to each other through a conductive structure.

14. The pixel driving circuit according to claim 5, characterized in that: The pixel driving circuit includes an auxiliary capacitor and a storage capacitor; the auxiliary capacitor includes a first electrode plate located at the first gate layer and a second electrode plate located at the light-shielding metal layer; the storage capacitor includes a first electrode plate located at the first gate layer and a second electrode plate located at the light-shielding metal layer; The switch transistor includes a voltage stabilizing transistor, a data writing transistor, and an electrode resetting transistor; The voltage stabilizing transistor comprises a bottom gate located at the first gate layer, an active layer located at the semiconductor layer, and a top gate located at the second gate layer; the bottom gate and the top gate of the voltage stabilizing transistor are both used to load a second reset control signal; the first conductive region of the voltage stabilizing transistor is used to load a first initialization voltage; The data writing transistor is used for loading the data voltage to the first electrode plate of the storage capacitor in response to the first scanning signal; The electrode reset transistor includes a bottom gate located at the first gate layer, a bottom gate located at the semiconductor layer The active layer of the body layer and the top gate located at the second gate layer; the bottom gate and the top gate of the electrode reset transistor are both used to load the first reset control signal; the first conductive area of ​​the electrode reset transistor is used to load the second initialization voltage; The second electrode plate of the auxiliary capacitor, the second electrode plate of the storage capacitor, and the second conductive area of ​​the voltage-stabilizing transistor are electrically connected to each other through a conductive structure.

15. The pixel driving circuit according to any one of claims 6 to 14, characterized in that: The conductive structure is located in one or more of the light-shielding metal layer, the first gate layer, the second gate layer, the semiconductor layer, and the source-drain metal layer.

16. A display panel, characterized in that: The invention comprises the pixel driving circuit according to any one of claims 1 to 15.

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